From 522b0c11efa9be870f806b452d0ca734738880c9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 29 Nov 2018 22:59:00 +0700
Subject: move nvic prio in hal/dcd to bsp for portability

---
 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c | 10 ----------
 1 file changed, 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
index 517f037d0..af7ceae0c 100644
--- a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
+++ b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
@@ -44,8 +44,6 @@
 #include "dcd_lpc175x_6x.h"
 #include "LPC17xx.h"
 
-#include "osal/osal.h"
-
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -199,14 +197,6 @@ bool dcd_init(uint8_t rhport)
   sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);    // connect
 
   // USB IRQ priority should be set by application previously
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  if ( NVIC_GetPriority(USB_IRQn) < configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY )
-  {
-    NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-  }
-#endif
-
   NVIC_ClearPendingIRQ(USB_IRQn);
   NVIC_EnableIRQ(USB_IRQn);
 
-- 
cgit v1.3.1


From d96347a0f5ec9272088b11425e1a8a3fb4115e8a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 12:48:06 +0700
Subject: rename OPT_MCU_LPC13UXX to OPT_MCU_LPC13XX

---
 examples/device/device_virtual_com/src/tusb_config.h   | 8 ++++----
 examples/obsolete/device/device_freertos/.cproject     | 2 +-
 examples/obsolete/device/device_os_none/.cproject      | 2 +-
 examples/obsolete/device/src/msc_device_app.h          | 2 +-
 examples/obsolete/device/src/tusb_config.h             | 8 ++++----
 hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c             | 2 +-
 src/class/msc/msc_device.c                             | 2 +-
 src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c | 2 +-
 src/tusb_option.h                                      | 4 ++--
 9 files changed, 16 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/examples/device/device_virtual_com/src/tusb_config.h b/examples/device/device_virtual_com/src/tusb_config.h
index fd3f41b01..77be85df3 100644
--- a/examples/device/device_virtual_com/src/tusb_config.h
+++ b/examples/device/device_virtual_com/src/tusb_config.h
@@ -92,7 +92,7 @@
 //--------------------------------------------------------------------+
 #ifdef __CODE_RED // compiled with lpcxpresso
 
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
     #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(.data.$RAM2) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned
   #elif CFG_TUSB_MCU == OPT_MCU_LPC175X_6X
     #define CFG_TUSB_MEM_SECTION // LPC17xx USB DMA can access all
@@ -102,7 +102,7 @@
 
 #elif defined  __CC_ARM // Compiled with Keil armcc, USBRAM_SECTION is defined in scatter files
 
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
     #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(USBRAM_SECTION) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned
   #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
     #define CFG_TUSB_MEM_SECTION  // LPC17xx USB DMA can access all address
@@ -112,7 +112,7 @@
 
 #elif defined __ICCARM__ // compiled with IAR
 
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
     #define CFG_TUSB_MEM_SECTION _Pragma("location=\"USB_PACKET_MEMORY\"") ATTR_ALIGNED(64)
   #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
     #define CFG_TUSB_MEM_SECTION
@@ -132,7 +132,7 @@
 
 
 // LPC11uxx and LPC13uxx requires each buffer has to be 64-byte alignment
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13UXX
+#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX
  #define CFG_TUSB_MEM_ALIGN   ATTR_ALIGNED(64)
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
  #define CFG_TUSB_MEM_ALIGN   ATTR_ALIGNED(4)
diff --git a/examples/obsolete/device/device_freertos/.cproject b/examples/obsolete/device/device_freertos/.cproject
index eb09f25e7..53b3552b1 100644
--- a/examples/obsolete/device/device_freertos/.cproject
+++ b/examples/obsolete/device/device_freertos/.cproject
@@ -34,7 +34,7 @@
 									<listOptionValue builtIn="false" value="__REDLIB__"/>
 									<listOptionValue builtIn="false" value="CFG_TUSB_OS=OPT_OS_FREERTOS"/>
 									<listOptionValue builtIn="false" value="CFG_TUD_TASK_PRIO=configMAX_PRIORITIES-5"/>
-									<listOptionValue builtIn="false" value="CFG_TUSB_MCU=OPT_MCU_LPC13UXX"/>
+									<listOptionValue builtIn="false" value="CFG_TUSB_MCU=OPT_MCU_LPC13XX"/>
 									<listOptionValue builtIn="false" value="BOARD=BOARD_LPCXPRESSO1347"/>
 									<listOptionValue builtIn="false" value="DEBUG"/>
 									<listOptionValue builtIn="false" value="__CODE_RED"/>
diff --git a/examples/obsolete/device/device_os_none/.cproject b/examples/obsolete/device/device_os_none/.cproject
index fabc46d88..355f8ba96 100644
--- a/examples/obsolete/device/device_os_none/.cproject
+++ b/examples/obsolete/device/device_os_none/.cproject
@@ -33,7 +33,7 @@
 								<option id="gnu.c.compiler.option.preprocessor.def.symbols.371325215" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="__REDLIB__"/>
 									<listOptionValue builtIn="false" value="CFG_TUSB_OS=OPT_OS_NONE"/>
-									<listOptionValue builtIn="false" value="CFG_TUSB_MCU=OPT_MCU_LPC13UXX"/>
+									<listOptionValue builtIn="false" value="CFG_TUSB_MCU=OPT_MCU_LPC13XX"/>
 									<listOptionValue builtIn="false" value="BOARD=BOARD_LPCXPRESSO1347"/>
 									<listOptionValue builtIn="false" value="DEBUG"/>
 									<listOptionValue builtIn="false" value="__CODE_RED"/>
diff --git a/examples/obsolete/device/src/msc_device_app.h b/examples/obsolete/device/src/msc_device_app.h
index cc3caa102..6f2e95630 100644
--- a/examples/obsolete/device/src/msc_device_app.h
+++ b/examples/obsolete/device/src/msc_device_app.h
@@ -63,7 +63,7 @@ enum
 If you find any bugs or get any questions, feel free to file an\r\n\
 issue at github.com/hathach/tinyusb"
 
-#if CFG_TUSB_MCU==OPT_MCU_LPC11UXX || CFG_TUSB_MCU==OPT_MCU_LPC13UXX
+#if CFG_TUSB_MCU==OPT_MCU_LPC11UXX || CFG_TUSB_MCU==OPT_MCU_LPC13XX
   #define MSCD_APP_ROMDISK
 #else // defaults is ram disk
   #define MSCD_APP_RAMDISK
diff --git a/examples/obsolete/device/src/tusb_config.h b/examples/obsolete/device/src/tusb_config.h
index c5739038f..bc9ff27fe 100644
--- a/examples/obsolete/device/src/tusb_config.h
+++ b/examples/obsolete/device/src/tusb_config.h
@@ -96,7 +96,7 @@
 //--------------------------------------------------------------------+
 #ifdef __CODE_RED // compiled with lpcxpresso
 
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
     #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(.data.$RAM2) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned
   #elif CFG_TUSB_MCU == OPT_MCU_LPC175X_6X
     #define CFG_TUSB_MEM_SECTION // LPC17xx USB DMA can access all
@@ -106,7 +106,7 @@
 
 #elif defined  __CC_ARM // Compiled with Keil armcc, USBRAM_SECTION is defined in scatter files
 
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
     #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(USBRAM_SECTION) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned
   #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
     #define CFG_TUSB_MEM_SECTION  // LPC17xx USB DMA can access all address
@@ -116,7 +116,7 @@
 
 #elif defined __ICCARM__ // compiled with IAR
 
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
     #define CFG_TUSB_MEM_SECTION _Pragma("location=\"USB_PACKET_MEMORY\"") ATTR_ALIGNED(64)
   #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
     #define CFG_TUSB_MEM_SECTION
@@ -131,7 +131,7 @@
 #endif
 
 // LPC11uxx and LPC13uxx requires each buffer has to be 64-byte alignment
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13UXX
+#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX
  #define CFG_TUSB_MEM_ALIGN   ATTR_ALIGNED(64)
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
  #define CFG_TUSB_MEM_ALIGN   ATTR_ALIGNED(4)
diff --git a/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c b/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
index c87387015..5c6c2e623 100644
--- a/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
+++ b/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
@@ -39,7 +39,7 @@
 #include "common/tusb_common.h"
 #include "hal.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC13UXX
+#if CFG_TUSB_MCU == OPT_MCU_LPC13XX
 
 void tusb_hal_int_enable(uint8_t rhport)
 {
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 4fc3dd1b5..83c9990d8 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -62,7 +62,7 @@ enum
 typedef struct {
   CFG_TUSB_MEM_ALIGN msc_cbw_t  cbw;
 
-//#if defined (__ICCARM__) && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+//#if defined (__ICCARM__) && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
 //  uint8_t padding1[64-sizeof(msc_cbw_t)]; // IAR cannot align struct's member
 //#endif
 
diff --git a/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c b/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
index 4e514d6e2..029677e7c 100644
--- a/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
+++ b/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
@@ -38,7 +38,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13UXX)
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
 
 #define _TINY_USB_SOURCE_FILE_
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e1aec3302..ea15f6c5d 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -49,8 +49,8 @@
  * \ref CFG_TUSB_MCU must be defined to one of these
  *  @{ */
 #define OPT_MCU_LPC11UXX       1 ///< NXP LPC11Uxx series
-#define OPT_MCU_LPC13XX        2 ///< NXP LPC13xx (not supported yet)
-#define OPT_MCU_LPC13UXX       3 ///< NXP LPC13xx 12 bit ADC series
+
+#define OPT_MCU_LPC13XX       3 ///< NXP LPC13xx 12 bit ADC series
 #define OPT_MCU_LPC175X_6X     4 ///< NXP LPC175x, LPC176x series
 #define OPT_MCU_LPC177X_8X     5 ///< NXP LPC177x, LPC178x series (not supported yet)
 #define OPT_MCU_LPC18XX        6 ///< NXP LPC18xx series (not supported yet)
-- 
cgit v1.3.1


From 723e02780d82946bf08349e1012b24885430e3b2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 12:51:54 +0700
Subject: clean up

---
 src/portable/nxp/lpc17xx/hal_mcu.h | 55 --------------------------------------
 1 file changed, 55 deletions(-)
 delete mode 100644 src/portable/nxp/lpc17xx/hal_mcu.h

(limited to 'src')

diff --git a/src/portable/nxp/lpc17xx/hal_mcu.h b/src/portable/nxp/lpc17xx/hal_mcu.h
deleted file mode 100644
index be1e71671..000000000
--- a/src/portable/nxp/lpc17xx/hal_mcu.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_lpc175x_6x.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#ifndef _TUSB_HAL_MCU_H_
-#define _TUSB_HAL_MCU_H_
-
-#include "LPC17xx.h"
-#include "lpc17xx_pinsel.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_HAL_MCU_H_ */
-
-- 
cgit v1.3.1


From 658c2ff570ffd912bc65f457a741952cf458a68b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 12:56:09 +0700
Subject: rename

---
 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c | 579 +++++++++++++++++++++
 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h |  57 ++
 .../nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c      | 579 ---------------------
 .../nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.h      |  57 --
 4 files changed, 636 insertions(+), 636 deletions(-)
 create mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c
 create mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h
 delete mode 100644 src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
 delete mode 100644 src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.h

(limited to 'src')

diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c
new file mode 100644
index 000000000..029677e7c
--- /dev/null
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c
@@ -0,0 +1,579 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc_11uxx_13uxx.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
+
+#define _TINY_USB_SOURCE_FILE_
+
+// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
+// endpoint's max packet size and need some soft DMA helper
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "hal/hal.h"
+#include "osal/osal.h"
+
+#include "device/dcd.h"
+#include "usbd_dcd.h"
+#include "dcd_lpc_11uxx_13uxx.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+#define DCD_11U_13U_QHD_COUNT 10
+
+enum {
+  DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
+};
+
+#ifdef __CC_ARM
+#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
+#endif
+
+enum {
+  INT_MASK_SOF           = BIT_(30),
+  INT_MASK_DEVICE_STATUS = BIT_(31)
+};
+
+#ifdef __CC_ARM
+#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
+#endif
+
+enum {
+  CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
+  CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
+  CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
+  CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16), ///< reflect the softconnect only, does not reflect the actual attached state
+  CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
+  CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
+  CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
+  CMDSTAT_RESET_CHANGE_MASK   = BIT_(26),
+  CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
+};
+
+// buffer input must be 64 byte alignment
+typedef struct ATTR_PACKED
+{
+  volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
+
+  volatile uint16_t nbytes      : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
+  uint16_t is_isochronous       : 1  ;
+  uint16_t feedback_toggle      : 1  ; ///< For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero. For the control endpoint zero this bit is used as the toggle value. When the toggle reset bit is set, the data toggle is updated with the value programmed in this bit. When the endpoint is used as an interrupt endpoint, it can be set to the following values. 0: Interrupt endpoint in ‘toggle mode’ 1: Interrupt endpoint in ‘rate feedback mode’. This means that the data toggle is fixed to zero for all data packets. When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to zero.
+  uint16_t toggle_reset         : 1  ; ///< When software sets this bit to one, the HW will set the toggle value equal to the value indicated in the “toggle value” (TV) bit. For the control endpoint zero, this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received. For the other endpoints, the toggle can only be reset to zero when the endpoint is reset.
+  uint16_t stall                : 1  ; ///< 0: The selected endpoint is not stalled 1: The selected endpoint is stalled The Active bit has always higher priority than the Stall bit. This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one. Software can only modify this bit when the active bit is zero.
+  uint16_t disable              : 1  ; ///< 0: The selected endpoint is enabled. 1: The selected endpoint is disabled. If a USB token is received for an endpoint that has the disabled bit set, hardware will ignore the token and not return any data or handshake. When a bus reset is received, software must set the disable bit of all endpoints to 1. Software can only modify this bit when the active bit is zero.
+  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
+}dcd_11u_13u_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
+
+// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
+// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
+// next_td stored the 2nd request information
+// current_td is used to keep track of number of remaining & xferred bytes of the current request.
+// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
+
+typedef struct {
+  dcd_11u_13u_qhd_t qhd[DCD_11U_13U_QHD_COUNT][2]; ///< must be 256 byte alignment, 2 for double buffer
+
+  // start at 80, the size should not exceed 48 (for setup_request align at 128)
+  struct {
+    uint16_t buff_addr_offset;
+    uint16_t total_bytes;
+  }next_td[DCD_11U_13U_QHD_COUNT];
+
+  uint32_t current_ioc;          ///< interrupt on complete mask for current TD
+  uint32_t next_ioc;             ///< interrupt on complete mask for next TD
+
+  // must start from 128
+  ATTR_ALIGNED(64) tusb_control_request_t setup_request;
+
+  struct {
+    uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
+    uint16_t xferred_total;          ///< xferred bytes of the current transfer
+
+    uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
+  }current_td[DCD_11U_13U_QHD_COUNT];
+
+  uint8_t  class_code[DCD_11U_13U_QHD_COUNT]; ///< class where the endpoints belongs to TODO no need for control endpoints
+
+}dcd_11u_13u_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// CFG_TUSB_MEM_SECTION must have ATTR_ALIGNED(64) for lpc11u & lpc13u
+#ifdef __ICCARM__
+ATTR_ALIGNED(256) CFG_TUSB_MEM_SECTION // for IAR the first ATTR_ALIGNED takes effect
+#else
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) // GCC & Keil the last ATTR_ALIGNED takes effect
+#endif
+STATIC_VAR dcd_11u_13u_data_t dcd_data;
+
+static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint16_t addr_offset(void const * p_buffer)
+{
+  TU_ASSERT( (((uint32_t) p_buffer) & 0x3f) == 0, 0 );
+  return (uint16_t) ( (((uint32_t) p_buffer) >> 6 ) & 0xFFFF) ;
+}
+
+static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
+static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
+static void queue_xfer_in_next_td(uint8_t ep_id);
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+
+  LPC_USB->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  LPC_USB->DEVCMDSTAT |= dev_addr;
+}
+
+bool dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
+  LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS;
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
+                          CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+
+  NVIC_EnableIRQ(USB_IRQn);
+
+  return true;
+}
+
+static void bus_reset(void)
+{
+  tu_memclr(&dcd_data, sizeof(dcd_11u_13u_data_t));
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++)
+  { // disable all non-control endpoints on bus reset
+    dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 1;
+  }
+
+  dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
+
+  LPC_USB->EPINUSE      = 0;
+  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
+  LPC_USB->EPSKIP       = 0xFFFFFFFF;
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
+  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
+}
+
+static void endpoint_non_control_isr(uint32_t int_status)
+{
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
+  {
+    if ( BIT_TEST_(int_status, ep_id) )
+    {
+      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
+
+      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
+      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
+      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
+
+      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
+
+      // there are still data to transfer.
+      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+      { // NOTE although buff_addr_offset has been increased when xfer is completed
+        // but we still need to increase it one more as we are using double buffering.
+        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
+      }
+      // short packet or (no more byte and both buffers are finished)
+      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
+      { // current TD (request) is completed
+        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
+
+        dcd_data.current_td[ep_id].remaining_bytes = 0;
+
+        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+        {
+          edpt_hdl_t edpt_hdl =
+          {
+              .rhport     = 0,
+              .index      = ep_id,
+              .class_code = dcd_data.class_code[ep_id]
+          };
+
+          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+
+          // TODO no way determine if the transfer is failed or not
+          dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
+        }
+
+        //------------- Next TD is available -------------//
+        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+        {
+          queue_xfer_in_next_td(ep_id);
+        }
+      }else
+      {
+        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
+      }
+    }
+  }
+}
+
+static void endpoint_control_isr(uint32_t int_status)
+{
+  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
+
+  // there are still data to transfer.
+  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+  {
+    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
+  }else
+  {
+    dcd_data.current_td[ep_id].remaining_bytes = 0;
+
+    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+    {
+      edpt_hdl_t edpt_hdl = { .rhport = 0 };
+
+      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+
+      // FIXME xferred_byte for control xfer is not needed now !!!
+      dcd_xfer_complete(edpt_hdl, 0, true);
+    }
+  }
+}
+
+void hal_dcd_isr(uint8_t rhport)
+{
+  (void) rhport;
+
+  uint32_t const int_enable = LPC_USB->INTEN;
+  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
+  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
+
+  if (int_status == 0) return;
+
+  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
+
+  dcd_event_t event = { .rhport = rhport };
+
+  //------------- Device Status -------------//
+  if ( int_status & INT_MASK_DEVICE_STATUS )
+  {
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    {
+      bus_reset();
+
+      event.event_id = DCD_EVENT_BUS_RESET;
+      dcd_event_handler(&event, true);
+    }
+
+    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    { // device disconnect
+      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      { // debouncing as this can be set when device is powering
+        event.event_id = DCD_EVENT_UNPLUGGED;
+        dcd_event_handler(&event, true);
+      }
+    }
+
+    // TODO support suspend & resume
+    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    {
+      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
+      { // suspend signal, bus idle for more than 3ms
+        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+        {
+          event.event_id = DCD_EVENT_SUSPENDED;
+          dcd_event_handler(&event, true);
+        }
+      }
+    }
+//        else
+//      { // resume signal
+//        event.event_id = DCD_EVENT_RESUME;
+//        dcd_event_handler(&event, true);
+//      }
+//    }
+  }
+
+  //------------- Setup Received -------------//
+  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  { // received control request from host
+    // copy setup request & acknowledge so that the next setup can be received by hw
+    event.event_id = DCD_EVENT_SETUP_RECEIVED;
+    event.setup_received = dcd_data.setup_request;
+
+    dcd_event_handler(&event, true);
+
+    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
+    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
+
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
+  }
+  //------------- Control Endpoint -------------//
+  else if ( int_status & 0x03 )
+  {
+    endpoint_control_isr(int_status);
+  }
+
+  //------------- Non-Control Endpoints -------------//
+  if( int_status & ~(0x03UL) )
+  {
+    endpoint_non_control_isr(int_status);
+  }
+}
+
+//--------------------------------------------------------------------+
+// CONTROL PIPE API
+//--------------------------------------------------------------------+
+void dcd_control_stall(uint8_t rhport)
+{
+  (void) rhport;
+  // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
+  dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
+}
+
+bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
+{
+  (void) rhport;
+
+  // determine Endpoint where Data & Status phase occurred (IN or OUT)
+  uint8_t const ep_data   = (dir == TUSB_DIR_IN) ? 1 : 0;
+  uint8_t const ep_status = 1 - ep_data;
+
+  dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, ep_status) : BIT_CLR_(dcd_data.current_ioc, ep_status);
+
+  //------------- Data Phase -------------//
+  if (length)
+  {
+    dcd_data.current_td[ep_data].remaining_bytes = length;
+    dcd_data.current_td[ep_data].xferred_total   = 0;
+
+    queue_xfer_to_buffer(ep_data, 0, addr_offset(p_buffer), length);
+  }
+
+  //------------- Status Phase -------------//
+  dcd_data.current_td[ep_status].remaining_bytes = 0;
+  dcd_data.current_td[ep_status].xferred_total   = 0;
+
+  queue_xfer_to_buffer(ep_status, 0, 0, 0);
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// PIPE HELPER
+//--------------------------------------------------------------------+
+static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
+{
+  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
+}
+
+#if 0
+static inline uint8_t edpt_phy2log(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
+{
+  return physical_endpoint/2;
+}
+#endif
+
+//--------------------------------------------------------------------+
+// BULK/INTERRUPT/ISOCHRONOUS PIPE API
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
+{
+  dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
+}
+
+bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
+{
+  return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
+{
+  uint8_t ep_id = edpt_addr2phy(edpt_addr);
+//  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
+
+  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
+
+  // since the next transfer always take place on buffer0 --> clear buffer0 toggle
+  dcd_data.qhd[ep_id][0].toggle_reset    = 1;
+  dcd_data.qhd[ep_id][0].feedback_toggle = 0;
+
+  //------------- clear stall must carry on any previously queued transfer -------------//
+  if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+  {
+    queue_xfer_in_next_td(ep_id);
+  }
+}
+
+edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
+{
+  (void) rhport;
+  edpt_hdl_t const null_handle = { 0 };
+
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
+
+  TU_ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
+
+  // TODO prevent to open if endpoint size is not 64
+
+  //------------- Prepare Queue Head -------------//
+  uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
+
+  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened, normally this means running out of endpoints
+
+  tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
+  dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  dcd_data.class_code[ep_id] = class_code;
+
+  dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
+
+  LPC_USB->EPBUFCFG |= BIT_(ep_id);
+  LPC_USB->INTEN    |= BIT_(ep_id);
+
+  return (edpt_hdl_t)
+      {
+          .rhport     = 0,
+          .index      = ep_id,
+          .class_code = class_code
+      };
+}
+
+bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
+{
+  return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
+}
+
+static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
+{
+  uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
+
+  dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
+  dcd_data.current_td[ep_id].remaining_bytes               -= queued_bytes;
+
+  dcd_data.qhd[ep_id][buff_idx].buff_addr_offset            = buff_addr_offset;
+  dcd_data.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
+
+  dcd_data.qhd[ep_id][buff_idx].active = 1;
+}
+
+static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
+{
+  dcd_data.current_td[ep_id].remaining_bytes         = total_bytes;
+  dcd_data.current_td[ep_id].xferred_total           = 0;
+  dcd_data.current_td[ep_id].queued_bytes_in_buff[0] = 0;
+  dcd_data.current_td[ep_id].queued_bytes_in_buff[1] = 0;
+
+  LPC_USB->EPINUSE  = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
+
+  // need to queue buffer1 first, as activate buffer0 can causes controller does transferring immediately
+  // while buffer1 is not ready yet
+  if ( total_bytes > DCD_11U_13U_MAX_BYTE_PER_TD)
+  {
+    queue_xfer_to_buffer(ep_id, 1, buff_addr_offset+1, total_bytes - DCD_11U_13U_MAX_BYTE_PER_TD);
+  }
+
+  queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
+}
+
+static void queue_xfer_in_next_td(uint8_t ep_id)
+{
+  dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
+
+  pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
+
+  dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
+}
+
+tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
+{
+  TU_ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
+
+  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+
+  pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
+
+  return TUSB_ERROR_NONE;
+}
+
+tusb_error_t  dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
+{
+  if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
+  { // save this transfer data to next td if pipe is busy or already been stalled
+    dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
+    dcd_data.next_td[edpt_hdl.index].total_bytes      = total_bytes;
+
+    dcd_data.next_ioc = int_on_complete ? BIT_SET_(dcd_data.next_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.next_ioc, edpt_hdl.index);
+  }else
+  {
+    dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+
+    pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
+  }
+
+	return TUSB_ERROR_NONE;
+}
+
+#endif
+
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h b/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h
new file mode 100644
index 000000000..530fcd808
--- /dev/null
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h
@@ -0,0 +1,57 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc13xx_12adc.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+/** \ingroup group_dcd
+ *  \defgroup group_dcd_lpc11_13u LPC11uxx LPC13uxx
+ *  @{ */
+
+#ifndef _TUSB_DCD_LPC13XX_12ADC_H_
+#define _TUSB_DCD_LPC13XX_12ADC_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_DCD_LPC13XX_12ADC_H_ */
+
+/** @} */
diff --git a/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c b/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
deleted file mode 100644
index 029677e7c..000000000
--- a/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.c
+++ /dev/null
@@ -1,579 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc_11uxx_13uxx.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
-
-#define _TINY_USB_SOURCE_FILE_
-
-// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
-// endpoint's max packet size and need some soft DMA helper
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "hal/hal.h"
-#include "osal/osal.h"
-
-#include "device/dcd.h"
-#include "usbd_dcd.h"
-#include "dcd_lpc_11uxx_13uxx.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-#define DCD_11U_13U_QHD_COUNT 10
-
-enum {
-  DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
-};
-
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
-enum {
-  INT_MASK_SOF           = BIT_(30),
-  INT_MASK_DEVICE_STATUS = BIT_(31)
-};
-
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
-enum {
-  CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
-  CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
-  CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16), ///< reflect the softconnect only, does not reflect the actual attached state
-  CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
-  CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
-  CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
-  CMDSTAT_RESET_CHANGE_MASK   = BIT_(26),
-  CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
-};
-
-// buffer input must be 64 byte alignment
-typedef struct ATTR_PACKED
-{
-  volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
-
-  volatile uint16_t nbytes      : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
-  uint16_t is_isochronous       : 1  ;
-  uint16_t feedback_toggle      : 1  ; ///< For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero. For the control endpoint zero this bit is used as the toggle value. When the toggle reset bit is set, the data toggle is updated with the value programmed in this bit. When the endpoint is used as an interrupt endpoint, it can be set to the following values. 0: Interrupt endpoint in ‘toggle mode’ 1: Interrupt endpoint in ‘rate feedback mode’. This means that the data toggle is fixed to zero for all data packets. When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to zero.
-  uint16_t toggle_reset         : 1  ; ///< When software sets this bit to one, the HW will set the toggle value equal to the value indicated in the “toggle value” (TV) bit. For the control endpoint zero, this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received. For the other endpoints, the toggle can only be reset to zero when the endpoint is reset.
-  uint16_t stall                : 1  ; ///< 0: The selected endpoint is not stalled 1: The selected endpoint is stalled The Active bit has always higher priority than the Stall bit. This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one. Software can only modify this bit when the active bit is zero.
-  uint16_t disable              : 1  ; ///< 0: The selected endpoint is enabled. 1: The selected endpoint is disabled. If a USB token is received for an endpoint that has the disabled bit set, hardware will ignore the token and not return any data or handshake. When a bus reset is received, software must set the disable bit of all endpoints to 1. Software can only modify this bit when the active bit is zero.
-  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
-}dcd_11u_13u_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
-
-// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
-// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
-// next_td stored the 2nd request information
-// current_td is used to keep track of number of remaining & xferred bytes of the current request.
-// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
-
-typedef struct {
-  dcd_11u_13u_qhd_t qhd[DCD_11U_13U_QHD_COUNT][2]; ///< must be 256 byte alignment, 2 for double buffer
-
-  // start at 80, the size should not exceed 48 (for setup_request align at 128)
-  struct {
-    uint16_t buff_addr_offset;
-    uint16_t total_bytes;
-  }next_td[DCD_11U_13U_QHD_COUNT];
-
-  uint32_t current_ioc;          ///< interrupt on complete mask for current TD
-  uint32_t next_ioc;             ///< interrupt on complete mask for next TD
-
-  // must start from 128
-  ATTR_ALIGNED(64) tusb_control_request_t setup_request;
-
-  struct {
-    uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
-    uint16_t xferred_total;          ///< xferred bytes of the current transfer
-
-    uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
-  }current_td[DCD_11U_13U_QHD_COUNT];
-
-  uint8_t  class_code[DCD_11U_13U_QHD_COUNT]; ///< class where the endpoints belongs to TODO no need for control endpoints
-
-}dcd_11u_13u_data_t;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-// CFG_TUSB_MEM_SECTION must have ATTR_ALIGNED(64) for lpc11u & lpc13u
-#ifdef __ICCARM__
-ATTR_ALIGNED(256) CFG_TUSB_MEM_SECTION // for IAR the first ATTR_ALIGNED takes effect
-#else
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) // GCC & Keil the last ATTR_ALIGNED takes effect
-#endif
-STATIC_VAR dcd_11u_13u_data_t dcd_data;
-
-static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint16_t addr_offset(void const * p_buffer)
-{
-  TU_ASSERT( (((uint32_t) p_buffer) & 0x3f) == 0, 0 );
-  return (uint16_t) ( (((uint32_t) p_buffer) >> 6 ) & 0xFFFF) ;
-}
-
-static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
-static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
-static void queue_xfer_in_next_td(uint8_t ep_id);
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-
-  LPC_USB->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
-  LPC_USB->DEVCMDSTAT |= dev_addr;
-}
-
-bool dcd_init(uint8_t rhport)
-{
-  (void) rhport;
-
-  LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
-  LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS;
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
-                          CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-
-  NVIC_EnableIRQ(USB_IRQn);
-
-  return true;
-}
-
-static void bus_reset(void)
-{
-  tu_memclr(&dcd_data, sizeof(dcd_11u_13u_data_t));
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++)
-  { // disable all non-control endpoints on bus reset
-    dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 1;
-  }
-
-  dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
-
-  LPC_USB->EPINUSE      = 0;
-  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
-  LPC_USB->EPSKIP       = 0xFFFFFFFF;
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
-  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
-}
-
-static void endpoint_non_control_isr(uint32_t int_status)
-{
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
-  {
-    if ( BIT_TEST_(int_status, ep_id) )
-    {
-      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
-
-      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
-      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
-      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
-
-      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
-
-      // there are still data to transfer.
-      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
-      { // NOTE although buff_addr_offset has been increased when xfer is completed
-        // but we still need to increase it one more as we are using double buffering.
-        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
-      }
-      // short packet or (no more byte and both buffers are finished)
-      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
-      { // current TD (request) is completed
-        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
-
-        dcd_data.current_td[ep_id].remaining_bytes = 0;
-
-        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
-        {
-          edpt_hdl_t edpt_hdl =
-          {
-              .rhport     = 0,
-              .index      = ep_id,
-              .class_code = dcd_data.class_code[ep_id]
-          };
-
-          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
-
-          // TODO no way determine if the transfer is failed or not
-          dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
-        }
-
-        //------------- Next TD is available -------------//
-        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
-        {
-          queue_xfer_in_next_td(ep_id);
-        }
-      }else
-      {
-        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
-      }
-    }
-  }
-}
-
-static void endpoint_control_isr(uint32_t int_status)
-{
-  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
-
-  // there are still data to transfer.
-  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
-  {
-    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
-  }else
-  {
-    dcd_data.current_td[ep_id].remaining_bytes = 0;
-
-    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
-    {
-      edpt_hdl_t edpt_hdl = { .rhport = 0 };
-
-      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
-
-      // FIXME xferred_byte for control xfer is not needed now !!!
-      dcd_xfer_complete(edpt_hdl, 0, true);
-    }
-  }
-}
-
-void hal_dcd_isr(uint8_t rhport)
-{
-  (void) rhport;
-
-  uint32_t const int_enable = LPC_USB->INTEN;
-  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
-  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;
-
-  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
-
-  dcd_event_t event = { .rhport = rhport };
-
-  //------------- Device Status -------------//
-  if ( int_status & INT_MASK_DEVICE_STATUS )
-  {
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
-    {
-      bus_reset();
-
-      event.event_id = DCD_EVENT_BUS_RESET;
-      dcd_event_handler(&event, true);
-    }
-
-    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
-    { // device disconnect
-      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-      { // debouncing as this can be set when device is powering
-        event.event_id = DCD_EVENT_UNPLUGGED;
-        dcd_event_handler(&event, true);
-      }
-    }
-
-    // TODO support suspend & resume
-    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
-    {
-      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
-      { // suspend signal, bus idle for more than 3ms
-        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-        {
-          event.event_id = DCD_EVENT_SUSPENDED;
-          dcd_event_handler(&event, true);
-        }
-      }
-    }
-//        else
-//      { // resume signal
-//        event.event_id = DCD_EVENT_RESUME;
-//        dcd_event_handler(&event, true);
-//      }
-//    }
-  }
-
-  //------------- Setup Received -------------//
-  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
-  { // received control request from host
-    // copy setup request & acknowledge so that the next setup can be received by hw
-    event.event_id = DCD_EVENT_SETUP_RECEIVED;
-    event.setup_received = dcd_data.setup_request;
-
-    dcd_event_handler(&event, true);
-
-    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
-    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
-
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
-    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
-  }
-  //------------- Control Endpoint -------------//
-  else if ( int_status & 0x03 )
-  {
-    endpoint_control_isr(int_status);
-  }
-
-  //------------- Non-Control Endpoints -------------//
-  if( int_status & ~(0x03UL) )
-  {
-    endpoint_non_control_isr(int_status);
-  }
-}
-
-//--------------------------------------------------------------------+
-// CONTROL PIPE API
-//--------------------------------------------------------------------+
-void dcd_control_stall(uint8_t rhport)
-{
-  (void) rhport;
-  // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
-  dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
-}
-
-bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
-{
-  (void) rhport;
-
-  // determine Endpoint where Data & Status phase occurred (IN or OUT)
-  uint8_t const ep_data   = (dir == TUSB_DIR_IN) ? 1 : 0;
-  uint8_t const ep_status = 1 - ep_data;
-
-  dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, ep_status) : BIT_CLR_(dcd_data.current_ioc, ep_status);
-
-  //------------- Data Phase -------------//
-  if (length)
-  {
-    dcd_data.current_td[ep_data].remaining_bytes = length;
-    dcd_data.current_td[ep_data].xferred_total   = 0;
-
-    queue_xfer_to_buffer(ep_data, 0, addr_offset(p_buffer), length);
-  }
-
-  //------------- Status Phase -------------//
-  dcd_data.current_td[ep_status].remaining_bytes = 0;
-  dcd_data.current_td[ep_status].xferred_total   = 0;
-
-  queue_xfer_to_buffer(ep_status, 0, 0, 0);
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// PIPE HELPER
-//--------------------------------------------------------------------+
-static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
-{
-  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
-}
-
-#if 0
-static inline uint8_t edpt_phy2log(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
-{
-  return physical_endpoint/2;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// BULK/INTERRUPT/ISOCHRONOUS PIPE API
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
-{
-  dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
-}
-
-bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
-{
-  return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
-{
-  uint8_t ep_id = edpt_addr2phy(edpt_addr);
-//  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
-
-  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
-
-  // since the next transfer always take place on buffer0 --> clear buffer0 toggle
-  dcd_data.qhd[ep_id][0].toggle_reset    = 1;
-  dcd_data.qhd[ep_id][0].feedback_toggle = 0;
-
-  //------------- clear stall must carry on any previously queued transfer -------------//
-  if ( dcd_data.next_td[ep_id].total_bytes != 0 )
-  {
-    queue_xfer_in_next_td(ep_id);
-  }
-}
-
-edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
-{
-  (void) rhport;
-  edpt_hdl_t const null_handle = { 0 };
-
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
-
-  TU_ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
-
-  // TODO prevent to open if endpoint size is not 64
-
-  //------------- Prepare Queue Head -------------//
-  uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
-
-  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened, normally this means running out of endpoints
-
-  tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
-  dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
-  dcd_data.class_code[ep_id] = class_code;
-
-  dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
-
-  LPC_USB->EPBUFCFG |= BIT_(ep_id);
-  LPC_USB->INTEN    |= BIT_(ep_id);
-
-  return (edpt_hdl_t)
-      {
-          .rhport     = 0,
-          .index      = ep_id,
-          .class_code = class_code
-      };
-}
-
-bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
-{
-  return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
-}
-
-static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
-{
-  uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
-
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
-  dcd_data.current_td[ep_id].remaining_bytes               -= queued_bytes;
-
-  dcd_data.qhd[ep_id][buff_idx].buff_addr_offset            = buff_addr_offset;
-  dcd_data.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
-
-  dcd_data.qhd[ep_id][buff_idx].active = 1;
-}
-
-static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
-{
-  dcd_data.current_td[ep_id].remaining_bytes         = total_bytes;
-  dcd_data.current_td[ep_id].xferred_total           = 0;
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[0] = 0;
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[1] = 0;
-
-  LPC_USB->EPINUSE  = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
-
-  // need to queue buffer1 first, as activate buffer0 can causes controller does transferring immediately
-  // while buffer1 is not ready yet
-  if ( total_bytes > DCD_11U_13U_MAX_BYTE_PER_TD)
-  {
-    queue_xfer_to_buffer(ep_id, 1, buff_addr_offset+1, total_bytes - DCD_11U_13U_MAX_BYTE_PER_TD);
-  }
-
-  queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
-}
-
-static void queue_xfer_in_next_td(uint8_t ep_id)
-{
-  dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
-
-  pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
-
-  dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
-}
-
-tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
-{
-  TU_ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
-
-  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
-
-  pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
-
-  return TUSB_ERROR_NONE;
-}
-
-tusb_error_t  dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
-{
-  if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
-  { // save this transfer data to next td if pipe is busy or already been stalled
-    dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
-    dcd_data.next_td[edpt_hdl.index].total_bytes      = total_bytes;
-
-    dcd_data.next_ioc = int_on_complete ? BIT_SET_(dcd_data.next_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.next_ioc, edpt_hdl.index);
-  }else
-  {
-    dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
-
-    pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
-  }
-
-	return TUSB_ERROR_NONE;
-}
-
-#endif
-
diff --git a/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.h b/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.h
deleted file mode 100644
index 530fcd808..000000000
--- a/src/portable/nxp/lpc11xx_lpc13xx/dcd_lpc_11uxx_13uxx.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc13xx_12adc.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc11_13u LPC11uxx LPC13uxx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC13XX_12ADC_H_
-#define _TUSB_DCD_LPC13XX_12ADC_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC13XX_12ADC_H_ */
-
-/** @} */
-- 
cgit v1.3.1


From 0ab62e6fa248a7e2f613743515bcd54c72c47ef5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 12:57:44 +0700
Subject: more rename

---
 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h     |  57 ++
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c    | 579 +++++++++++++++++++++
 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c | 579 ---------------------
 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h |  57 --
 4 files changed, 636 insertions(+), 636 deletions(-)
 create mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h
 create mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
 delete mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c
 delete mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h

(limited to 'src')

diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h
new file mode 100644
index 000000000..530fcd808
--- /dev/null
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h
@@ -0,0 +1,57 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc13xx_12adc.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+/** \ingroup group_dcd
+ *  \defgroup group_dcd_lpc11_13u LPC11uxx LPC13uxx
+ *  @{ */
+
+#ifndef _TUSB_DCD_LPC13XX_12ADC_H_
+#define _TUSB_DCD_LPC13XX_12ADC_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_DCD_LPC13XX_12ADC_H_ */
+
+/** @} */
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
new file mode 100644
index 000000000..029677e7c
--- /dev/null
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -0,0 +1,579 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc_11uxx_13uxx.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
+
+#define _TINY_USB_SOURCE_FILE_
+
+// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
+// endpoint's max packet size and need some soft DMA helper
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "hal/hal.h"
+#include "osal/osal.h"
+
+#include "device/dcd.h"
+#include "usbd_dcd.h"
+#include "dcd_lpc_11uxx_13uxx.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+#define DCD_11U_13U_QHD_COUNT 10
+
+enum {
+  DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
+};
+
+#ifdef __CC_ARM
+#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
+#endif
+
+enum {
+  INT_MASK_SOF           = BIT_(30),
+  INT_MASK_DEVICE_STATUS = BIT_(31)
+};
+
+#ifdef __CC_ARM
+#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
+#endif
+
+enum {
+  CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
+  CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
+  CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
+  CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16), ///< reflect the softconnect only, does not reflect the actual attached state
+  CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
+  CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
+  CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
+  CMDSTAT_RESET_CHANGE_MASK   = BIT_(26),
+  CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
+};
+
+// buffer input must be 64 byte alignment
+typedef struct ATTR_PACKED
+{
+  volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
+
+  volatile uint16_t nbytes      : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
+  uint16_t is_isochronous       : 1  ;
+  uint16_t feedback_toggle      : 1  ; ///< For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero. For the control endpoint zero this bit is used as the toggle value. When the toggle reset bit is set, the data toggle is updated with the value programmed in this bit. When the endpoint is used as an interrupt endpoint, it can be set to the following values. 0: Interrupt endpoint in ‘toggle mode’ 1: Interrupt endpoint in ‘rate feedback mode’. This means that the data toggle is fixed to zero for all data packets. When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to zero.
+  uint16_t toggle_reset         : 1  ; ///< When software sets this bit to one, the HW will set the toggle value equal to the value indicated in the “toggle value” (TV) bit. For the control endpoint zero, this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received. For the other endpoints, the toggle can only be reset to zero when the endpoint is reset.
+  uint16_t stall                : 1  ; ///< 0: The selected endpoint is not stalled 1: The selected endpoint is stalled The Active bit has always higher priority than the Stall bit. This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one. Software can only modify this bit when the active bit is zero.
+  uint16_t disable              : 1  ; ///< 0: The selected endpoint is enabled. 1: The selected endpoint is disabled. If a USB token is received for an endpoint that has the disabled bit set, hardware will ignore the token and not return any data or handshake. When a bus reset is received, software must set the disable bit of all endpoints to 1. Software can only modify this bit when the active bit is zero.
+  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
+}dcd_11u_13u_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
+
+// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
+// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
+// next_td stored the 2nd request information
+// current_td is used to keep track of number of remaining & xferred bytes of the current request.
+// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
+
+typedef struct {
+  dcd_11u_13u_qhd_t qhd[DCD_11U_13U_QHD_COUNT][2]; ///< must be 256 byte alignment, 2 for double buffer
+
+  // start at 80, the size should not exceed 48 (for setup_request align at 128)
+  struct {
+    uint16_t buff_addr_offset;
+    uint16_t total_bytes;
+  }next_td[DCD_11U_13U_QHD_COUNT];
+
+  uint32_t current_ioc;          ///< interrupt on complete mask for current TD
+  uint32_t next_ioc;             ///< interrupt on complete mask for next TD
+
+  // must start from 128
+  ATTR_ALIGNED(64) tusb_control_request_t setup_request;
+
+  struct {
+    uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
+    uint16_t xferred_total;          ///< xferred bytes of the current transfer
+
+    uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
+  }current_td[DCD_11U_13U_QHD_COUNT];
+
+  uint8_t  class_code[DCD_11U_13U_QHD_COUNT]; ///< class where the endpoints belongs to TODO no need for control endpoints
+
+}dcd_11u_13u_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// CFG_TUSB_MEM_SECTION must have ATTR_ALIGNED(64) for lpc11u & lpc13u
+#ifdef __ICCARM__
+ATTR_ALIGNED(256) CFG_TUSB_MEM_SECTION // for IAR the first ATTR_ALIGNED takes effect
+#else
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) // GCC & Keil the last ATTR_ALIGNED takes effect
+#endif
+STATIC_VAR dcd_11u_13u_data_t dcd_data;
+
+static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint16_t addr_offset(void const * p_buffer)
+{
+  TU_ASSERT( (((uint32_t) p_buffer) & 0x3f) == 0, 0 );
+  return (uint16_t) ( (((uint32_t) p_buffer) >> 6 ) & 0xFFFF) ;
+}
+
+static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
+static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
+static void queue_xfer_in_next_td(uint8_t ep_id);
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+
+  LPC_USB->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  LPC_USB->DEVCMDSTAT |= dev_addr;
+}
+
+bool dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
+  LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS;
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
+                          CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+
+  NVIC_EnableIRQ(USB_IRQn);
+
+  return true;
+}
+
+static void bus_reset(void)
+{
+  tu_memclr(&dcd_data, sizeof(dcd_11u_13u_data_t));
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++)
+  { // disable all non-control endpoints on bus reset
+    dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 1;
+  }
+
+  dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
+
+  LPC_USB->EPINUSE      = 0;
+  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
+  LPC_USB->EPSKIP       = 0xFFFFFFFF;
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
+  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
+}
+
+static void endpoint_non_control_isr(uint32_t int_status)
+{
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
+  {
+    if ( BIT_TEST_(int_status, ep_id) )
+    {
+      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
+
+      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
+      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
+      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
+
+      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
+
+      // there are still data to transfer.
+      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+      { // NOTE although buff_addr_offset has been increased when xfer is completed
+        // but we still need to increase it one more as we are using double buffering.
+        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
+      }
+      // short packet or (no more byte and both buffers are finished)
+      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
+      { // current TD (request) is completed
+        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
+
+        dcd_data.current_td[ep_id].remaining_bytes = 0;
+
+        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+        {
+          edpt_hdl_t edpt_hdl =
+          {
+              .rhport     = 0,
+              .index      = ep_id,
+              .class_code = dcd_data.class_code[ep_id]
+          };
+
+          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+
+          // TODO no way determine if the transfer is failed or not
+          dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
+        }
+
+        //------------- Next TD is available -------------//
+        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+        {
+          queue_xfer_in_next_td(ep_id);
+        }
+      }else
+      {
+        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
+      }
+    }
+  }
+}
+
+static void endpoint_control_isr(uint32_t int_status)
+{
+  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
+
+  // there are still data to transfer.
+  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+  {
+    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
+  }else
+  {
+    dcd_data.current_td[ep_id].remaining_bytes = 0;
+
+    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+    {
+      edpt_hdl_t edpt_hdl = { .rhport = 0 };
+
+      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+
+      // FIXME xferred_byte for control xfer is not needed now !!!
+      dcd_xfer_complete(edpt_hdl, 0, true);
+    }
+  }
+}
+
+void hal_dcd_isr(uint8_t rhport)
+{
+  (void) rhport;
+
+  uint32_t const int_enable = LPC_USB->INTEN;
+  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
+  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
+
+  if (int_status == 0) return;
+
+  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
+
+  dcd_event_t event = { .rhport = rhport };
+
+  //------------- Device Status -------------//
+  if ( int_status & INT_MASK_DEVICE_STATUS )
+  {
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    {
+      bus_reset();
+
+      event.event_id = DCD_EVENT_BUS_RESET;
+      dcd_event_handler(&event, true);
+    }
+
+    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    { // device disconnect
+      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      { // debouncing as this can be set when device is powering
+        event.event_id = DCD_EVENT_UNPLUGGED;
+        dcd_event_handler(&event, true);
+      }
+    }
+
+    // TODO support suspend & resume
+    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    {
+      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
+      { // suspend signal, bus idle for more than 3ms
+        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+        {
+          event.event_id = DCD_EVENT_SUSPENDED;
+          dcd_event_handler(&event, true);
+        }
+      }
+    }
+//        else
+//      { // resume signal
+//        event.event_id = DCD_EVENT_RESUME;
+//        dcd_event_handler(&event, true);
+//      }
+//    }
+  }
+
+  //------------- Setup Received -------------//
+  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  { // received control request from host
+    // copy setup request & acknowledge so that the next setup can be received by hw
+    event.event_id = DCD_EVENT_SETUP_RECEIVED;
+    event.setup_received = dcd_data.setup_request;
+
+    dcd_event_handler(&event, true);
+
+    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
+    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
+
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
+  }
+  //------------- Control Endpoint -------------//
+  else if ( int_status & 0x03 )
+  {
+    endpoint_control_isr(int_status);
+  }
+
+  //------------- Non-Control Endpoints -------------//
+  if( int_status & ~(0x03UL) )
+  {
+    endpoint_non_control_isr(int_status);
+  }
+}
+
+//--------------------------------------------------------------------+
+// CONTROL PIPE API
+//--------------------------------------------------------------------+
+void dcd_control_stall(uint8_t rhport)
+{
+  (void) rhport;
+  // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
+  dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
+}
+
+bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
+{
+  (void) rhport;
+
+  // determine Endpoint where Data & Status phase occurred (IN or OUT)
+  uint8_t const ep_data   = (dir == TUSB_DIR_IN) ? 1 : 0;
+  uint8_t const ep_status = 1 - ep_data;
+
+  dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, ep_status) : BIT_CLR_(dcd_data.current_ioc, ep_status);
+
+  //------------- Data Phase -------------//
+  if (length)
+  {
+    dcd_data.current_td[ep_data].remaining_bytes = length;
+    dcd_data.current_td[ep_data].xferred_total   = 0;
+
+    queue_xfer_to_buffer(ep_data, 0, addr_offset(p_buffer), length);
+  }
+
+  //------------- Status Phase -------------//
+  dcd_data.current_td[ep_status].remaining_bytes = 0;
+  dcd_data.current_td[ep_status].xferred_total   = 0;
+
+  queue_xfer_to_buffer(ep_status, 0, 0, 0);
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// PIPE HELPER
+//--------------------------------------------------------------------+
+static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
+{
+  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
+}
+
+#if 0
+static inline uint8_t edpt_phy2log(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
+{
+  return physical_endpoint/2;
+}
+#endif
+
+//--------------------------------------------------------------------+
+// BULK/INTERRUPT/ISOCHRONOUS PIPE API
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
+{
+  dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
+}
+
+bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
+{
+  return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
+{
+  uint8_t ep_id = edpt_addr2phy(edpt_addr);
+//  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
+
+  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
+
+  // since the next transfer always take place on buffer0 --> clear buffer0 toggle
+  dcd_data.qhd[ep_id][0].toggle_reset    = 1;
+  dcd_data.qhd[ep_id][0].feedback_toggle = 0;
+
+  //------------- clear stall must carry on any previously queued transfer -------------//
+  if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+  {
+    queue_xfer_in_next_td(ep_id);
+  }
+}
+
+edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
+{
+  (void) rhport;
+  edpt_hdl_t const null_handle = { 0 };
+
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
+
+  TU_ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
+
+  // TODO prevent to open if endpoint size is not 64
+
+  //------------- Prepare Queue Head -------------//
+  uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
+
+  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened, normally this means running out of endpoints
+
+  tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
+  dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  dcd_data.class_code[ep_id] = class_code;
+
+  dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
+
+  LPC_USB->EPBUFCFG |= BIT_(ep_id);
+  LPC_USB->INTEN    |= BIT_(ep_id);
+
+  return (edpt_hdl_t)
+      {
+          .rhport     = 0,
+          .index      = ep_id,
+          .class_code = class_code
+      };
+}
+
+bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
+{
+  return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
+}
+
+static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
+{
+  uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
+
+  dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
+  dcd_data.current_td[ep_id].remaining_bytes               -= queued_bytes;
+
+  dcd_data.qhd[ep_id][buff_idx].buff_addr_offset            = buff_addr_offset;
+  dcd_data.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
+
+  dcd_data.qhd[ep_id][buff_idx].active = 1;
+}
+
+static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
+{
+  dcd_data.current_td[ep_id].remaining_bytes         = total_bytes;
+  dcd_data.current_td[ep_id].xferred_total           = 0;
+  dcd_data.current_td[ep_id].queued_bytes_in_buff[0] = 0;
+  dcd_data.current_td[ep_id].queued_bytes_in_buff[1] = 0;
+
+  LPC_USB->EPINUSE  = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
+
+  // need to queue buffer1 first, as activate buffer0 can causes controller does transferring immediately
+  // while buffer1 is not ready yet
+  if ( total_bytes > DCD_11U_13U_MAX_BYTE_PER_TD)
+  {
+    queue_xfer_to_buffer(ep_id, 1, buff_addr_offset+1, total_bytes - DCD_11U_13U_MAX_BYTE_PER_TD);
+  }
+
+  queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
+}
+
+static void queue_xfer_in_next_td(uint8_t ep_id)
+{
+  dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
+
+  pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
+
+  dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
+}
+
+tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
+{
+  TU_ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
+
+  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+
+  pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
+
+  return TUSB_ERROR_NONE;
+}
+
+tusb_error_t  dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
+{
+  if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
+  { // save this transfer data to next td if pipe is busy or already been stalled
+    dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
+    dcd_data.next_td[edpt_hdl.index].total_bytes      = total_bytes;
+
+    dcd_data.next_ioc = int_on_complete ? BIT_SET_(dcd_data.next_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.next_ioc, edpt_hdl.index);
+  }else
+  {
+    dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+
+    pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
+  }
+
+	return TUSB_ERROR_NONE;
+}
+
+#endif
+
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c
deleted file mode 100644
index 029677e7c..000000000
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.c
+++ /dev/null
@@ -1,579 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc_11uxx_13uxx.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
-
-#define _TINY_USB_SOURCE_FILE_
-
-// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
-// endpoint's max packet size and need some soft DMA helper
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "hal/hal.h"
-#include "osal/osal.h"
-
-#include "device/dcd.h"
-#include "usbd_dcd.h"
-#include "dcd_lpc_11uxx_13uxx.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-#define DCD_11U_13U_QHD_COUNT 10
-
-enum {
-  DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
-};
-
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
-enum {
-  INT_MASK_SOF           = BIT_(30),
-  INT_MASK_DEVICE_STATUS = BIT_(31)
-};
-
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
-enum {
-  CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
-  CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
-  CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16), ///< reflect the softconnect only, does not reflect the actual attached state
-  CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
-  CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
-  CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
-  CMDSTAT_RESET_CHANGE_MASK   = BIT_(26),
-  CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
-};
-
-// buffer input must be 64 byte alignment
-typedef struct ATTR_PACKED
-{
-  volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
-
-  volatile uint16_t nbytes      : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
-  uint16_t is_isochronous       : 1  ;
-  uint16_t feedback_toggle      : 1  ; ///< For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero. For the control endpoint zero this bit is used as the toggle value. When the toggle reset bit is set, the data toggle is updated with the value programmed in this bit. When the endpoint is used as an interrupt endpoint, it can be set to the following values. 0: Interrupt endpoint in ‘toggle mode’ 1: Interrupt endpoint in ‘rate feedback mode’. This means that the data toggle is fixed to zero for all data packets. When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to zero.
-  uint16_t toggle_reset         : 1  ; ///< When software sets this bit to one, the HW will set the toggle value equal to the value indicated in the “toggle value” (TV) bit. For the control endpoint zero, this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received. For the other endpoints, the toggle can only be reset to zero when the endpoint is reset.
-  uint16_t stall                : 1  ; ///< 0: The selected endpoint is not stalled 1: The selected endpoint is stalled The Active bit has always higher priority than the Stall bit. This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one. Software can only modify this bit when the active bit is zero.
-  uint16_t disable              : 1  ; ///< 0: The selected endpoint is enabled. 1: The selected endpoint is disabled. If a USB token is received for an endpoint that has the disabled bit set, hardware will ignore the token and not return any data or handshake. When a bus reset is received, software must set the disable bit of all endpoints to 1. Software can only modify this bit when the active bit is zero.
-  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
-}dcd_11u_13u_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
-
-// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
-// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
-// next_td stored the 2nd request information
-// current_td is used to keep track of number of remaining & xferred bytes of the current request.
-// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
-
-typedef struct {
-  dcd_11u_13u_qhd_t qhd[DCD_11U_13U_QHD_COUNT][2]; ///< must be 256 byte alignment, 2 for double buffer
-
-  // start at 80, the size should not exceed 48 (for setup_request align at 128)
-  struct {
-    uint16_t buff_addr_offset;
-    uint16_t total_bytes;
-  }next_td[DCD_11U_13U_QHD_COUNT];
-
-  uint32_t current_ioc;          ///< interrupt on complete mask for current TD
-  uint32_t next_ioc;             ///< interrupt on complete mask for next TD
-
-  // must start from 128
-  ATTR_ALIGNED(64) tusb_control_request_t setup_request;
-
-  struct {
-    uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
-    uint16_t xferred_total;          ///< xferred bytes of the current transfer
-
-    uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
-  }current_td[DCD_11U_13U_QHD_COUNT];
-
-  uint8_t  class_code[DCD_11U_13U_QHD_COUNT]; ///< class where the endpoints belongs to TODO no need for control endpoints
-
-}dcd_11u_13u_data_t;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-// CFG_TUSB_MEM_SECTION must have ATTR_ALIGNED(64) for lpc11u & lpc13u
-#ifdef __ICCARM__
-ATTR_ALIGNED(256) CFG_TUSB_MEM_SECTION // for IAR the first ATTR_ALIGNED takes effect
-#else
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) // GCC & Keil the last ATTR_ALIGNED takes effect
-#endif
-STATIC_VAR dcd_11u_13u_data_t dcd_data;
-
-static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint16_t addr_offset(void const * p_buffer)
-{
-  TU_ASSERT( (((uint32_t) p_buffer) & 0x3f) == 0, 0 );
-  return (uint16_t) ( (((uint32_t) p_buffer) >> 6 ) & 0xFFFF) ;
-}
-
-static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
-static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
-static void queue_xfer_in_next_td(uint8_t ep_id);
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-
-  LPC_USB->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
-  LPC_USB->DEVCMDSTAT |= dev_addr;
-}
-
-bool dcd_init(uint8_t rhport)
-{
-  (void) rhport;
-
-  LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
-  LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS;
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
-                          CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-
-  NVIC_EnableIRQ(USB_IRQn);
-
-  return true;
-}
-
-static void bus_reset(void)
-{
-  tu_memclr(&dcd_data, sizeof(dcd_11u_13u_data_t));
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++)
-  { // disable all non-control endpoints on bus reset
-    dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 1;
-  }
-
-  dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
-
-  LPC_USB->EPINUSE      = 0;
-  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
-  LPC_USB->EPSKIP       = 0xFFFFFFFF;
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
-  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
-}
-
-static void endpoint_non_control_isr(uint32_t int_status)
-{
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
-  {
-    if ( BIT_TEST_(int_status, ep_id) )
-    {
-      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
-
-      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
-      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
-      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
-
-      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
-
-      // there are still data to transfer.
-      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
-      { // NOTE although buff_addr_offset has been increased when xfer is completed
-        // but we still need to increase it one more as we are using double buffering.
-        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
-      }
-      // short packet or (no more byte and both buffers are finished)
-      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
-      { // current TD (request) is completed
-        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
-
-        dcd_data.current_td[ep_id].remaining_bytes = 0;
-
-        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
-        {
-          edpt_hdl_t edpt_hdl =
-          {
-              .rhport     = 0,
-              .index      = ep_id,
-              .class_code = dcd_data.class_code[ep_id]
-          };
-
-          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
-
-          // TODO no way determine if the transfer is failed or not
-          dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
-        }
-
-        //------------- Next TD is available -------------//
-        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
-        {
-          queue_xfer_in_next_td(ep_id);
-        }
-      }else
-      {
-        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
-      }
-    }
-  }
-}
-
-static void endpoint_control_isr(uint32_t int_status)
-{
-  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
-
-  // there are still data to transfer.
-  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
-  {
-    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
-  }else
-  {
-    dcd_data.current_td[ep_id].remaining_bytes = 0;
-
-    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
-    {
-      edpt_hdl_t edpt_hdl = { .rhport = 0 };
-
-      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
-
-      // FIXME xferred_byte for control xfer is not needed now !!!
-      dcd_xfer_complete(edpt_hdl, 0, true);
-    }
-  }
-}
-
-void hal_dcd_isr(uint8_t rhport)
-{
-  (void) rhport;
-
-  uint32_t const int_enable = LPC_USB->INTEN;
-  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
-  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;
-
-  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
-
-  dcd_event_t event = { .rhport = rhport };
-
-  //------------- Device Status -------------//
-  if ( int_status & INT_MASK_DEVICE_STATUS )
-  {
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
-    {
-      bus_reset();
-
-      event.event_id = DCD_EVENT_BUS_RESET;
-      dcd_event_handler(&event, true);
-    }
-
-    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
-    { // device disconnect
-      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-      { // debouncing as this can be set when device is powering
-        event.event_id = DCD_EVENT_UNPLUGGED;
-        dcd_event_handler(&event, true);
-      }
-    }
-
-    // TODO support suspend & resume
-    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
-    {
-      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
-      { // suspend signal, bus idle for more than 3ms
-        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-        {
-          event.event_id = DCD_EVENT_SUSPENDED;
-          dcd_event_handler(&event, true);
-        }
-      }
-    }
-//        else
-//      { // resume signal
-//        event.event_id = DCD_EVENT_RESUME;
-//        dcd_event_handler(&event, true);
-//      }
-//    }
-  }
-
-  //------------- Setup Received -------------//
-  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
-  { // received control request from host
-    // copy setup request & acknowledge so that the next setup can be received by hw
-    event.event_id = DCD_EVENT_SETUP_RECEIVED;
-    event.setup_received = dcd_data.setup_request;
-
-    dcd_event_handler(&event, true);
-
-    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
-    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
-
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
-    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
-  }
-  //------------- Control Endpoint -------------//
-  else if ( int_status & 0x03 )
-  {
-    endpoint_control_isr(int_status);
-  }
-
-  //------------- Non-Control Endpoints -------------//
-  if( int_status & ~(0x03UL) )
-  {
-    endpoint_non_control_isr(int_status);
-  }
-}
-
-//--------------------------------------------------------------------+
-// CONTROL PIPE API
-//--------------------------------------------------------------------+
-void dcd_control_stall(uint8_t rhport)
-{
-  (void) rhport;
-  // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
-  dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
-}
-
-bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
-{
-  (void) rhport;
-
-  // determine Endpoint where Data & Status phase occurred (IN or OUT)
-  uint8_t const ep_data   = (dir == TUSB_DIR_IN) ? 1 : 0;
-  uint8_t const ep_status = 1 - ep_data;
-
-  dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, ep_status) : BIT_CLR_(dcd_data.current_ioc, ep_status);
-
-  //------------- Data Phase -------------//
-  if (length)
-  {
-    dcd_data.current_td[ep_data].remaining_bytes = length;
-    dcd_data.current_td[ep_data].xferred_total   = 0;
-
-    queue_xfer_to_buffer(ep_data, 0, addr_offset(p_buffer), length);
-  }
-
-  //------------- Status Phase -------------//
-  dcd_data.current_td[ep_status].remaining_bytes = 0;
-  dcd_data.current_td[ep_status].xferred_total   = 0;
-
-  queue_xfer_to_buffer(ep_status, 0, 0, 0);
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// PIPE HELPER
-//--------------------------------------------------------------------+
-static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
-{
-  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
-}
-
-#if 0
-static inline uint8_t edpt_phy2log(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
-{
-  return physical_endpoint/2;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// BULK/INTERRUPT/ISOCHRONOUS PIPE API
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
-{
-  dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
-}
-
-bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
-{
-  return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
-{
-  uint8_t ep_id = edpt_addr2phy(edpt_addr);
-//  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
-
-  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
-
-  // since the next transfer always take place on buffer0 --> clear buffer0 toggle
-  dcd_data.qhd[ep_id][0].toggle_reset    = 1;
-  dcd_data.qhd[ep_id][0].feedback_toggle = 0;
-
-  //------------- clear stall must carry on any previously queued transfer -------------//
-  if ( dcd_data.next_td[ep_id].total_bytes != 0 )
-  {
-    queue_xfer_in_next_td(ep_id);
-  }
-}
-
-edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
-{
-  (void) rhport;
-  edpt_hdl_t const null_handle = { 0 };
-
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
-
-  TU_ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
-
-  // TODO prevent to open if endpoint size is not 64
-
-  //------------- Prepare Queue Head -------------//
-  uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
-
-  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened, normally this means running out of endpoints
-
-  tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
-  dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
-  dcd_data.class_code[ep_id] = class_code;
-
-  dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
-
-  LPC_USB->EPBUFCFG |= BIT_(ep_id);
-  LPC_USB->INTEN    |= BIT_(ep_id);
-
-  return (edpt_hdl_t)
-      {
-          .rhport     = 0,
-          .index      = ep_id,
-          .class_code = class_code
-      };
-}
-
-bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
-{
-  return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
-}
-
-static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
-{
-  uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
-
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
-  dcd_data.current_td[ep_id].remaining_bytes               -= queued_bytes;
-
-  dcd_data.qhd[ep_id][buff_idx].buff_addr_offset            = buff_addr_offset;
-  dcd_data.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
-
-  dcd_data.qhd[ep_id][buff_idx].active = 1;
-}
-
-static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
-{
-  dcd_data.current_td[ep_id].remaining_bytes         = total_bytes;
-  dcd_data.current_td[ep_id].xferred_total           = 0;
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[0] = 0;
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[1] = 0;
-
-  LPC_USB->EPINUSE  = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
-
-  // need to queue buffer1 first, as activate buffer0 can causes controller does transferring immediately
-  // while buffer1 is not ready yet
-  if ( total_bytes > DCD_11U_13U_MAX_BYTE_PER_TD)
-  {
-    queue_xfer_to_buffer(ep_id, 1, buff_addr_offset+1, total_bytes - DCD_11U_13U_MAX_BYTE_PER_TD);
-  }
-
-  queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
-}
-
-static void queue_xfer_in_next_td(uint8_t ep_id)
-{
-  dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
-
-  pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
-
-  dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
-}
-
-tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
-{
-  TU_ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
-
-  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
-
-  pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
-
-  return TUSB_ERROR_NONE;
-}
-
-tusb_error_t  dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
-{
-  if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
-  { // save this transfer data to next td if pipe is busy or already been stalled
-    dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
-    dcd_data.next_td[edpt_hdl.index].total_bytes      = total_bytes;
-
-    dcd_data.next_ioc = int_on_complete ? BIT_SET_(dcd_data.next_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.next_ioc, edpt_hdl.index);
-  }else
-  {
-    dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
-
-    pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
-  }
-
-	return TUSB_ERROR_NONE;
-}
-
-#endif
-
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h b/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h
deleted file mode 100644
index 530fcd808..000000000
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11uxx_13uxx.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc13xx_12adc.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc11_13u LPC11uxx LPC13uxx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC13XX_12ADC_H_
-#define _TUSB_DCD_LPC13XX_12ADC_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC13XX_12ADC_H_ */
-
-/** @} */
-- 
cgit v1.3.1


From 1f076bd94535270efd2669eef7f80a565ddf595a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 12:59:23 +0700
Subject: rename cont

---
 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h  | 14 ++++----------
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c |  2 +-
 2 files changed, 5 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h
index 530fcd808..92946e346 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.h
@@ -1,6 +1,6 @@
 /**************************************************************************/
 /*!
-    @file     dcd_lpc13xx_12adc.h
+    @file     dcd_lpc11_13_15.h
     @author   hathach (tinyusb.org)
 
     @section LICENSE
@@ -36,12 +36,8 @@
 */
 /**************************************************************************/
 
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc11_13u LPC11uxx LPC13uxx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC13XX_12ADC_H_
-#define _TUSB_DCD_LPC13XX_12ADC_H_
+#ifndef _TUSB_DCD_LPC11_13_15_H_
+#define _TUSB_DCD_LPC11_13_15_H_
 
 #ifdef __cplusplus
  extern "C" {
@@ -52,6 +48,4 @@
  }
 #endif
 
-#endif /* _TUSB_DCD_LPC13XX_12ADC_H_ */
-
-/** @} */
+#endif /* _TUSB_DCD_LPC11_13_15_H_ */
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index 029677e7c..83f584f05 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -1,6 +1,6 @@
 /**************************************************************************/
 /*!
-    @file     dcd_lpc_11uxx_13uxx.c
+    @file     dcd_lpc11_13_15.c
     @author   hathach (tinyusb.org)
 
     @section LICENSE
-- 
cgit v1.3.1


From 3c49bfb588be94062db886d7459085f26f35e31f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 13:05:20 +0700
Subject: remove obsolete example

---
 .../device_virtual_com/segger/LPC4300_Startup.s    |   126 -
 .../device_virtual_com/segger/LPC4300_Target.js    |    19 -
 .../segger/LPC4357 Cortex-M4_MemoryMap.xml         |     7 -
 .../segger/LPC43xx_Registers.xml                   | 33526 -------------------
 .../device_virtual_com/segger/LPC43xx_Vectors.s    |   540 -
 .../device/device_virtual_com/segger/SEGGER_RTT.c  |  1329 -
 .../device/device_virtual_com/segger/SEGGER_RTT.h  |   234 -
 .../device_virtual_com/segger/SEGGER_RTT_Conf.h    |   242 -
 .../device_virtual_com/segger/SEGGER_RTT_SES.c     |    76 -
 .../segger/device_virtual_com.emProject            |   218 -
 .../segger/device_virtual_com.emSession            |    87 -
 .../segger/device_virtual_com_EA4357.jlink         |    39 -
 .../device_virtual_com/segger/flash_placement.xml  |    37 -
 .../device/device_virtual_com/segger/thumb_crt0.s  |   420 -
 examples/device/device_virtual_com/src/main.c      |   154 -
 .../device/device_virtual_com/src/tusb_config.h    |   148 -
 .../device_virtual_com/src/tusb_descriptors.c      |   100 -
 .../device/device_virtual_com/xpresso/.cproject    |   207 -
 .../device/device_virtual_com/xpresso/.project     |    63 -
 src/tusb_option.h                                  |    10 +-
 20 files changed, 5 insertions(+), 37577 deletions(-)
 delete mode 100644 examples/device/device_virtual_com/segger/LPC4300_Startup.s
 delete mode 100644 examples/device/device_virtual_com/segger/LPC4300_Target.js
 delete mode 100644 examples/device/device_virtual_com/segger/LPC4357 Cortex-M4_MemoryMap.xml
 delete mode 100644 examples/device/device_virtual_com/segger/LPC43xx_Registers.xml
 delete mode 100644 examples/device/device_virtual_com/segger/LPC43xx_Vectors.s
 delete mode 100644 examples/device/device_virtual_com/segger/SEGGER_RTT.c
 delete mode 100644 examples/device/device_virtual_com/segger/SEGGER_RTT.h
 delete mode 100644 examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h
 delete mode 100644 examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c
 delete mode 100644 examples/device/device_virtual_com/segger/device_virtual_com.emProject
 delete mode 100644 examples/device/device_virtual_com/segger/device_virtual_com.emSession
 delete mode 100644 examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink
 delete mode 100644 examples/device/device_virtual_com/segger/flash_placement.xml
 delete mode 100644 examples/device/device_virtual_com/segger/thumb_crt0.s
 delete mode 100644 examples/device/device_virtual_com/src/main.c
 delete mode 100644 examples/device/device_virtual_com/src/tusb_config.h
 delete mode 100644 examples/device/device_virtual_com/src/tusb_descriptors.c
 delete mode 100644 examples/device/device_virtual_com/xpresso/.cproject
 delete mode 100644 examples/device/device_virtual_com/xpresso/.project

(limited to 'src')

diff --git a/examples/device/device_virtual_com/segger/LPC4300_Startup.s b/examples/device/device_virtual_com/segger/LPC4300_Startup.s
deleted file mode 100644
index 3df2ad963..000000000
--- a/examples/device/device_virtual_com/segger/LPC4300_Startup.s
+++ /dev/null
@@ -1,126 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * NO_FPU_ENABLE                                                             *
- *                                                                           *
- *   If defined, FPU will not be enabled.                                    *
- *                                                                           *
- * NO_STACK_INIT                                                             *
- *                                                                           *
- *   If defined, the stack pointer will not be initialised.                  *
- *                                                                           *
- * NO_SYSTEM_INIT                                                            *
- *                                                                           *
- *   If defined, the SystemInit() function will not be called. By default    *
- *   SystemInit() is called after reset to enable the clocks and memories to *
- *   be initialised prior to any C startup initialisation.                   *
- *                                                                           *
- * NO_VTOR_CONFIG                                                            *
- *                                                                           *
- *   If defined, the vector table offset register will not be configured.    *
- *                                                                           *
- * MEMORY_INIT                                                               *
- *                                                                           *
- *   If defined, the MemoryInit() function will be called. By default        *
- *   MemoryInit() is called after SystemInit() to enable an external memory  *
- *   controller.                                                             *
- *                                                                           *
- * STACK_INIT_VAL                                                            *
- *                                                                           *
- *   If defined, specifies the initial stack pointer value. If undefined,    *
- *   the stack pointer will be initialised to point to the end of the        *
- *   RAM segment.                                                            *
- *                                                                           *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, the exception vectors will be copied from Flash to RAM.     *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-
-  .global Reset_Handler
-  .extern _vectors
-
-  .section .init, "ax"
-  .thumb_func
-
-  .equ VTOR_REG, 0xE000ED08
-  .equ FPU_CPACR_REG, 0xE000ED88
-
-#ifndef STACK_INIT_VAL
-#define STACK_INIT_VAL __RAM_segment_end__
-#endif
-
-Reset_Handler:
-#ifndef NO_STACK_INIT
-  /* Initialise main stack */
-  ldr r0, =STACK_INIT_VAL
-  ldr r1, =0x7
-  bics r0, r1
-  mov sp, r0
-#endif
-
-#ifndef NO_SYSTEM_INIT
-  /* Initialise system */
-  ldr r0, =SystemInit
-  blx r0
-#endif
-
-#ifdef MEMORY_INIT
-  ldr r0, =MemoryInit
-  blx r0
-#endif
-
-#ifdef VECTORS_IN_RAM
-  /* Copy exception vectors into RAM */
-  ldr r0, =__vectors_start__
-  ldr r1, =__vectors_end__
-  ldr r2, =__vectors_ram_start__
-1:
-  cmp r0, r1
-  beq 2f
-  ldr r3, [r0]
-  str r3, [r2]
-  adds r0, r0, #4
-  adds r2, r2, #4
-  b 1b
-2:
-#endif
-
-#ifndef NO_VTOR_CONFIG
-  /* Configure vector table offset register */
-  ldr r0, =VTOR_REG
-#ifdef VECTORS_IN_RAM
-  ldr r1, =_vectors_ram
-#else
-  ldr r1, =_vectors
-#endif
-  str r1, [r0]
-#endif
-
-#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
-  /* Enable FPU */
-  ldr r0, =FPU_CPACR_REG
-  ldr r1, [r0]
-  orr r1, r1, #(0xF << 20)
-  str r1, [r0]
-  dsb
-  isb
-#endif
-
-  /* Jump to program start */
-  b _start
-
-
diff --git a/examples/device/device_virtual_com/segger/LPC4300_Target.js b/examples/device/device_virtual_com/segger/LPC4300_Target.js
deleted file mode 100644
index 20560af43..000000000
--- a/examples/device/device_virtual_com/segger/LPC4300_Target.js
+++ /dev/null
@@ -1,19 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-function Reset() {
-  TargetInterface.resetAndStop();
-}
-
-function EnableTrace(traceInterfaceType) {
-  // TODO: Enable trace
-}
-
diff --git a/examples/device/device_virtual_com/segger/LPC4357 Cortex-M4_MemoryMap.xml b/examples/device/device_virtual_com/segger/LPC4357 Cortex-M4_MemoryMap.xml
deleted file mode 100644
index eb42b7bfd..000000000
--- a/examples/device/device_virtual_com/segger/LPC4357 Cortex-M4_MemoryMap.xml	
+++ /dev/null
@@ -1,7 +0,0 @@
-<!DOCTYPE Board_Memory_Definition_File>
-<root name="LPC4357 Cortex-M4">
-  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
-  <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" />
-  <MemorySegment name="RAM2" start="0x20000000" size="0x00010000" access="Read/Write" />
-</root>
diff --git a/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml b/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml
deleted file mode 100644
index 9c0946466..000000000
--- a/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml
+++ /dev/null
@@ -1,33526 +0,0 @@
-<!DOCTYPE Register_Definition_File>
-<Processor name="LPC43xx" description="Register cmsis file for LPC43xx parts">
-  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
-    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
-        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
-        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
-      </BitField>
-      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
-        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
-        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
-        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
-        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
-        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
-        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
-      </BitField>
-      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
-      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
-      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
-      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
-      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
-      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
-      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
-        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
-      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
-      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
-      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
-      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
-        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
-        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
-      </BitField>
-      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
-      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
-    </Register>
-    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
-      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
-    </Register>
-    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="STATE_L" description="State variable." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="5" name="STATE_H" description="State variable." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
-      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
-      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
-      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
-      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
-      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
-      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
-      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
-      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
-      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
-      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
-      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
-      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
-      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
-      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
-      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
-    </Register>
-    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
-        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
-        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
-        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
-      </BitField>
-    </Register>
-    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
-        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
-        <Enum name="NO_CHANGE" start="0x0" description="No change." />
-        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
-        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
-        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
-      </BitField>
-    </Register>
-    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
-    </Register>
-    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
-      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
-    </Register>
-    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
-      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
-      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
-    </Register>
-    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
-      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
-    </Register>
-    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
-      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
-    </Register>
-    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
-    </Register>
-    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
-      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
-        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
-        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
-      </BitField>
-      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
-        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
-        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
-      </BitField>
-      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
-      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
-        <Enum name="LOW" start="0x0" description="LOW" />
-        <Enum name="RISE" start="0x1" description="Rise" />
-        <Enum name="FALL" start="0x2" description="Fall" />
-        <Enum name="HIGH" start="0x3" description="HIGH" />
-      </BitField>
-      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
-        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
-        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
-        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
-        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
-      </BitField>
-      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
-        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
-        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
-      </BitField>
-      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
-      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
-      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
-        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
-        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
-        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
-      </BitField>
-      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
-    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
-        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
-        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
-    </Register>
-    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
-        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
-        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
-      </BitField>
-      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
-      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
-      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
-        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
-        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
-        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
-        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
-        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
-        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
-        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
-        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
-      </BitField>
-      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
-        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
-        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
-        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
-        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
-        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
-        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
-        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
-        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
-      </BitField>
-      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
-        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
-        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
-        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
-      </BitField>
-      <BitField start="24" size="1" name="S" description="Source AHB master select:">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
-      </BitField>
-      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
-        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
-        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
-      </BitField>
-      <BitField start="26" size="1" name="SI" description="Source increment:">
-        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
-        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
-      </BitField>
-      <BitField start="27" size="1" name="DI" description="Destination increment:">
-        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
-        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
-      </BitField>
-      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
-        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
-        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
-      </BitField>
-      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
-        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
-        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
-      </BitField>
-      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
-        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
-        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
-      </BitField>
-      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
-        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
-        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
-      </BitField>
-    </Register>
-    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
-        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
-        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
-      </BitField>
-      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
-        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
-        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
-        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
-        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
-        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
-        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
-        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
-      </BitField>
-      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
-        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
-        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
-        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
-        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
-        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
-        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
-        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
-        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
-        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
-      </BitField>
-      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
-        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
-        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
-        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
-        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
-      </BitField>
-      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
-      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
-      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
-      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
-      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
-        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
-        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
-      </BitField>
-      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
-      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
-      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
-      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
-      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
-        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
-        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
-        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
-        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
-      </BitField>
-      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
-        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
-        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
-      </BitField>
-      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
-        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
-        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
-        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
-        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
-      </BitField>
-      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
-    </Register>
-    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
-      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
-        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
-        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
-      </BitField>
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDRESS" description="Address." />
-    </Register>
-    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
-    </Register>
-    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
-    </Register>
-    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="DATA" description="Input or output data" />
-    </Register>
-    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
-      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
-      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
-      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
-      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
-        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
-        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
-        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
-        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
-      </BitField>
-      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
-        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
-        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
-        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
-        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
-        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
-      </BitField>
-      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
-    </Register>
-    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
-      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
-      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
-      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
-      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
-      </BitField>
-      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
-      </BitField>
-      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
-        <Enum name="NO_CHANGE" start="0" description="No change." />
-        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
-        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
-        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
-        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
-        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
-      </BitField>
-      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
-      </BitField>
-      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
-        <Enum name="NO_CHANGE" start="0" description="No change" />
-        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
-      </BitField>
-      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
-        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
-      </BitField>
-      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
-        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
-        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
-      </BitField>
-      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
-      </BitField>
-      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
-      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
-      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
-        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
-        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
-      </BitField>
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
-      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
-      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
-      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
-      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
-    </Register>
-    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
-      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
-        <Enum name="NONE" start="0" description="None. No response expected from card" />
-        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
-      </BitField>
-      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
-        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
-        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
-      </BitField>
-      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
-        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
-        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
-      </BitField>
-      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
-        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
-        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
-      </BitField>
-      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
-        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
-        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
-      </BitField>
-      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
-        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
-        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
-      </BitField>
-      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
-        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
-        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
-      </BitField>
-      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
-        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
-        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
-      </BitField>
-      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
-        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
-        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
-      </BitField>
-      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
-        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
-        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
-      </BitField>
-      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
-      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
-        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
-      </BitField>
-      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
-        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
-      </BitField>
-      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
-      </BitField>
-      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
-      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
-      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
-        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
-        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
-      </BitField>
-      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
-        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
-        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
-      </BitField>
-      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
-    </Register>
-    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
-    </Register>
-    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
-    </Register>
-    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
-    </Register>
-    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
-    </Register>
-    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
-      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
-      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
-      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
-      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
-      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
-      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
-      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
-      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
-      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
-      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
-      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
-      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
-      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
-    </Register>
-    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
-      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
-    </Register>
-    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
-    </Register>
-    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
-      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
-      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
-      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
-      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
-        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
-        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
-        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
-        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
-        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
-        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
-        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
-        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
-      </BitField>
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
-    </Register>
-    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
-    </Register>
-    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
-      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
-      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
-      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
-      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
-      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
-      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
-    </Register>
-    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
-    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
-        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
-        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
-        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
-        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
-        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
-        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
-        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
-        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
-      </BitField>
-      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM" description="Endian mode.">
-        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
-        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
-      </BitField>
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
-        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
-        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
-        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
-        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
-        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
-        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
-        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
-        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
-        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
-        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
-      </BitField>
-      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RD" description="Read data strategy.">
-        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
-        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
-        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
-        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
-      </BitField>
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="2" name="MD" description="Memory device.">
-        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
-        <Enum name="RESERVED" start="0x1" description="Reserved." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
-      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="2" name="CAS" description="CAS latency.">
-        <Enum name="RESERVED" start="0x0" description="Reserved." />
-        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
-        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
-        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="MW" description="Memory width.">
-        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
-        <Enum name="16_BIT" start="0x1" description="16 bit." />
-        <Enum name="32_BIT" start="0x2" description="32 bit." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
-        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
-        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
-        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
-        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
-      </BitField>
-      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
-        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
-        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
-      </BitField>
-      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
-        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
-      </BitField>
-      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
-        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
-        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="P" description="Write protect.">
-        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
-        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
-      </BitField>
-      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
-        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
-        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
-      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
-      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
-      </BitField>
-      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
-      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
-      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
-        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
-        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
-      </BitField>
-      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
-      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
-        <Enum name="DISABLED_" start="0" description="Disabled." />
-        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
-      </BitField>
-      <BitField start="8" size="1" name="ID" description="USB ID">
-        <Enum name="A_DEVICE" start="0" description="A-device" />
-        <Enum name="B_DEVICE" start="1" description="B-device" />
-      </BitField>
-      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
-      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
-      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
-      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
-      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
-      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
-      <BitField start="15" size="1" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
-      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
-      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
-      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
-      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
-      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
-      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
-      <BitField start="23" size="1" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
-      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="6" size="26" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
-      <BitField start="6" size="10" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
-      <BitField start="22" size="10" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="reserved" />
-      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
-    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
-      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
-      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
-      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
-      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
-      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
-      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
-      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
-      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
-      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
-      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
-      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
-      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
-      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
-      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
-      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
-        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
-      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
-      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
-      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
-      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RS" description="Run/Stop">
-        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
-        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
-      </BitField>
-      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
-        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
-        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
-      </BitField>
-      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
-      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
-      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
-        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
-      </BitField>
-      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
-        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
-        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
-      </BitField>
-      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
-        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
-        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
-        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
-        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
-      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="6" size="1" name="URI" description="USB reset received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="DCSuspend">
-        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
-      </BitField>
-      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
-        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
-        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
-    </Register>
-    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
-      </BitField>
-      <BitField start="2" size="1" name="PCI" description="Port change detect.">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
-      </BitField>
-      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
-      </BitField>
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRI" description="SOF received">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
-      </BitField>
-      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
-      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="HCH" description="HCHalted">
-        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
-        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
-      </BitField>
-      <BitField start="13" size="1" name="RCL" description="Reclamation">
-        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
-        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
-      </BitField>
-      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
-      </BitField>
-      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
-        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
-        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
-      </BitField>
-      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
-        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
-        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
-      </BitField>
-      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
-      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
-      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
-      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
-      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
-      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
-      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
-      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
-      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
-      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
-      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
-      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
-      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
-      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="reserved" />
-      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
-        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
-        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
-      </BitField>
-      <BitField start="25" size="7" name="USBADR" description="USB device address" />
-    </Register>
-    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
-    </Register>
-    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="11" name="RESERVED" description="reserved" />
-      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
-    </Register>
-    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
-    </Register>
-    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
-      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
-      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
-      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
-      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
-      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
-      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
-      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
-      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
-        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
-        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
-      </BitField>
-      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
-        <Enum name="READ" start="0" description="Read" />
-        <Enum name="WRITE" start="1" description="Write" />
-      </BitField>
-      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
-    </Register>
-    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BINT" description="bInterval value" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status">
-        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
-        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
-      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
-      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
-        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
-        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
-      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="amber" />
-        <Enum name="GREEN" start="0x2" description="green" />
-        <Enum name="UNDEFINED" start="0x3" description="undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
-        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
-        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
-        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
-        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
-        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
-        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
-      </BitField>
-      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
-        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
-        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
-        <Enum name="NO_CHANGE_" start="0" description="No change." />
-        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
-      </BitField>
-      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
-        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
-        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
-      </BitField>
-      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
-      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
-        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
-      </BitField>
-      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
-        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
-      </BitField>
-      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
-        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
-      </BitField>
-      <BitField start="9" size="1" name="HSP" description="High-speed status">
-        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
-        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
-      </BitField>
-      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
-        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
-        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
-        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
-        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
-        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
-      </BitField>
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
-        <Enum name="OFF" start="0x0" description="Port indicators are off." />
-        <Enum name="AMBER" start="0x1" description="Amber" />
-        <Enum name="GREEN" start="0x2" description="Green" />
-        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
-      </BitField>
-      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
-        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
-        <Enum name="J_STATE" start="0x1" description="J_STATE" />
-        <Enum name="K_STATE" start="0x2" description="K_STATE" />
-        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
-        <Enum name="PACKET" start="0x4" description="Packet" />
-        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
-        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
-        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
-      </BitField>
-      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
-      </BitField>
-      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
-        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
-        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
-      </BitField>
-      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
-        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
-        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
-      </BitField>
-      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
-        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
-        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
-      </BitField>
-      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
-        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
-        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
-      </BitField>
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
-        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
-        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
-        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
-      </BitField>
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
-        <Enum name="ULPI" start="0x2" description="ULPI" />
-        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
-      </BitField>
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
-        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
-        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
-      </BitField>
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
-        <Enum name="IDLE" start="0x0" description="Idle" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
-        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
-      </BitField>
-      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
-        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
-        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
-      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
-        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
-        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
-      </BitField>
-      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
-        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
-        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
-      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
-      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="RXT" description="Endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
-        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
-        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
-      </BitField>
-      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
-        <Enum name="CONTROL" start="0x0" description="Control" />
-        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
-        <Enum name="BULK" start="0x2" description="Bulk" />
-        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
-        <Enum name="ENABLED" start="0" description="Enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled" />
-      </BitField>
-      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
-      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
-        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
-        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
-      </BitField>
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
-    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
-      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
-      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
-      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
-    </Register>
-    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
-      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
-      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
-      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
-    </Register>
-    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
-      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
-      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
-      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
-      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
-      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
-      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
-      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
-      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
-      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
-      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
-      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
-      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
-      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
-      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
-      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
-      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
-      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
-      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
-      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
-      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
-      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
-      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
-      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
-      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
-      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
-      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
-      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
-      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
-      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
-      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
-    </Register>
-    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
-    </Register>
-    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
-      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
-      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
-      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
-      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
-      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
-    </Register>
-    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
-    </Register>
-    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
-      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
-      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RED" description="Red color component" />
-      <BitField start="8" size="8" name="GREEN" description="Green color component" />
-      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
-    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
-      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
-      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
-      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
-      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
-    </Register>
-    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
-    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
-      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
-      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
-      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
-      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
-      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
-      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
-      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
-      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
-      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
-      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
-      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
-      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
-      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
-      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
-      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
-      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
-      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
-      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
-      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
-      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
-    </Register>
-    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
-    </Register>
-    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
-      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
-      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
-      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
-      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
-      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
-      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
-      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
-      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
-      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
-    </Register>
-    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
-      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
-      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
-      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
-      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
-      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
-      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
-      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
-      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
-      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
-    </Register>
-    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
-      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
-      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
-      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
-      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
-      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
-    </Register>
-    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
-      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="MO" description="Always 1" />
-    </Register>
-    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
-    </Register>
-    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
-      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
-      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
-      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
-      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
-      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
-      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
-      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
-      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
-      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
-      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
-      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
-      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
-      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
-      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
-    </Register>
-    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
-    </Register>
-    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
-      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
-    </Register>
-    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
-    </Register>
-    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
-      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
-    </Register>
-    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
-    </Register>
-    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
-    </Register>
-    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
-      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
-      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
-      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
-      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
-      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
-      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
-      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
-      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
-      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
-      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
-      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
-      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
-      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
-    </Register>
-    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
-    </Register>
-    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
-    </Register>
-    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
-      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
-      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
-      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
-      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
-      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
-      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
-      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
-      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
-      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
-      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
-      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
-      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
-      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
-      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
-      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
-      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
-      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
-      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
-      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
-      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
-      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
-      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
-      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
-      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
-      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
-      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
-      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
-      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
-      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
-      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
-      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
-      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
-      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
-      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
-      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
-      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
-      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
-      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
-      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
-      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
-      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
-    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
-    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
-    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M4 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register." />
-      <BitField start="1" size="1" name="ENA_EVENT1" description="Writing a 1 enables the Cortex-M0 core and the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Cortex-M0 subsystem core to put the part into any of&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;the Power-down modes Deep-sleep, Power-down, or&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Deep power-down depending on the value in the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;PD0_SLEEP0_MODE register." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 3CBA = Power-down mode with M0SUB SRAM maintained&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
-    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
-        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
-        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
-        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
-        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
-        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
-        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
-      </BitField>
-      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
-        <Enum name="POWERED" start="0" description="Powered." />
-        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
-        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
-        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
-      </BitField>
-      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
-        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
-        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INACTIVE" start="0x3" description="Inactive." />
-      </BitField>
-      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.">
-        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
-        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
-        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
-        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
-      </BitField>
-      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.">
-        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
-        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
-        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
-        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
-      </BitField>
-      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
-        <Enum name="RESERVED" start="0x0" description="Reserved" />
-        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x3" description="Reserved." />
-      </BitField>
-      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved." />
-        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
-      </BitField>
-      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
-        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
-      </BitField>
-      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="M4MEMMAP" access="Read/Write" description="ARM Cortex-M4 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M4MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="10" name="RESERVED" description="Reserved." />
-      <BitField start="10" size="1" name="M0SUBTAPSEL" description="JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="11" size="1" name="M4TAPSEL" description="JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="12" size="1" name="M0APPTAPSEL" description="JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
-      </BitField>
-      <BitField start="13" size="19" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
-        <Enum name="SPIFI" start="0x0" description="SPIFI" />
-        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
-        <Enum name="SGPIO14" start="0x2" description="SGPIO14" />
-        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
-      </BitField>
-      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
-        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
-        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
-        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
-        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
-        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
-        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
-        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
-        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
-      </BitField>
-      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
-        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
-        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
-        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
-        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
-      </BitField>
-      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
-        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
-        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="SGPIO15" start="0x3" description="SGPIO15" />
-      </BitField>
-      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
-        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
-        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="SGPIO14" start="0x3" description="SGPIO14" />
-      </BitField>
-      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
-        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
-        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-        <Enum name="ADCHS_WRITE" start="0x3" description="ADCHS write" />
-      </BitField>
-      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
-        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
-        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-        <Enum name="ADCHS_READ" start="0x3" description="ADCHS read" />
-      </BitField>
-      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
-        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
-        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
-        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
-        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
-        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
-        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
-        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
-        <Enum name="SGPIO14" start="0x1" description="SGPIO14" />
-        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
-        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
-        <Enum name="SGPIO15" start="0x1" description="SGPIO15" />
-        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
-        <Enum name="ADC0" start="0x0" description="ADC0" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
-        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
-      </BitField>
-      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
-        <Enum name="ADC1" start="0x0" description="ADC1" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
-        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
-      </BitField>
-      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
-        <Enum name="DAC" start="0x0" description="DAC" />
-        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
-        <Enum name="SGPIO15" start="0x2" description="SGPIO15" />
-        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
-      </BitField>
-    </Register>
-    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
-        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
-      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
-        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
-        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
-        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
-        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
-        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
-        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
-        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
-        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
-        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
-        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
-      </BitField>
-      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
-      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
-        <Enum name="POWER_DOWN" start="0" description="Power-down" />
-        <Enum name="ACTIVE" start="1" description="Active (Default)" />
-      </BitField>
-    </Register>
-    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
-        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
-        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
-        <Enum name="MII" start="0x0" description="MII" />
-        <Enum name="RMII" start="0x4" description="RMII" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
-        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
-        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
-      </BitField>
-      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
-        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
-        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
-      </BitField>
-      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
-        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
-        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x130" size="4" name="M4TXEVENT" access="Read/Write" description="Cortex-M4 TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M4 TXEV event.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)" />
-    </Register>
-    <Register start="+0x308" size="4" name="M0SUBMEMMAP" access="Read/Write" description="ARM Cortex-M0SUB memory mapping" reset_value="0x18400000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M0SUBMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x314" size="4" name="M0SUBTXEVENT" access="Read/Write" description="Cortex-M0SUB TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0SUB TXEV event handling.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="M0APPTXEVENT" access="Read/Write" description="Cortex-M0APP TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0APP TXEV event handling.">
-        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
-        <Enum name="NO_EFFECT" start="1" description="No effect." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="M0APPMEMMAP" access="Read/Write" description="ARM Cortex-M0APP memory mapping" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
-      <BitField start="12" size="20" name="M0APPMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
-    </Register>
-    <Register start="+0x500" size="4" name="USB0FLADJ" access="Read/Write" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
-    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
-        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
-        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
-        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
-      </BitField>
-      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
-      </BitField>
-      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
-      </BitField>
-      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
-      </BitField>
-      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
-      </BitField>
-      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
-      </BitField>
-      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
-      </BitField>
-      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
-      </BitField>
-      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
-      </BitField>
-      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
-      </BitField>
-      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
-      </BitField>
-      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
-      </BitField>
-      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
-      </BitField>
-      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
-      </BitField>
-      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
-      </BitField>
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
-      </BitField>
-      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
-        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
-        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
-      </BitField>
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
-      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
-      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
-      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
-      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
-      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
-      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
-      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
-      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
-      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
-      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
-      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
-      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
-      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
-      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
-      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
-      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
-      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
-      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
-      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
-      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
-      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
-      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
-      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
-      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
-      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
-      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
-      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
-      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
-      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
-      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
-      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
-      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
-      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
-      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
-      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
-      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
-      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
-      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
-      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
-      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
-      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
-      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
-      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
-      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
-      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
-      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
-      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
-      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
-      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
-      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
-      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
-      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
-    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
-      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
-        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
-        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect." />
-        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
-      </BitField>
-      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
-      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
-        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
-        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
-      </BitField>
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
-      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
-      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
-      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
-      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
-      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
-      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
-      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
-      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
-      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
-      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
-      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
-      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
-      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
-      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
-      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
-      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
-        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
-        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
-        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
-        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
-        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
-      </BitField>
-      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
-      </BitField>
-      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
-        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
-        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
-        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
-        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
-      </BitField>
-      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
-      </BitField>
-      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
-        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
-      </BitField>
-      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
-        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
-        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
-      </BitField>
-      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
-        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
-        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
-      </BitField>
-      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
-        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
-        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
-      </BitField>
-      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
-        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
-        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
-        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
-        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
-      </BitField>
-    </Register>
-    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
-      </BitField>
-      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
-      </BitField>
-      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
-        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
-      </BitField>
-      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
-        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
-      </BitField>
-      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
-      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
-        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
-        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
-      </BitField>
-    </Register>
-    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
-      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
-      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
-      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
-      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
-      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
-    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
-      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
-      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
-        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
-        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
-      </BitField>
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
-        <Enum name="IRC" start="0x01" description="IRC" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="RESERVED" start="0x0B" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="ENABLE" start="0" description="Enable" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
-        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
-        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
-      </BitField>
-      <BitField start="2" size="1" name="HF" description="Select frequency range">
-        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
-      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
-      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
-    </Register>
-    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
-      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL0 power down">
-        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
-        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
-        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
-      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
-      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="FRM" description="Free running mode" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
-      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
-        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
-        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
-      </BitField>
-      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
-        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
-        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
-      </BitField>
-      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
-      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
-      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="PLL1 power down">
-        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
-        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
-      </BitField>
-      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
-        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
-        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
-      </BitField>
-      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
-      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
-      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
-        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
-        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
-      </BitField>
-      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="PEQ2" start="0x1" description="2 (default)" />
-        <Enum name="PEQ4" start="0x2" description="4" />
-        <Enum name="8" start="0x3" description="8" />
-      </BitField>
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
-        <Enum name="1" start="0x0" description="1" />
-        <Enum name="NEQ2" start="0x1" description="2" />
-        <Enum name="NEQ3" start="0x2" description="3 (default)" />
-        <Enum name="4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="RESERVED" start="0x09" description="Reserved" />
-        <Enum name="RESERVED" start="0x0A" description="Reserved" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
-        <Enum name="DIV1" start="0x0" description="1 (default)" />
-        <Enum name="DIV2" start="0x1" description="2" />
-        <Enum name="DIV3" start="0x2" description="3" />
-        <Enum name="DIV4" start="0x3" description="4" />
-      </BitField>
-      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
-      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Integer divider power down">
-        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="Power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
-        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="BASE_M4_CLK" access="Read/Write" description="Output stage BASE_M4_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="BASE_SPI_CLK" access="Read/Write" description="Output stage BASE_SPI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="PD" description="Output stage power down">
-        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
-        <Enum name="POWER_DOWN" start="1" description="power-down" />
-      </BitField>
-      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
-        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
-        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
-      </BitField>
-      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
-        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
-        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
-        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
-        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
-        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
-        <Enum name="RESERVED" start="0x05" description="Reserved" />
-        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
-        <Enum name="RESERVED" start="0x07" description="Reserved" />
-        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
-        <Enum name="PLL1" start="0x09" description="PLL1" />
-        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
-        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
-        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
-        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
-        <Enum name="IDIVE" start="0x10" description="IDIVE" />
-      </BitField>
-      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_M4_BUS_CFG" access="Read/Write" description="CLK_M4_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0408" size="4" name="CLK_M4_SPIFI_CFG" access="Read/Write" description="CLK_M4_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0410" size="4" name="CLK_M4_GPIO_CFG" access="Read/Write" description="CLK_M4_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0418" size="4" name="CLK_M4_LCD_CFG" access="Read/Write" description="CLK_M4_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0420" size="4" name="CLK_M4_ETHERNET_CFG" access="Read/Write" description="CLK_M4_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0428" size="4" name="CLK_M4_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0430" size="4" name="CLK_M4_EMC_CFG" access="Read/Write" description="CLK_M4_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0438" size="4" name="CLK_M4_SDIO_CFG" access="Read/Write" description="CLK_M4_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0440" size="4" name="CLK_M4_DMA_CFG" access="Read/Write" description="CLK_M4_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0448" size="4" name="CLK_M4_M4CORE_CFG" access="Read/Write" description="CLK_M4_M4CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0468" size="4" name="CLK_M4_SCT_CFG" access="Read/Write" description="CLK_M4_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0470" size="4" name="CLK_M4_USB1_CFG" access="Read/Write" description="CLK_M4_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0478" size="4" name="CLK_M4_EMCDIV_CFG" access="Read/Write" description="CLK_M4_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="5" size="3" name="DIV" description="Clock divider value">
-        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
-        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0480" size="4" name="CLK_M4_FLASHA_CFG" access="Read/Write" description="CLK_M4_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0488" size="4" name="CLK_M4_FLASHB_CFG" access="Read/Write" description="CLK_M4_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0490" size="4" name="CLK_M4_M0APP_CFG" access="Read/Write" description="CLK_M0APP_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0498" size="4" name="CLK_M4_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A0" size="4" name="CLK_M4_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_M4_WWDT_CFG" access="Read/Write" description="CLK_M4_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0508" size="4" name="CLK_M4_USART0_CFG" access="Read/Write" description="CLK_M4_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0510" size="4" name="CLK_M4_UART1_CFG" access="Read/Write" description="CLK_M4_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0518" size="4" name="CLK_M4_SSP0_CFG" access="Read/Write" description="CLK_M4_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0520" size="4" name="CLK_M4_TIMER0_CFG" access="Read/Write" description="CLK_M4_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0528" size="4" name="CLK_M4_TIMER1_CFG" access="Read/Write" description="CLK_M4_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0530" size="4" name="CLK_M4_SCU_CFG" access="Read/Write" description="CLK_M4_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0538" size="4" name="CLK_M4_CREG_CFG" access="Read/Write" description="CLK_M4_CREGclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_M4_RITIMER_CFG" access="Read/Write" description="CLK_M4_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0608" size="4" name="CLK_M4_USART2_CFG" access="Read/Write" description="CLK_M4_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0610" size="4" name="CLK_M4_USART3_CFG" access="Read/Write" description="CLK_M4_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0618" size="4" name="CLK_M4_TIMER2_CFG" access="Read/Write" description="CLK_M4_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0620" size="4" name="CLK_M4_TIMER3_CFG" access="Read/Write" description="CLK_M4_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0628" size="4" name="CLK_M4_SSP1_CFG" access="Read/Write" description="CLK_M4_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0630" size="4" name="CLK_M4_QEI_CFG" access="Read/Write" description="CLK_M4_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0700" size="4" name="CLK_PERIPH_BUS_CFG" access="Read/Write" description="CLK_PERIPH_BUS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0710" size="4" name="CLK_PERIPH_CORE_CFG" access="Read/Write" description="CLK_PERIPH_CORE_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0718" size="4" name="CLK_PERIPH_SGPIO_CFG" access="Read/Write" description="CLK_PERIPH_SGPIO_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xA00" size="4" name="CLK_SPI_CFG" access="Read/Write" description="CLK_SPI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xB00" size="4" name="CLK_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
-        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x404" size="4" name="CLK_M4_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040C" size="4" name="CLK_M4_SPIFI_STAT" access="ReadOnly" description="CLK_M4_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0414" size="4" name="CLK_M4_GPIO_STAT" access="ReadOnly" description="CLK_M4_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x041C" size="4" name="CLK_M4_LCD_STAT" access="ReadOnly" description="CLK_M4_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0424" size="4" name="CLK_M4_ETHERNET_STAT" access="ReadOnly" description="CLK_M4_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x042C" size="4" name="CLK_M4_USB0_STAT" access="ReadOnly" description="CLK_M4_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0434" size="4" name="CLK_M4_EMC_STAT" access="ReadOnly" description="CLK_M4_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x043C" size="4" name="CLK_M4_SDIO_STAT" access="ReadOnly" description="CLK_M4_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0444" size="4" name="CLK_M4_DMA_STAT" access="ReadOnly" description="CLK_M4_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044C" size="4" name="CLK_M4_M4CORE_STAT" access="ReadOnly" description="CLK_M4_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x046C" size="4" name="CLK_M4_SCT_STAT" access="ReadOnly" description="CLK_M4_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0474" size="4" name="CLK_M4_USB1_STAT" access="ReadOnly" description="CLK_M4_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x047C" size="4" name="CLK_M4_EMCDIV_STAT" access="ReadOnly" description="CLK_M4_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0484" size="4" name="CLK_M4_FLASHA_STAT" access="ReadOnly" description="CLK_M4_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048C" size="4" name="CLK_M4_FLASHB_STAT" access="ReadOnly" description="CLK_M4_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0494" size="4" name="CLK_M4_M0APP_STAT" access="ReadOnly" description="CLK_M4_MOAPP clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x049C" size="4" name="CLK_M4_ADCHS_STAT" access="ReadOnly" description="CLK_M4_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04A4" size="4" name="CLK_M4_EEPROM_STAT" access="ReadOnly" description="CLK_M4_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504" size="4" name="CLK_M4_WWDT_STAT" access="ReadOnly" description="CLK_M4_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050C" size="4" name="CLK_M4_USART0_STAT" access="ReadOnly" description="CLK_M4_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0514" size="4" name="CLK_M4_UART1_STAT" access="ReadOnly" description="CLK_M4_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x051C" size="4" name="CLK_M4_SSP0_STAT" access="ReadOnly" description="CLK_M4_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0524" size="4" name="CLK_M4_TIMER0_STAT" access="ReadOnly" description="CLK_M4_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x052C" size="4" name="CLK_M4_TIMER1_STAT" access="ReadOnly" description="CLK_M4_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0534" size="4" name="CLK_M4_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x053C" size="4" name="CLK_M4_CREG_STAT" access="ReadOnly" description="CLK_M4_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x604" size="4" name="CLK_M4_RITIMER_STAT" access="ReadOnly" description="CLK_M4_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060C" size="4" name="CLK_M4_USART2_STAT" access="ReadOnly" description="CLK_M4_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0614" size="4" name="CLK_M4_USART3_STAT" access="ReadOnly" description="CLK_M4_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x061C" size="4" name="CLK_M4_TIMER2_STAT" access="ReadOnly" description="CLK_M4_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0624" size="4" name="CLK_M4_TIMER3_STAT" access="ReadOnly" description="CLK_M4_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x062C" size="4" name="CLK_M4_SSP1_STAT" access="ReadOnly" description="CLK_M4_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0634" size="4" name="CLK_M4_QEI_STAT" access="ReadOnly" description="CLK_M4_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_PERIPH_BUS_STAT" access="ReadOnly" description="CLK_PERIPH_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0714" size="4" name="CLK_PERIPH_CORE_STAT" access="ReadOnly" description="CLK_CORE_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x071C" size="4" name="CLK_PERIPH_SGPIO_STAT" access="ReadOnly" description="CLK_CORE_SGPIO_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xA04" size="4" name="CLK_SPI_STAT" access="ReadOnly" description="CLK_SPI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xB04" size="4" name="CLK_ADCHS_STAT" access="ReadOnly" description="CLK_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
-    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable">
-        <Enum name="DISABLED" start="0" description="Clock is disabled." />
-        <Enum name="ENABLED" start="1" description="Clock is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
-        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
-        <Enum name="ENABLED" start="1" description="Auto is enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
-        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
-        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
-      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
-      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
-    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
-      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="13" size="1" name="M4_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="24" size="1" name="M0APP_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
-      <BitField start="25" size="1" name="SGPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="26" size="1" name="SPI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="1" name="ADCHS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
-      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="M4_RST" description="Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-    </Register>
-    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="16" size="2" name="M0APP_RST" description="Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="18" size="2" name="SGPIO_RST" description="Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="20" size="2" name="SPI_RST" description="Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="2" name="ADCHS_RST" description="Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
-      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="M4_RST" description="Current status of the M4_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="24" size="1" name="M0APP_RST" description="Current status of the M0APP_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="25" size="1" name="SGPIO_RST" description="Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="26" size="1" name="SPI_RST" description="Current status of the SPI_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="28" size="1" name="ADCHS_RST" description="Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset" />
-      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x430" size="4" name="RESET_EXT_STAT12" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E0" size="4" name="RESET_EXT_STAT56" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E4" size="4" name="RESET_EXT_STAT57" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04E8" size="4" name="RESET_EXT_STAT58" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-    <Register start="+0x04F0" size="4" name="RESET_EXT_STAT60" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
-    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
-        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
-        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
-      </BitField>
-      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
-        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
-        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
-      </BitField>
-      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
-      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
-      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
-        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
-        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
-    </Register>
-    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="Count" description="Counter timer value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
-        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
-      </BitField>
-      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
-        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
-        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart." />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
-        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
-      </BitField>
-      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
-        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
-      </BitField>
-      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
-      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
-      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
-      </BitField>
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
-        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
-      </BitField>
-      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
-        <Enum name="T_EQ_0" start="0" description="T = 0" />
-        <Enum name="T_EQ_1" start="1" description="T = 1" />
-      </BitField>
-      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
-      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="AAD enable">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
-        <Enum name="DISABLED" start="0" description="Disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
-        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
-        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
-      </BitField>
-      <BitField start="2" size="1" name="FES" description="Edge sampling.">
-        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
-        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
-      </BitField>
-      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
-        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
-        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
-      </BitField>
-      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
-        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
-        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
-      </BitField>
-      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
-        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
-        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
-      </BitField>
-      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
-        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
-        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
-    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
-      </BitField>
-      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
-      </BitField>
-      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
-      </BitField>
-      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
-      </BitField>
-      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
-        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
-        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
-        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
-        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
-      </BitField>
-      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
-        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
-        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
-        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
-        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
-        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
-      </BitField>
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
-      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
-      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
-        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
-      </BitField>
-      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
-        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
-      </BitField>
-      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
-      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
-        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
-        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
-        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
-        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
-    </Register>
-    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
-        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
-        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
-        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
-        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
-      </BitField>
-      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
-        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
-        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
-      </BitField>
-      <BitField start="3" size="1" name="PE" description="Parity Enable.">
-        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
-        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
-      </BitField>
-      <BitField start="4" size="2" name="PS" description="Parity Select.">
-        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
-        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
-        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
-        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
-      </BitField>
-      <BitField start="6" size="1" name="BC" description="Break Control.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
-      </BitField>
-      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
-      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
-      </BitField>
-      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
-        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
-        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
-      </BitField>
-      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
-      </BitField>
-      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
-      </BitField>
-      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
-        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
-      </BitField>
-      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
-        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
-        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
-      </BitField>
-      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
-      </BitField>
-      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
-        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
-        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
-      </BitField>
-      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
-        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
-        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
-      </BitField>
-      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
-      </BitField>
-      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
-        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
-      </BitField>
-      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
-        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
-        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
-      </BitField>
-      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
-      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
-      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
-      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
-        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
-        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
-      </BitField>
-      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
-        <Enum name="MODE_0" start="0" description="Mode 0." />
-        <Enum name="MODE_1" start="1" description="Mode 1." />
-      </BitField>
-      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
-        <Enum name="NO_RESTART" start="0" description="No restart" />
-        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
-      </BitField>
-      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
-        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
-        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
-      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
-        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
-      </BitField>
-      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
-        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
-        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
-      </BitField>
-      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
-        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SEL" description="Direction control.">
-        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
-        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
-      </BitField>
-      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
-        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
-        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
-      </BitField>
-      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
-        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
-        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
-    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
-        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
-        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
-        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
-        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
-        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
-        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
-        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
-        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
-        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
-        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
-        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
-        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
-        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
-      </BitField>
-      <BitField start="4" size="2" name="FRF" description="Frame Format.">
-        <Enum name="SPI" start="0x0" description="SPI" />
-        <Enum name="TI" start="0x1" description="TI" />
-        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
-        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
-      </BitField>
-      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
-        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
-        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
-      </BitField>
-      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
-        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
-        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
-      </BitField>
-      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
-        <Enum name="NORMAL" start="0" description="During normal operation." />
-        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
-      </BitField>
-      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
-        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
-        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
-      </BitField>
-      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
-        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
-        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
-      </BitField>
-      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
-      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
-      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
-      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
-      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
-      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
-      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
-      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
-      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
-      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
-      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
-      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
-    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
-      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
-      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
-      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
-      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
-      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
-      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
-      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
-      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
-      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="TC" description="Timer counter value." />
-    </Register>
-    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
-    </Register>
-    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
-    </Register>
-    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
-      </BitField>
-      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
-      </BitField>
-      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
-      </BitField>
-      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
-      </BitField>
-      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
-      </BitField>
-      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
-      </BitField>
-      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
-        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
-      </BitField>
-      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
-      </BitField>
-      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
-      </BitField>
-      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
-        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
-      </BitField>
-      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
-      </BitField>
-      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
-        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
-        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
-    </Register>
-    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
-      </BitField>
-      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
-      </BitField>
-      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
-      </BitField>
-      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
-      </BitField>
-      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
-        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
-        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
-      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
-        <Enum name="NOP" start="0x0" description="Do Nothing." />
-        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
-        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
-        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
-        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
-        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
-        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
-      </BitField>
-      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
-        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
-        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
-        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
-        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
-    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
-        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="SLOW" start="0" description="Slow" />
-        <Enum name="FAST" start="1" description="Fast" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="8" size="2" name="EHD" description="Select drive strength">
-        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
-      </BitField>
-      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
-        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
-        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
-        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
-        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
-      </BitField>
-      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
-        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
-        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
-        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="MODE" description="Select pin function.">
-        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
-        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
-        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
-        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
-        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
-        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
-        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
-        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
-      </BitField>
-      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
-        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
-        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-      </BitField>
-      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
-        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
-        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
-      </BitField>
-      <BitField start="5" size="1" name="EHS" description="Slew rate">
-        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
-        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
-      </BitField>
-      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
-        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
-        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
-      </BitField>
-      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
-        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
-        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
-      </BitField>
-      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
-        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
-        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
-      </BitField>
-      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
-        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
-        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
-        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
-        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
-      </BitField>
-      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
-        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
-        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
-        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
-        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
-      </BitField>
-      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
-      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
-        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
-        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
-      </BitField>
-      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
-        <Enum name="DISABLED" start="0" description="Disabled" />
-        <Enum name="ENABLED" start="1" description="Enabled" />
-      </BitField>
-      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
-        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
-        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
-      </BitField>
-      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
-        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
-      </BitField>
-    </Register>
-    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
-      </BitField>
-      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
-      </BitField>
-      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
-      </BitField>
-      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
-      </BitField>
-      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
-      </BitField>
-      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
-      </BitField>
-      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
-      </BitField>
-      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DAC" description="Select DAC">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
-        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
-      </BitField>
-      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
-        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
-        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
-      </BitField>
-    </Register>
-    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
-      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
-    </Register>
-    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
-      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
-      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
-      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
-      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
-        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
-        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
-        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
-        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
-        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
-        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
-        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
-        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
-      </BitField>
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
-    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
-    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
-        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
-        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
-      </BitField>
-      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
-        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
-        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
-      </BitField>
-      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
-        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
-        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
-    </Register>
-    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
-    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
-        <Enum name="STOP_" start="0" description="Stop." />
-        <Enum name="RUN_" start="1" description="Run." />
-      </BitField>
-      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
-        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
-        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
-      </BitField>
-      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
-        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
-        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
-      </BitField>
-      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
-        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
-        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
-      </BitField>
-      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
-        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
-        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
-      </BitField>
-      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
-        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
-        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
-      </BitField>
-      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
-        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
-        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
-      </BitField>
-      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
-        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
-        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
-      </BitField>
-    </Register>
-    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
-      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
-      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
-      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
-    </Register>
-    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MCMAT" description="Match value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
-      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
-      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
-      <BitField start="30" size="2" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
-        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
-        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
-      </BitField>
-      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
-        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
-        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
-        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
-        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
-        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
-        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
-        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
-        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
-        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
-        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
-      </BitField>
-      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
-    </Register>
-    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
-        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
-        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
-        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
-        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
-      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
-      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
-        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
-        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
-        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
-        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
-        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
-        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
-      </BitField>
-      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
-      </BitField>
-      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
-      </BitField>
-      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
-      </BitField>
-      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
-      </BitField>
-      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
-        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
-        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
-      </BitField>
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
-        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
-        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
-      </BitField>
-      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
-        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
-        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
-      </BitField>
-      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
-        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
-        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
-      </BitField>
-    </Register>
-    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
-      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
-    </Register>
-    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
-      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
-      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
-      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
-    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
-      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
-      <BitField start="4" size="1" name="STO" description="STOP flag." />
-      <BitField start="5" size="1" name="STA" description="START flag." />
-      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
-      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
-      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
-      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
-      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
-      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
-        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
-        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
-      </BitField>
-      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
-      </BitField>
-      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
-        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
-        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
-      </BitField>
-      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
-    </Register>
-    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
-      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
-      <BitField start="1" size="7" name="MASK" description="Mask bits." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
-    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
-        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
-        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
-        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
-        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
-      </BitField>
-      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
-      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
-      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
-      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
-      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
-    </Register>
-    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
-      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
-      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
-      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
-      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
-      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
-      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
-      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
-      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
-      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
-        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
-        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
-        <Enum name="RESERVED" start="0x1" description="Reserved" />
-        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
-      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
-    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
-    </Register>
-    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
-    </Register>
-    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
-        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
-        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
-      </BitField>
-      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
-        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
-        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
-      </BitField>
-      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
-        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
-        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
-      </BitField>
-      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
-        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
-        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
-    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
-      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
-      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
-      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
-      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
-      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
-      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
-      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
-      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
-      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
-      <BitField start="20" size="12" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
-      <BitField start="1" size="31" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="POS" description="Current position value." />
-    </Register>
-    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
-    </Register>
-    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
-    </Register>
-    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
-    </Register>
-    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
-    </Register>
-    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
-    </Register>
-    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
-    </Register>
-    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
-    </Register>
-    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
-    </Register>
-    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
-    </Register>
-    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
-    </Register>
-    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
-    </Register>
-    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
-    </Register>
-    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
-    </Register>
-    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
-    </Register>
-    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
-      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
-      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
-      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
-      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
-      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
-      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
-      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
-      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
-      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
-      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
-      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
-      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
-      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
-      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
-      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
-    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="SGPIO3_DIV" start="0x1" description="SGPIO3_DIV" />
-        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
-        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
-        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
-        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO12_DIV" start="0x1" description="SGPIO12_DIV" />
-        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
-        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
-        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
-        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
-        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
-        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
-        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
-        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
-        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="SGPIO3_DIV" start="0x2" description="SGPIO3_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
-        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
-        <Enum name="SGPIO12" start="0x2" description="SGPIO12" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
-        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
-        <Enum name="RESERVED" start="0x2" description="Reserved" />
-        <Enum name="RESERVED" start="0x3" description="Reserved" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
-        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
-        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
-        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
-        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
-        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
-        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
-        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
-        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
-        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
-        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
-        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
-        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x060" size="4" name="ADCHS_TRIGGER_IN" access="Read/Write" description="ADCHS trigger input multiplexer (GIMA output 24)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0xA to 0xF are reserved.">
-        <Enum name="GPIO6_28" start="0x0" description="GPIO6[28]" />
-        <Enum name="GPIO5_3" start="0x1" description="GPIO5[3]" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO12" start="0x3" description="SGPIO12" />
-        <Enum name="RESERVED" start="0x4" description="Reserved" />
-        <Enum name="MCOB2" start="0x5" description="MCOB2" />
-        <Enum name="CTOUT_0_OR_T0_MAT0" start="0x6" description="CTOUT_0 or T0_MAT0" />
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x7" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T0_MAT0" start="0x8" description="T0_MAT0" />
-        <Enum name="T2_MAT0" start="0x9" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
-        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
-        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
-        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
-        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
-        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
-        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
-        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INV" description="Invert input">
-        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
-        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
-      </BitField>
-      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
-        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
-        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
-      </BitField>
-      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
-        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
-        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
-      </BitField>
-      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
-        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
-        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
-      </BitField>
-      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
-        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
-        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
-      <BitField start="16" size="1" name="BIAS" description="Settling time">
-        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
-        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
-      </BitField>
-      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
-        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
-        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
-      </BitField>
-      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
-        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
-        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
-      </BitField>
-      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
-        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
-        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
-      </BitField>
-      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
-        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
-        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
-      </BitField>
-      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
-    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="INIT" description="Initialization">
-        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
-        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
-        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
-      </BitField>
-      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
-        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
-        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
-      </BitField>
-      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
-        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
-        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
-      </BitField>
-      <BitField start="4" size="1" name="RESERVED" description="reserved" />
-      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
-        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
-        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
-      </BitField>
-      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
-        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
-        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
-      </BitField>
-      <BitField start="7" size="1" name="TEST" description="Test mode enable">
-        <Enum name="TEST_MODE_" start="1" description="Test mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
-        <Enum name="NO_ERROR_" start="0x0" description="No error." />
-        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
-        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
-        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
-        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
-        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
-        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
-        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
-      </BitField>
-      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
-        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
-        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
-      </BitField>
-      <BitField start="5" size="1" name="EPASS" description="Error passive">
-        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
-        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
-      </BitField>
-      <BitField start="6" size="1" name="EWARN" description="Warning status">
-        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
-        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
-      </BitField>
-      <BitField start="7" size="1" name="BOFF" description="Busoff status">
-        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
-        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
-      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
-      <BitField start="15" size="1" name="RP" description="Receive error passive">
-        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
-        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
-      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
-      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
-      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
-      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="2" name="RESERVED" description="tbd." />
-      <BitField start="2" size="1" name="BASIC" description="Basic mode">
-        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
-        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
-      </BitField>
-      <BitField start="3" size="1" name="SILENT" description="Silent mode">
-        <Enum name="SILENT" start="1" description="The module is in silent mode." />
-        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
-      </BitField>
-      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
-        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
-        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
-      </BitField>
-      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
-        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
-        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
-        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
-        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
-      </BitField>
-      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
-        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
-        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
-      </BitField>
-      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
-      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
-      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
-        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
-        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
-        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
-      </BitField>
-      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
-        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
-        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
-      </BitField>
-      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
-        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
-        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
-      </BitField>
-      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
-        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
-        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
-      </BitField>
-      <BitField start="4" size="1" name="CTRL" description="Access control bits">
-        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
-        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
-      </BitField>
-      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
-        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
-        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
-      </BitField>
-      <BitField start="6" size="1" name="MASK" description="Access mask bits">
-        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
-        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
-      </BitField>
-      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
-      <BitField start="8" size="24" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="16" size="16" name="RESERVED" description="reserved" />
-    </Register>
-    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
-      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
-      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
-        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
-        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
-        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
-        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
-      <BitField start="13" size="1" name="DIR" description="Message direction">
-        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
-        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
-      </BitField>
-      <BitField start="14" size="1" name="XTD" description="Extend identifier">
-        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
-        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
-      </BitField>
-      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
-        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
-        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
-      <BitField start="4" size="3" name="RESERVED" description="reserved" />
-      <BitField start="7" size="1" name="EOB" description="End of buffer">
-        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
-        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
-      </BitField>
-      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
-        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
-        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
-      </BitField>
-      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
-        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
-        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
-      </BitField>
-      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
-      </BitField>
-      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
-        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
-        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
-      </BitField>
-      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
-        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
-        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
-      </BitField>
-      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
-        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
-        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
-      </BitField>
-      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
-        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
-      </BitField>
-      <BitField start="15" size="1" name="NEWDAT" description="New data">
-        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
-        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
-      </BitField>
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
-      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
-      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
-      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
-      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
-      <BitField start="4" size="28" name="RESERVED" description="reserved" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
-      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
-      <BitField start="16" size="1" name="BURST" description="Burst mode">
-        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
-        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
-      </BitField>
-      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
-        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
-        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
-        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
-        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
-        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
-        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
-        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
-        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
-      </BitField>
-      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="21" size="1" name="PDN" description="Power mode">
-        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
-        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
-      </BitField>
-      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
-        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
-        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
-        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
-        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
-        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
-        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
-        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
-        <Enum name="RESERVED_" start="0x7" description="Reserved." />
-      </BitField>
-      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
-        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
-        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
-      </BitField>
-      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
-      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
-    </Register>
-    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
-      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
-      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
-      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
-      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
-      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
-    </Register>
-    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
-      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
-      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
-      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="ADCHS" start="0x400F0000" description="12-bit Analog-to-Digital Converter  High-Speed (ADCHS)">
-    <Register start="+0x0000" size="4" name="FLUSH" access="WriteOnly" description="Flushes FIFO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFO_FLUSH" description="1= fifo is cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0004" size="4" name="DMA_REQ" access="Read/Write" description="Set or clear DMA write request" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DMA_REQ_WR" description="1 = Dma_req_wr is set (initially used to fill second table),  0 = Dma_req_wr is cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0008" size="4" name="FIFO_STS" access="ReadOnly" description="Indicates FIFO fill level status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="5" name="LEVEL" description="0 = FIFO is empty  1...15 = FIFO is partially full  16 = FIFO is full" />
-      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x000C" size="4" name="FIFO_CFG" access="Read/Write" description="Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PACKED_READ" description="0 = one sample is packed in one 32-bit read cycle  1 = two samples are packed in one 32-bit read cycle" />
-      <BitField start="1" size="5" name="LEVEL" description="When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." />
-      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0010" size="4" name="TRIGGER" access="WriteOnly" description="Enable software trigger to start descriptor processing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SW_TRIGGER" description="Auto cleared" />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0014" size="4" name="DSCR_STS" access="Read/Write" description="Indicates active descriptor table and descriptor entry" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="ACT_TABLE" description="0 = table 0 is active  1 = table 1 is active." />
-      <BitField start="1" size="3" name="ACT_DESCRIPTOR" description="ID of the descriptor that is active." />
-      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0018" size="4" name="POWER_DOWN" access="Read/Write" description="Set or clear power down mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PD_CTRL" description="0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set.   1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." />
-      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x001C" size="4" name="CONFIG" access="Read/Write" description="Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." reset_value="0x00002400" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="TRIGGER__MASK" description="00 = triggers off  01 = software trigger only  10 = external trigger only  11 = both triggers allowed" />
-      <BitField start="2" size="2" name="TRIGGER_MODE" description="00 = rising external trigger  01 = falling external trigger  10 = low external trigger  11 = high external trigger" />
-      <BitField start="4" size="1" name="TRIGGER_SYNC" description="0  = do not synchronize external  trigger input  1 = synchronize external  trigger input" />
-      <BitField start="5" size="1" name="CHANNEL_ID_EN" description="0 = do not add channel ID to FIFO output data  1 = add channel ID to FIFO output data" />
-      <BitField start="6" size="8" name="RECOVERY_TIME" description="ADC recovery time from power down" />
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0020" size="4" name="THR_A" access="Read/Write" description="Configures window comparator A levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="THR_LOW_A" description="Low Compare Threshold Register A:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="16" size="12" name="THR_HIGH_A" description="High Compare Threshold Register A:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0024" size="4" name="THR_B" access="Read/Write" description="Configures window comparator B levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="THR_LOW_B" description="Low Compare Threshold Register B:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="16" size="12" name="THR_HIGH_B" description="High Compare Threshold Register B:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
-      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0028+0" size="4" name="LAST_SAMPLE[0]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+4" size="4" name="LAST_SAMPLE[1]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+8" size="4" name="LAST_SAMPLE[2]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+12" size="4" name="LAST_SAMPLE[3]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+16" size="4" name="LAST_SAMPLE[4]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0028+20" size="4" name="LAST_SAMPLE[5]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
-      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
-      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
-      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
-      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
-      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
-      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0104" size="4" name="ADC_SPEED" access="Read/Write" description="ADC speed control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="DGEC0" description="Speed0" />
-      <BitField start="4" size="4" name="DGEC1" description="Speed1" />
-      <BitField start="8" size="4" name="DGEC2" description="Speed2" />
-      <BitField start="12" size="4" name="DGEC3" description="Speed3" />
-      <BitField start="16" size="4" name="DGEC4" description="Speed4" />
-      <BitField start="20" size="4" name="DGEC5" description="Speed5" />
-      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0108" size="4" name="POWER_CONTROL" access="Read/Write" description="Configures ADC power vs. speed, DC-in biasing, output format and power gating." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="CRS" description="current setting for power versus speed programming" />
-      <BitField start="4" size="6" name="DCINNEG" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_neg side" />
-      <BitField start="10" size="6" name="DCINPOS" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_pos side" />
-      <BitField start="16" size="1" name="TWOS" description="Output data format selection  0 = offset binary  1 = two's complement" />
-      <BitField start="17" size="1" name="POWER_SWITCH" description="0 = ADC is powered down 1 = ADC is active" />
-      <BitField start="18" size="1" name="BGAP_SWITCH" description="0 = ADC band gap reference is powered down  1 = ADC band gap reference is active" />
-      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0200+0" size="4" name="FIFO_OUTPUT[0]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+4" size="4" name="FIFO_OUTPUT[1]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+8" size="4" name="FIFO_OUTPUT[2]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+12" size="4" name="FIFO_OUTPUT[3]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+16" size="4" name="FIFO_OUTPUT[4]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+20" size="4" name="FIFO_OUTPUT[5]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+24" size="4" name="FIFO_OUTPUT[6]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+28" size="4" name="FIFO_OUTPUT[7]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+32" size="4" name="FIFO_OUTPUT[8]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+36" size="4" name="FIFO_OUTPUT[9]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+40" size="4" name="FIFO_OUTPUT[10]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+44" size="4" name="FIFO_OUTPUT[11]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+48" size="4" name="FIFO_OUTPUT[12]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+52" size="4" name="FIFO_OUTPUT[13]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+56" size="4" name="FIFO_OUTPUT[14]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0200+60" size="4" name="FIFO_OUTPUT[15]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
-      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
-      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
-      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
-      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
-      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
-    </Register>
-    <Register start="+0x0300+0" size="4" name="DESCRIPTOR0_[0]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+4" size="4" name="DESCRIPTOR0_[1]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+8" size="4" name="DESCRIPTOR0_[2]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+12" size="4" name="DESCRIPTOR0_[3]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+16" size="4" name="DESCRIPTOR0_[4]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+20" size="4" name="DESCRIPTOR0_[5]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+24" size="4" name="DESCRIPTOR0_[6]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0300+28" size="4" name="DESCRIPTOR0_[7]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+0" size="4" name="DESCRIPTOR1_[0]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+4" size="4" name="DESCRIPTOR1_[1]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+8" size="4" name="DESCRIPTOR1_[2]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+12" size="4" name="DESCRIPTOR1_[3]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+16" size="4" name="DESCRIPTOR1_[4]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+20" size="4" name="DESCRIPTOR1_[5]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+24" size="4" name="DESCRIPTOR1_[6]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0320+28" size="4" name="DESCRIPTOR1_[7]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
-      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
-      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
-      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
-      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
-      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
-      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
-      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
-      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
-      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
-    </Register>
-    <Register start="+0x0F00" size="4" name="CLR_EN0" access="WriteOnly" description="Interrupt 0 clear mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CEN0" description="Interrupt clear enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F04" size="4" name="SET_EN0" access="WriteOnly" description="Interrupt 0 set mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SEN0" description="Interrupt set enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F08" size="4" name="MASK0" access="ReadOnly" description="Interrupt 0 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="M0" description="Interrupt enable" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F0C" size="4" name="STATUS0" access="ReadOnly" description="Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="FIFO_FULL" description="0: number of samples in FIFO less than or equal to FIFO_LEVEL  1: number of samples in FIFO is more than FIFO_LEVEL" />
-      <BitField start="1" size="1" name="FIFO_EMPTY" description="0: FIFO is not empty   1: FIFO is empty" />
-      <BitField start="2" size="1" name="FIFO_OVERFLOW" description="FIFO was full; conversion sample is not stored  and lost" />
-      <BitField start="3" size="1" name="DSCR_DONE" description="The descriptor INTERRUPT field was enabled and its sample is converted." />
-      <BitField start="4" size="1" name="DSCR_ERROR" description="The ADC was not fully woken up when a sample was converted and the conversion results is unreliable" />
-      <BitField start="5" size="1" name="ADC_OVF" description="Converted sample value was over range of the 12 bit output code." />
-      <BitField start="6" size="1" name="ADC_UNF" description="Converted sample value was under range of the 12 bit output code." />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F10" size="4" name="CLR_STAT0" access="WriteOnly" description="Interrupt 0 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="CSTAT0" description="Interrupt clear status" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F14" size="4" name="SET_STAT0" access="WriteOnly" description="Interrupt 0 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="7" name="SSTAT0" description="Interrupt set status" />
-      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F20" size="4" name="CLR_EN1" access="WriteOnly" description="Interrupt 1 mask clear enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="CEN1" description="Interrupt clear enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F24" size="4" name="SET_EN1" access="WriteOnly" description="Interrupt 1 mask set enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SEN1" description="Interrupt set enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F28" size="4" name="MASK1" access="ReadOnly" description="Interrupt 1 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="M1" description="Interrupt enable" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0F2C" size="4" name="STATUS1" access="ReadOnly" description="Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="THCMP_BRANGE0" description="Input channel 0 result below  range" />
-      <BitField start="1" size="1" name="THCMP_ARANGE0" description="Input channel 0 result above range" />
-      <BitField start="2" size="1" name="THCMP_DCROSS0" description="Input channel 0 result  downward threshold crossing detected" />
-      <BitField start="3" size="1" name="THCMP_UCROSS0" description="Input channel 0 result upward threshold crossing detected" />
-      <BitField start="4" size="1" name="OVERRUN_0" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [0]  before it has been read" />
-      <BitField start="5" size="1" name="THCMP_BRANGE1" description="Input channel 1 result below  range" />
-      <BitField start="6" size="1" name="THCMP_ARANGE1" description="Input channel 1 result above range" />
-      <BitField start="7" size="1" name="THCMP_DCROSS1" description="Input channel 1 result  downward threshold crossing detected" />
-      <BitField start="8" size="1" name="THCMP_UCROSS1" description="Input channel 1 result upward threshold crossing detected" />
-      <BitField start="9" size="1" name="OVERRUN_1" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [1]  before it has been read" />
-      <BitField start="10" size="1" name="THCMP_BRANGE2" description="Input channel 2 result below  range" />
-      <BitField start="11" size="1" name="THCMP_ARANGE2" description="Input channel 2 result above range" />
-      <BitField start="12" size="1" name="THCMP_DCROSS2" description="Input channel 2 result  downward threshold crossing detected" />
-      <BitField start="13" size="1" name="THCMP_UCROSS2" description="Input channel 2 result upward threshold crossing detected" />
-      <BitField start="14" size="1" name="OVERRUN_2" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [2]  before it has been read" />
-      <BitField start="15" size="1" name="THCMP_BRANGE3" description="Input channel 3 result below  range" />
-      <BitField start="16" size="1" name="THCMP_ARANGE3" description="Input channel 3 result above range" />
-      <BitField start="17" size="1" name="THCMP_DCROSS3" description="Input channel 3 result  downward threshold crossing detected" />
-      <BitField start="18" size="1" name="THCMP_UCROSS3" description="Input channel 3 result upward threshold crossing detected" />
-      <BitField start="19" size="1" name="OVERRUN_3" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [3]  before it has been read" />
-      <BitField start="20" size="1" name="THCMP_BRANGE4" description="Input channel 4 result below  range" />
-      <BitField start="21" size="1" name="THCMP_ARANGE4" description="Input channel 4 result above range" />
-      <BitField start="22" size="1" name="THCMP_DCROSS4" description="Input channel 4 result  downward threshold crossing detected" />
-      <BitField start="23" size="1" name="THCMP_UCROSS4" description="Input channel 4 result upward threshold crossing detected" />
-      <BitField start="24" size="1" name="OVERRUN_4" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [4]  before it has been read" />
-      <BitField start="25" size="1" name="THCMP_BRANGE5" description="Input channel 5 result below  range" />
-      <BitField start="26" size="1" name="THCMP_ARANGE5" description="Input channel 5 result above range" />
-      <BitField start="27" size="1" name="THCMP_DCROSS5" description="Input channel 5 result  downward threshold crossing detected" />
-      <BitField start="28" size="1" name="THCMP_UCROSS5" description="Input channel 5 result upward threshold crossing detected" />
-      <BitField start="29" size="1" name="OVERRUN_5" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [5]  before it has been read" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F30" size="4" name="CLR_STAT1" access="WriteOnly" description="Interrupt 1 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="CSTAT1" description="Interrupt clear status" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F34" size="4" name="SET_STAT1" access="WriteOnly" description="Interrupt 1 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="30" name="SSTAT1" description="Interrupt set status" />
-      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
-    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
-      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
-    </Register>
-    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
-    </Register>
-    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
-    </Register>
-    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
-    </Register>
-    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
-    </Register>
-    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
-    </Register>
-    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
-    </Register>
-    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
-    </Register>
-    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
-      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SPI" start="0x40100000" description="SPI ">
-    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
-        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
-      </BitField>
-      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
-        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
-        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
-      </BitField>
-      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
-        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
-        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
-      </BitField>
-      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
-        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
-        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
-      </BitField>
-      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
-        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
-        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
-      </BitField>
-      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
-        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
-        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
-      </BitField>
-      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
-        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
-        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
-        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
-        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
-        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
-        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
-        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
-        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
-        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
-      </BitField>
-      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
-      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x010" size="4" name="TCR" access="Read/Write" description="SPI Test Control register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="1" size="7" name="TEST" description="SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x014" size="4" name="TSR" access="Read/Write" description="SPI Test Status register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="3" size="1" name="ABRT" description="Slave abort." />
-      <BitField start="4" size="1" name="MODF" description="Mode fault." />
-      <BitField start="5" size="1" name="ROVR" description="Read overrun." />
-      <BitField start="6" size="1" name="WCOL" description="Write collision." />
-      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
-      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SGPIO" start="0x40101000" description="Serial GPIO (SGPIO)">
-    <Register start="+0x0000+0" size="4" name="OUT_MUX_CFG[0]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+4" size="4" name="OUT_MUX_CFG[1]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+8" size="4" name="OUT_MUX_CFG[2]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+12" size="4" name="OUT_MUX_CFG[3]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+16" size="4" name="OUT_MUX_CFG[4]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+20" size="4" name="OUT_MUX_CFG[5]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+24" size="4" name="OUT_MUX_CFG[6]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+28" size="4" name="OUT_MUX_CFG[7]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+32" size="4" name="OUT_MUX_CFG[8]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+36" size="4" name="OUT_MUX_CFG[9]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+40" size="4" name="OUT_MUX_CFG[10]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+44" size="4" name="OUT_MUX_CFG[11]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+48" size="4" name="OUT_MUX_CFG[12]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+52" size="4" name="OUT_MUX_CFG[13]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+56" size="4" name="OUT_MUX_CFG[14]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0000+60" size="4" name="OUT_MUX_CFG[15]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
-        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
-        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
-        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
-        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
-        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
-        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
-        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
-        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
-        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
-        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
-        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
-        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
-      </BitField>
-      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
-        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
-        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
-        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
-        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
-        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
-      </BitField>
-      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0040+0" size="4" name="SGPIO_MUX_CFG[0]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+4" size="4" name="SGPIO_MUX_CFG[1]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+8" size="4" name="SGPIO_MUX_CFG[2]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+12" size="4" name="SGPIO_MUX_CFG[3]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+16" size="4" name="SGPIO_MUX_CFG[4]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+20" size="4" name="SGPIO_MUX_CFG[5]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+24" size="4" name="SGPIO_MUX_CFG[6]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+28" size="4" name="SGPIO_MUX_CFG[7]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+32" size="4" name="SGPIO_MUX_CFG[8]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+36" size="4" name="SGPIO_MUX_CFG[9]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+40" size="4" name="SGPIO_MUX_CFG[10]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+44" size="4" name="SGPIO_MUX_CFG[11]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+48" size="4" name="SGPIO_MUX_CFG[12]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+52" size="4" name="SGPIO_MUX_CFG[13]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+56" size="4" name="SGPIO_MUX_CFG[14]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0040+60" size="4" name="SGPIO_MUX_CFG[15]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
-        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
-        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
-      </BitField>
-      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
-        <Enum name="SLICE_D" start="0x0" description="Slice D" />
-        <Enum name="SLICE_H" start="0x1" description="Slice H" />
-        <Enum name="SLICE_O" start="0x2" description="Slice O" />
-        <Enum name="SLICE_P" start="0x3" description="Slice P" />
-      </BitField>
-      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
-        <Enum name="ENABLE" start="0x0" description="Enable" />
-        <Enum name="DISABLE" start="0x1" description="Disable" />
-        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
-        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
-      </BitField>
-      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
-        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
-        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
-        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
-        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
-      </BitField>
-      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
-        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
-        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
-        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
-        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
-      </BitField>
-      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
-        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
-        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
-      </BitField>
-      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
-        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
-        <Enum name="2_SLICES" start="0x1" description="2 slices" />
-        <Enum name="4_SLICES" start="0x2" description="4 slices" />
-        <Enum name="8_SLICES" start="0x3" description="8 slices" />
-      </BitField>
-      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
-    </Register>
-    <Register start="+0x0080+0" size="4" name="SLICE_MUX_CFG[0]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+4" size="4" name="SLICE_MUX_CFG[1]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+8" size="4" name="SLICE_MUX_CFG[2]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+12" size="4" name="SLICE_MUX_CFG[3]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+16" size="4" name="SLICE_MUX_CFG[4]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+20" size="4" name="SLICE_MUX_CFG[5]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+24" size="4" name="SLICE_MUX_CFG[6]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+28" size="4" name="SLICE_MUX_CFG[7]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+32" size="4" name="SLICE_MUX_CFG[8]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+36" size="4" name="SLICE_MUX_CFG[9]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+40" size="4" name="SLICE_MUX_CFG[10]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+44" size="4" name="SLICE_MUX_CFG[11]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+48" size="4" name="SLICE_MUX_CFG[12]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+52" size="4" name="SLICE_MUX_CFG[13]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+56" size="4" name="SLICE_MUX_CFG[14]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0080+60" size="4" name="SLICE_MUX_CFG[15]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
-        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
-        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
-      </BitField>
-      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
-        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
-        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
-      </BitField>
-      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
-        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
-        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
-      </BitField>
-      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
-        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
-        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
-      </BitField>
-      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
-        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
-        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
-        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
-        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
-      </BitField>
-      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
-        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
-        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
-        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
-        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
-      </BitField>
-      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
-        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
-        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
-      </BitField>
-      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x00C0+0" size="4" name="REG[0]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+4" size="4" name="REG[1]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+8" size="4" name="REG[2]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+12" size="4" name="REG[3]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+16" size="4" name="REG[4]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+20" size="4" name="REG[5]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+24" size="4" name="REG[6]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+28" size="4" name="REG[7]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+32" size="4" name="REG[8]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+36" size="4" name="REG[9]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+40" size="4" name="REG[10]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+44" size="4" name="REG[11]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+48" size="4" name="REG[12]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+52" size="4" name="REG[13]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+56" size="4" name="REG[14]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x00C0+60" size="4" name="REG[15]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
-    </Register>
-    <Register start="+0x0100+0" size="4" name="REG_SS[0]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+4" size="4" name="REG_SS[1]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+8" size="4" name="REG_SS[2]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+12" size="4" name="REG_SS[3]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+16" size="4" name="REG_SS[4]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+20" size="4" name="REG_SS[5]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+24" size="4" name="REG_SS[6]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+28" size="4" name="REG_SS[7]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+32" size="4" name="REG_SS[8]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+36" size="4" name="REG_SS[9]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+40" size="4" name="REG_SS[10]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+44" size="4" name="REG_SS[11]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+48" size="4" name="REG_SS[12]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+52" size="4" name="REG_SS[13]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+56" size="4" name="REG_SS[14]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0100+60" size="4" name="REG_SS[15]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
-    </Register>
-    <Register start="+0x0140+0" size="4" name="PRESET[0]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+4" size="4" name="PRESET[1]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+8" size="4" name="PRESET[2]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+12" size="4" name="PRESET[3]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+16" size="4" name="PRESET[4]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+20" size="4" name="PRESET[5]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+24" size="4" name="PRESET[6]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+28" size="4" name="PRESET[7]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+32" size="4" name="PRESET[8]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+36" size="4" name="PRESET[9]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+40" size="4" name="PRESET[10]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+44" size="4" name="PRESET[11]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+48" size="4" name="PRESET[12]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+52" size="4" name="PRESET[13]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+56" size="4" name="PRESET[14]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0140+60" size="4" name="PRESET[15]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+0" size="4" name="COUNT[0]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+4" size="4" name="COUNT[1]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+8" size="4" name="COUNT[2]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+12" size="4" name="COUNT[3]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+16" size="4" name="COUNT[4]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+20" size="4" name="COUNT[5]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+24" size="4" name="COUNT[6]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+28" size="4" name="COUNT[7]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+32" size="4" name="COUNT[8]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+36" size="4" name="COUNT[9]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+40" size="4" name="COUNT[10]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+44" size="4" name="COUNT[11]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+48" size="4" name="COUNT[12]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+52" size="4" name="COUNT[13]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+56" size="4" name="COUNT[14]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0180+60" size="4" name="COUNT[15]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
-      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+0" size="4" name="POS[0]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+4" size="4" name="POS[1]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+8" size="4" name="POS[2]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+12" size="4" name="POS[3]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+16" size="4" name="POS[4]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+20" size="4" name="POS[5]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+24" size="4" name="POS[6]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+28" size="4" name="POS[7]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+32" size="4" name="POS[8]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+36" size="4" name="POS[9]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+40" size="4" name="POS[10]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+44" size="4" name="POS[11]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+48" size="4" name="POS[12]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+52" size="4" name="POS[13]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+56" size="4" name="POS[14]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x01C0+60" size="4" name="POS[15]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
-      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0200" size="4" name="MASK_A" access="Read/Write" description="Mask for pattern match function of slice A" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_A" description="Mask for pattern match function of slice A  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0204" size="4" name="MASK_H" access="Read/Write" description="Mask for pattern match function of slice H" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_H" description="Mask for pattern match function of slice H  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0208" size="4" name="MASK_I" access="Read/Write" description="Mask for pattern match function of slice I" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_I" description="Mask for pattern match function of slice I  0 = No effect . 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x020C" size="4" name="MASK_P" access="Read/Write" description="Mask for pattern match function of slice P" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="32" name="MASK_P" description="Mask for pattern match function of slice P  0 = No effect. 1 = Mask this bit." />
-    </Register>
-    <Register start="+0x0210" size="4" name="GPIO_INREG" access="ReadOnly" description="GPIO input status register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_INi" description="Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0214" size="4" name="GPIO_OUTREG" access="Read/Write" description="GPIO output control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_OUT" description="GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0218" size="4" name="GPIO_OENREG" access="Read/Write" description="GPIO OE control register" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="GPIO_OE" description="Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x021C" size="4" name="CTRL_ENABLE" access="Read/Write" description="Enables the slice COUNT counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTRL_EN" description="Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0220" size="4" name="CTRL_DISABLE" access="Read/Write" description="Disables the slice POS counter" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CTRL_DIS" description="Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F00" size="4" name="CLR_EN_0" access="WriteOnly" description="Shift clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_SCI" description="1 = Shift clock interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F04" size="4" name="SET_EN_0" access="WriteOnly" description="Shift clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_SCI" description="1 = Shift clock interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F08" size="4" name="ENABLE_0" access="ReadOnly" description="Shift clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_SCI" description="1 = Shift clock interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F0C" size="4" name="STATUS_0" access="ReadOnly" description="Shift clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_SCI" description="Shift clock interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F10" size="4" name="CLR_STATUS_0" access="WriteOnly" description="Shift clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_SCI" description="Shift clock interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F14" size="4" name="SET_STATUS_0" access="WriteOnly" description="Shift clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_SCI" description="Shift clock interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F20" size="4" name="CLR_EN_1" access="WriteOnly" description="Exchange clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN_CCI" description="1 = Exchange clock interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F24" size="4" name="SET_EN_1" access="WriteOnly" description="Exchange clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_CCI" description="1 = Exchange clock interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F28" size="4" name="ENABLE_1" access="ReadOnly" description="Exchange clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_CCI" description="Exchange clock interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F2C" size="4" name="STATUS_1" access="ReadOnly" description="Exchange clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_CCI" description="Exchange clock interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F30" size="4" name="CLR_STATUS_1" access="WriteOnly" description="Exchange clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_CCI" description="Exchange clock interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F34" size="4" name="SET_STATUS_1" access="WriteOnly" description="Exchange clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_CCI" description="Exchange clock interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F40" size="4" name="CLR_EN_2" access="WriteOnly" description="Pattern match interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN2_PMI" description="1 = Match interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F44" size="4" name="SET_EN_2" access="WriteOnly" description="Pattern match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_PMI" description="1 = Match interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F48" size="4" name="ENABLE_2" access="ReadOnly" description="Pattern match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE_PMI" description="Match interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F4C" size="4" name="STATUS_2" access="ReadOnly" description="Pattern match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_PMI" description="Match interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F50" size="4" name="CLR_STATUS_2" access="WriteOnly" description="Pattern match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_PMI" description="Match interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F54" size="4" name="SET_STATUS_2" access="WriteOnly" description="Pattern match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_PMI" description="Match interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F60" size="4" name="CLR_EN_3" access="WriteOnly" description="Input interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_EN_INPI" description="1 = Input interrupt clear mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F64" size="4" name="SET_EN_3" access="WriteOnly" description="Input bit match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_EN_INPI" description="1 = Input interrupt set mask of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F68" size="4" name="ENABLE_3" access="ReadOnly" description="Input bit match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="ENABLE3_INPI" description="Input interrupt enable of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F6C" size="4" name="STATUS_3" access="ReadOnly" description="Input bit match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="STATUS_INPI" description="Input interrupt status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F70" size="4" name="CLR_STATUS_3" access="WriteOnly" description="Input bit match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="CLR_STATUS_INPI" description="Input interrupt clear status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-    <Register start="+0x0F74" size="4" name="SET_STATUS_3" access="WriteOnly" description="Input bit match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
-      <BitField start="0" size="16" name="SET_STATUS_INPI" description="Shift interrupt set status of slice n." />
-      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
-    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
-      <BitField name="DAC" start="0" size="1" />
-      <BitField name="DMA" start="2" size="1" />
-      <BitField name="FLASH" start="4" size="1" />
-      <BitField name="ETHERNET" start="5" size="1" />
-      <BitField name="SDIO" start="6" size="1" />
-      <BitField name="LCD" start="7" size="1" />
-      <BitField name="USB0" start="8" size="1" />
-      <BitField name="USB1" start="9" size="1" />
-      <BitField name="SCT" start="10" size="1" />
-      <BitField name="RITIMER" start="11" size="1" />
-      <BitField name="TIMER0" start="12" size="1" />
-      <BitField name="TIMER1" start="13" size="1" />
-      <BitField name="TIMER2" start="14" size="1" />
-      <BitField name="TIMER3" start="15" size="1" />
-      <BitField name="MCPWM" start="16" size="1" />
-      <BitField name="ADC0" start="17" size="1" />
-      <BitField name="I2C0" start="18" size="1" />
-      <BitField name="I2C1" start="19" size="1" />
-      <BitField name="SPI_INT" start="20" size="1" />
-      <BitField name="ADC1" start="21" size="1" />
-      <BitField name="SSP0" start="22" size="1" />
-      <BitField name="SSP1" start="23" size="1" />
-      <BitField name="USART0" start="24" size="1" />
-      <BitField name="UART1" start="25" size="1" />
-      <BitField name="USART2" start="26" size="1" />
-      <BitField name="USART3" start="27" size="1" />
-      <BitField name="I2S0" start="28" size="1" />
-      <BitField name="I2S1" start="29" size="1" />
-      <BitField name="SPIFI" start="30" size="1" />
-      <BitField name="SGPIO_IINT" start="31" size="1" />
-    </Register>
-    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
-      <BitField name="PIN_INT0" start="0" size="1" />
-      <BitField name="PIN_INT1" start="1" size="1" />
-      <BitField name="PIN_INT2" start="2" size="1" />
-      <BitField name="PIN_INT3" start="3" size="1" />
-      <BitField name="PIN_INT4" start="4" size="1" />
-      <BitField name="PIN_INT5" start="5" size="1" />
-      <BitField name="PIN_INT6" start="6" size="1" />
-      <BitField name="PIN_INT7" start="7" size="1" />
-      <BitField name="GINT0" start="8" size="1" />
-      <BitField name="GINT1" start="9" size="1" />
-      <BitField name="EVENTROUTER" start="10" size="1" />
-      <BitField name="C_CAN1" start="11" size="1" />
-      <BitField name="ADCHS" start="13" size="1" />
-      <BitField name="ATIMER" start="14" size="1" />
-      <BitField name="RTC" start="15" size="1" />
-      <BitField name="WWDT" start="17" size="1" />
-      <BitField name="C_CAN0" start="19" size="1" />
-      <BitField name="QEI" start="20" size="1" />
-    </Register>
-    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
-      <BitField name="DAC" start="5" size="3" />
-      <BitField name="DMA" start="21" size="3" />
-    </Register>
-    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
-      <BitField name="FLASH" start="5" size="3" />
-      <BitField name="ETHERNET" start="13" size="3" />
-      <BitField name="SDIO" start="21" size="3" />
-      <BitField name="LCD" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
-      <BitField name="USB0" start="5" size="3" />
-      <BitField name="USB1" start="13" size="3" />
-      <BitField name="SCT" start="21" size="3" />
-      <BitField name="RITIMER" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
-      <BitField name="TIMER0" start="5" size="3" />
-      <BitField name="TIMER1" start="13" size="3" />
-      <BitField name="TIMER2" start="21" size="3" />
-      <BitField name="TIMER3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
-      <BitField name="MCPWM" start="5" size="3" />
-      <BitField name="ADC0" start="13" size="3" />
-      <BitField name="I2C0" start="21" size="3" />
-      <BitField name="I2C1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
-      <BitField name="SPI_INT" start="5" size="3" />
-      <BitField name="ADC1" start="13" size="3" />
-      <BitField name="SSP0" start="21" size="3" />
-      <BitField name="SSP1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
-      <BitField name="USART0" start="5" size="3" />
-      <BitField name="UART1" start="13" size="3" />
-      <BitField name="USART2" start="21" size="3" />
-      <BitField name="USART3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
-      <BitField name="I2S0" start="5" size="3" />
-      <BitField name="I2S1" start="13" size="3" />
-      <BitField name="SPIFI" start="21" size="3" />
-      <BitField name="SGPIO_IINT" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
-      <BitField name="PIN_INT0" start="5" size="3" />
-      <BitField name="PIN_INT1" start="13" size="3" />
-      <BitField name="PIN_INT2" start="21" size="3" />
-      <BitField name="PIN_INT3" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
-      <BitField name="PIN_INT4" start="5" size="3" />
-      <BitField name="PIN_INT5" start="13" size="3" />
-      <BitField name="PIN_INT6" start="21" size="3" />
-      <BitField name="PIN_INT7" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
-      <BitField name="GINT0" start="5" size="3" />
-      <BitField name="GINT1" start="13" size="3" />
-      <BitField name="EVENTROUTER" start="21" size="3" />
-      <BitField name="C_CAN1" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
-      <BitField name="ADCHS" start="13" size="3" />
-      <BitField name="ATIMER" start="21" size="3" />
-      <BitField name="RTC" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
-      <BitField name="WWDT" start="13" size="3" />
-      <BitField name="C_CAN0" start="29" size="3" />
-    </Register>
-    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
-      <BitField name="QEI" start="5" size="3" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
-    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
-      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
-      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
-      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
-    </Register>
-    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
-      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
-    </Register>
-    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
-      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
-    </Register>
-    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
-      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
-      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
-      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="SCB" start="" description="System Control Block">
-    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
-      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
-      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
-      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
-      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
-    </Register>
-    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
-      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
-      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
-      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
-      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
-    </Register>
-    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
-      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
-      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
-      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
-      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
-      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
-      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
-      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
-      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
-      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
-      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
-    </Register>
-    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
-      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
-    </Register>
-    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
-      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
-      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
-      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
-      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
-      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
-      <BitField name="VECTRESET" start="0" size="1" description="" />
-    </Register>
-    <Register name="SCR" start="0xE000ED10" description="System Control Register">
-      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
-      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
-      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
-    </Register>
-    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
-      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
-      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
-      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
-      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
-      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
-      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
-    </Register>
-    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
-      <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" />
-      <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" />
-      <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" />
-    </Register>
-    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
-      <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" />
-    </Register>
-    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
-      <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" />
-      <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" />
-    </Register>
-    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
-      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
-      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
-      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
-      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
-      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
-      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
-      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
-      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
-      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
-      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
-      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
-      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
-      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
-      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
-    </Register>
-    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
-      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
-      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
-      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
-      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
-      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
-      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
-    </Register>
-    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
-      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
-      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
-      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
-      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
-      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
-      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
-      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
-    </Register>
-    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
-      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
-      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
-      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
-      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
-      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
-      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
-    </Register>
-    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
-      <BitField name="DEBUGEVT" start="31" size="1" description="" />
-      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
-      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
-    </Register>
-    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
-      <BitField name="EXTERNAL" start="4" size="1" description="" />
-      <BitField name="VCATCH" start="3" size="1" description="" />
-      <BitField name="DWTTRAP" start="2" size="1" description="" />
-      <BitField name="BKPT" start="1" size="1" description="" />
-      <BitField name="HALTED" start="0" size="1" description="" />
-    </Register>
-    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
-    </Register>
-    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
-      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
-    </Register>
-    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
-      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="FPU" description="Floating Point Unit">
-    <Register name="CPACR" start="0xE000ED88" description="Coprocessor Access Control Register">
-      <BitField name="CP11" start="22" size="2" description="Access privileges for coprocessor 11" />
-      <BitField name="CP10" start="20" size="2" description="Access privileges for coprocessor 10" />
-    </Register>
-    <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register">
-      <BitField name="ASPEN" start="31" size="1" description="Automatic State Preservation" />
-      <BitField name="LSPEN" start="30" size="1" description="Lazy State Preservation Enabled" />
-      <BitField name="MONRDY" start="8" size="1" description="Monitor Ready" />
-      <BitField name="BFRDY" start="6" size="1" description="BusFault Ready" />
-      <BitField name="MMRDY" start="5" size="1" description="MemManage Ready" />
-      <BitField name="HFRDY" start="4" size="1" description="HardFault Ready" />
-      <BitField name="THREAD" start="3" size="1" description="Thread Mode Allocated Stack Frame" />
-      <BitField name="USER" start="1" size="1" description="User Allocated Stack Frame" />
-      <BitField name="LSPACT" start="0" size="1" description="Lazy State Preservation Active" />
-    </Register>
-    <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register">
-      <BitField name="ADDRESSS" start="3" size="29" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" />
-    </Register>
-    <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Status Control Register">
-      <BitField name="N" start="31" size="1" description="Negative condition code flag" />
-      <BitField name="Z" start="30" size="1" description="Zero condition code flag" />
-      <BitField name="C" start="29" size="1" description="Carry condition code flag" />
-      <BitField name="V" start="28" size="1" description="Overflow condition code flag" />
-      <BitField name="AHP" start="26" size="1" description="Alternative half-precision control bit" />
-      <BitField name="DN" start="25" size="1" description="Default NaN mode control bit" />
-      <BitField name="FZ" start="24" size="1" description="Flush-to-zero mode control bit" />
-      <BitField name="RMode" start="22" size="2" description="Rounding Mode control field" />
-      <BitField name="IDC" start="7" size="1" description="Input Denormal cumulative exception bit" />
-      <BitField name="IXC" start="4" size="1" description="Inexact cumulative exception bit" />
-      <BitField name="UFC" start="3" size="1" description="Underflow cumulative exception bit" />
-      <BitField name="OFC" start="2" size="1" description="Overflow cumulative exception bit" />
-      <BitField name="DZC" start="1" size="1" description="Division by Zero cumulative exception bit" />
-      <BitField name="IOC" start="0" size="1" description="Invalid Operation cumulative exception bit" />
-    </Register>
-  </RegisterGroup>
-  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
-    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
-      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
-      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
-      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
-    </Register>
-    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
-      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
-      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
-      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
-    </Register>
-    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
-      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
-    </Register>
-    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
-      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
-      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
-      <BitField name="REGION" start="0" size="4" description="MPU region field" />
-    </Register>
-    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
-      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
-      <BitField name="AP" start="24" size="3" description="Access permission field" />
-      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
-      <BitField name="S" start="18" size="1" description="Shareable bit" />
-      <BitField name="C" start="17" size="1" description="Memory access attribute" />
-      <BitField name="B" start="16" size="1" description="Memory access attribute" />
-      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
-      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
-      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
-    </Register>
-  </RegisterGroup>
-</Processor>
diff --git a/examples/device/device_virtual_com/segger/LPC43xx_Vectors.s b/examples/device/device_virtual_com/segger/LPC43xx_Vectors.s
deleted file mode 100644
index ab223b8a1..000000000
--- a/examples/device/device_virtual_com/segger/LPC43xx_Vectors.s
+++ /dev/null
@@ -1,540 +0,0 @@
-/*****************************************************************************
- *                   SEGGER Microcontroller GmbH & Co. KG                    *
- *            Solutions for real time microcontroller applications           *
- *****************************************************************************
- *                                                                           *
- *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
- *                                                                           *
- *           Internet: www.segger.com   Support: support@segger.com          *
- *                                                                           *
- *****************************************************************************/
-
-/*****************************************************************************
- *                         Preprocessor Definitions                          *
- *                         ------------------------                          *
- * VECTORS_IN_RAM                                                            *
- *                                                                           *
- *   If defined, an area of RAM will large enough to store the vector table  *
- *   will be reserved.                                                       *
- *                                                                           *
- *****************************************************************************/
-
-  .syntax unified
-  .code 16
-
-  .section .init, "ax"
-  .align 0
-
-/*****************************************************************************
- * Default Exception Handlers                                                *
- *****************************************************************************/
-
-  .thumb_func
-  .weak NMI_Handler
-NMI_Handler:
-  b .
-
-  .thumb_func
-  .weak HardFault_Handler
-HardFault_Handler:
-  b .
-
-  .thumb_func
-  .weak SVC_Handler
-SVC_Handler:
-  b .
-
-  .thumb_func
-  .weak PendSV_Handler
-PendSV_Handler:
-  b .
-
-  .thumb_func
-  .weak SysTick_Handler
-SysTick_Handler:
-  b .
-
-  .thumb_func
-Dummy_Handler:
-  b .
-
-#if defined(__OPTIMIZATION_SMALL)
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Dummy_Handler
-
-  .weak DMA_IRQHandler
-  .thumb_set DMA_IRQHandler,Dummy_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Dummy_Handler
-
-  .weak ETHERNET_IRQHandler
-  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
-
-  .weak SDIO_IRQHandler
-  .thumb_set SDIO_IRQHandler,Dummy_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Dummy_Handler
-
-  .weak USB0_IRQHandler
-  .thumb_set USB0_IRQHandler,Dummy_Handler
-
-  .weak USB1_IRQHandler
-  .thumb_set USB1_IRQHandler,Dummy_Handler
-
-  .weak SCT_IRQHandler
-  .thumb_set SCT_IRQHandler,Dummy_Handler
-
-  .weak RITIMER_IRQHandler
-  .thumb_set RITIMER_IRQHandler,Dummy_Handler
-
-  .weak TIMER0_IRQHandler
-  .thumb_set TIMER0_IRQHandler,Dummy_Handler
-
-  .weak TIMER1_IRQHandler
-  .thumb_set TIMER1_IRQHandler,Dummy_Handler
-
-  .weak TIMER2_IRQHandler
-  .thumb_set TIMER2_IRQHandler,Dummy_Handler
-
-  .weak TIMER3_IRQHandler
-  .thumb_set TIMER3_IRQHandler,Dummy_Handler
-
-  .weak MCPWM_IRQHandler
-  .thumb_set MCPWM_IRQHandler,Dummy_Handler
-
-  .weak ADC0_IRQHandler
-  .thumb_set ADC0_IRQHandler,Dummy_Handler
-
-  .weak I2C0_IRQHandler
-  .thumb_set I2C0_IRQHandler,Dummy_Handler
-
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Dummy_Handler
-
-  .weak SPI_INT_IRQHandler
-  .thumb_set SPI_INT_IRQHandler,Dummy_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Dummy_Handler
-
-  .weak SSP0_IRQHandler
-  .thumb_set SSP0_IRQHandler,Dummy_Handler
-
-  .weak SSP1_IRQHandler
-  .thumb_set SSP1_IRQHandler,Dummy_Handler
-
-  .weak USART0_IRQHandler
-  .thumb_set USART0_IRQHandler,Dummy_Handler
-
-  .weak UART1_IRQHandler
-  .thumb_set UART1_IRQHandler,Dummy_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Dummy_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Dummy_Handler
-
-  .weak I2S0_IRQHandler
-  .thumb_set I2S0_IRQHandler,Dummy_Handler
-
-  .weak I2S1_IRQHandler
-  .thumb_set I2S1_IRQHandler,Dummy_Handler
-
-  .weak SPIFI_IRQHandler
-  .thumb_set SPIFI_IRQHandler,Dummy_Handler
-
-  .weak SGPIO_IINT_IRQHandler
-  .thumb_set SGPIO_IINT_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT0_IRQHandler
-  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT1_IRQHandler
-  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT2_IRQHandler
-  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT3_IRQHandler
-  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT4_IRQHandler
-  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT5_IRQHandler
-  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT6_IRQHandler
-  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
-
-  .weak PIN_INT7_IRQHandler
-  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
-
-  .weak GINT0_IRQHandler
-  .thumb_set GINT0_IRQHandler,Dummy_Handler
-
-  .weak GINT1_IRQHandler
-  .thumb_set GINT1_IRQHandler,Dummy_Handler
-
-  .weak EVENTROUTER_IRQHandler
-  .thumb_set EVENTROUTER_IRQHandler,Dummy_Handler
-
-  .weak C_CAN1_IRQHandler
-  .thumb_set C_CAN1_IRQHandler,Dummy_Handler
-
-  .weak ADCHS_IRQHandler
-  .thumb_set ADCHS_IRQHandler,Dummy_Handler
-
-  .weak ATIMER_IRQHandler
-  .thumb_set ATIMER_IRQHandler,Dummy_Handler
-
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Dummy_Handler
-
-  .weak WWDT_IRQHandler
-  .thumb_set WWDT_IRQHandler,Dummy_Handler
-
-  .weak C_CAN0_IRQHandler
-  .thumb_set C_CAN0_IRQHandler,Dummy_Handler
-
-  .weak QEI_IRQHandler
-  .thumb_set QEI_IRQHandler,Dummy_Handler
-
-#else
-
-  .thumb_func
-  .weak DAC_IRQHandler
-DAC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak DMA_IRQHandler
-DMA_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak FLASH_IRQHandler
-FLASH_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ETHERNET_IRQHandler
-ETHERNET_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SDIO_IRQHandler
-SDIO_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak LCD_IRQHandler
-LCD_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB0_IRQHandler
-USB0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USB1_IRQHandler
-USB1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SCT_IRQHandler
-SCT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RITIMER_IRQHandler
-RITIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER0_IRQHandler
-TIMER0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER1_IRQHandler
-TIMER1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER2_IRQHandler
-TIMER2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak TIMER3_IRQHandler
-TIMER3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak MCPWM_IRQHandler
-MCPWM_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC0_IRQHandler
-ADC0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C0_IRQHandler
-I2C0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2C1_IRQHandler
-I2C1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPI_INT_IRQHandler
-SPI_INT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADC1_IRQHandler
-ADC1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP0_IRQHandler
-SSP0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SSP1_IRQHandler
-SSP1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART0_IRQHandler
-USART0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak UART1_IRQHandler
-UART1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART2_IRQHandler
-USART2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak USART3_IRQHandler
-USART3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S0_IRQHandler
-I2S0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak I2S1_IRQHandler
-I2S1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SPIFI_IRQHandler
-SPIFI_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak SGPIO_IINT_IRQHandler
-SGPIO_IINT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT0_IRQHandler
-PIN_INT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT1_IRQHandler
-PIN_INT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT2_IRQHandler
-PIN_INT2_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT3_IRQHandler
-PIN_INT3_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT4_IRQHandler
-PIN_INT4_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT5_IRQHandler
-PIN_INT5_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT6_IRQHandler
-PIN_INT6_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak PIN_INT7_IRQHandler
-PIN_INT7_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT0_IRQHandler
-GINT0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak GINT1_IRQHandler
-GINT1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak EVENTROUTER_IRQHandler
-EVENTROUTER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN1_IRQHandler
-C_CAN1_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ADCHS_IRQHandler
-ADCHS_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak ATIMER_IRQHandler
-ATIMER_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak RTC_IRQHandler
-RTC_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak WWDT_IRQHandler
-WWDT_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak C_CAN0_IRQHandler
-C_CAN0_IRQHandler:
-  b .
-
-  .thumb_func
-  .weak QEI_IRQHandler
-QEI_IRQHandler:
-  b .
-
-#endif
-
-/*****************************************************************************
- * Vector Table                                                              *
- *****************************************************************************/
-
-  .section .vectors, "ax"
-  .align 0
-  .global _vectors
-  .extern __stack_end__
-  .extern Reset_Handler
-
-_vectors:
-  .word __stack_end__
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word SVC_Handler
-  .word 0 /* Reserved */
-  .word 0 /* Reserved */
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word DAC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word DMA_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word FLASH_IRQHandler
-  .word ETHERNET_IRQHandler
-  .word SDIO_IRQHandler
-  .word LCD_IRQHandler
-  .word USB0_IRQHandler
-  .word USB1_IRQHandler
-  .word SCT_IRQHandler
-  .word RITIMER_IRQHandler
-  .word TIMER0_IRQHandler
-  .word TIMER1_IRQHandler
-  .word TIMER2_IRQHandler
-  .word TIMER3_IRQHandler
-  .word MCPWM_IRQHandler
-  .word ADC0_IRQHandler
-  .word I2C0_IRQHandler
-  .word I2C1_IRQHandler
-  .word SPI_INT_IRQHandler
-  .word ADC1_IRQHandler
-  .word SSP0_IRQHandler
-  .word SSP1_IRQHandler
-  .word USART0_IRQHandler
-  .word UART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word I2S0_IRQHandler
-  .word I2S1_IRQHandler
-  .word SPIFI_IRQHandler
-  .word SGPIO_IINT_IRQHandler
-  .word PIN_INT0_IRQHandler
-  .word PIN_INT1_IRQHandler
-  .word PIN_INT2_IRQHandler
-  .word PIN_INT3_IRQHandler
-  .word PIN_INT4_IRQHandler
-  .word PIN_INT5_IRQHandler
-  .word PIN_INT6_IRQHandler
-  .word PIN_INT7_IRQHandler
-  .word GINT0_IRQHandler
-  .word GINT1_IRQHandler
-  .word EVENTROUTER_IRQHandler
-  .word C_CAN1_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word ADCHS_IRQHandler
-  .word ATIMER_IRQHandler
-  .word RTC_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word WWDT_IRQHandler
-  .word Dummy_Handler /* Reserved */
-  .word C_CAN0_IRQHandler
-  .word QEI_IRQHandler
-_vectors_end:
-
-#ifdef VECTORS_IN_RAM
-  .section .vectors_ram, "ax"
-  .align 0
-  .global _vectors_ram
-
-_vectors_ram:
-  .space _vectors_end - _vectors, 0
-#endif
diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT.c b/examples/device/device_virtual_com/segger/SEGGER_RTT.c
deleted file mode 100644
index aee5bd21e..000000000
--- a/examples/device/device_virtual_com/segger/SEGGER_RTT.c
+++ /dev/null
@@ -1,1329 +0,0 @@
-/*********************************************************************
-*               SEGGER MICROCONTROLLER GmbH & Co. KG                 *
-*       Solutions for real time microcontroller applications         *
-**********************************************************************
-*                                                                    *
-*       (c) 2014 - 2016  SEGGER Microcontroller GmbH & Co. KG        *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* * This software may in its unmodified form be freely redistributed *
-*   in source form.                                                  *
-* * The source code may be modified, provided the source code        *
-*   retains the above copyright notice, this list of conditions and  *
-*   the following disclaimer.                                        *
-* * Modified versions of this software in source or linkable form    *
-*   may not be distributed without prior consent of SEGGER.          *
-* * This software may only be used for communication with SEGGER     *
-*   J-Link debug probes.                                             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       RTT version: 5.12e                                           *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT.c
-Purpose : Implementation of SEGGER real-time transfer (RTT) which
-          allows real-time communication on targets which support
-          debugger memory accesses while the CPU is running.
-
-Additional information:
-          Type "int" is assumed to be 32-bits in size
-          H->T    Host to target communication
-          T->H    Target to host communication
-
-          RTT channel 0 is always present and reserved for Terminal usage.
-          Name is fixed to "Terminal"
-
-          Effective buffer size: SizeOfBuffer - 1
-
-          WrOff == RdOff:       Buffer is empty
-          WrOff == (RdOff - 1): Buffer is full
-          WrOff >  RdOff:       Free space includes wrap-around
-          WrOff <  RdOff:       Used space includes wrap-around
-          (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0):  
-                                Buffer full and wrap-around after next byte
-
-
-----------------------------------------------------------------------
-*/
-
-#include "SEGGER_RTT.h"
-
-#include <string.h>                 // for memcpy
-
-/*********************************************************************
-*
-*       Configuration, default values
-*
-**********************************************************************
-*/
-
-#ifndef   BUFFER_SIZE_UP
-  #define BUFFER_SIZE_UP                                  1024  // Size of the buffer for terminal output of target, up to host
-#endif
-
-#ifndef   BUFFER_SIZE_DOWN
-  #define BUFFER_SIZE_DOWN                                16    // Size of the buffer for terminal input to target from host (Usually keyboard input)
-#endif
-
-#ifndef   SEGGER_RTT_MAX_NUM_UP_BUFFERS
-  #define SEGGER_RTT_MAX_NUM_UP_BUFFERS                    2    // Number of up-buffers (T->H) available on this target
-#endif
-
-#ifndef   SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
-  #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS                  2    // Number of down-buffers (H->T) available on this target
-#endif
-
-#ifndef SEGGER_RTT_BUFFER_SECTION
-  #if defined SEGGER_RTT_SECTION
-    #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION
-  #endif
-#endif
-
-#ifndef   SEGGER_RTT_MODE_DEFAULT
-  #define SEGGER_RTT_MODE_DEFAULT                         SEGGER_RTT_MODE_NO_BLOCK_SKIP
-#endif
-
-#ifndef   SEGGER_RTT_LOCK
-  #define SEGGER_RTT_LOCK()
-#endif
-
-#ifndef   SEGGER_RTT_UNLOCK
-  #define SEGGER_RTT_UNLOCK()
-#endif
-
-#ifndef   STRLEN
-  #define STRLEN(a)                                       strlen((a))
-#endif
-
-#ifndef   MEMCPY
-  #define MEMCPY(pDest, pSrc, NumBytes)                   memcpy((pDest), (pSrc), (NumBytes))
-#endif
-
-#ifndef   MIN
-  #define MIN(a, b)         (((a) < (b)) ? (a) : (b))
-#endif
-
-#ifndef   MAX
-  #define MAX(a, b)         (((a) > (b)) ? (a) : (b))
-#endif
-//
-// For some environments, NULL may not be defined until certain headers are included
-//
-#ifndef NULL
-  #define NULL 0
-#endif
-
-/*********************************************************************
-*
-*       Static const data
-*
-**********************************************************************
-*/
-
-static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
-
-/*********************************************************************
-*
-*       Static data
-*
-**********************************************************************
-*/
-//
-// RTT Control Block and allocate buffers for channel 0
-//
-#ifdef SEGGER_RTT_SECTION
-  #if (defined __GNUC__)
-    __attribute__ ((section (SEGGER_RTT_SECTION))) SEGGER_RTT_CB _SEGGER_RTT;
-  #elif (defined __ICCARM__) || (defined __ICCRX__)
-    #pragma location=SEGGER_RTT_SECTION
-    SEGGER_RTT_CB _SEGGER_RTT;
-  #elif (defined __CC_ARM__)
-    __attribute__ ((section (SEGGER_RTT_SECTION), zero_init)) SEGGER_RTT_CB _SEGGER_RTT;
-  #else
-    SEGGER_RTT_CB _SEGGER_RTT;
-  #endif
-#else
-    SEGGER_RTT_CB _SEGGER_RTT;
-#endif
-
-#ifdef SEGGER_RTT_BUFFER_SECTION
-  #if (defined __GNUC__)
-    __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION))) static char _acUpBuffer  [BUFFER_SIZE_UP];
-    __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION))) static char _acDownBuffer[BUFFER_SIZE_DOWN];
-  #elif (defined __ICCARM__) || (defined __ICCRX__)
-    #pragma location=SEGGER_RTT_BUFFER_SECTION
-    static char _acUpBuffer  [BUFFER_SIZE_UP];
-    #pragma location=SEGGER_RTT_BUFFER_SECTION
-    static char _acDownBuffer[BUFFER_SIZE_DOWN];
-  #elif (defined __CC_ARM__)
-    __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION), zero_init)) static char _acUpBuffer  [BUFFER_SIZE_UP];
-    __attribute__ ((section (SEGGER_RTT_BUFFER_SECTION), zero_init)) static char _acDownBuffer[BUFFER_SIZE_DOWN];
-  #else
-    static char _acUpBuffer  [BUFFER_SIZE_UP];
-    static char _acDownBuffer[BUFFER_SIZE_DOWN];
-  #endif
-#else
-    static char _acUpBuffer  [BUFFER_SIZE_UP];
-    static char _acDownBuffer[BUFFER_SIZE_DOWN];
-#endif
-
-static char _ActiveTerminal;
-
-/*********************************************************************
-*
-*       Static functions
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       _DoInit()
-*
-*  Function description
-*    Initializes the control block an buffers.
-*    May only be called via INIT() to avoid overriding settings.
-*
-*/
-#define INIT()  do {                                            \
-                  if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); }  \
-                } while (0)
-static void _DoInit(void) {
-  SEGGER_RTT_CB* p;
-  //
-  // Initialize control block
-  //
-  p = &_SEGGER_RTT;
-  p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
-  p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
-  //
-  // Initialize up buffer 0
-  //
-  p->aUp[0].sName         = "Terminal";
-  p->aUp[0].pBuffer       = _acUpBuffer;
-  p->aUp[0].SizeOfBuffer  = sizeof(_acUpBuffer);
-  p->aUp[0].RdOff         = 0u;
-  p->aUp[0].WrOff         = 0u;
-  p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
-  //
-  // Initialize down buffer 0
-  //
-  p->aDown[0].sName         = "Terminal";
-  p->aDown[0].pBuffer       = _acDownBuffer;
-  p->aDown[0].SizeOfBuffer  = sizeof(_acDownBuffer);
-  p->aDown[0].RdOff         = 0u;
-  p->aDown[0].WrOff         = 0u;
-  p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
-  //
-  // Finish initialization of the control block.
-  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
-  // in initializer memory (usually flash) by J-Link
-  //
-  strcpy(&p->acID[7], "RTT");
-  strcpy(&p->acID[0], "SEGGER");
-  p->acID[6] = ' ';
-}
-
-/*********************************************************************
-*
-*       _WriteBlocking()
-*
-*  Function description
-*    Stores a specified number of characters in SEGGER RTT ring buffer
-*    and updates the associated write pointer which is periodically
-*    read by the host.
-*    The caller is responsible for managing the write chunk sizes as
-*    _WriteBlocking() will block until all data has been posted successfully.
-*
-*  Parameters
-*    pRing        Ring buffer to post to.
-*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
-*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
-*
-*  Return value
-*    >= 0 - Number of bytes written into buffer.
-*/
-static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) {
-  unsigned NumBytesToWrite;
-  unsigned NumBytesWritten;
-  unsigned RdOff;
-  unsigned WrOff;
-  //
-  // Write data to buffer and handle wrap-around if necessary
-  //
-  NumBytesWritten = 0u;
-  WrOff = pRing->WrOff;
-  do {
-    RdOff = pRing->RdOff;                         // May be changed by host (debug probe) in the meantime
-    if (RdOff > WrOff) {
-      NumBytesToWrite = RdOff - WrOff - 1u;
-    } else {
-      NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u);
-    }
-    NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff));      // Number of bytes that can be written until buffer wrap-around
-    NumBytesToWrite = MIN(NumBytesToWrite, NumBytes);
-    memcpy(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite);
-    NumBytesWritten += NumBytesToWrite;
-    pBuffer         += NumBytesToWrite;
-    NumBytes        -= NumBytesToWrite;
-    WrOff           += NumBytesToWrite;
-    if (WrOff == pRing->SizeOfBuffer) {
-      WrOff = 0u;
-    }
-    pRing->WrOff = WrOff;
-  } while (NumBytes);
-  //
-  return NumBytesWritten;
-}
-
-/*********************************************************************
-*
-*       _WriteNoCheck()
-*
-*  Function description
-*    Stores a specified number of characters in SEGGER RTT ring buffer
-*    and updates the associated write pointer which is periodically
-*    read by the host.
-*    It is callers responsibility to make sure data actually fits in buffer.
-*
-*  Parameters
-*    pRing        Ring buffer to post to.
-*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
-*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
-*
-*  Notes
-*    (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking
-*/
-static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) {
-  unsigned NumBytesAtOnce;
-  unsigned WrOff;
-  unsigned Rem;
-
-  WrOff = pRing->WrOff;
-  Rem = pRing->SizeOfBuffer - WrOff;
-  if (Rem > NumBytes) {
-    //
-    // All data fits before wrap around
-    //
-    memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
-    pRing->WrOff = WrOff + NumBytes;
-  } else {
-    //
-    // We reach the end of the buffer, so need to wrap around
-    //
-    NumBytesAtOnce = Rem;
-    memcpy(pRing->pBuffer + WrOff, pData, NumBytesAtOnce);
-    NumBytesAtOnce = NumBytes - Rem;
-    memcpy(pRing->pBuffer, pData + Rem, NumBytesAtOnce);
-    pRing->WrOff = NumBytesAtOnce;
-  }
-}
-
-/*********************************************************************
-*
-*       _PostTerminalSwitch()
-*
-*  Function description
-*    Switch terminal to the given terminal ID.  It is the caller's
-*    responsibility to ensure the terminal ID is correct and there is
-*    enough space in the buffer for this to complete successfully.
-*
-*  Parameters
-*    pRing        Ring buffer to post to.
-*    TerminalId   Terminal ID to switch to.
-*/
-static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) {
-  char ac[2];
-
-  ac[0] = 0xFFu;
-  ac[1] = _aTerminalId[TerminalId];  // Caller made already sure that TerminalId does not exceed our terminal limit
-  _WriteBlocking(pRing, ac, 2u);
-}
-
-/*********************************************************************
-*
-*       _GetAvailWriteSpace()
-*
-*  Function description
-*    Returns the number of bytes that can be written to the ring
-*    buffer without blocking.
-*
-*  Parameters
-*    pRing        Ring buffer to check.
-*
-*  Return value
-*    Number of bytes that are free in the buffer.
-*/
-static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) {
-  unsigned RdOff;
-  unsigned WrOff;
-  unsigned r;
-  //
-  // Avoid warnings regarding volatile access order.  It's not a problem
-  // in this case, but dampen compiler enthusiasm.
-  //
-  RdOff = pRing->RdOff;
-  WrOff = pRing->WrOff;
-  if (RdOff <= WrOff) {
-    r = pRing->SizeOfBuffer - 1u - WrOff + RdOff;
-  } else {
-    r = RdOff - WrOff - 1u;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       Public code
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       SEGGER_RTT_ReadNoLock()
-*
-*  Function description
-*    Reads characters from SEGGER real-time-terminal control block
-*    which have been previously stored by the host.
-*    Do not lock against interrupts and multiple access.
-*
-*  Parameters
-*    BufferIndex  Index of Down-buffer to be used (e.g. 0 for "Terminal").
-*    pBuffer      Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to.
-*    BufferSize   Size of the target application buffer.
-*
-*  Return value
-*    Number of bytes that have been read.
-*/
-unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) {
-  unsigned                NumBytesRem;
-  unsigned                NumBytesRead;
-  unsigned                RdOff;
-  unsigned                WrOff;
-  unsigned char*          pBuffer;
-  SEGGER_RTT_BUFFER_DOWN* pRing;
-  //
-  INIT();
-  pRing = &_SEGGER_RTT.aDown[BufferIndex];
-  pBuffer = (unsigned char*)pData;
-  RdOff = pRing->RdOff;
-  WrOff = pRing->WrOff;
-  NumBytesRead = 0u;
-  //
-  // Read from current read position to wrap-around of buffer, first
-  //
-  if (RdOff > WrOff) {
-    NumBytesRem = pRing->SizeOfBuffer - RdOff;
-    NumBytesRem = MIN(NumBytesRem, BufferSize);
-    memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
-    NumBytesRead += NumBytesRem;
-    pBuffer      += NumBytesRem;
-    BufferSize   -= NumBytesRem;
-    RdOff        += NumBytesRem;
-    //
-    // Handle wrap-around of buffer
-    //
-    if (RdOff == pRing->SizeOfBuffer) {
-      RdOff = 0u;
-    }
-  }
-  //
-  // Read remaining items of buffer
-  //
-  NumBytesRem = WrOff - RdOff;
-  NumBytesRem = MIN(NumBytesRem, BufferSize);
-  if (NumBytesRem > 0u) {
-    memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
-    NumBytesRead += NumBytesRem;
-    pBuffer      += NumBytesRem;
-    BufferSize   -= NumBytesRem;
-    RdOff        += NumBytesRem;
-  }
-  if (NumBytesRead) {
-    pRing->RdOff = RdOff;
-  }
-  //
-  return NumBytesRead;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_Read
-*
-*  Function description
-*    Reads characters from SEGGER real-time-terminal control block
-*    which have been previously stored by the host.
-*
-*  Parameters
-*    BufferIndex  Index of Down-buffer to be used (e.g. 0 for "Terminal").
-*    pBuffer      Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to.
-*    BufferSize   Size of the target application buffer.
-*
-*  Return value
-*    Number of bytes that have been read.
-*/
-unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
-  unsigned NumBytesRead;
-  //
-  SEGGER_RTT_LOCK();
-  //
-  // Call the non-locking read function
-  //
-  NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize);
-  //
-  // Finish up.
-  //
-  SEGGER_RTT_UNLOCK();
-  //
-  return NumBytesRead;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_WriteWithOverwriteNoLock
-*
-*  Function description
-*    Stores a specified number of characters in SEGGER RTT
-*    control block.
-*    SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application 
-*    and overwrites data if the data does not fit into the buffer.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
-*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
-*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
-*
-*  Notes
-*    (1) If there is not enough space in the "Up"-buffer, data is overwritten.
-*    (2) For performance reasons this function does not call Init()
-*        and may only be called after RTT has been initialized.
-*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
-*    (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link 
-*        connection reads RTT data.
-*/
-void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
-  const char*           pData;
-  SEGGER_RTT_BUFFER_UP* pRing;
-  unsigned              Avail;
-
-  pData = (const char *)pBuffer;
-  //
-  // Get "to-host" ring buffer and copy some elements into local variables.
-  //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
-  //
-  // Check if we will overwrite data and need to adjust the RdOff.
-  //
-  if (pRing->WrOff == pRing->RdOff) {
-    Avail = pRing->SizeOfBuffer - 1u;
-  } else if ( pRing->WrOff < pRing->RdOff) {
-    Avail = pRing->RdOff - pRing->WrOff - 1u;
-  } else {
-    Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer;
-  }
-  if (NumBytes > Avail) {
-    pRing->RdOff += (NumBytes - Avail);
-    while (pRing->RdOff >= pRing->SizeOfBuffer) {
-      pRing->RdOff -= pRing->SizeOfBuffer;
-    }
-  }
-  //
-  // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds
-  //
-  Avail = pRing->SizeOfBuffer - pRing->WrOff;
-  do {
-    if (Avail > NumBytes) {
-      //
-      // Last round
-      //
-#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead.
-      char* pDst;
-      pDst = pRing->pBuffer + pRing->WrOff;
-      pRing->WrOff += NumBytes;
-      do {
-        *pDst++ = *pData++;
-      } while (--NumBytes);
-#else
-      memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
-      pRing->WrOff += NumBytes;
-#endif
-      break;  //Alternatively: NumBytes = 0;
-    } else {
-      //
-      //  Wrap-around necessary, write until wrap-around and reset WrOff
-      //
-      memcpy(pRing->pBuffer + pRing->WrOff, pData, Avail);
-      pData += Avail;
-      pRing->WrOff = 0;
-      NumBytes -= Avail;
-      Avail = (pRing->SizeOfBuffer - 1);
-    }
-  } while (NumBytes);
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_WriteSkipNoLock
-*
-*  Function description
-*    Stores a specified number of characters in SEGGER RTT
-*    control block which is then read by the host.
-*    SEGGER_RTT_WriteSkipNoLock does not lock the application and
-*    skips all data, if the data does not fit into the buffer.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
-*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
-*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
-*
-*  Return value
-*    Number of bytes which have been stored in the "Up"-buffer.
-*
-*  Notes
-*    (1) If there is not enough space in the "Up"-buffer, all data is dropped.
-*    (2) For performance reasons this function does not call Init()
-*        and may only be called after RTT has been initialized.
-*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
-*/
-unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
-  const char*           pData;
-  SEGGER_RTT_BUFFER_UP* pRing;
-  unsigned              Avail;
-  unsigned              RdOff;
-  unsigned              WrOff;
-  unsigned              Rem;
-
-  pData = (const char *)pBuffer;
-  //
-  // Get "to-host" ring buffer and copy some elements into local variables.
-  //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
-  RdOff = pRing->RdOff;
-  WrOff = pRing->WrOff;
-  //
-  // Handle the most common cases fastest.
-  // Which is:
-  //    RdOff <= WrOff -> Space until wrap around is free.
-  //  AND
-  //    WrOff + NumBytes < SizeOfBuffer -> No Wrap around necessary.
-  //
-  //  OR
-  //
-  //    RdOff > WrOff -> Space until RdOff - 1 is free.
-  //  AND
-  //    WrOff + NumBytes < RdOff -> Data fits into buffer
-  //
-  if (RdOff <= WrOff) {
-    //
-    // Get space until WrOff will be at wrap around.
-    //
-    Avail = pRing->SizeOfBuffer - 1u - WrOff ;
-    if (Avail >= NumBytes) {
-#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead.
-      char* pDst;
-      pDst = pRing->pBuffer + WrOff;
-      WrOff += NumBytes;
-      do {
-        *pDst++ = *pData++;
-      } while (--NumBytes);
-      pRing->WrOff = WrOff + NumBytes;
-#else
-      memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
-      pRing->WrOff = WrOff + NumBytes;
-#endif
-      return 1;
-    }
-    //
-    // If data did not fit into space until wrap around calculate complete space in buffer.
-    //
-    Avail += RdOff;
-    //
-    // If there is still no space for the whole of this output, don't bother.
-    //
-    if (Avail >= NumBytes) {
-      //
-      //  OK, we have enough space in buffer. Copy in one or 2 chunks
-      //
-      Rem = pRing->SizeOfBuffer - WrOff;      // Space until end of buffer
-      if (Rem > NumBytes) {
-        memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
-        pRing->WrOff = WrOff + NumBytes;
-      } else {
-        //
-        // We reach the end of the buffer, so need to wrap around
-        //
-        memcpy(pRing->pBuffer + WrOff, pData, Rem);
-        memcpy(pRing->pBuffer, pData + Rem, NumBytes - Rem);
-        pRing->WrOff = NumBytes - Rem;
-      }
-      return 1;
-    }
-  } else {
-    Avail = RdOff - WrOff - 1u;
-    if (Avail >= NumBytes) {
-      memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
-      pRing->WrOff = WrOff + NumBytes;
-      return 1;
-    }
-  }
-  //
-  // If we reach this point no data has been written
-  //
-  return 0;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_WriteNoLock
-*
-*  Function description
-*    Stores a specified number of characters in SEGGER RTT
-*    control block which is then read by the host.
-*    SEGGER_RTT_WriteNoLock does not lock the application.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
-*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
-*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
-*
-*  Return value
-*    Number of bytes which have been stored in the "Up"-buffer.
-*
-*  Notes
-*    (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped.
-*    (2) For performance reasons this function does not call Init()
-*        and may only be called after RTT has been initialized.
-*        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
-*/
-unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
-  unsigned              Status;
-  unsigned              Avail;
-  const char*           pData;
-  SEGGER_RTT_BUFFER_UP* pRing;
-
-  pData = (const char *)pBuffer;
-  //
-  // Get "to-host" ring buffer.
-  //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
-  //
-  // How we output depends upon the mode...
-  //
-  switch (pRing->Flags) {
-  case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
-    //
-    // If we are in skip mode and there is no space for the whole
-    // of this output, don't bother.
-    //
-    Avail = _GetAvailWriteSpace(pRing);
-    if (Avail < NumBytes) {
-      Status = 0u;
-    } else {
-      Status = NumBytes;
-      _WriteNoCheck(pRing, pData, NumBytes);
-    }
-    break;
-  case SEGGER_RTT_MODE_NO_BLOCK_TRIM:
-    //
-    // If we are in trim mode, trim to what we can output without blocking.
-    //
-    Avail = _GetAvailWriteSpace(pRing);
-    Status = Avail < NumBytes ? Avail : NumBytes;
-    _WriteNoCheck(pRing, pData, Status);
-    break;
-  case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL:
-    //
-    // If we are in blocking mode, output everything.
-    //
-    Status = _WriteBlocking(pRing, pData, NumBytes);
-    break;
-  default:
-    Status = 0u;
-    break;
-  }
-  //
-  // Finish up.
-  //
-  return Status;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_Write
-*
-*  Function description
-*    Stores a specified number of characters in SEGGER RTT
-*    control block which is then read by the host.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
-*    pBuffer      Pointer to character array. Does not need to point to a \0 terminated string.
-*    NumBytes     Number of bytes to be stored in the SEGGER RTT control block.
-*
-*  Return value
-*    Number of bytes which have been stored in the "Up"-buffer.
-*
-*  Notes
-*    (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped.
-*/
-unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
-  unsigned Status;
-  //
-  INIT();
-  SEGGER_RTT_LOCK();
-  //
-  // Call the non-locking write function
-  //
-  Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes);
-  //
-  // Finish up.
-  //
-  SEGGER_RTT_UNLOCK();
-  //
-  return Status;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_WriteString
-*
-*  Function description
-*    Stores string in SEGGER RTT control block.
-*    This data is read by the host.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
-*    s            Pointer to string.
-*
-*  Return value
-*    Number of bytes which have been stored in the "Up"-buffer.
-*
-*  Notes
-*    (1) If there is not enough space in the "Up"-buffer, depending on configuration,
-*        remaining characters may be dropped or RTT module waits until there is more space in the buffer.
-*    (2) String passed to this function has to be \0 terminated
-*    (3) \0 termination character is *not* stored in RTT buffer
-*/
-unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) {
-  unsigned Len;
-
-  Len = STRLEN(s);
-  return SEGGER_RTT_Write(BufferIndex, s, Len);
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_GetKey
-*
-*  Function description
-*    Reads one character from the SEGGER RTT buffer.
-*    Host has previously stored data there.
-*
-*  Return value
-*    <  0 -   No character available (buffer empty).
-*    >= 0 -   Character which has been read. (Possible values: 0 - 255)
-*
-*  Notes
-*    (1) This function is only specified for accesses to RTT buffer 0.
-*/
-int SEGGER_RTT_GetKey(void) {
-  char c;
-  int r;
-
-  r = (int)SEGGER_RTT_Read(0u, &c, 1u);
-  if (r == 1) {
-    r = (int)(unsigned char)c;
-  } else {
-    r = -1;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_WaitKey
-*
-*  Function description
-*    Waits until at least one character is avaible in the SEGGER RTT buffer.
-*    Once a character is available, it is read and this function returns.
-*
-*  Return value
-*    >=0 -   Character which has been read.
-*
-*  Notes
-*    (1) This function is only specified for accesses to RTT buffer 0
-*    (2) This function is blocking if no character is present in RTT buffer
-*/
-int SEGGER_RTT_WaitKey(void) {
-  int r;
-
-  do {
-    r = SEGGER_RTT_GetKey();
-  } while (r < 0);
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_HasKey
-*
-*  Function description
-*    Checks if at least one character for reading is available in the SEGGER RTT buffer.
-*
-*  Return value
-*    == 0 -     No characters are available to read.
-*    == 1 -     At least one character is available.
-*
-*  Notes
-*    (1) This function is only specified for accesses to RTT buffer 0
-*/
-int SEGGER_RTT_HasKey(void) {
-  unsigned RdOff;
-  int r;
-
-  INIT();
-  RdOff = _SEGGER_RTT.aDown[0].RdOff;
-  if (RdOff != _SEGGER_RTT.aDown[0].WrOff) {
-    r = 1;
-  } else {
-    r = 0;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_HasData
-*
-*  Function description
-*    Check if there is data from the host in the given buffer.
-*
-*  Return value:
-*  ==0:  No data
-*  !=0:  Data in buffer
-*
-*/
-unsigned SEGGER_RTT_HasData(unsigned BufferIndex) {
-  SEGGER_RTT_BUFFER_DOWN* pRing;
-  unsigned                v;
-
-  pRing = &_SEGGER_RTT.aDown[BufferIndex];
-  v = pRing->WrOff;
-  return v - pRing->RdOff;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_AllocDownBuffer
-*
-*  Function description
-*    Run-time configuration of the next down-buffer (H->T).
-*    The next buffer, which is not used yet is configured.
-*    This includes: Buffer address, size, name, flags, ...
-*
-*  Parameters
-*    sName        Pointer to a constant name string.
-*    pBuffer      Pointer to a buffer to be used.
-*    BufferSize   Size of the buffer.
-*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
-*
-*  Return value
-*    >= 0 - O.K. Buffer Index
-*     < 0 - Error
-*/
-int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
-  int BufferIndex;
-
-  INIT();
-  SEGGER_RTT_LOCK();
-  BufferIndex = 0;
-  do {
-    if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) {
-      break;
-    }
-    BufferIndex++;
-  } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers);
-  if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) {
-    _SEGGER_RTT.aDown[BufferIndex].sName        = sName;
-    _SEGGER_RTT.aDown[BufferIndex].pBuffer      = pBuffer;
-    _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize;
-    _SEGGER_RTT.aDown[BufferIndex].RdOff        = 0u;
-    _SEGGER_RTT.aDown[BufferIndex].WrOff        = 0u;
-    _SEGGER_RTT.aDown[BufferIndex].Flags        = Flags;
-  } else {
-    BufferIndex = -1;
-  }
-  SEGGER_RTT_UNLOCK();
-  return BufferIndex;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_AllocUpBuffer
-*
-*  Function description
-*    Run-time configuration of the next up-buffer (T->H).
-*    The next buffer, which is not used yet is configured.
-*    This includes: Buffer address, size, name, flags, ...
-*
-*  Parameters
-*    sName        Pointer to a constant name string.
-*    pBuffer      Pointer to a buffer to be used.
-*    BufferSize   Size of the buffer.
-*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
-*
-*  Return value
-*    >= 0 - O.K. Buffer Index
-*     < 0 - Error
-*/
-int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
-  int BufferIndex;
-
-  INIT();
-  SEGGER_RTT_LOCK();
-  BufferIndex = 0;
-  do {
-    if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) {
-      break;
-    }
-    BufferIndex++;
-  } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers);
-  if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) {
-    _SEGGER_RTT.aUp[BufferIndex].sName        = sName;
-    _SEGGER_RTT.aUp[BufferIndex].pBuffer      = pBuffer;
-    _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize;
-    _SEGGER_RTT.aUp[BufferIndex].RdOff        = 0u;
-    _SEGGER_RTT.aUp[BufferIndex].WrOff        = 0u;
-    _SEGGER_RTT.aUp[BufferIndex].Flags        = Flags;
-  } else {
-    BufferIndex = -1;
-  }
-  SEGGER_RTT_UNLOCK();
-  return BufferIndex;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_ConfigUpBuffer
-*
-*  Function description
-*    Run-time configuration of a specific up-buffer (T->H).
-*    Buffer to be configured is specified by index.
-*    This includes: Buffer address, size, name, flags, ...
-*
-*  Parameters
-*    BufferIndex  Index of the buffer to configure.
-*    sName        Pointer to a constant name string.
-*    pBuffer      Pointer to a buffer to be used.
-*    BufferSize   Size of the buffer.
-*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
-*
-*  Return value
-*    >= 0 - O.K.
-*     < 0 - Error
-*/
-int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
-  int r;
-
-  INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
-    SEGGER_RTT_LOCK();
-    if (BufferIndex > 0u) {
-      _SEGGER_RTT.aUp[BufferIndex].sName        = sName;
-      _SEGGER_RTT.aUp[BufferIndex].pBuffer      = pBuffer;
-      _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize;
-      _SEGGER_RTT.aUp[BufferIndex].RdOff        = 0u;
-      _SEGGER_RTT.aUp[BufferIndex].WrOff        = 0u;
-    }
-    _SEGGER_RTT.aUp[BufferIndex].Flags          = Flags;
-    SEGGER_RTT_UNLOCK();
-    r =  0;
-  } else {
-    r = -1;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_ConfigDownBuffer
-*
-*  Function description
-*    Run-time configuration of a specific down-buffer (H->T).
-*    Buffer to be configured is specified by index.
-*    This includes: Buffer address, size, name, flags, ...
-*
-*  Parameters
-*    BufferIndex  Index of the buffer to configure.
-*    sName        Pointer to a constant name string.
-*    pBuffer      Pointer to a buffer to be used.
-*    BufferSize   Size of the buffer.
-*    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
-*
-*  Return value
-*    >= 0  O.K.
-*     < 0  Error
-*/
-int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
-  int r;
-
-  INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
-    SEGGER_RTT_LOCK();
-    if (BufferIndex > 0u) {
-      _SEGGER_RTT.aDown[BufferIndex].sName        = sName;
-      _SEGGER_RTT.aDown[BufferIndex].pBuffer      = pBuffer;
-      _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize;
-      _SEGGER_RTT.aDown[BufferIndex].RdOff        = 0u;
-      _SEGGER_RTT.aDown[BufferIndex].WrOff        = 0u;
-    }
-    _SEGGER_RTT.aDown[BufferIndex].Flags          = Flags;
-    SEGGER_RTT_UNLOCK();
-    r =  0;
-  } else {
-    r = -1;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_SetNameUpBuffer
-*
-*  Function description
-*    Run-time configuration of a specific up-buffer name (T->H).
-*    Buffer to be configured is specified by index.
-*
-*  Parameters
-*    BufferIndex  Index of the buffer to renamed.
-*    sName        Pointer to a constant name string.
-*
-*  Return value
-*    >= 0  O.K.
-*     < 0  Error
-*/
-int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
-  int r;
-
-  INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
-    SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aUp[BufferIndex].sName = sName;
-    SEGGER_RTT_UNLOCK();
-    r =  0;
-  } else {
-    r = -1;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_SetNameDownBuffer
-*
-*  Function description
-*    Run-time configuration of a specific Down-buffer name (T->H).
-*    Buffer to be configured is specified by index.
-*
-*  Parameters
-*    BufferIndex  Index of the buffer to renamed.
-*    sName        Pointer to a constant name string.
-*
-*  Return value
-*    >= 0  O.K.
-*     < 0  Error
-*/
-int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
-  int r;
-
-  INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
-    SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aDown[BufferIndex].sName = sName;
-    SEGGER_RTT_UNLOCK();
-    r =  0;
-  } else {
-    r = -1;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_Init
-*
-*  Function description
-*    Initializes the RTT Control Block.
-*    Should be used in RAM targets, at start of the application.
-*
-*/
-void SEGGER_RTT_Init (void) {
-  _DoInit();
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_SetTerminal
-*
-*  Function description
-*    Sets the terminal to be used for output on channel 0.
-*
-*  Parameters
-*    TerminalId  Index of the terminal.
-*
-*  Return value
-*    >= 0  O.K.
-*     < 0  Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id)
-*/
-int SEGGER_RTT_SetTerminal (char TerminalId) {
-  char                  ac[2];
-  SEGGER_RTT_BUFFER_UP* pRing;
-  unsigned Avail;
-  int r;
-  //
-  INIT();
-  //
-  r = 0;
-  ac[0] = 0xFFU;
-  if ((unsigned char)TerminalId < (unsigned char)sizeof(_aTerminalId)) { // We only support a certain number of channels
-    ac[1] = _aTerminalId[(unsigned char)TerminalId];
-    pRing = &_SEGGER_RTT.aUp[0];    // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed
-    SEGGER_RTT_LOCK();    // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
-    if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) {
-      _ActiveTerminal = TerminalId;
-      _WriteBlocking(pRing, ac, 2u);
-    } else {                                                                            // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes
-      Avail = _GetAvailWriteSpace(pRing);
-      if (Avail >= 2) {
-        _ActiveTerminal = TerminalId;    // Only change active terminal in case of success
-        _WriteNoCheck(pRing, ac, 2u);
-      } else {
-        r = -1;
-      }
-    }
-    SEGGER_RTT_UNLOCK();
-  } else {
-    r = -1;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_TerminalOut
-*
-*  Function description
-*    Writes a string to the given terminal
-*     without changing the terminal for channel 0.
-*
-*  Parameters
-*    TerminalId   Index of the terminal.
-*    s            String to be printed on the terminal.
-*
-*  Return value
-*    >= 0 - Number of bytes written.
-*     < 0 - Error.
-*
-*/
-int SEGGER_RTT_TerminalOut (char TerminalId, const char* s) {
-  int                   Status;
-  unsigned              FragLen;
-  unsigned              Avail;
-  SEGGER_RTT_BUFFER_UP* pRing;
-  //
-  INIT();
-  //
-  // Validate terminal ID.
-  //
-  if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels
-    //
-    // Get "to-host" ring buffer.
-    //
-    pRing = &_SEGGER_RTT.aUp[0];
-    //
-    // Need to be able to change terminal, write data, change back.
-    // Compute the fixed and variable sizes.
-    //
-    FragLen = strlen(s);
-    //
-    // How we output depends upon the mode...
-    //
-    SEGGER_RTT_LOCK();
-    Avail = _GetAvailWriteSpace(pRing);
-    switch (pRing->Flags & SEGGER_RTT_MODE_MASK) {
-    case SEGGER_RTT_MODE_NO_BLOCK_SKIP:
-      //
-      // If we are in skip mode and there is no space for the whole
-      // of this output, don't bother switching terminals at all.
-      //
-      if (Avail < (FragLen + 4u)) {
-        Status = 0;
-      } else {
-        _PostTerminalSwitch(pRing, TerminalId);
-        Status = (int)_WriteBlocking(pRing, s, FragLen);
-        _PostTerminalSwitch(pRing, _ActiveTerminal);
-      }
-      break;
-    case SEGGER_RTT_MODE_NO_BLOCK_TRIM:
-      //
-      // If we are in trim mode and there is not enough space for everything,
-      // trim the output but always include the terminal switch.  If no room
-      // for terminal switch, skip that totally.
-      //
-      if (Avail < 4u) {
-        Status = -1;
-      } else {
-        _PostTerminalSwitch(pRing, TerminalId);
-        Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u));
-        _PostTerminalSwitch(pRing, _ActiveTerminal);
-      }
-      break;
-    case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL:
-      //
-      // If we are in blocking mode, output everything.
-      //
-      _PostTerminalSwitch(pRing, TerminalId);
-      Status = (int)_WriteBlocking(pRing, s, FragLen);
-      _PostTerminalSwitch(pRing, _ActiveTerminal);
-      break;
-    default:
-      Status = -1;
-      break;
-    }
-    //
-    // Finish up.
-    //
-    SEGGER_RTT_UNLOCK();
-  } else {
-    Status = -1;
-  }
-  return Status;
-}
-
-
-/*************************** End of file ****************************/
diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT.h b/examples/device/device_virtual_com/segger/SEGGER_RTT.h
deleted file mode 100644
index d3cac44dd..000000000
--- a/examples/device/device_virtual_com/segger/SEGGER_RTT.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*********************************************************************
-*               SEGGER MICROCONTROLLER GmbH & Co. KG                 *
-*       Solutions for real time microcontroller applications         *
-**********************************************************************
-*                                                                    *
-*       (c) 2014 - 2016  SEGGER Microcontroller GmbH & Co. KG        *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* * This software may in its unmodified form be freely redistributed *
-*   in source form.                                                  *
-* * The source code may be modified, provided the source code        *
-*   retains the above copyright notice, this list of conditions and  *
-*   the following disclaimer.                                        *
-* * Modified versions of this software in source or linkable form    *
-*   may not be distributed without prior consent of SEGGER.          *
-* * This software may only be used for communication with SEGGER     *
-*   J-Link debug probes.                                             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       RTT version: 5.12e                                           *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT.h
-Purpose : Implementation of SEGGER real-time transfer which allows
-          real-time communication on targets which support debugger 
-          memory accesses while the CPU is running.
-----------------------------------------------------------------------
-*/
-
-#ifndef SEGGER_RTT_H
-#define SEGGER_RTT_H
-
-#include "SEGGER_RTT_Conf.h"
-
-/*********************************************************************
-*
-*       Defines, fixed
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       Types
-*
-**********************************************************************
-*/
-
-//
-// Description for a circular buffer (also called "ring buffer")
-// which is used as up-buffer (T->H)
-//
-typedef struct {
-  const     char*    sName;         // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
-            char*    pBuffer;       // Pointer to start of buffer
-            unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
-            unsigned WrOff;         // Position of next item to be written by either target.
-  volatile  unsigned RdOff;         // Position of next item to be read by host. Must be volatile since it may be modified by host.
-            unsigned Flags;         // Contains configuration flags
-} SEGGER_RTT_BUFFER_UP;
-
-//
-// Description for a circular buffer (also called "ring buffer")
-// which is used as down-buffer (H->T)
-//
-typedef struct {
-  const     char*    sName;         // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
-            char*    pBuffer;       // Pointer to start of buffer
-            unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
-  volatile  unsigned WrOff;         // Position of next item to be written by host. Must be volatile since it may be modified by host.
-            unsigned RdOff;         // Position of next item to be read by target (down-buffer).
-            unsigned Flags;         // Contains configuration flags
-} SEGGER_RTT_BUFFER_DOWN;
-
-//
-// RTT control block which describes the number of buffers available
-// as well as the configuration for each buffer
-//
-//
-typedef struct {
-  char                    acID[16];                                 // Initialized to "SEGGER RTT"
-  int                     MaxNumUpBuffers;                          // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2)
-  int                     MaxNumDownBuffers;                        // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2)
-  SEGGER_RTT_BUFFER_UP    aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS];       // Up buffers, transferring information up from target via debug probe to host
-  SEGGER_RTT_BUFFER_DOWN  aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS];   // Down buffers, transferring information down from host via debug probe to target
-} SEGGER_RTT_CB;
-
-/*********************************************************************
-*
-*       Global data
-*
-**********************************************************************
-*/
-extern SEGGER_RTT_CB _SEGGER_RTT;
-
-/*********************************************************************
-*
-*       RTT API functions
-*
-**********************************************************************
-*/
-#ifdef __cplusplus
-  extern "C" {
-#endif
-int          SEGGER_RTT_AllocDownBuffer  (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
-int          SEGGER_RTT_AllocUpBuffer    (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
-int          SEGGER_RTT_ConfigUpBuffer   (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
-int          SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
-int          SEGGER_RTT_GetKey           (void);
-unsigned     SEGGER_RTT_HasData          (unsigned BufferIndex);
-int          SEGGER_RTT_HasKey           (void);
-void         SEGGER_RTT_Init             (void);
-unsigned     SEGGER_RTT_Read             (unsigned BufferIndex,       void* pBuffer, unsigned BufferSize);
-unsigned     SEGGER_RTT_ReadNoLock       (unsigned BufferIndex,       void* pData,   unsigned BufferSize);
-int          SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName);
-int          SEGGER_RTT_SetNameUpBuffer  (unsigned BufferIndex, const char* sName);
-int          SEGGER_RTT_WaitKey          (void);
-unsigned     SEGGER_RTT_Write            (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
-unsigned     SEGGER_RTT_WriteNoLock      (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
-unsigned     SEGGER_RTT_WriteSkipNoLock  (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
-unsigned     SEGGER_RTT_WriteString      (unsigned BufferIndex, const char* s);
-void         SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
-//
-// Function macro for performance optimization
-//
-#define      SEGGER_RTT_HASDATA(n)       (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff)
-
-/*********************************************************************
-*
-*       RTT "Terminal" API functions
-*
-**********************************************************************
-*/
-int     SEGGER_RTT_SetTerminal        (char TerminalId);
-int     SEGGER_RTT_TerminalOut        (char TerminalId, const char* s);
-
-/*********************************************************************
-*
-*       RTT printf functions (require SEGGER_RTT_printf.c)
-*
-**********************************************************************
-*/
-int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...);
-#ifdef __cplusplus
-  }
-#endif
-
-/*********************************************************************
-*
-*       Defines
-*
-**********************************************************************
-*/
-
-//
-// Operating modes. Define behavior if buffer is full (not enough space for entire message)
-//
-#define SEGGER_RTT_MODE_NO_BLOCK_SKIP         (0U)     // Skip. Do not block, output nothing. (Default)
-#define SEGGER_RTT_MODE_NO_BLOCK_TRIM         (1U)     // Trim: Do not block, output as much as fits.
-#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL    (2U)     // Block: Wait until there is space in the buffer.
-#define SEGGER_RTT_MODE_MASK                  (3U)
-
-//
-// Control sequences, based on ANSI.
-// Can be used to control color, and clear the screen
-//
-#define RTT_CTRL_RESET                ""         // Reset to default colors
-#define RTT_CTRL_CLEAR                ""         // Clear screen, reposition cursor to top left
-
-#define RTT_CTRL_TEXT_BLACK           ""
-#define RTT_CTRL_TEXT_RED             ""
-#define RTT_CTRL_TEXT_GREEN           ""
-#define RTT_CTRL_TEXT_YELLOW          ""
-#define RTT_CTRL_TEXT_BLUE            ""
-#define RTT_CTRL_TEXT_MAGENTA         ""
-#define RTT_CTRL_TEXT_CYAN            ""
-#define RTT_CTRL_TEXT_WHITE           ""
-
-#define RTT_CTRL_TEXT_BRIGHT_BLACK    ""
-#define RTT_CTRL_TEXT_BRIGHT_RED      ""
-#define RTT_CTRL_TEXT_BRIGHT_GREEN    ""
-#define RTT_CTRL_TEXT_BRIGHT_YELLOW   ""
-#define RTT_CTRL_TEXT_BRIGHT_BLUE     ""
-#define RTT_CTRL_TEXT_BRIGHT_MAGENTA  ""
-#define RTT_CTRL_TEXT_BRIGHT_CYAN     ""
-#define RTT_CTRL_TEXT_BRIGHT_WHITE    ""
-
-#define RTT_CTRL_BG_BLACK             ""
-#define RTT_CTRL_BG_RED               ""
-#define RTT_CTRL_BG_GREEN             ""
-#define RTT_CTRL_BG_YELLOW            ""
-#define RTT_CTRL_BG_BLUE              ""
-#define RTT_CTRL_BG_MAGENTA           ""
-#define RTT_CTRL_BG_CYAN              ""
-#define RTT_CTRL_BG_WHITE             ""
-
-#define RTT_CTRL_BG_BRIGHT_BLACK      ""
-#define RTT_CTRL_BG_BRIGHT_RED        ""
-#define RTT_CTRL_BG_BRIGHT_GREEN      ""
-#define RTT_CTRL_BG_BRIGHT_YELLOW     ""
-#define RTT_CTRL_BG_BRIGHT_BLUE       ""
-#define RTT_CTRL_BG_BRIGHT_MAGENTA    ""
-#define RTT_CTRL_BG_BRIGHT_CYAN       ""
-#define RTT_CTRL_BG_BRIGHT_WHITE      ""
-
-
-#endif
-
-/*************************** End of file ****************************/
diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h b/examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h
deleted file mode 100644
index aef3b4053..000000000
--- a/examples/device/device_virtual_com/segger/SEGGER_RTT_Conf.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/*********************************************************************
-*               SEGGER MICROCONTROLLER GmbH & Co. KG                 *
-*       Solutions for real time microcontroller applications         *
-**********************************************************************
-*                                                                    *
-*       (c) 2014 - 2016  SEGGER Microcontroller GmbH & Co. KG        *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* * This software may in its unmodified form be freely redistributed *
-*   in source form.                                                  *
-* * The source code may be modified, provided the source code        *
-*   retains the above copyright notice, this list of conditions and  *
-*   the following disclaimer.                                        *
-* * Modified versions of this software in source or linkable form    *
-*   may not be distributed without prior consent of SEGGER.          *
-* * This software may only be used for communication with SEGGER     *
-*   J-Link debug probes.                                             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       RTT version: 5.12e                                           *
-*                                                                    *
-**********************************************************************
-----------------------------------------------------------------------
-File    : SEGGER_RTT_Conf.h
-Purpose : Implementation of SEGGER real-time transfer (RTT) which 
-          allows real-time communication on targets which support 
-          debugger memory accesses while the CPU is running.
----------------------------END-OF-HEADER------------------------------
-*/
-
-#ifndef SEGGER_RTT_CONF_H
-#define SEGGER_RTT_CONF_H
-
-#ifdef __ICCARM__
-  #include <intrinsics.h>
-#endif
-
-/*********************************************************************
-*
-*       Defines, configurable
-*
-**********************************************************************
-*/
-
-#define SEGGER_RTT_MAX_NUM_UP_BUFFERS             (2)     // Max. number of up-buffers (T->H) available on this target    (Default: 2)
-#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS           (2)     // Max. number of down-buffers (H->T) available on this target  (Default: 2)
-
-#define BUFFER_SIZE_UP                            (1024)  // Size of the buffer for terminal output of target, up to host (Default: 1k)
-#define BUFFER_SIZE_DOWN                          (16)    // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
-
-#define SEGGER_RTT_PRINTF_BUFFER_SIZE             (64u)    // Size of buffer for RTT printf to bulk-send chars via RTT     (Default: 64)
-
-#define SEGGER_RTT_MODE_DEFAULT                   SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
-
-//
-// Target is not allowed to perform other RTT operations while string still has not been stored completely.
-// Otherwise we would probably end up with a mixed string in the buffer.
-// If using  RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
-// 
-// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
-// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
-// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
-// (Higher priority = lower priority number)
-// Default value for embOS: 128u
-// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-// In case of doubt mask all interrupts: 0u
-// 
-
-#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY         (0x20)   // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
-
-/*********************************************************************
-*
-*       RTT lock configuration for SEGGER Embedded Studio, 
-*       Rowley CrossStudio and GCC
-*/
-#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)
-  #ifdef __ARM_ARCH_6M__
-    #define SEGGER_RTT_LOCK()   {                                                                   \
-                                    unsigned int LockState;                                         \
-                                  __asm volatile ("mrs   %0, primask  \n\t"                         \
-                                                  "mov   r1, $1     \n\t"                           \
-                                                  "msr   primask, r1  \n\t"                         \
-                                                  : "=r" (LockState)                                \
-                                                  :                                                 \
-                                                  : "r1"                                            \
-                                                  );                            
-    
-    #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   primask, %0  \n\t"                         \
-                                                  :                                                 \
-                                                  : "r" (LockState)                                 \
-                                                  :                                                 \
-                                                  );                                                \
-                                }                                             
-                                  
-  #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
-    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
-      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
-    #endif
-    #define SEGGER_RTT_LOCK()   {                                                                   \
-                                    unsigned int LockState;                                         \
-                                  __asm volatile ("mrs   %0, basepri  \n\t"                         \
-                                                  "mov   r1, %1       \n\t"                         \
-                                                  "msr   basepri, r1  \n\t"                         \
-                                                  : "=r" (LockState)                                \
-                                                  : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY)          \
-                                                  : "r1"                                            \
-                                                  );                            
-    
-    #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   basepri, %0  \n\t"                         \
-                                                  :                                                 \
-                                                  : "r" (LockState)                                 \
-                                                  :                                                 \
-                                                  );                                                \
-                                }
-  
-  #elif defined(__ARM_ARCH_7A__)
-    #define SEGGER_RTT_LOCK() {                                                \
-                                 unsigned int LockState;                       \
-                                 __asm volatile ("mrs r1, CPSR \n\t"           \
-                                                 "mov %0, r1 \n\t"             \
-                                                 "orr r1, r1, #0xC0 \n\t"      \
-                                                 "msr CPSR_c, r1 \n\t"         \
-                                                 : "=r" (LockState)            \
-                                                 :                             \
-                                                 : "r1"                        \
-                                                 );
-
-    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"              \
-                                                "mrs r1, CPSR \n\t"            \
-                                                "bic r1, r1, #0xC0 \n\t"       \
-                                                "and r0, r0, #0xC0 \n\t"       \
-                                                "orr r1, r1, r0 \n\t"          \
-                                                "msr CPSR_c, r1 \n\t"          \
-                                                :                              \
-                                                : "r" (LockState)              \
-                                                : "r0", "r1"                   \
-                                                );                             \
-                            }
-#else
-    #define SEGGER_RTT_LOCK()  
-    #define SEGGER_RTT_UNLOCK()
-  #endif
-#endif
-
-/*********************************************************************
-*
-*       RTT lock configuration for IAR EWARM
-*/
-#ifdef __ICCARM__
-  #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__))
-    #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_PRIMASK();                                      \
-                                  __set_PRIMASK(1);                           
-                                    
-    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(LockState);                                         \
-                                }
-  #elif ((defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined (__ARM7M__) && (__CORE__ == __ARM7M__)))
-    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
-      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
-    #endif
-    #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_BASEPRI();                                      \
-                                  __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);                           
-                                    
-    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(LockState);                                         \
-                                }  
-  #endif
-#endif
-
-/*********************************************************************
-*
-*       RTT lock configuration for KEIL ARM
-*/
-#ifdef __CC_ARM
-  #if (defined __TARGET_ARCH_6S_M)
-    #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  register unsigned char PRIMASK __asm( "primask");                 \
-                                  LockState = PRIMASK;                                              \
-                                  PRIMASK = 1u;                                                     \
-                                  __schedule_barrier();
-
-    #define SEGGER_RTT_UNLOCK()   PRIMASK = LockState;                                              \
-                                  __schedule_barrier();                                             \
-                                }
-  #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
-    #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
-      #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
-    #endif
-    #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  register unsigned char BASEPRI __asm( "basepri");                 \
-                                  LockState = BASEPRI;                                              \
-                                  BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY;                      \
-                                  __schedule_barrier();
-
-    #define SEGGER_RTT_UNLOCK()   BASEPRI = LockState;                                              \
-                                  __schedule_barrier();                                             \
-                                }
-  #endif
-#endif
-
-/*********************************************************************
-*
-*       RTT lock configuration fallback
-*/
-#ifndef   SEGGER_RTT_LOCK
-  #define SEGGER_RTT_LOCK()                // Lock RTT (nestable)   (i.e. disable interrupts)
-#endif
-
-#ifndef   SEGGER_RTT_UNLOCK
-  #define SEGGER_RTT_UNLOCK()              // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
-#endif
-
-#endif
-/*************************** End of file ****************************/
diff --git a/examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c b/examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c
deleted file mode 100644
index 6ca09e9e7..000000000
--- a/examples/device/device_virtual_com/segger/SEGGER_RTT_SES.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*********************************************************************
-*               SEGGER MICROCONTROLLER GmbH & Co. KG                 *
-*       Solutions for real time microcontroller applications         *
-**********************************************************************
-*                                                                    *
-*       (c) 2014 - 2015  SEGGER Microcontroller GmbH & Co. KG        *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* * This software may in its unmodified form be freely redistributed *
-*   in source form.                                                  *
-* * The source code may be modified, provided the source code        *
-*   retains the above copyright notice, this list of conditions and  *
-*   the following disclaimer.                                        *
-* * Modified versions of this software in source or linkable form    *
-*   may not be distributed without prior consent of SEGGER.          *
-* * This software may only be used for communication with SEGGER     *
-*   J-Link debug probes.                                             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
---------  END-OF-HEADER  ---------------------------------------------
-File    : SEGGER_RTT_Syscalls_SES.c
-Purpose : Reimplementation of printf, puts and 
-          implementation of __putchar and __getchar using RTT in SES.
-          To use RTT for printf output, include this file in your 
-          application.
-----------------------------------------------------------------------
-*/
-#include "SEGGER_RTT.h"
-#include "__libc.h"
-#include <stdarg.h>
-#include <stdio.h>
-
-int printf(const char *fmt,...) {
-  char buffer[512];
-  va_list args;
-  va_start (args, fmt);
-  int n = vsnprintf(buffer, sizeof(buffer), fmt, args);
-  SEGGER_RTT_Write(0, buffer, n);
-  va_end(args);
-  return n;
-}
-
-int puts(const char *s) {
-  return SEGGER_RTT_WriteString(0, s);
-}
-
-int __putchar(int x, __printf_tag_ptr ctx) {
-  (void)ctx;
-  SEGGER_RTT_Write(0, (char *)&x, 1);
-  return x;
-}
-
-int __getchar() {
-  return SEGGER_RTT_WaitKey();
-}
-
-/****** End Of File *************************************************/
diff --git a/examples/device/device_virtual_com/segger/device_virtual_com.emProject b/examples/device/device_virtual_com/segger/device_virtual_com.emProject
deleted file mode 100644
index 63927ff9d..000000000
--- a/examples/device/device_virtual_com/segger/device_virtual_com.emProject
+++ /dev/null
@@ -1,218 +0,0 @@
-<!DOCTYPE CrossStudio_Project_File>
-<solution Name="device_virtual_com" target="8" version="2">
-  <project Name="device_virtual_com">
-    <configuration
-      Name="Common"
-      Placement="Flash"
-      Target="LPC4357 Cortex-M4"
-      arm_architecture="v7EM"
-      arm_core_type="Cortex-M4"
-      arm_endian="Little"
-      arm_fp_abi="Hard"
-      arm_fpu_type="FPv4-SP-D16"
-      arm_interwork="No"
-      arm_linker_heap_size="2048"
-      arm_linker_process_stack_size="0"
-      arm_linker_stack_size="2048"
-      arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00008000;ROM;0x1A000000;0x00080000;ROM;0x1B000000;0x00080000;RAM;0x20000000;0x00010000"
-      arm_target_debug_interface_type="ADIv5"
-      arm_target_device_name="LPC4357_M4"
-      arm_target_interface_type="SWD"
-      c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1"
-      c_user_include_directories="../src;$(ProjectDir)/LPC4300/CMSIS/Device/Include;$(RepoDir)/hw/cmsis/Include;$(RepoDir)/hw/mcu/nxp/lpc43xx/tusb_port;$(RepoDir)/hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc;$(RepoDir)/hw/;$(RepoDir)/tinyusb"
-      debug_register_definition_file="$(ProjectDir)/LPC43xx_Registers.xml"
-      debug_target_connection="J-Link"
-      gcc_entry_point="Reset_Handler"
-      linker_memory_map_file="$(ProjectDir)/LPC4357 Cortex-M4_MemoryMap.xml"
-      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
-      macros="DeviceHeaderFile=$(PackagesDir)/LPC4300/CMSIS/Device/Include/LPC43xx.h;DeviceLibraryIdentifier=M4lf;DeviceSystemFile=$(PackagesDir)/LPC4300/CMSIS/Device/Source/system_LPC43xx.c;DeviceVectorsFile=$(PackagesDir)/LPC4300/Source/LPC43xx_Vectors.s;DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;RepoDir=../../../.."
-      package_dependencies="LPC4300"
-      project_directory=""
-      project_type="Executable"
-      target_reset_script="Reset();"
-      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
-    <folder Name="RTT Files">
-      <file file_name="SEGGER_RTT.c" />
-      <file file_name="SEGGER_RTT.h" />
-      <file file_name="SEGGER_RTT_Conf.h" />
-      <file file_name="SEGGER_RTT_SES.c" />
-    </folder>
-    <folder Name="Script Files">
-      <file file_name="LPC4300_Target.js">
-        <configuration Name="Common" file_type="Reset Script" />
-      </file>
-    </folder>
-    <folder Name="src">
-      <configuration Name="Common" filter="c;cpp;cxx;cc;h;s;asm;inc" />
-      <file file_name="../src/main.c" />
-      <file file_name="../src/tusb_config.h" />
-      <file file_name="../src/tusb_descriptors.c" />
-      <file file_name="../src/tusb_descriptors.h" />
-    </folder>
-    <folder Name="System Files">
-      <file file_name="thumb_crt0.s" />
-      <file file_name="LPC4300_Startup.s" />
-      <file file_name="LPC43xx_Vectors.s">
-        <configuration Name="Common" file_type="Assembly" />
-      </file>
-    </folder>
-    <configuration Name="Debug" c_user_include_directories="." />
-    <folder
-      Name="tinyusb"
-      exclude=""
-      filter="*.c;*.h"
-      path="../../../../tinyusb"
-      recurse="Yes" />
-    <folder Name="hw">
-      <folder Name="bsp">
-        <file file_name="../../../../hw/bsp/ansi_escape.h" />
-        <file file_name="../../../../hw/bsp/board.c" />
-        <file file_name="../../../../hw/bsp/board.h" />
-        <file file_name="../../../../hw/bsp/printf_retarget.c" />
-        <folder Name="ea4357">
-          <file file_name="../../../../hw/bsp/ea4357/board_ea4357.c" />
-          <file file_name="../../../../hw/bsp/ea4357/board_ea4357.h" />
-          <file file_name="../../../../hw/bsp/ea4357/emac.c" />
-          <file file_name="../../../../hw/bsp/ea4357/emac.h" />
-          <file file_name="../../../../hw/bsp/ea4357/sdram.c" />
-          <file file_name="../../../../hw/bsp/ea4357/sdram.h" />
-          <folder Name="oem_base_board">
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/acc.c" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/acc.h" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/base_eeprom.c" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/base_eeprom.h" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/lm75a.c" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/lm75a.h" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/memreg.c" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/memreg.h" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/pca9532.c" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/pca9532.h" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/uda1380.c" />
-            <file file_name="../../../../hw/bsp/ea4357/oem_base_board/uda1380.h" />
-          </folder>
-        </folder>
-      </folder>
-      <folder Name="cmsis">
-        <folder Name="Include">
-          <file file_name="../../../../hw/cmsis/Include/arm_common_tables.h" />
-          <file file_name="../../../../hw/cmsis/Include/arm_const_structs.h" />
-          <file file_name="../../../../hw/cmsis/Include/arm_math.h" />
-          <file file_name="../../../../hw/cmsis/Include/cmsis_armcc.h" />
-          <file file_name="../../../../hw/cmsis/Include/cmsis_armcc_V6.h" />
-          <file file_name="../../../../hw/cmsis/Include/cmsis_gcc.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cm0.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cm0plus.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cm3.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cm4.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cm7.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cmFunc.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cmInstr.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_cmSimd.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_sc000.h" />
-          <file file_name="../../../../hw/cmsis/Include/core_sc300.h" />
-        </folder>
-      </folder>
-      <folder Name="mcu">
-        <folder Name="nxp">
-          <folder Name="lpc43xx">
-            <folder Name="CMSIS_LPC43xx_DriverLib">
-              <folder Name="inc">
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/debug_frmwrk.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_enable.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/fpu_init.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LCDTerm.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_adc.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_atimer.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_can.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_cgu.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_dac.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_emc.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_evrt.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_gpdma.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_gpio.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_i2c.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_i2s.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_lcd.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_libcfg_default.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_mcpwm.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_nvic.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_pwr.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_qei.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rgu.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rit.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_rtc.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sct.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_scu.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sdif.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_sdmmc.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_ssp.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_timer.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_uart.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc43xx_wwdt.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc_sdmmc.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/lpc_types.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/sdio.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/spifi_rom_api.h" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/system_LPC43xx.h" />
-              </folder>
-              <folder Name="src">
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/debug_frmwrk.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/Font5x7.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/LCDTerm.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_adc.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_atimer.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_can.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_dac.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_evrt.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpdma.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpio.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2s.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_lcd.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_nvic.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_pwr.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_qei.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rgu.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rit.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rtc.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sct.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdif.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdmmc.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_ssp.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_timer.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_uart.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_wwdt.c" />
-                <file file_name="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c" />
-              </folder>
-            </folder>
-            <folder Name="tusb_port">
-              <file file_name="../../../../hw/mcu/nxp/lpc43xx/tusb_port/dcd_lpc43xx.c" />
-              <file file_name="../../../../hw/mcu/nxp/lpc43xx/tusb_port/dcd_lpc43xx.h" />
-              <file file_name="../../../../hw/mcu/nxp/lpc43xx/tusb_port/hal_lpc43xx.c" />
-            </folder>
-          </folder>
-        </folder>
-      </folder>
-    </folder>
-    <configuration
-      Name="EA4357"
-      c_preprocessor_definitions="BOARD=BOARD_EA4357;CFG_TUSB_MCU=MCU_LPC43XX" />
-  </project>
-  <configuration
-    Name="Debug"
-    c_preprocessor_definitions="DEBUG"
-    gcc_debugging_level="Level 3"
-    gcc_optimization_level="None" />
-  <configuration
-    Name="Release"
-    c_preprocessor_definitions="NDEBUG"
-    gcc_debugging_level="None"
-    gcc_omit_frame_pointer="Yes"
-    gcc_optimization_level="Level 1" />
-  <configuration Name="EA4357" />
-</solution>
diff --git a/examples/device/device_virtual_com/segger/device_virtual_com.emSession b/examples/device/device_virtual_com/segger/device_virtual_com.emSession
deleted file mode 100644
index 4858f6b1d..000000000
--- a/examples/device/device_virtual_com/segger/device_virtual_com.emSession
+++ /dev/null
@@ -1,87 +0,0 @@
-<!DOCTYPE CrossStudio_Session_File>
-<session>
- <Bookmarks/>
- <Breakpoints groups="Breakpoints" active_group="Breakpoints"/>
- <ExecutionProfileWindow/>
- <FrameBufferWindow>
-  <FrameBufferWindow bufferHeight="-1" addressSpace="" addressText="" bufferWidth="-1"/>
- </FrameBufferWindow>
- <Memory1>
-  <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/>
- </Memory1>
- <Memory2>
-  <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/>
- </Memory2>
- <Memory3>
-  <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/>
- </Memory3>
- <Memory4>
-  <MemoryWindow addressSpace="" dataSize="1" autoEvaluate="0" viewMode="0" addressOrder="0" columnsText="" refreshPeriod="0" name="device_virtual_com" radix="16" sizeText="" addressText=""/>
- </Memory4>
- <Project>
-  <ProjectSessionItem path="device_virtual_com"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;bsp"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;cmsis"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp;lpc43xx"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp;lpc43xx;CMSIS_LPC43xx_DriverLib"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;hw;mcu;nxp;lpc43xx;tusb_port"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;RTT Files"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;Script Files"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;src"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;System Files"/>
-  <ProjectSessionItem path="device_virtual_com;device_virtual_com;tinyusb"/>
- </Project>
- <Register1>
-  <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/>
- </Register1>
- <Register2>
-  <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/>
- </Register2>
- <Register3>
-  <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/>
- </Register3>
- <Register4>
-  <RegisterWindow visibleNodes="CPU - Current Context/r0;CPU - Current Context/r1;CPU - Current Context/r2;CPU - Current Context/r3;CPU - Current Context/r4;CPU - Current Context/r5;CPU - Current Context/r6;CPU - Current Context/r7;CPU - Current Context/r8;CPU - Current Context/r9;CPU - Current Context/r10;CPU - Current Context/r11;CPU - Current Context/r12;CPU - Current Context/sp(r13);CPU - Current Context/lr(r14);CPU - Current Context/pc(r15);CPU - Current Context/apsr;CPU/r0;CPU/r1;CPU/r2;CPU/r3;CPU/r4;CPU/r5;CPU/r6;CPU/r7;CPU/r8;CPU/r9;CPU/r10;CPU/r11;CPU/r12;CPU/sp(r13);CPU/lr(r14);CPU/pc(r15);CPU/xpsr;CPU/msp;CPU/psp;CPU/cfbp" binaryNodes="" asciiNodes="" openNodes="CPU - Current Context" name="device_virtual_com" decimalNodes="" octalNodes="" unsignedNodes=""/>
- </Register4>
- <TraceWindow>
-  <Trace enabled="Yes"/>
- </TraceWindow>
- <Watch1>
-  <Watches active="1" update="Never"/>
- </Watch1>
- <Watch2>
-  <Watches active="0" update="Never"/>
- </Watch2>
- <Watch3>
-  <Watches active="0" update="Never"/>
- </Watch3>
- <Watch4>
-  <Watches active="0" update="Never"/>
- </Watch4>
- <Files>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="61" useTextEdit="1" useBinaryEdit="0" left="0" path="../src/main.c" debugPath="../src/main.c" selected="0" top="44" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="39" useTextEdit="1" useBinaryEdit="0" left="0" path="../src/tusb_descriptors.h" debugPath="../src/tusb_descriptors.h" selected="0" top="16" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="38" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../tinyusb/tusb_option.h" debugPath="../../../../tinyusb/tusb_option.h" selected="0" top="29" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="108" useTextEdit="1" useBinaryEdit="0" left="0" path="../src/tusb_config.h" debugPath="../src/tusb_config.h" selected="0" top="86" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="33" useTextEdit="1" useBinaryEdit="0" left="0" path="flash_placement.xml" debugPath="flash_placement.xml" selected="0" top="6" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="64" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h" debugPath="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/inc/LPC43xx.h" selected="0" top="47" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="100" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/board.h" debugPath="../../../../hw/bsp/board.h" selected="0" top="85" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="251" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/ea4357/nand.c" debugPath="../../../../hw/bsp/ea4357/nand.c" selected="0" top="243" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="276" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/ea4357/oem_base_board/norflash.c" debugPath="../../../../hw/bsp/ea4357/oem_base_board/norflash.c" selected="0" top="269" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="149" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c" debugPath="../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c" selected="0" top="130" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="45" useTextEdit="1" useBinaryEdit="0" left="0" path="LPC43xx_Vectors.s" debugPath="LPC43xx_Vectors.s" selected="1" top="22" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="0" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/board.c" debugPath="../../../../hw/bsp/board.c" selected="0" top="72" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="87" useTextEdit="1" useBinaryEdit="0" left="0" path="../../../../hw/bsp/printf_retarget.c" debugPath="../../../../hw/bsp/printf_retarget.c" selected="0" top="73" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="51" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT_SES.c" debugPath="SEGGER_RTT_SES.c" selected="0" top="44" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="332" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT.c" debugPath="SEGGER_RTT.c" selected="0" top="51" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="0" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT.h" debugPath="SEGGER_RTT.h" selected="0" top="183" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="179" useTextEdit="1" useBinaryEdit="0" left="0" path="SEGGER_RTT_Conf.h" debugPath="SEGGER_RTT_Conf.h" selected="0" top="174" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="0" useTextEdit="1" useBinaryEdit="0" left="0" path="LPC4300_Startup.s" debugPath="LPC4300_Startup.s" selected="0" top="0" codecName="Default"/>
-  <SessionOpenFile windowGroup="DockEditLeft" x="0" y="13" useTextEdit="1" useBinaryEdit="0" left="0" path="thumb_crt0.s" debugPath="thumb_crt0.s" selected="0" top="0" codecName="Default"/>
- </Files>
- <ARMCrossStudioWindow activeProject="device_virtual_com" fileDialogDefaultFilter="*.c" autoConnectTarget="J-Link" buildConfiguration="EA4357" debugSearchFileMap="" fileDialogInitialDirectory="/home/hathach/Dropbox/tinyusb/workspace/tinyusb/hw/mcu/nxp/lpc43xx/tusb_port" debugSearchPath="" autoConnectCapabilities="3199"/>
-</session>
diff --git a/examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink b/examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink
deleted file mode 100644
index 39b6d054a..000000000
--- a/examples/device/device_virtual_com/segger/device_virtual_com_EA4357.jlink
+++ /dev/null
@@ -1,39 +0,0 @@
-[BREAKPOINTS]
-ForceImpTypeAny = 0
-ShowInfoWin = 1
-EnableFlashBP = 2
-BPDuringExecution = 0
-[CFI]
-CFISize = 0x00
-CFIAddr = 0x00
-[CPU]
-MonModeVTableAddr = 0xFFFFFFFF
-MonModeDebug = 0
-MaxNumAPs = 0
-LowPowerHandlingMode = 0
-OverrideMemMap = 0
-AllowSimulation = 1
-ScriptFile=""
-[FLASH]
-CacheExcludeSize = 0x00
-CacheExcludeAddr = 0x00
-MinNumBytesFlashDL = 0
-SkipProgOnCRCMatch = 1
-VerifyDownload = 1
-AllowCaching = 1
-EnableFlashDL = 2
-Override = 0
-Device="ARM7"
-[GENERAL]
-WorkRAMSize = 0x00
-WorkRAMAddr = 0x00
-RAMUsageLimit = 0x00
-[SWO]
-SWOLogFile=""
-[MEM]
-RdOverrideOrMask = 0x00
-RdOverrideAndMask = 0xFFFFFFFF
-RdOverrideAddr = 0xFFFFFFFF
-WrOverrideOrMask = 0x00
-WrOverrideAndMask = 0xFFFFFFFF
-WrOverrideAddr = 0xFFFFFFFF
diff --git a/examples/device/device_virtual_com/segger/flash_placement.xml b/examples/device/device_virtual_com/segger/flash_placement.xml
deleted file mode 100644
index 951d23710..000000000
--- a/examples/device/device_virtual_com/segger/flash_placement.xml
+++ /dev/null
@@ -1,37 +0,0 @@
-<!DOCTYPE Linker_Placement_File>
-<Root name="Flash Section Placement">
-  <MemorySegment name="$(FLASH_NAME:FLASH)">
-    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
-    <ProgramSection alignment="4" load="Yes" name=".init" />
-    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".text" />
-    <ProgramSection alignment="4" load="Yes" name=".dtors" />
-    <ProgramSection alignment="4" load="Yes" name=".ctors" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata" />
-    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
-    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
-    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
-    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
-    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
-    <ProgramSection alignment="4" load="No" name=".fast_run" />
-    <ProgramSection alignment="4" load="No" name=".data_run" />
-    <ProgramSection alignment="4" load="No" name=".tdata_run" />
-    <ProgramSection alignment="4" load="No" name=".bss" />
-    <ProgramSection alignment="4" load="No" name=".tbss" />
-    <ProgramSection alignment="4" load="No" name=".non_init" />
-    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
-    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
-    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
-  </MemorySegment>
-  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
-    <ProgramSection alignment="4" load="Yes" name=".text2" />
-    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
-    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
-  </MemorySegment>
-  <MemorySegment name="$(RAM2_NAME:RAM2)">
-    <ProgramSection alignment="4" load="No" name=".data2_run" />
-    <ProgramSection alignment="4" load="No" name=".bss2" />
-  </MemorySegment>
-</Root>
diff --git a/examples/device/device_virtual_com/segger/thumb_crt0.s b/examples/device/device_virtual_com/segger/thumb_crt0.s
deleted file mode 100644
index 71820cb51..000000000
--- a/examples/device/device_virtual_com/segger/thumb_crt0.s
+++ /dev/null
@@ -1,420 +0,0 @@
-// SEGGER Embedded Studio, runtime support.
-//
-// Copyright (c) 2014-2017 SEGGER Microcontroller GmbH & Co KG
-// Copyright (c) 2001-2017 Rowley Associates Limited.
-//
-// This file may be distributed under the terms of the License Agreement
-// provided with this software.
-//
-// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
-// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-//
-//
-//                           Preprocessor Definitions
-//                           ------------------------
-// APP_ENTRY_POINT
-//
-//   Defines the application entry point function, if undefined this setting
-//   defaults to "main".
-//
-// INITIALIZE_STACK
-//
-//   If defined, the contents of the stack will be initialized to a the
-//   value 0xCC.
-//
-// INITIALIZE_SECONDARY_SECTIONS
-//
-//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
-//
-// INITIALIZE_TCM_SECTIONS
-//
-//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
-//   will be initialized.
-//
-// INITIALIZE_USER_SECTIONS
-//
-//   If defined, the function InitializeUserMemorySections will be called prior
-//   to entering main in order to allow the user to initialize any user defined
-//   memory sections.
-//
-// FULL_LIBRARY
-//
-//  If defined then 
-//    - argc, argv are setup by the debug_getargs.
-//    - the exit symbol is defined and executes on return from main.
-//    - the exit symbol calls destructors, atexit functions and then debug_exit.
-//  
-//  If not defined then
-//    - argc and argv are zero.
-//    - the exit symbol is defined, executes on return from main and loops
-//
-
-#ifndef APP_ENTRY_POINT
-#define APP_ENTRY_POINT main
-#endif
-
-#ifndef ARGSSPACE
-#define ARGSSPACE 128
-#endif
-  .syntax unified
-
-  .global _start
-  .extern APP_ENTRY_POINT
-  .global exit
-  .weak exit
-
-#ifdef INITIALIZE_USER_SECTIONS
-  .extern InitializeUserMemorySections
-#endif
-
-  .section .init, "ax"
-  .code 16
-  .align 2
-  .thumb_func
-
-_start:
-  /* Set up main stack if size > 0 */
-  ldr r1, =__stack_end__
-  ldr r0, =__stack_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  mov sp, r1
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  ldr r0, =__stack_start__
-  bl memory_set
-#endif
-1:
-
-  /* Set up process stack if size > 0 */
-  ldr r1, =__stack_process_end__
-  ldr r0, =__stack_process_start__
-  subs r2, r1, r0
-  beq 1f
-#ifdef __ARM_EABI__
-  movs r2, #0x7
-  bics r1, r2
-#endif
-  msr psp, r1
-  movs r2, #2
-  msr control, r2
-#ifdef INITIALIZE_STACK
-  movs r2, #0xCC
-  bl memory_set
-#endif
-1:
-
-  /* Copy initialized memory sections into RAM (if necessary). */
-  ldr r0, =__data_load_start__
-  ldr r1, =__data_start__
-  ldr r2, =__data_end__
-  bl memory_copy
-  ldr r0, =__text_load_start__
-  ldr r1, =__text_start__
-  ldr r2, =__text_end__
-  bl memory_copy
-  ldr r0, =__fast_load_start__
-  ldr r1, =__fast_start__
-  ldr r2, =__fast_end__
-  bl memory_copy
-  ldr r0, =__ctors_load_start__
-  ldr r1, =__ctors_start__
-  ldr r2, =__ctors_end__
-  bl memory_copy
-  ldr r0, =__dtors_load_start__
-  ldr r1, =__dtors_start__
-  ldr r2, =__dtors_end__
-  bl memory_copy
-  ldr r0, =__rodata_load_start__
-  ldr r1, =__rodata_start__
-  ldr r2, =__rodata_end__
-  bl memory_copy
-  ldr r0, =__tdata_load_start__
-  ldr r1, =__tdata_start__
-  ldr r2, =__tdata_end__
-  bl memory_copy
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__data2_load_start__
-  ldr r1, =__data2_start__
-  ldr r2, =__data2_end__
-  bl memory_copy
-  ldr r0, =__text2_load_start__
-  ldr r1, =__text2_start__
-  ldr r2, =__text2_end__
-  bl memory_copy
-  ldr r0, =__rodata2_load_start__
-  ldr r1, =__rodata2_start__
-  ldr r2, =__rodata2_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__data_tcm_load_start__
-  ldr r1, =__data_tcm_start__
-  ldr r2, =__data_tcm_end__
-  bl memory_copy
-  ldr r0, =__text_tcm_load_start__
-  ldr r1, =__text_tcm_start__
-  ldr r2, =__text_tcm_end__
-  bl memory_copy
-  ldr r0, =__rodata_tcm_load_start__
-  ldr r1, =__rodata_tcm_start__
-  ldr r2, =__rodata_tcm_end__
-  bl memory_copy
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Zero the bss. */
-  ldr r0, =__bss_start__
-  ldr r1, =__bss_end__
-  movs r2, #0
-  bl memory_set
-  ldr r0, =__tbss_start__
-  ldr r1, =__tbss_end__
-  movs r2, #0
-  bl memory_set
-#ifdef INITIALIZE_SECONDARY_SECTIONS
-  ldr r0, =__bss2_start__
-  ldr r1, =__bss2_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
-#ifdef INITIALIZE_TCM_SECTIONS
-  ldr r0, =__bss_tcm_start__
-  ldr r1, =__bss_tcm_end__
-  mov r2, #0
-  bl memory_set
-#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
-
-  /* Initialize the heap */
-  ldr r0, = __heap_start__
-  ldr r1, = __heap_end__
-  subs r1, r1, r0
-  cmp r1, #8
-  blt 1f
-  movs r2, #0
-  str r2, [r0]
-  adds r0, r0, #4
-  str r1, [r0]
-1:
-
-#ifdef INITIALIZE_USER_SECTIONS
-  ldr r2, =InitializeUserMemorySections
-  blx r2
-#endif
-
-  /* Call constructors */
-  ldr r0, =__ctors_start__
-  ldr r1, =__ctors_end__
-ctor_loop:
-  cmp r0, r1
-  beq ctor_end
-  ldr r2, [r0]
-  adds r0, #4
-  push {r0-r1}  
-  blx r2
-  pop {r0-r1}
-  b ctor_loop
-ctor_end:
-
-  /* Setup initial call frame */
-  movs r0, #0
-  mov lr, r0
-  mov r12, sp
-
-  .type start, function
-start:
-  /* Jump to application entry point */
-#ifdef FULL_LIBRARY
-  movs r0, #ARGSSPACE
-  ldr r1, =args
-  ldr r2, =debug_getargs  
-  blx r2
-  ldr r1, =args
-#else
-  movs r0, #0
-  movs r1, #0
-#endif
-  ldr r2, =APP_ENTRY_POINT
-  blx r2
-
-  .thumb_func
-exit:
-#ifdef FULL_LIBRARY  
-  mov r5, r0 // save the exit parameter/return result
-
-  /* Call destructors */
-  ldr r0, =__dtors_start__
-  ldr r1, =__dtors_end__
-dtor_loop:
-  cmp r0, r1
-  beq dtor_end
-  ldr r2, [r0]
-  add r0, #4
-  push {r0-r1}
-  blx r2
-  pop {r0-r1}
-  b dtor_loop
-dtor_end:
-
-  /* Call atexit functions */
-  ldr r2, =_execute_at_exit_fns  
-  blx r2
-
-  /* Call debug_exit with return result/exit parameter */
-  mov r0, r5
-  ldr r2, =debug_exit  
-  blx r2
-#endif
-
-  /* Returned from application entry point, loop forever. */
-exit_loop:
-  b exit_loop
-
-  .thumb_func
-memory_copy:
-  cmp r0, r1
-  beq 2f
-  subs r2, r2, r1
-  beq 2f
-1:
-  ldrb r3, [r0]
-  adds r0, r0, #1
-  strb r3, [r1]
-  adds r1, r1, #1
-  subs r2, r2, #1
-  bne 1b
-2:
-  bx lr
-
-  .thumb_func
-memory_set:
-  cmp r0, r1
-  beq 1f
-  strb r2, [r0]
-  adds r0, r0, #1
-  b memory_set
-1:
-  bx lr
-
-  // default C/C++ library helpers
-
-.macro HELPER helper_name
-  .section .text.\helper_name, "ax", %progbits
-  .global \helper_name
-  .weak \helper_name  
-\helper_name:
-  .thumb_func
-.endm
-
-.macro JUMPTO name
-#if defined(__thumb__) && !defined(__thumb2__)
-  mov r12, r0
-  ldr r0, =\name
-  push {r0}
-  mov r0, r12
-  pop {pc}
-#else
-  b \name
-#endif
-.endm
-
-HELPER __aeabi_read_tp
-  ldr r0, =__tbss_start__-8
-  bx lr
-HELPER __heap_lock
-  bx lr
-HELPER __heap_unlock
-  bx lr
-HELPER __printf_lock
-  bx lr
-HELPER __printf_unlock
-  bx lr
-HELPER __scanf_lock
-  bx lr
-HELPER __scanf_unlock
-  bx lr
-HELPER __debug_io_lock
-  bx lr
-HELPER __debug_io_unlock
-  bx lr
-HELPER abort
-  b .
-HELPER __assert
-  b .
-HELPER __aeabi_assert
-  b .
-HELPER __cxa_pure_virtual
-  b .
-HELPER __cxa_guard_acquire
-  ldr r3, [r0]
-#if defined(__thumb__) && !defined(__thumb2__)
-  movs r0, #1
-  tst r3, r0
-#else
-  tst r3, #1
-#endif
-  beq 1f
-  movs r0, #0
-  bx lr
-1:
-  movs r0, #1
-  bx lr
-HELPER __cxa_guard_release
-  movs r3, #1
-  str r3, [r0]
-  bx lr
-HELPER __cxa_guard_abort
-  bx lr
-HELPER __sync_synchronize
-  bx lr
-HELPER __getchar
-  JUMPTO debug_getchar
-HELPER __putchar
-  JUMPTO debug_putchar
-HELPER __open
-  JUMPTO debug_fopen
-HELPER __close
-  JUMPTO debug_fclose
-HELPER __write   
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1  
-  JUMPTO debug_fwrite
-HELPER __read  
-  mov r3, r0
-  mov r0, r1
-  movs r1, #1 
-  JUMPTO debug_fread
-HELPER __seek
-  push {r4, lr}
-  mov r4, r0
-  bl debug_fseek
-  cmp r0, #0
-  bne 1f
-  mov r0, r4
-  bl debug_ftell
-  pop {r4, pc}
-1:
-  ldr r0, =-1
-  pop {r4, pc}
-  // char __user_locale_name_buffer[];
-  .section .bss.__user_locale_name_buffer, "aw", %nobits
-  .global __user_locale_name_buffer
-  .weak __user_locale_name_buffer
-  __user_locale_name_buffer:
-  .word 0x0
-
-#ifdef FULL_LIBRARY
-  .bss
-args:
-  .space ARGSSPACE
-#endif
-
-  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
-  .section .stack, "wa", %nobits
-  .section .stack_process, "wa", %nobits
-  .section .heap, "wa", %nobits
-
diff --git a/examples/device/device_virtual_com/src/main.c b/examples/device/device_virtual_com/src/main.c
deleted file mode 100644
index 60f93a000..000000000
--- a/examples/device/device_virtual_com/src/main.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     main.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "bsp/board.h"
-#include "tusb.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-void print_greeting(void);
-void led_blinking_task(void);
-void virtual_com_task(void);
-
-/*------------- MAIN -------------*/
-int main(void)
-{
-  board_init();
-  print_greeting();
-
-  tusb_init();
-
-  while (1)
-  {
-    tusb_task();
-
-    led_blinking_task();
-    virtual_com_task();
-  }
-
-  return 0;
-}
-
-void virtual_com_task(void)
-{
-  // connected and there are data available
-  if ( tud_mounted() && tud_cdc_available() )
-  {
-    uint8_t buf[64];
-
-    // read and echo back
-    uint32_t count = tud_cdc_read(buf, sizeof(buf));
-
-    tud_cdc_write(buf, count);
-  }
-}
-
-
-//--------------------------------------------------------------------+
-// tinyusb callbacks
-//--------------------------------------------------------------------+
-void tud_mount_cb(void)
-{
-
-}
-
-void tud_umount_cb(void)
-{
-}
-
-void tud_cdc_rx_cb(uint8_t itf)
-{
-}
-
-//--------------------------------------------------------------------+
-// BLINKING TASK
-//--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
-  enum { BLINK_INTEVAL = 1000 };
-
-  static bool led_state = false;
-  static uint32_t last_blink = 0;
-
-  // not enough time
-  if ( last_blink + BLINK_INTEVAL > tusb_hal_tick_get() ) return;
-
-  last_blink += BLINK_INTEVAL;
-
-  board_led_control(BOARD_LED0, led_state);
-  led_state = 1 - led_state; // toggle
-}
-
-//--------------------------------------------------------------------+
-// HELPER FUNCTION
-//--------------------------------------------------------------------+
-void print_greeting(void)
-{
-  char const * const rtos_name[] =
-  {
-      [OPT_OS_NONE]      = "None",
-      [OPT_OS_FREERTOS]  = "FreeRTOS",
-  };
-
-  printf("\n\
---------------------------------------------------------------------\n\
--                     Device Demo (a tinyusb example)\n\
-- if you find any bugs or get any questions, feel free to file an\n\
-- issue at https://github.com/hathach/tinyusb\n\
---------------------------------------------------------------------\n\n"
-  );
-
-  puts("This DEVICE demo is configured to support:");
-  printf("  - RTOS = %s\n", rtos_name[CFG_TUSB_OS]);
-  if (CFG_TUD_HID_MOUSE    ) puts("  - HID Mouse");
-  if (CFG_TUD_HID_KEYBOARD ) puts("  - HID Keyboard");
-  if (CFG_TUD_MSC          ) puts("  - Mass Storage");
-  if (CFG_TUD_CDC          ) puts("  - Communication Device Class");
-}
diff --git a/examples/device/device_virtual_com/src/tusb_config.h b/examples/device/device_virtual_com/src/tusb_config.h
deleted file mode 100644
index 77be85df3..000000000
--- a/examples/device/device_virtual_com/src/tusb_config.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     tusb_config.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#ifndef _TUSB_CONFIG_H_
-#define _TUSB_CONFIG_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// CONTROLLER CONFIGURATION
-//--------------------------------------------------------------------+
-//#define CFG_TUSB_MCU will be passed from IDE/command line for easy board/mcu switching
-
-#define CFG_TUSB_RHPORT0_MODE  (OPT_MODE_DEVICE)
-//#define CFG_TUSB_RHPORT1_MODE  (OPT_MODE_DEVICE)
-
-#define CFG_TUSB_DEBUG            2
-
-/*------------- RTOS -------------*/
-//#define CFG_TUSB_OS               OPT_OS_NONE // be passed from IDE/command line for easy project switching
-//#define CFG_TUD_TASK_PRIO         0
-//#define CFG_TUD_TASK_QUEUE_SZ     16
-//#define CFG_TUD_TASK_STACK_SZ     150
-
-//--------------------------------------------------------------------+
-// DEVICE CONFIGURATION
-//--------------------------------------------------------------------+
-
-/*------------- Core -------------*/
-#define CFG_TUD_DESC_AUTO         1
-
-// #define CFG_TUD_DESC_VID          0xCAFE
-// #define CFG_TUD_DESC_PID          0x0001
-
-#define CFG_TUD_ENDOINT0_SIZE     64
-
-
-//------------- CLASS -------------//
-#define CFG_TUD_CDC               1
-#define CFG_TUD_MSC               0
-#define CFG_TUD_HID_KEYBOARD      0
-#define CFG_TUD_HID_MOUSE         0
-
-
-/*------------------------------------------------------------------*/
-/* CLASS DRIVER
- *------------------------------------------------------------------*/
-
-// FIFO size of CDC TX and RX
-#define CFG_TUD_CDC_RX_BUFSIZE    64
-#define CFG_TUD_CDC_TX_BUFSIZE    64
-
-//--------------------------------------------------------------------+
-// USB RAM PLACEMENT
-//--------------------------------------------------------------------+
-#ifdef __CODE_RED // compiled with lpcxpresso
-
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
-    #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(.data.$RAM2) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned
-  #elif CFG_TUSB_MCU == OPT_MCU_LPC175X_6X
-    #define CFG_TUSB_MEM_SECTION // LPC17xx USB DMA can access all
-  #elif  (CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-    #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(.data.$RAM3)
-  #endif
-
-#elif defined  __CC_ARM // Compiled with Keil armcc, USBRAM_SECTION is defined in scatter files
-
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
-    #define CFG_TUSB_MEM_SECTION  ATTR_SECTION(USBRAM_SECTION) ATTR_ALIGNED(64) // lp11u & lp13u requires data to be 64 byte aligned
-  #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
-    #define CFG_TUSB_MEM_SECTION  // LPC17xx USB DMA can access all address
-  #elif  (CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-    #define CFG_TUSB_MEM_SECTION // Use keil tool configure to have AHB SRAM as default memory
-  #endif
-
-#elif defined __ICCARM__ // compiled with IAR
-
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || (CFG_TUSB_MCU == OPT_MCU_LPC13XX)
-    #define CFG_TUSB_MEM_SECTION _Pragma("location=\"USB_PACKET_MEMORY\"") ATTR_ALIGNED(64)
-  #elif (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
-    #define CFG_TUSB_MEM_SECTION
-  #elif  (CFG_TUSB_MCU == OPT_MCU_LPC43XX)
-    #define CFG_TUSB_MEM_SECTION _Pragma("location=\".ahb_sram1\"")
-  #endif
-
-#elif defined __SES_ARM
-
-#define CFG_TUSB_MEM_SECTION  ATTR_SECTION(.bss2)
-
-#else
-
-  #error compiler not specified
-
-#endif
-
-
-// LPC11uxx and LPC13uxx requires each buffer has to be 64-byte alignment
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX
- #define CFG_TUSB_MEM_ALIGN   ATTR_ALIGNED(64)
-#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
- #define CFG_TUSB_MEM_ALIGN   ATTR_ALIGNED(4)
-#else
- #define CFG_TUSB_MEM_ALIGN
-#endif
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/device_virtual_com/src/tusb_descriptors.c b/examples/device/device_virtual_com/src/tusb_descriptors.c
deleted file mode 100644
index 2ba5434cc..000000000
--- a/examples/device/device_virtual_com/src/tusb_descriptors.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     tusb_descriptors.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb.h"
-
-//--------------------------------------------------------------------+
-// STRING DESCRIPTORS
-//--------------------------------------------------------------------+
-#define STRING_LEN_UNICODE(n) (2 + (2*(n))) // also includes 2 byte header
-#define ENDIAN_BE16_FROM( high, low) ENDIAN_BE16(high << 8 | low)
-
-// array of pointer to string descriptors
-uint16_t const * const string_desc_arr [] =
-{
-    [0] = (uint16_t []) { // supported language
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(1), TUSB_DESC_STRING ),
-        0x0409 // English
-    },
-
-    [1] = (uint16_t []) { // manufacturer
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(11), TUSB_DESC_STRING),
-        't', 'i', 'n', 'y', 'u', 's', 'b', '.', 'o', 'r', 'g' // len = 11
-    },
-
-    [2] = (uint16_t []) { // product
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(14), TUSB_DESC_STRING),
-        't', 'i', 'n', 'y', 'u', 's', 'b', ' ', 'd', 'e', 'v', 'i', 'c', 'e' // len = 14
-    },
-
-    [3] = (uint16_t []) { // serials
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(4), TUSB_DESC_STRING),
-        '1', '2', '3', '4' // len = 4
-    },
-
-    [4] = (uint16_t []) { // CDC Interface
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(3), TUSB_DESC_STRING),
-        'c', 'd', 'c' // len = 3
-    },
-
-    [5] = (uint16_t []) { // Keyboard Interface
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(5), TUSB_DESC_STRING),
-        'm', 'o', 'u', 's', 'e' // len = 5
-    },
-
-    [6] = (uint16_t []) { // Keyboard Interface
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(8), TUSB_DESC_STRING),
-        'k', 'e', 'y', 'b', 'o', 'a', 'r', 'd' // len = 8
-    },
-
-    [7] = (uint16_t []) { // MSC Interface
-        ENDIAN_BE16_FROM( STRING_LEN_UNICODE(3), TUSB_DESC_STRING),
-        'm', 's', 'c' // len = 3
-    }
-};
-
-
-// tud_desc_set is required by tinyusb stack
-// since CFG_TUD_DESC_AUTO is enabled, we only need to set string_arr
-tud_desc_set_t tud_desc_set =
-{
-    .device     = NULL,
-    .config     = NULL,
-    .string_arr = (uint8_t const **) string_desc_arr,
-    .hid_report = NULL
-};
diff --git a/examples/device/device_virtual_com/xpresso/.cproject b/examples/device/device_virtual_com/xpresso/.cproject
deleted file mode 100644
index 1e76a688c..000000000
--- a/examples/device/device_virtual_com/xpresso/.cproject
+++ /dev/null
@@ -1,207 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.crt.advproject.config.exe.debug.1203173668.586387399">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1203173668.586387399" moduleId="org.eclipse.cdt.core.settings" name="EA4357">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.1203173668.586387399" name="EA4357" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; # arm-none-eabi-objcopy -v -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
-					<folderInfo id="com.crt.advproject.config.exe.debug.1203173668.586387399." name="/" resourcePath="">
-						<toolChain id="com.crt.advproject.toolchain.exe.debug.797521259" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
-							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.546357503" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
-							<builder buildPath="${workspace_loc:/device_virtual_com}/Debug" id="com.crt.advproject.builder.exe.debug.1377782676" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
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-								<option id="com.crt.advproject.link.crpenable.983788363" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.crpenable" useByScannerDiscovery="false" value="false" valueType="boolean"/>
-								<option id="com.crt.advproject.link.gcc.multicore.slave.312914823" name="Multicore configuration" superClass="com.crt.advproject.link.gcc.multicore.slave" useByScannerDiscovery="false"/>
-								<option defaultValue="com.crt.advproject.heapAndStack.lpcXpressoStyle" id="com.crt.advproject.link.memory.heapAndStack.style.848801259" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style" useByScannerDiscovery="false" valueType="enumerated"/>
-								<option id="com.crt.advproject.link.memory.load.image.959137799" superClass="com.crt.advproject.link.memory.load.image" value="" valueType="string"/>
-								<option id="com.crt.advproject.link.memory.data.296058697" superClass="com.crt.advproject.link.memory.data" value="" valueType="string"/>
-								<option id="com.crt.advproject.link.memory.sections.459230125" superClass="com.crt.advproject.link.memory.sections" valueType="stringList"/>
-								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1952169203" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
-									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-								</inputType>
-							</tool>
-						</toolChain>
-					</folderInfo>
-					<sourceEntries>
-						<entry excluding="hw/bsp/hitex|hw/bsp/keil|hw/mcu/nordic|hw/bsp/lpcxpresso|hw/mcu/nxp/lpc13uxx|hw/bsp/lpcxpresso1347|hw/mcu/nxp/lpc11uxx|hw/bsp/lpcxpresso1769|hw/mcu/nxp/lpc175x_6x|hw/bsp/pca10056|hw/bsp/ngx|hw/bsp/lpcxpresso11u68" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
-					</sourceEntries>
-				</configuration>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-	</storageModule>
-	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="device_virtual_com.com.crt.advproject.projecttype.exe.577278554" name="Executable" projectType="com.crt.advproject.projecttype.exe"/>
-	</storageModule>
-	<storageModule moduleId="scannerConfiguration">
-		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
-	<storageModule moduleId="com.crt.config">
-		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;
-&lt;TargetConfig&gt;
-&lt;Properties property_0="None" property_2="LPC18x7_43x7_2x512_BootA.cfx" property_3="NXP" property_4="LPC4357" property_count="5" version="100200"/&gt;
-&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC4357" flash_driver="LPC18x7_43x7_2x512_BootA.cfx" match_id="0x0" name="LPC4357" resetscript="LPC18LPC43InternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC4357&lt;/name&gt;
-&lt;family&gt;LPC43xx&lt;/family&gt;
-&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;
-&lt;reset board="None" core="Real" sys="Real"/&gt;
-&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;
-&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;
-&lt;memory id="RAM" type="RAM"/&gt;
-&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;
-&lt;memoryInstance derived_from="Flash" edited="true" id="MFlashA512" location="0x1a000000" size="0x80000"/&gt;
-&lt;memoryInstance derived_from="Flash" edited="true" id="MFlashB512" location="0x1b000000" size="0x80000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="RamLoc32" location="0x10000000" size="0x8000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="RamLoc40" location="0x10080000" size="0xa000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="RamAHB32" location="0x20000000" size="0x8000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="RamAHB16" location="0x20008000" size="0x4000"/&gt;
-&lt;memoryInstance derived_from="RAM" edited="true" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/&gt;
-&lt;prog_flash blocksz="0x2000" location="0x1a000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;
-&lt;prog_flash blocksz="0x10000" location="0x1a010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/&gt;
-&lt;prog_flash blocksz="0x2000" location="0x1b000000" maxprgbuff="0x400" progwithcode="TRUE" size="0x10000"/&gt;
-&lt;prog_flash blocksz="0x10000" location="0x1b010000" maxprgbuff="0x400" progwithcode="TRUE" size="0x70000"/&gt;
-&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;
-&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;
-&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;
-&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;
-&lt;peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/&gt;
-&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/&gt;
-&lt;peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/&gt;
-&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/&gt;
-&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/&gt;
-&lt;peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/&gt;
-&lt;peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/&gt;
-&lt;peripheralInstance derived_from="LCD" id="LCD" location="0x40008000"/&gt;
-&lt;peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/&gt;
-&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/&gt;
-&lt;peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/&gt;
-&lt;peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/&gt;
-&lt;peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/&gt;
-&lt;peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/&gt;
-&lt;peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/&gt;
-&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/&gt;
-&lt;peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/&gt;
-&lt;peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/&gt;
-&lt;peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/&gt;
-&lt;peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/&gt;
-&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/&gt;
-&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/&gt;
-&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/&gt;
-&lt;peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/&gt;
-&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/&gt;
-&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/&gt;
-&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/&gt;
-&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/&gt;
-&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/&gt;
-&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/&gt;
-&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/&gt;
-&lt;peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/&gt;
-&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/&gt;
-&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/&gt;
-&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/&gt;
-&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/&gt;
-&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/&gt;
-&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/&gt;
-&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/&gt;
-&lt;peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/&gt;
-&lt;peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/&gt;
-&lt;peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/&gt;
-&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/&gt;
-&lt;peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/&gt;
-&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/&gt;
-&lt;peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/&gt;
-&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/&gt;
-&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/&gt;
-&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/&gt;
-&lt;peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/&gt;
-&lt;peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/&gt;
-&lt;/chip&gt;
-&lt;processor&gt;&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;
-&lt;family&gt;Cortex-M&lt;/family&gt;
-&lt;/processor&gt;
-&lt;link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/&gt;
-&lt;/info&gt;
-&lt;/infoList&gt;
-&lt;/TargetConfig&gt;</projectStorage>
-	</storageModule>
-	<storageModule moduleId="refreshScope" versionNumber="2">
-		<configuration configurationName="Debug">
-			<resource resourceType="PROJECT" workspacePath="/device_virtual_com"/>
-		</configuration>
-		<configuration configurationName="Release">
-			<resource resourceType="PROJECT" workspacePath="/device_virtual_com"/>
-		</configuration>
-	</storageModule>
-	<storageModule moduleId="com.crt.advproject">
-		<boardId>MCB4357</boardId>
-	</storageModule>
-	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
-</cproject>
diff --git a/examples/device/device_virtual_com/xpresso/.project b/examples/device/device_virtual_com/xpresso/.project
deleted file mode 100644
index c3c9ed67d..000000000
--- a/examples/device/device_virtual_com/xpresso/.project
+++ /dev/null
@@ -1,63 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>device_virtual_com</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<triggers>full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-	<linkedResources>
-		<link>
-			<name>hw</name>
-			<type>2</type>
-			<locationURI>PARENT-4-PROJECT_LOC/hw</locationURI>
-		</link>
-		<link>
-			<name>src</name>
-			<type>2</type>
-			<locationURI>PARENT-1-PROJECT_LOC/src</locationURI>
-		</link>
-		<link>
-			<name>tinyusb</name>
-			<type>2</type>
-			<locationURI>PARENT-4-PROJECT_LOC/src</locationURI>
-		</link>
-	</linkedResources>
-	<filteredResources>
-		<filter>
-			<id>1520932840443</id>
-			<name></name>
-			<type>22</type>
-			<matcher>
-				<id>org.eclipse.ui.ide.multiFilter</id>
-				<arguments>1.0-name-matches-false-false-*.d</arguments>
-			</matcher>
-		</filter>
-		<filter>
-			<id>1520932840444</id>
-			<name></name>
-			<type>22</type>
-			<matcher>
-				<id>org.eclipse.ui.ide.multiFilter</id>
-				<arguments>1.0-name-matches-false-false-*.o</arguments>
-			</matcher>
-		</filter>
-	</filteredResources>
-</projectDescription>
diff --git a/src/tusb_option.h b/src/tusb_option.h
index ea15f6c5d..fa7bfde0c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -48,12 +48,12 @@
 /** \defgroup group_mcu Supported MCU
  * \ref CFG_TUSB_MCU must be defined to one of these
  *  @{ */
-#define OPT_MCU_LPC11UXX       1 ///< NXP LPC11Uxx series
+#define OPT_MCU_LPC11UXX       1 ///< NXP LPC11Uxx
 
-#define OPT_MCU_LPC13XX       3 ///< NXP LPC13xx 12 bit ADC series
-#define OPT_MCU_LPC175X_6X     4 ///< NXP LPC175x, LPC176x series
-#define OPT_MCU_LPC177X_8X     5 ///< NXP LPC177x, LPC178x series (not supported yet)
-#define OPT_MCU_LPC18XX        6 ///< NXP LPC18xx series (not supported yet)
+#define OPT_MCU_LPC13XX        3 ///< NXP LPC13xx
+#define OPT_MCU_LPC175X_6X     4 ///< NXP LPC175x, LPC176x
+#define OPT_MCU_LPC177X_8X     5 ///< NXP LPC177x, LPC178x
+#define OPT_MCU_LPC18XX        6 ///< NXP LPC18xx series
 #define OPT_MCU_LPC43XX        7 ///< NXP LPC43xx series
 
 #define OPT_MCU_NRF5X        100 ///< Nordic nRF5x series
-- 
cgit v1.3.1


From 804c60304ef0c16b5ff593d6aa4143957fc180dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 13:25:58 +0700
Subject: adding ses lpc13xx

---
 .../device/cdc_msc_hid/ses/cdc_msc_hid.emProject   |    1 +
 .../cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s      |  113 +
 .../cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js      |   19 +
 .../ses/lpc13xx/LPC1347FBD64_MemoryMap.xml         |    6 +
 .../cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml | 5515 ++++++++++++++++++++
 .../cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s     |  342 ++
 .../cdc_msc_hid/ses/lpc13xx/flash_placement.xml    |   37 +
 .../cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject      |  105 +
 .../device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s    |  415 ++
 src/tusb_option.h                                  |    4 +-
 10 files changed, 6555 insertions(+), 2 deletions(-)
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
index 93f70e222..6a7fed690 100644
--- a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
+++ b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
@@ -5,4 +5,5 @@
   <import file_name="samd51/samd51.emProject" />
   <import file_name="lpc43xx/lpc43xx.emProject" />
   <import file_name="lpc175x_6x/lpc175x_6x.emProject" />
+  <import file_name="lpc13xx/lpc13xx.emProject" />
 </solution>
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s
new file mode 100644
index 000000000..ad41afb99
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Startup.s
@@ -0,0 +1,113 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                         Preprocessor Definitions                          *
+ *                         ------------------------                          *
+ * NO_STACK_INIT                                                             *
+ *                                                                           *
+ *   If defined, the stack pointer will not be initialised.                  *
+ *                                                                           *
+ * NO_SYSTEM_INIT                                                            *
+ *                                                                           *
+ *   If defined, the SystemInit() function will not be called. By default    *
+ *   SystemInit() is called after reset to enable the clocks and memories to *
+ *   be initialised prior to any C startup initialisation.                   *
+ *                                                                           *
+ * NO_VTOR_CONFIG                                                            *
+ *                                                                           *
+ *   If defined, the vector table offset register will not be configured.    *
+ *                                                                           *
+ * MEMORY_INIT                                                               *
+ *                                                                           *
+ *   If defined, the MemoryInit() function will be called. By default        *
+ *   MemoryInit() is called after SystemInit() to enable an external memory  *
+ *   controller.                                                             *
+ *                                                                           *
+ * STACK_INIT_VAL                                                            *
+ *                                                                           *
+ *   If defined, specifies the initial stack pointer value. If undefined,    *
+ *   the stack pointer will be initialised to point to the end of the        *
+ *   RAM segment.                                                            *
+ *                                                                           *
+ * VECTORS_IN_RAM                                                            *
+ *                                                                           *
+ *   If defined, the exception vectors will be copied from Flash to RAM.     *
+ *                                                                           *
+ *****************************************************************************/
+
+  .syntax unified
+
+  .global Reset_Handler
+  .extern _vectors
+
+  .section .init, "ax"
+  .thumb_func
+
+  .equ VTOR_REG, 0xE000ED08
+
+#ifndef STACK_INIT_VAL
+#define STACK_INIT_VAL __RAM_segment_end__
+#endif
+
+Reset_Handler:
+#ifndef NO_STACK_INIT
+  /* Initialise main stack */
+  ldr r0, =STACK_INIT_VAL
+  bic r0, #0x7
+  mov sp, r0
+#endif
+
+#ifndef NO_SYSTEM_INIT
+  /* Initialise system */
+  ldr r0, =SystemInit
+  blx r0
+  .pushsection .init_array, "aw", %init_array
+  .word SystemCoreClockUpdate
+  .popsection
+#endif
+
+#ifdef MEMORY_INIT
+  ldr r0, =MemoryInit
+  blx r0
+#endif
+
+#ifdef VECTORS_IN_RAM
+  /* Copy exception vectors into RAM */
+  ldr r0, =__vectors_start__
+  ldr r1, =__vectors_end__
+  ldr r2, =__vectors_ram_start__
+1:
+  cmp r0, r1
+  beq 2f
+  ldr r3, [r0]
+  str r3, [r2]
+  adds r0, r0, #4
+  adds r2, r2, #4
+  b 1b
+2:
+#endif
+
+#ifndef NO_VTOR_CONFIG
+  /* Configure vector table offset register */
+  ldr r0, =VTOR_REG
+#ifdef VECTORS_IN_RAM
+  ldr r1, =_vectors_ram
+#else
+  ldr r1, =_vectors
+#endif
+  str r1, [r0]
+#endif
+
+  /* Jump to program start */
+  b _start
+
+
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js
new file mode 100644
index 000000000..20560af43
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1300_Target.js
@@ -0,0 +1,19 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+function Reset() {
+  TargetInterface.resetAndStop();
+}
+
+function EnableTrace(traceInterfaceType) {
+  // TODO: Enable trace
+}
+
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
new file mode 100644
index 000000000..bdc880272
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC1347FBD64_MemoryMap.xml
@@ -0,0 +1,6 @@
+<!DOCTYPE Board_Memory_Definition_File>
+<root name="LPC1347FBD64">
+  <MemorySegment name="FLASH" start="0x00000000" size="0x00010000" access="ReadOnly" />
+  <MemorySegment name="RAM" start="0x10000000" size="0x00002000" access="Read/Write" />
+  <MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" />
+</root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml
new file mode 100644
index 000000000..0f605ce04
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Registers.xml
@@ -0,0 +1,5515 @@
+<!DOCTYPE Register_Definition_File>
+<Processor name="LPC13Uxx" description="LPC1315/16/17/35/36/37 Cortex-M3 MCU; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM">
+  <RegisterGroup name="I2C" start="0x40000000" description="I2C">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I2C_MODULE_WILL_" start="1" description="The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="HIGH" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="NORMAL" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="MATCH" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="ANYADDRESS" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from reserved bits is undefined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDT" start="0x40004000" description="Windowed Watchdog Timer (WWDT) ">
+    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
+        <Enum name="STOPPED" start="0" description="The watchdog timer is stopped." />
+        <Enum name="RUNNING" start="1" description="The watchdog timer is running." />
+      </BitField>
+      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0.">
+        <Enum name="INTERRUPT" start="0" description="A watchdog timeout will not cause a chip reset." />
+        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
+      </BitField>
+      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1." />
+      <BitField start="3" size="1" name="WDINT" description="Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software." />
+      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit can be set once by software and is only cleared by a reset.">
+        <Enum name="NOT_LOCKED" start="0" description="The watchdog time-out value (TC) can be changed at any time." />
+        <Enum name="LOCKED" start="1" description="The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
+      </BitField>
+      <BitField start="5" size="1" name="LOCK" description="A 1 in this bit prevents disabling or powering down the clock source selected by bit 0 of the WDCLKSRC register and also prevents switching to a clock source that is disabled or powered down. This bit can be set once by software and is only cleared by any reset. If this bit is one and the WWDT clock source is the IRC when Deep-sleep or Power-down modes are entered, the IRC remains running thereby increasing power consumption in Deep-sleep mode and potentially preventing the part of entering Power-down mode correctly (see Section 15.7)." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This 24-bit register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="COUNT" description="Watchdog time-out value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="FEED" description="Feed value should be 0xAA followed by 0x55." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="COUNT" description="Counter timer value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CLKSEL" access="Read/Write" description="Watchdog clock select register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLKSEL" description="Selects source of WDT clock">
+        <Enum name="IRC" start="0" description="IRC" />
+        <Enum name="WATCHDOG_OSCILLATOR_" start="1" description="Watchdog oscillator (WDOSC)" />
+      </BitField>
+      <BitField start="1" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="31" size="1" name="LOCK" description="If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0." />
+    </Register>
+    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CT16B0" start="0x4000C000" description="16-bit counter/timers CT16B0">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="Counter enable.">
+        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
+      </BitField>
+      <BitField start="1" size="1" name="CRST" description="Counter reset.">
+        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TC" description="Timer counter value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="PCVAL" description="Prescale value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="PC" description="Prescale counter value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT16B0_CAP0 rising edge: a sequence of 0 then 1 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT16B0_CAP0 falling edge: a sequence of 1 then 0 on CT16B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT16B0_CAP0 event: a CR0 load due to a CT16B0_CAP0 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="CAP1RE" description="Capture on CT16B0_CAP1 rising edge: a sequence of 0 then 1 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP1FE" description="Capture on CT16B0_CAP1 falling edge: a sequence of 1 then 0 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC. This bit is reserved for 16-bit timer1 CT16B1.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP1I" description="Interrupt on CT16B0_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt. This bit is reserved for 16-bit timer1 CT16B1.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x034" size="4" name="CR1" access="ReadOnly" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B0_CAP1 input." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved.">
+        <Enum name="CT16B0_CAP0_" start="0x0" description="CT16B0_CAP0." />
+        <Enum name="RESERVED_" start="0x1" description="Reserved." />
+        <Enum name="CT16B0_CAP1_" start="0x2" description="CT16B0_CAP1." />
+      </BitField>
+      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
+      <BitField start="5" size="3" name="SELCC" description="Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
+        <Enum name="RISING_EDGE_OF_CT16B" start="0x0" description="Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)." />
+        <Enum name="FALLING_EDGE_OF_CT16" start="0x1" description="Falling Edge of CT16B0_CCAP0 clears the timer (if bit 4 is set)." />
+        <Enum name="RESERVED_" start="0x2" description="Reserved." />
+        <Enum name="RESERVED_" start="0x3" description="Reserved." />
+        <Enum name="RISING_EDGE_OF_CT16B" start="0x4" description="Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)." />
+        <Enum name="FALLING_EDGE_OF_CT16" start="0x5" description="Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
+        <Enum name="CT16BN_MAT0_IS_CONTR" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
+      </BitField>
+      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
+        <Enum name="CT16BN_MAT01_IS_CONT" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
+      </BitField>
+      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
+        <Enum name="CT16BN_MAT2_IS_CONTR" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
+        <Enum name="CT16BN_MAT3_IS_CONTR" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CT16B1" start="0x40010000" description="16-bit counter/timers CT16B1">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="Counter enable.">
+        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
+      </BitField>
+      <BitField start="1" size="1" name="CRST" description="Counter reset.">
+        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TC" description="Timer counter value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="PCVAL" description="Prescale value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="PC" description="Prescale counter value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH" description="Timer counter match value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT16B1_CAP0 rising edge: a sequence of 0 then 1 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT16B11_CAP0 falling edge: a sequence of 1 then 0 on CT16B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT16B1_CAP0 event: a CR0 load due to a CT16B1_CAP0 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CT16B1_CAP1 rising edge: a sequence of 0 then 1 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CT16B1_CAP1 falling edge: a sequence of 1 then 0 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CT16B1_CAP1 event: a CR1 load due to a CT16B0_CAP1 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x030" size="4" name="CR1" access="ReadOnly" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT16B1_CAP1 input." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="16" name="CAP" description="Timer counter capture value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of match channel 2. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0. Table 296 shows the encoding of these bits.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT0 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT0 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT1 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT1 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT2 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT2 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT16Bn_MAT3 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT16Bn_MAT3 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x2 to 0x3 are reserved.">
+        <Enum name="CT16B1_CAP0_" start="0x0" description="CT16B1_CAP0." />
+        <Enum name="CT16B1_CAP1_" start="0x1" description="CT16B1_CAP1." />
+      </BitField>
+      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
+      <BitField start="5" size="3" name="SELCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x6 to 0x7 are reserved.">
+        <Enum name="RISING_EDGE_OF_CT16B" start="0x0" description="Rising Edge of CT16B1_CAP0 clears the timer (if bit 4 is set)." />
+        <Enum name="FALLING_EDGE_OF_CT16" start="0x1" description="Falling Edge of CT16B1_CAP0 clears the timer (if bit 4 is set)." />
+        <Enum name="RISING_EDGE_OF_CT16B" start="0x2" description="Rising Edge of CT16B1_CAP1 clears the timer (if bit 4 is set)." />
+        <Enum name="FALLING_EDGE_OF_CT16" start="0x3" description="Falling Edge of CT16B1_CAP1 clears the timer (if bit 4 is set)." />
+        <Enum name="RESERVED_" start="0x4" description="Reserved." />
+        <Enum name="RESERVED_" start="0x5" description="Reserved." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
+        <Enum name="CT16BN_MAT0_IS_CONTR" start="0" description="CT16Bn_MAT0 is controlled by EM0." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT0." />
+      </BitField>
+      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
+        <Enum name="CT16BN_MAT01_IS_CONT" start="0" description="CT16Bn_MAT01 is controlled by EM1." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT1." />
+      </BitField>
+      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
+        <Enum name="CT16BN_MAT2_IS_CONTR" start="0" description="CT16Bn_MAT2 is controlled by EM2." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT2." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3.">
+        <Enum name="CT16BN_MAT3_IS_CONTR" start="0" description="CT16Bn_MAT3 is controlled by EM3." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT16Bn_MAT3." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CT32B0" start="0x40014000" description="32-bit counter/timers CT32B0">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved," />
+      <BitField start="6" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="Counter enable.">
+        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
+      </BitField>
+      <BitField start="1" size="1" name="CRST" description="Counter reset.">
+        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT32B0_CAP0 rising edge: a sequence of 0 then 1 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT32B0_CAP0 falling edge: a sequence of 1 then 0 on CT32B0_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT32B0_CAP0 event: a CR0 load due to a CT32B0_CAP0 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="CAP1RE" description="Capture on CT32B0_CAP1 rising edge: a sequence of 0 then 1 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP1FE" description="Capture on CT32B0_CAP1 falling edge: a sequence of 1 then 0 on CT32B0_CAP1 will cause CR1 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP1I" description="Interrupt on CT32B0_CAP1 event: a CR1 load due to a CT32B0_CAP1 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x034" size="4" name="CR1" access="Read/Write" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B0_CAP1 input." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking.  If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x1 and0x3 are reserved.">
+        <Enum name="CT32B0_CAP0" start="0x0" description="CT32B0_CAP0" />
+        <Enum name="RESERVED_" start="0x1" description="Reserved." />
+        <Enum name="CT32B0_CAP1" start="0x2" description="CT32B0_CAP1" />
+      </BitField>
+      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
+      <BitField start="5" size="3" name="SElCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.">
+        <Enum name="RISING_EDGE_OF_CT32B" start="0x0" description="Rising Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)" />
+        <Enum name="FALLING_EDGE_OF_CT32" start="0x1" description="Falling Edge of CT32B0_CAP0 clears the timer (if bit 4 is set)" />
+        <Enum name="RESERVED" start="0x2" description="Reserved," />
+        <Enum name="RESERVED_" start="0x3" description="Reserved." />
+        <Enum name="RISING_EDGE_OF_CT32B" start="0x4" description="Rising Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)" />
+        <Enum name="FALLING_EDGE_OF_CT32" start="0x5" description="Falling Edge of CT32B0_CAP1 clears the timer (if bit 4 is set)" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
+        <Enum name="CT32BN_MAT0_IS_CONTR" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
+      </BitField>
+      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
+        <Enum name="CT32BN_MAT01_IS_CONT" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
+      </BitField>
+      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
+        <Enum name="CT32BN_MAT2_IS_CONTR" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
+        <Enum name="CT32BN_MAT3_IS_CONTR" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CT32B1" start="0x40018000" description="32-bit counter/timers CT32B1">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="Counter enable.">
+        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and Prescale Counter are enabled for counting." />
+      </BitField>
+      <BitField start="1" size="1" name="CRST" description="Counter reset.">
+        <Enum name="DO_NOTHING_" start="0" description="Do nothing." />
+        <Enum name="THE_TIMER_COUNTER_AN" start="1" description="The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCVAL" description="Prescaler value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0: the TC will be reset if MR0 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1: the TC will be reset if MR1 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2: the TC will be reset if MR2 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3: the TC will be reset if MR3 matches it.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.">
+        <Enum name="ENABLED" start="1" description="Enabled" />
+        <Enum name="DISABLED" start="0" description="Disabled" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CT32B1_CAP0 rising edge: a sequence of 0 then 1 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CT32B1_CAP0 falling edge: a sequence of 1 then 0 on CT32B1_CAP0 will cause CR0 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CT32B1_CAP0 event: a CR0 load due to a CT32B1_CAP0 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CT32B1_CAP1 rising edge: a sequence of 0 then 1 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CT32B1_CAP1 falling edge: a sequence of 1 then 0 on CT32B1_CAP1 will cause CR1 to be loaded with the contents of TC.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CT32B1_CAP1 event: a CR1 load due to a CT32B1_CAP1 event will generate an interrupt.">
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x030" size="4" name="CR1" access="Read/Write" description="Capture Register 1. CR1 is loaded with the value of TC when there is an event on the CT32B1_CAP1 input." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTM" description="Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_TC_IS_" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CIS" description="Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking.  If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. Values 0x2 to 0x3 are reserved.">
+        <Enum name="CT32B1_CAP0" start="0x0" description="CT32B1_CAP0" />
+        <Enum name="CT32B1_CAP1" start="0x1" description="CT32B1_CAP1" />
+      </BitField>
+      <BitField start="4" size="1" name="ENCC" description="Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs." />
+      <BitField start="5" size="3" name="SElCC" description="When bit 4 is a 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x3 to 0x7 are reserved.">
+        <Enum name="RISING_EDGE_OF_CT32B" start="0x0" description="Rising Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)" />
+        <Enum name="FALLING_EDGE_OF_CT32" start="0x1" description="Falling Edge of CT32B1_CAP0 clears the timer (if bit 4 is set)" />
+        <Enum name="RISING_EDGE_OF_CT32B" start="0x2" description="Rising Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)" />
+        <Enum name="FALLING_EDGE_OF_CT32" start="0x3" description="Falling Edge of CT32B1_CAP1 clears the timer (if bit 4 is set)" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="PWMC" access="Read/Write" description="PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMEN0" description="PWM mode enable for channel0.">
+        <Enum name="CT32BN_MAT0_IS_CONTR" start="0" description="CT32Bn_MAT0 is controlled by EM0." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT0." />
+      </BitField>
+      <BitField start="1" size="1" name="PWMEN1" description="PWM mode enable for channel1.">
+        <Enum name="CT32BN_MAT01_IS_CONT" start="0" description="CT32Bn_MAT01 is controlled by EM1." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT1." />
+      </BitField>
+      <BitField start="2" size="1" name="PWMEN2" description="PWM mode enable for channel2.">
+        <Enum name="CT32BN_MAT2_IS_CONTR" start="0" description="CT32Bn_MAT2 is controlled by EM2." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT32Bn_MAT2." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMEN3" description="PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.">
+        <Enum name="CT32BN_MAT3_IS_CONTR" start="0" description="CT32Bn_MAT3 is controlled by EM3." />
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled for CT132Bn_MAT3." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART" start="0x40008000" description="USART">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRINTEN" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupt." />
+        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREINTEN" description="THRE Interrupt Enable. Enables the THRE interrupt. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupt." />
+        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RLSINTEN" description="Enables the Receive Line Status interrupt. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE_THE_RLS_INTE" start="0" description="Disable the RLS interrupt." />
+        <Enum name="ENABLE_THE_RLS_INTER" start="1" description="Enable the RLS interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="MSINTEN" description="Enables the Modem Status interrupt. The components of this interrupt can be read from the MSR.">
+        <Enum name="DISABLE_THE_MS_INTER" start="0" description="Disable the MS interrupt." />
+        <Enum name="ENABLE_THE_MS_INTERR" start="1" description="Enable the MS interrupt." />
+      </BitField>
+      <BitField start="4" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
+        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other values of IER[3:1] not listed below are reserved.">
+        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
+        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
+        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
+        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt." />
+        <Enum name="4_MODEM_STATUS" start="0x0" description="4   - Modem status" />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOEN" description="These bits are equivalent to FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable">
+        <Enum name="DISABLED" start="0" description="USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset">
+        <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset">
+        <Enum name="NO_IMPACT" start="0" description="No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
+        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
+        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select">
+        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
+        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control">
+        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
+        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
+        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
+        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DTRCTRL" description="Source for modem output pin DTR. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="1" size="1" name="RTSCTRL" description="Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The DSR, CTS, DCD, and RI pins are ignored. Externally, DTR and  RTS are set inactive. Internally, the upper four bits of the MSR are driven by the lower four bits of the MCR. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.">
+        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
+        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="RTSEN" description="RTS enable">
+        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
+        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
+      </BitField>
+      <BitField start="7" size="1" name="CTSEN" description="CTS enable">
+        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
+        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready:LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="RBR_IS_EMPTY_" start="0" description="RBR is empty." />
+        <Enum name="RBR_CONTAINS_VALID_D" start="1" description="RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="THR_CONTAINS_VALID_D" start="0" description="THR contains valid data." />
+        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="VALID_D" start="0" description="THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERRO" start="1" description="USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Tx Error. In smart card T=0 operation, this bit is set when the smart card has NACKed a transmitted character, one more than the number of times indicated by the TXRETRY field." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
+        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
+      </BitField>
+      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
+        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
+      </BitField>
+      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
+        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
+      </BitField>
+      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
+        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
+      </BitField>
+      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
+      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
+      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
+      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="This bit is automatically cleared after auto-baud completion.">
+        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
+        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0_" start="0" description="Mode 0." />
+        <Enum name="MODE_1_" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Start mode">
+        <Enum name="NO_RESTART" start="0" description="No restart" />
+        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write only accessible).">
+        <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write only accessible).">
+        <Enum name="NO_IMPACT" start="0" description="Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA (remote control) mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable">
+        <Enum name="IRDA_MODE_IS_DISABLE" start="0" description="IrDA mode is disabled, USARTn acts as a standard USART." />
+        <Enum name="IRDA_MODE_IS_ENABLED" start="1" description="IrDA mode is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input inverter">
+        <Enum name="INVERTED" start="0" description="The serial input is not inverted." />
+        <Enum name="NOT_INVERTED" start="1" description="The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse width when FixPulseEn = 1.">
+        <Enum name="3_DIV_16_X_BAUD_RATE" start="0x0" description="3 / (16 x baud rate)" />
+        <Enum name="2_X_TPCLK" start="0x1" description="2 x TPCLK" />
+        <Enum name="4_X_TPCLK" start="0x2" description="4 x TPCLK" />
+        <Enum name="8_X_TPCLK" start="0x3" description="8 x TPCLK" />
+        <Enum name="16_X_TPCLK" start="0x4" description="16 x TPCLK" />
+        <Enum name="32_X_TPCLK" start="0x5" description="32 x TPCLK" />
+        <Enum name="64_X_TPCLK" start="0x6" description="64 x TPCLK" />
+        <Enum name="128_X_TPCLK" start="0x7" description="128 x TPCLK" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half duplex enable register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLE_HALF_DUPLEX_" start="0" description="Disable half-duplex mode." />
+        <Enum name="ENABLE_HALF_DUPLEX_M" start="1" description="Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface Control register. Enables and configures the Smart Card Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
+        <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="3" name="TXRETRY" description="When the protocol selection T bit (above) is 0, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK. When NACK has occurred this number of times plus one, the Tx Error bit in the LSR is set, an interrupt is requested if enabled, and the USART is locked until the FIFO is cleared." />
+      <BitField start="8" size="8" name="XTRAGUARD" description="When the protocol selection T bit (above) is 0, this field indicates the number of bit times (ETUs) by which the guard time after a character transmitted by the USART should exceed the nominal 2 bit times. 0xFF in this field may indicate that there is just a single bit after a character and 11 bit times/character" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="RS_485_EIA_485_NORMA" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="RS_485_EIA_485_NORMA" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="THE_RECEIVER_IS_ENAB" start="0" description="The receiver is enabled." />
+        <Enum name="THE_RECEIVER_IS_DISA" start="1" description="The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
+        <Enum name="AUTO_ADDRESS_DETECT_" start="0" description="Auto Address Detect (AAD) is disabled." />
+        <Enum name="AUTO_ADDRESS_DETECT_" start="1" description="Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SEL" description="Select direction control pin">
+        <Enum name="RTS" start="0" description="If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
+        <Enum name="DTR" start="1" description="If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
+      </BitField>
+      <BitField start="4" size="1" name="DCTRL" description="Auto direction control enable.">
+        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
+        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
+        <Enum name="LOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
+        <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Falling edge sampling.">
+        <Enum name="RISING" start="0" description="RxD is sampled on the rising edge of SCLK " />
+        <Enum name="FALLING" start="1" description="RxD is sampled on the falling edge of SCLK" />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNC" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic" />
+        <Enum name="NOSYNC" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
+        <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
+      </BitField>
+      <BitField start="5" size="1" name="SSDIS" description="Start/stop bits">
+        <Enum name="SEND_START_STOP" start="0" description="Send start and stop bits as in other modes." />
+        <Enum name="NOT_SEND_START_STOP" start="1" description="Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
+        <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC" start="0x4001C000" description="ADC">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SEL" description="Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7.  In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1.  In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)." />
+      <BitField start="8" size="8" name="CLKDIV" description="The main clock (PCLK_ADC) is divided by (this value plus one) to produce the clock for  the A/D converter. The clock should be less than or equal to 15.5 MHz(12-bit mode) or 31 MHz (10-bit mode) in software-controlled mode (BURST bit = 0).. Typically, software should program the smallest value in this field that yields a clock of 15.5 MHz or slightly less, but in certain cases (such as a high-impedance analog  source) a slower clock may be desirable." />
+      <BitField start="16" size="1" name="BURST" description="Burst mode If BURST is set to 1, the ADGINTEN bit in the INTEN register (Table 327) must be set to 0.">
+        <Enum name="SOFTWARE_CONTROLLED_" start="0" description="Software-controlled mode: Conversions are software-controlled and require 31 clocks." />
+        <Enum name="HARDWARE_SCAN_MODE_" start="1" description="Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by ones in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher  bits (pins) set to one are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1, or conversions will not start." />
+      </BitField>
+      <BitField start="17" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="21" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="22" size="1" name="LPWRMODE" description="Low-power mode">
+        <Enum name="DISABLE_THE_LOW_POWE" start="0" description="Disable the low-power ADC mode. The analog circuitry remains activated when no conversions are requested." />
+        <Enum name="ENABLE_THE_LOW_POWER" start="1" description="Enable the low-power ADC mode.  The analog circuitry is automatically powered-down when no conversions are taking  place. When any (hardware or software) triggering event is detected, the analog circuitry  is enabled. After the required start-up time, the requested conversion will be launched.  Once the conversion completes, the analog-circuitry will again be powered-down provided  no further conversions are pending.  This mode will NOT power-up the A/D if the ADC is powered down (ADC_PD bit in the PDRUNCFG register is HIGH) or if the part is in Deep-sleep, Power-down, or Deep power-down mode." />
+      </BitField>
+      <BitField start="23" size="1" name="MODE10BIT" description="10-bit conversion rate mode">
+        <Enum name="DISABLE_THE_10_BIT_C" start="0" description="Disable the 10-bit conversion rate mode." />
+        <Enum name="ENABLE_THE_10_BIT_CO" start="1" description="Enable the 10-bit conversion rate mode with high conversion rate.The A/D resolution is reduced to 10 bits (the two LSB of the conversion result will be forced  to 0). The clock rate (set via the CLKDIV field) can be doubled to up to 31 MHz to  achieve a conversion rate of up to one million samples per second." />
+      </BitField>
+      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
+        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
+        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
+        <Enum name="PIO0_2" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0." />
+        <Enum name="PIO1_5" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0." />
+        <Enum name="CT32B0_MAT0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]." />
+        <Enum name="CT32B0_MAT1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]." />
+        <Enum name="CT16B0_MAT0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]." />
+        <Enum name="CT16B0_MAT1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]." />
+      </BitField>
+      <BitField start="27" size="1" name="EDGE" description="Edge control. This bit is significant only when the START field contains 010-111.">
+        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
+        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. These bits always read as zeros." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin or as it falls within the range of VREFP to  VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS/VREFN, while 0xFFF indicates that the voltage on ADn was close to, equal to, or greater than that on VDD/VREFP." />
+      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeros." />
+      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the result bits V_VREF were converted." />
+      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeros." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
+      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. This bit must be set to 0 in burst mode (BURST = 1 in the CR register)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Unused, always 0." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="DR[0]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+4" size="4" name="DR[1]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+8" size="4" name="DR[2]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+12" size="4" name="DR[3]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+16" size="4" name="DR[4]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+20" size="4" name="DR[5]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+24" size="4" name="DR[6]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+28" size="4" name="DR[7]" access="Read/Write" description="A/D Channel N Data&#xa;Register. This register contains the result of the most recent conversion&#xa;completed on channel n" reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="12" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREFN/VSS, while 0xFFF indicates that the voltage on AD input was close to, equal to, or greater than that on VREFP/VDD." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel n." />
+      <BitField start="8" size="8" name="OVERRUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
+      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Unused, always 0." />
+    </Register>
+    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="A/D trim register" reset_value="0xF00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
+      <BitField start="8" size="4" name="TRIM" description="Written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PMU" start="0x40038000" description="Power Management Unit (PMU)">
+    <Register start="+0x000" size="4" name="PCON" access="Read/Write" description="Power control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="PM" description="Power mode">
+        <Enum name="DEFAULT" start="0x0" description="Default. The part is in active or sleep mode." />
+        <Enum name="DEEPSLEEP" start="0x1" description="ARM WFI will enter Deep-sleep mode." />
+        <Enum name="POWERDOWN" start="0x2" description="ARM WFI will enter Power-down mode." />
+        <Enum name="DEEPPOWERDOWN" start="0x3" description="ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down)." />
+      </BitField>
+      <BitField start="3" size="1" name="NODPD" description="A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM field above, the SLEEPDEEP bit is set, and a WFI is executed. Execution continues after the WFI if this bit is 1.  This bit is cleared only by power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode is blocked." />
+      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to this bit." />
+      <BitField start="8" size="1" name="SLEEPFLAG" description="Sleep mode flag">
+        <Enum name="NOPOWERDOWN" start="0" description="Read: No power-down mode entered. LPC11U1x is in Active mode. Write: No effect." />
+        <Enum name="POWERDOWN" start="1" description="Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0." />
+      </BitField>
+      <BitField start="9" size="2" name="RESERVED" description="Reserved. Do not write ones to this bit." />
+      <BitField start="11" size="1" name="DPDFLAG" description="Deep power-down flag">
+        <Enum name="DPNOTENTERED" start="0" description="Read: Deep power-down mode  not entered. Write: No effect." />
+        <Enum name="DPENTERED" start="1" description="Read: Deep power-down mode entered. Write: Clear the Deep power-down flag." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to this bit." />
+    </Register>
+    <Register start="+0x004+0" size="4" name="GPREG0" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
+    </Register>
+    <Register start="+0x004+4" size="4" name="GPREG1" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
+    </Register>
+    <Register start="+0x004+8" size="4" name="GPREG2" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
+    </Register>
+    <Register start="+0x004+12" size="4" name="GPREG3" access="Read/Write" description="General purpose register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="GPDATA" description="Data retained during Deep power-down mode." />
+    </Register>
+    <Register start="+0x014" size="4" name="GPREG4" access="Read/Write" description="General purpose register 4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="RESERVED" description="Reserved. Do not write ones to this bit." />
+      <BitField start="10" size="1" name="WAKEUPHYS" description="WAKEUP pin hysteresis enable">
+        <Enum name="DISABLED" start="0" description="Hysteresis for WAKEUP pin disabled." />
+        <Enum name="ENABLED" start="1" description="Hysteresis for WAKEUP pin enabled." />
+      </BitField>
+      <BitField start="11" size="21" name="GPDATA" description="Data retained during Deep power-down mode." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FLASHCTRL" start="0x4003C000" description="Flash programming firmware  ">
+    <Register start="+0x09C" size="4" name="EEMSSTART" access="Read/Write" description="EEPROM BIST start address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="14" name="STARTA" description="BIST start address: Bit 0 is fixed zero since only even addresses are allowed." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A0" size="4" name="EEMSSTOP" access="Read/Write" description="EEPROM BIST stop address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="14" name="STOPA" description="BIST stop address: Bit 0 is fixed zero since only even addresses are allowed." />
+      <BitField start="14" size="16" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="DEVSEL" description="BIST device select bit 0: the BIST signature is generated over the total memory space. Singe pages are interleaved over the EEPROM devices when multiple devices are used, the signature is generated over memory of multiple devices. 1: the BIST signature is generated only over a memory range located on a single EEPROM device. Therefore the internal address generation is done such that the  address' CS bits are kept stable to select only the same device. The address' MSB and LSB bits are used to step through the memory range specified by the start and stop address fields. Note: if this bit is set the start and stop address fields must be programmed such that they both address the same EEPROM device. Therefore the address' CS bits in both the start and stop address must be the same." />
+      <BitField start="31" size="1" name="STRTBIST" description="BIST start bit Setting this bit will start the BIST. This bit is self-clearing." />
+    </Register>
+    <Register start="+0x0A4" size="4" name="EEMSSIG" access="ReadOnly" description="EEPROM 24-bit BIST signature register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA_SIG" description="BIST 16-bit signature calculated from only the data bytes" />
+      <BitField start="16" size="16" name="PARITY_SIG" description="BIST 16-bit signature calculated from only the parity bits of the data bytes" />
+    </Register>
+    <Register start="+0x010" size="4" name="FLASHCFG" access="Read/Write" description="Flash memory access time configuration register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="FLASHTIM" description="Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.">
+        <Enum name="1_SYSTEM_CLOCK_FLASH" start="0x0" description="1 system clock flash access time (for system clock frequencies of up to 20 MHz)." />
+        <Enum name="2_SYSTEM_CLOCKS_FLAS" start="0x1" description="2 system clocks flash access time (for system clock frequencies of up to 40 MHz)." />
+        <Enum name="3_SYSTEM_CLOCKS_FLAS" start="0x2" description="3 system clocks flash access time (for system clock frequencies of up to 50 MHz)." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read." />
+    </Register>
+    <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." />
+      <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation.">
+        <Enum name="SIGNATURE_GENERATION" start="0" description="Signature generation is stopped" />
+        <Enum name="INITIATE_SIGNATURE_G" start="1" description="Initiate signature generation" />
+      </BitField>
+      <BitField start="18" size="14" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="Word 0 [31:0]" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." />
+    </Register>
+    <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="Word 1 [63:32]" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." />
+    </Register>
+    <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="Word 2 [95:64]" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." />
+    </Register>
+    <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="Word 3 [127:96]" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="FMSTAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="FMSTATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP0" start="0x40040000" description="SSP/SPI">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
+        <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
+        <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SPI Enable.">
+        <Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IOCON" start="0x40044000" description="IO ocnfiguration">
+    <Register start="+0x000" size="4" name="RESET_PIO0_0" access="Read/Write" description="I/O configuration for pin RESET/PIO0_0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="RESET_" start="0x0" description="RESET." />
+        <Enum name="PIO0_0_" start="0x1" description="PIO0_0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="PIO0_1" access="Read/Write" description="I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/ USB_FTOGGLE" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO0_1_" start="0x0" description="PIO0_1." />
+        <Enum name="CLKOUT_" start="0x1" description="CLKOUT." />
+        <Enum name="CT32B0_MAT2_" start="0x2" description="CT32B0_MAT2." />
+        <Enum name="USB_FTOGGLE_" start="0x3" description="USB_FTOGGLE." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x008" size="4" name="PIO0_2" access="Read/Write" description="I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO0_2_" start="0x0" description="PIO0_2." />
+        <Enum name="SSEL0_" start="0x1" description="SSEL0." />
+        <Enum name="CT16B0_CAP0_" start="0x2" description="CT16B0_CAP0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PIO0_3" access="Read/Write" description="I/O configuration for pin PIO0_3/USB_VBUS" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO0_3_" start="0x0" description="PIO0_3." />
+        <Enum name="USB_VBUS_" start="0x1" description="USB_VBUS." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="PIO0_4" access="Read/Write" description="I/O configuration for pin PIO0_4/SCL" reset_value="0x0000080" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO0_4_OPEN_DRAIN_P" start="0x0" description="PIO0_4 (open-drain pin)." />
+        <Enum name="I2C_SCL_OPEN_DRAIN_" start="0x1" description="I2C SCL (open-drain pin)." />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 6.3.8). Select Standard mode (I2CMODE = 0, default) or Standard I/O functionality (I2CMODE = 1) if the pin function is GPIO (FUNC = 0).">
+        <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
+        <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
+        <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
+        <Enum name="RESERVED_" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="PIO0_5" access="Read/Write" description="I/O configuration for pin PIO0_5/SDA" reset_value="0x0000080" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO0_5_OPEN_DRAIN_P" start="0x0" description="PIO0_5 (open-drain pin)." />
+        <Enum name="I2C_SDA_OPEN_DRAIN_" start="0x1" description="I2C SDA (open-drain pin)." />
+      </BitField>
+      <BitField start="8" size="2" name="I2CMODE" description="Selects I2C mode (see Section 6.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 0).">
+        <Enum name="STANDARD_MODE_FAST" start="0x0" description="Standard mode/ Fast-mode I2C." />
+        <Enum name="STANDARD_IO_FUNCTIO" start="0x1" description="Standard I/O functionality" />
+        <Enum name="FAST_MODE_PLUS_I2C" start="0x2" description="Fast-mode Plus I2C" />
+        <Enum name="RESERVED_" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018" size="4" name="PIO0_6" access="Read/Write" description="I/O configuration for pin PIO0_6/USB_CONNECT/SCK0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO0_6_" start="0x0" description="PIO0_6." />
+        <Enum name="USB_CONNECT_" start="0x1" description="USB_CONNECT." />
+        <Enum name="SCK0_" start="0x2" description="SCK0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C" size="4" name="PIO0_7" access="Read/Write" description="I/O configuration for pin PIO0_7/CTS" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO0_7_" start="0x0" description="PIO0_7." />
+        <Enum name="CTS_" start="0x1" description="CTS." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x020" size="4" name="PIO0_8" access="Read/Write" description="I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/ ARM_TRACE_CLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO0_8_" start="0x0" description="PIO0_8." />
+        <Enum name="MISO0_" start="0x1" description="MISO0." />
+        <Enum name="CT16B0_MAT0_" start="0x2" description="CT16B0_MAT0." />
+        <Enum name="ARM_TRACE_CLK" start="0x3" description="ARM_TRACE_CLK" />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x024" size="4" name="PIO0_9" access="Read/Write" description="I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/ ARM_TRACE_SWV" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO0_9_" start="0x0" description="PIO0_9." />
+        <Enum name="MOSI0_" start="0x1" description="MOSI0." />
+        <Enum name="CT16B0_MAT1_" start="0x2" description="CT16B0_MAT1." />
+        <Enum name="ARM_TRACE_SWV" start="0x3" description="ARM_TRACE_SWV" />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x028" size="4" name="SWCLK_PIO0_10" access="Read/Write" description="I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="SWCLK_" start="0x0" description="SWCLK." />
+        <Enum name="PIO0_10_" start="0x1" description="PIO0_10." />
+        <Enum name="SCK0_" start="0x2" description="SCK0." />
+        <Enum name="CT16B0_MAT2_" start="0x3" description="CT16B0_MAT2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x02C" size="4" name="TDI_PIO0_11" access="Read/Write" description="I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="TDI_" start="0x0" description="TDI." />
+        <Enum name="PIO0_11_" start="0x1" description="PIO0_11." />
+        <Enum name="AD0_" start="0x2" description="AD0." />
+        <Enum name="CT32B0_MAT3_" start="0x3" description="CT32B0_MAT3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x030" size="4" name="TMS_PIO0_12" access="Read/Write" description="I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="TMS_" start="0x0" description="TMS." />
+        <Enum name="PIO0_12_" start="0x1" description="PIO0_12." />
+        <Enum name="AD1_" start="0x2" description="AD1." />
+        <Enum name="CT32B1_CAP0_" start="0x3" description="CT32B1_CAP0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x034" size="4" name="TDO_PIO0_13" access="Read/Write" description="I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="TDO_" start="0x0" description="TDO." />
+        <Enum name="PIO0_13_" start="0x1" description="PIO0_13." />
+        <Enum name="AD2_" start="0x2" description="AD2." />
+        <Enum name="CT32B1_MAT0_" start="0x3" description="CT32B1_MAT0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x038" size="4" name="TRST_PIO0_14" access="Read/Write" description="I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="TRST_" start="0x0" description="TRST." />
+        <Enum name="PIO0_14_" start="0x1" description="PIO0_14." />
+        <Enum name="AD3_" start="0x2" description="AD3." />
+        <Enum name="CT32B1_MAT1_" start="0x3" description="CT32B1_MAT1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x03C" size="4" name="SWDIO_PIO0_15" access="Read/Write" description="I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="SWDIO_" start="0x0" description="SWDIO." />
+        <Enum name="PIO0_15_" start="0x1" description="PIO0_15." />
+        <Enum name="AD4_" start="0x2" description="AD4." />
+        <Enum name="CT32B1_MAT2_" start="0x3" description="CT32B1_MAT2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x040" size="4" name="PIO0_16" access="Read/Write" description="I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. This pin functions as WAKEUP pin if the LPC1315/16/17/45/46/47 is in Deep power-down mode regardless of the value of FUNC. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO0_16_" start="0x0" description="PIO0_16." />
+        <Enum name="AD5_" start="0x1" description="AD5." />
+        <Enum name="CT32B1_MAT3_" start="0x2" description="CT32B1_MAT3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x044" size="4" name="PIO0_17" access="Read/Write" description="I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO0_17_" start="0x0" description="PIO0_17." />
+        <Enum name="RTS_" start="0x1" description="RTS." />
+        <Enum name="CT32B0_CAP0_" start="0x2" description="CT32B0_CAP0." />
+        <Enum name="SCLK_UART_SYNCHRONO" start="0x3" description="SCLK (UART synchronous clock)." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x048" size="4" name="PIO0_18" access="Read/Write" description="I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO0_18_" start="0x0" description="PIO0_18." />
+        <Enum name="RXD_" start="0x1" description="RXD." />
+        <Enum name="CT32B0_MAT0_" start="0x2" description="CT32B0_MAT0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x04C" size="4" name="PIO0_19" access="Read/Write" description="I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO0_19_" start="0x0" description="PIO0_19." />
+        <Enum name="TXD_" start="0x1" description="TXD." />
+        <Enum name="CT32B0_MAT1_" start="0x2" description="CT32B0_MAT1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x050" size="4" name="PIO0_20" access="Read/Write" description="I/O configuration for pin PIO0_20/CT16B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO0_20_" start="0x0" description="PIO0_20." />
+        <Enum name="CT16B1_CAP0_" start="0x1" description="CT16B1_CAP0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x054" size="4" name="PIO0_21" access="Read/Write" description="I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO0_21_" start="0x0" description="PIO0_21." />
+        <Enum name="CT16B1_MAT0_" start="0x1" description="CT16B1_MAT0." />
+        <Enum name="MOSI1_" start="0x2" description="MOSI1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x058" size="4" name="PIO0_22" access="Read/Write" description="I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO0_22_" start="0x0" description="PIO0_22." />
+        <Enum name="AD6_" start="0x1" description="AD6." />
+        <Enum name="CT16B1_MAT1_" start="0x2" description="CT16B1_MAT1." />
+        <Enum name="MISO1_" start="0x3" description="MISO1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x05C" size="4" name="PIO0_23" access="Read/Write" description="I/O configuration for pin PIO0_23/AD7" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO0_23_" start="0x0" description="PIO0_23." />
+        <Enum name="AD7_" start="0x1" description="AD7." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_ENABLED_" start="0" description="Filter enabled." />
+        <Enum name="FILTER_DISABLED_" start="1" description="Filter disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x060" size="4" name="PIO1_0" access="Read/Write" description="I/O configuration for pin PIO1_0/CT32B1_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_0_" start="0x0" description="PIO1_0." />
+        <Enum name="CT32B1_MAT1_" start="0x1" description="CT32B1_MAT1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x064" size="4" name="PIO1_1" access="Read/Write" description="I/O configuration for pin PIO1_1/CT32B1_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_1_" start="0x0" description="PIO1_1." />
+        <Enum name="CT32B1_MAT1_" start="0x1" description="CT32B1_MAT1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x068" size="4" name="PIO1_2" access="Read/Write" description="I/O configuration for pin PIO1_2/CT32B1_MAT2" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_2_" start="0x0" description="PIO1_2." />
+        <Enum name="CT32B1_MAT2_" start="0x1" description="CT32B1_MAT2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x06C" size="4" name="PIO1_3" access="Read/Write" description="I/O configuration for pin PIO1_3/CT32B1_MAT3" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_3_" start="0x0" description="PIO1_3." />
+        <Enum name="CT32B1_MAT3_" start="0x1" description="CT32B1_MAT3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x070" size="4" name="PIO1_4" access="Read/Write" description="I/O configuration for pin PIO1_4/CT32B1_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_4_" start="0x0" description="PIO1_4." />
+        <Enum name="CT32B1_CAP0_" start="0x1" description="CT32B1_CAP0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x074" size="4" name="PIO1_5" access="Read/Write" description="I/O configuration for pin PIO1_5/CT32B1_CAP1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_5_" start="0x0" description="PIO1_5." />
+        <Enum name="CT32B1_CAP1_" start="0x1" description="CT32B1_CAP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x07C" size="4" name="PIO1_7" access="Read/Write" description="I/O configuration for pin PIO1_7" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_7_" start="0x0" description="PIO1_7." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x080" size="4" name="PIO1_8" access="Read/Write" description="I/O configuration for pin PIO1_8" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
+        <Enum name="PIO1_8_" start="0x0" description="PIO1_8." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x088" size="4" name="PIO1_10" access="Read/Write" description="I/O configuration for pin PIO1_10" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
+        <Enum name="PIO1_10_" start="0x0" description="PIO1_10." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x08C" size="4" name="PIO1_11" access="Read/Write" description="I/O configuration for pin PIO1_11" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
+        <Enum name="PIO1_11_" start="0x0" description="PIO1_11." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x094" size="4" name="PIO1_13" access="Read/Write" description="I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO1_13" start="0x0" description="PIO1_13" />
+        <Enum name="DTR" start="0x1" description="DTR" />
+        <Enum name="CT16B0_MAT0" start="0x2" description="CT16B0_MAT0" />
+        <Enum name="TXD" start="0x3" description="TXD" />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x098" size="4" name="PIO1_14" access="Read/Write" description="I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO1_14_" start="0x0" description="PIO1_14." />
+        <Enum name="DSR" start="0x1" description="DSR" />
+        <Enum name="CT16B0_MAT1" start="0x2" description="CT16B0_MAT1" />
+        <Enum name="RXD" start="0x3" description="RXD" />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x09C" size="4" name="PIO1_15" access="Read/Write" description="I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x4 to 0x7 are reserved.">
+        <Enum name="PIO1_15_" start="0x0" description="PIO1_15." />
+        <Enum name="DCD_" start="0x1" description="DCD." />
+        <Enum name="CT16B0_MAT2_" start="0x2" description="CT16B0_MAT2." />
+        <Enum name="SCK1_" start="0x3" description="SCK1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0A0" size="4" name="PIO1_16" access="Read/Write" description="I/O configuration for pin PIO1_16/RI/CT16B0_CAP0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_16_" start="0x0" description="PIO1_16." />
+        <Enum name="RI_" start="0x1" description="RI." />
+        <Enum name="CT16B0_CAP0_" start="0x2" description="CT16B0_CAP0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0A4" size="4" name="PIO1_17" access="Read/Write" description="I/O configuration for PIO1_17/CT16B0_CAP1/RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_17_" start="0x0" description="PIO1_17." />
+        <Enum name="CT16B0_CAP1" start="0x1" description="CT16B0_CAP1" />
+        <Enum name="RXD" start="0x2" description="RXD" />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0A8" size="4" name="PIO1_18" access="Read/Write" description="I/O configuration for PIO1_18/CT16B1_CAP1/TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_18" start="0x0" description="PIO1_18" />
+        <Enum name="CT16B1_CAP1" start="0x1" description="CT16B1_CAP1" />
+        <Enum name="TXD" start="0x2" description="TXD" />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0AC" size="4" name="PIO1_19" access="Read/Write" description="I/O configuration for pin PIO1_19/DTR/SSEL1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_19_" start="0x0" description="PIO1_19." />
+        <Enum name="DTR_" start="0x1" description="DTR." />
+        <Enum name="SSEL1_" start="0x2" description="SSEL1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0B0" size="4" name="PIO1_20" access="Read/Write" description="I/O configuration for pin PIO1_20/DSR/SCK1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_20_" start="0x0" description="PIO1_20." />
+        <Enum name="DSR_" start="0x1" description="DSR." />
+        <Enum name="SCK1_" start="0x2" description="SCK1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0B4" size="4" name="PIO1_21" access="Read/Write" description="I/O configuration for pin PIO1_21/DCD/MISO1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_21_" start="0x0" description="PIO1_21." />
+        <Enum name="DCD_" start="0x1" description="DCD." />
+        <Enum name="MISO1_" start="0x2" description="MISO1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0B8" size="4" name="PIO1_22" access="Read/Write" description="I/O configuration for pin PIO1_22/RI/MOSI1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_22_" start="0x0" description="PIO1_22." />
+        <Enum name="RI_" start="0x1" description="RI." />
+        <Enum name="MOSI1_" start="0x2" description="MOSI1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0BC" size="4" name="PIO1_23" access="Read/Write" description="I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_23_" start="0x0" description="PIO1_23." />
+        <Enum name="CT16B1_MAT1_" start="0x1" description="CT16B1_MAT1." />
+        <Enum name="SSEL1_" start="0x2" description="SSEL1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0C0" size="4" name="PIO1_24" access="Read/Write" description="I/O configuration for pin PIO1_24/ CT32B0_MAT0" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_24_" start="0x0" description="PIO1_24." />
+        <Enum name="CT32B0_MAT0_" start="0x1" description="CT32B0_MAT0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0C4" size="4" name="PIO1_25" access="Read/Write" description="I/O configuration for pin PIO1_25/CT32B0_MAT1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x2 to 0x7 are reserved.">
+        <Enum name="PIO1_25_" start="0x0" description="PIO1_25." />
+        <Enum name="CT32B0_MAT1_" start="0x1" description="CT32B0_MAT1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0C8" size="4" name="PIO1_26" access="Read/Write" description="I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_26_" start="0x0" description="PIO1_26." />
+        <Enum name="CT32B0_MAT2" start="0x1" description="CT32B0_MAT2" />
+        <Enum name="RXD_" start="0x2" description="RXD." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0CC" size="4" name="PIO1_27" access="Read/Write" description="I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_27_" start="0x0" description="PIO1_27." />
+        <Enum name="CT32B0_MAT3_" start="0x1" description="CT32B0_MAT3." />
+        <Enum name="TXD_" start="0x2" description="TXD." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0D0" size="4" name="PIO1_28" access="Read/Write" description="I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_28_" start="0x0" description="PIO1_28." />
+        <Enum name="CT32B0_CAP0_" start="0x1" description="CT32B0_CAP0." />
+        <Enum name="SCLK_" start="0x2" description="SCLK." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0D4" size="4" name="PIO1_29" access="Read/Write" description="I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x3 to 0x7 are reserved.">
+        <Enum name="PIO1_29_" start="0x0" description="PIO1_29." />
+        <Enum name="SCK0_" start="0x1" description="SCK0." />
+        <Enum name="CT32B0_CAP1_" start="0x2" description="CT32B0_CAP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0DC" size="4" name="PIO1_31" access="Read/Write" description="I/O configuration for pin PIO1_31" reset_value="0x0000090" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function. Values 0x1 to 0x7 are reserved.">
+        <Enum name="PIO1_31_" start="0x0" description="PIO1_31." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1)." />
+      </BitField>
+      <BitField start="7" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SYSCON" start="0x40048000" description="System control block ">
+    <Register start="+0x000" size="4" name="SYSMEMREMAP" access="Read/Write" description="System memory remap" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MAP" description="System memory remap. Value 0x3 is reserved.">
+        <Enum name="BOOT_LOADER_MODE_IN" start="0x0" description="Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM." />
+        <Enum name="USER_RAM_MODE_INTER" start="0x1" description="User RAM Mode. Interrupt vectors are re-mapped to Static RAM." />
+        <Enum name="USER_FLASH_MODE_INT" start="0x2" description="User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="PRESETCTRL" access="Read/Write" description="Peripheral reset control" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SSP0_RST_N" description="SSP0 reset control">
+        <Enum name="RESETS_THE_SSP0_PERI" start="0" description="Resets the SSP0 peripheral." />
+        <Enum name="SSP0_RESET_DE_ASSERT" start="1" description="SSP0 reset de-asserted." />
+      </BitField>
+      <BitField start="1" size="1" name="I2C_RST_N" description="I2C reset control">
+        <Enum name="RESETS_THE_I2C_PERIP" start="0" description="Resets the I2C peripheral." />
+        <Enum name="I2C_RESET_DE_ASSERTE" start="1" description="I2C reset de-asserted." />
+      </BitField>
+      <BitField start="2" size="1" name="SSP1_RST_N" description="SSP1 reset control">
+        <Enum name="RESETS_THE_SSP0_PERI" start="0" description="Resets the SSP0 peripheral." />
+        <Enum name="SSP1_RESET_DE_ASSERT" start="1" description="SSP1 reset de-asserted." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="SYSPLLCTRL" access="Read/Write" description="System PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
+      <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
+        <Enum name="P_EQ_1" start="0x0" description="P = 1" />
+        <Enum name="P_EQ_2" start="0x1" description="P = 2" />
+        <Enum name="P_EQ_4" start="0x2" description="P = 4" />
+        <Enum name="P_EQ_8" start="0x3" description="P = 8" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SYSPLLSTAT" access="ReadOnly" description="System PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL lock status">
+        <Enum name="PLL_NOT_LOCKED" start="0" description="PLL not locked" />
+        <Enum name="PLL_LOCKED" start="1" description="PLL locked" />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="USBPLLCTRL" access="Read/Write" description="USB PLL control" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="MSEL" description="Feedback divider value. The division value M is the programmed MSEL value + 1.  00000: Division ratio M = 1 to 11111: Division ratio M = 32" />
+      <BitField start="5" size="2" name="PSEL" description="Post divider ratio P. The division ratio is 2 x P.">
+        <Enum name="P_EQ_1" start="0x0" description="P = 1" />
+        <Enum name="P_EQ_2" start="0x1" description="P = 2" />
+        <Enum name="P_EQ_4" start="0x2" description="P = 4" />
+        <Enum name="P_EQ_8" start="0x3" description="P = 8" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Do not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x014" size="4" name="USBPLLSTAT" access="ReadOnly" description="USB PLL status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL lock status">
+        <Enum name="PLL_NOT_LOCKED" start="0" description="PLL not locked" />
+        <Enum name="PLL_LOCKED" start="1" description="PLL locked" />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="SYSOSCCTRL" access="Read/Write" description="System oscillator control" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="BYPASS" description="Bypass system oscillator">
+        <Enum name="OSCILLATOR_IS_NOT_BY" start="0" description="Oscillator is not bypassed." />
+        <Enum name="BYPASS_ENABLED_PLL_" start="1" description="Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN pin bypassing the oscillator. Use this mode when using an external clock source instead of the crystal oscillator." />
+      </BitField>
+      <BitField start="1" size="1" name="FREQRANGE" description="Determines frequency range for Low-power oscillator.">
+        <Enum name="1__20_MHZ_FREQUENCY" start="0" description="1 - 20 MHz frequency range." />
+        <Enum name="15__25_MHZ_FREQUENC" start="1" description="15 - 25 MHz frequency range" />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024" size="4" name="WDTOSCCTRL" access="Read/Write" description="Watchdog oscillator control" reset_value="0x0A0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DIVSEL" description="Select divider for Fclkana.  wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64" />
+      <BitField start="5" size="4" name="FREQSEL" description="Select watchdog oscillator analog output frequency (Fclkana).">
+        <Enum name="0_6_MHZ" start="0x1" description="0.6 MHz" />
+        <Enum name="1_05_MHZ" start="0x2" description="1.05 MHz" />
+        <Enum name="1_4_MHZ" start="0x3" description="1.4 MHz" />
+        <Enum name="1_75_MHZ" start="0x4" description="1.75 MHz" />
+        <Enum name="2_1_MHZ" start="0x5" description="2.1 MHz" />
+        <Enum name="2_4_MHZ" start="0x6" description="2.4 MHz" />
+        <Enum name="2_7_MHZ" start="0x7" description="2.7 MHz" />
+        <Enum name="3_0_MHZ" start="0x8" description="3.0 MHz" />
+        <Enum name="3_25_MHZ" start="0x9" description="3.25 MHz" />
+        <Enum name="3_5_MHZ" start="0xA" description="3.5 MHz" />
+        <Enum name="3_75_MHZ" start="0xB" description="3.75 MHz" />
+        <Enum name="4_0_MHZ" start="0xC" description="4.0 MHz" />
+        <Enum name="4_2_MHZ" start="0xD" description="4.2 MHz" />
+        <Enum name="4_4_MHZ" start="0xE" description="4.4 MHz" />
+        <Enum name="4_6_MHZ" start="0xF" description="4.6 MHz" />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030" size="4" name="SYSRSTSTAT" access="Read/Write" description="System reset status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POR" description="POR reset status">
+        <Enum name="NO_POR_DETECTED" start="0" description="No POR detected" />
+        <Enum name="POR_DETECTED" start="1" description="POR detected" />
+      </BitField>
+      <BitField start="1" size="1" name="EXTRST" description="Status of the external RESET pin">
+        <Enum name="NO_RESET_EVENT_DETEC" start="0" description="No reset event detected" />
+        <Enum name="RESET_DETECTED" start="1" description="Reset detected" />
+      </BitField>
+      <BitField start="2" size="1" name="WDT" description="Status of the Watchdog reset">
+        <Enum name="NO_WDT_RESET_DETECTE" start="0" description="No WDT reset detected" />
+        <Enum name="WDT_RESET_DETECTED" start="1" description="WDT reset detected" />
+      </BitField>
+      <BitField start="3" size="1" name="BOD" description="Status of the Brown-out detect reset">
+        <Enum name="NO_BOD_RESET_DETECTE" start="0" description="No BOD reset detected" />
+        <Enum name="BOD_RESET_DETECTED" start="1" description="BOD reset detected" />
+      </BitField>
+      <BitField start="4" size="1" name="SYSRST" description="Status of the software system reset">
+        <Enum name="NO_SYSTEM_RESET_DETE" start="0" description="No System reset detected" />
+        <Enum name="SYSTEM_RESET_DETECTE" start="1" description="System reset detected" />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="SYSPLLCLKSEL" access="Read/Write" description="System PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SEL" description="System PLL clock source">
+        <Enum name="IRC" start="0x0" description="IRC" />
+        <Enum name="CRYSTAL_OSCILLATOR_" start="0x1" description="Crystal Oscillator (SYSOSC)" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048" size="4" name="USBPLLCLKSEL" access="Read/Write" description="USB PLL clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SEL" description="USB PLL clock source">
+        <Enum name="IRC_THE_USB_PLL_CLO" start="0x0" description="IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation." />
+        <Enum name="SYSTEM_OSCILLATOR" start="0x1" description="System oscillator" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x070" size="4" name="MAINCLKSEL" access="Read/Write" description="Main clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SEL" description="Clock source for main clock">
+        <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC Oscillator" />
+        <Enum name="PLL_INPUT" start="0x1" description="PLL input" />
+        <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
+        <Enum name="PLL_OUTPUT" start="0x3" description="PLL output" />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x078" size="4" name="SYSAHBCLKDIV" access="Read/Write" description="System clock divider" reset_value="0x001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="System AHB clock divider values  0: System clock disabled.  1: Divide by 1.  to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080" size="4" name="SYSAHBCLKCTRL" access="Read/Write" description="System clock control" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SYS" description="Enables the clock for the AHB, the APB bridge, the Cortex-M3 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.">
+        <Enum name="RESERVED" start="0" description="Reserved" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="1" size="1" name="ROM" description="Enables clock for ROM.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="2" size="1" name="RAM0" description="Enables clock for SRAM0.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="3" size="1" name="FLASHREG" description="Enables clock for flash register interface.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="4" size="1" name="FLASHARRAY" description="Enables clock for flash array access.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="5" size="1" name="I2C" description="Enables clock for I2C.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="6" size="1" name="GPIO" description="Enables clock for GPIO port registers.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="7" size="1" name="CT16B0" description="Enables clock for 16-bit counter/timer 0.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="8" size="1" name="CT16B1" description="Enables clock for 16-bit counter/timer 1.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="9" size="1" name="CT32B0" description="Enables clock for 32-bit counter/timer 0.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="10" size="1" name="CT32B1" description="Enables clock for 32-bit counter/timer 1.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="11" size="1" name="SSP0" description="Enables clock for SSP0.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="12" size="1" name="USART" description="Enables clock for UART.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="13" size="1" name="ADC" description="Enables clock for ADC.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="14" size="1" name="USB" description="Enables clock to the USB register interface.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="15" size="1" name="WWDT" description="Enables clock for WWDT.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="16" size="1" name="IOCON" description="Enables clock for I/O configuration block.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="SSP1" description="Enables clock for SSP1.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="19" size="1" name="PINT" description="Enables clock to GPIO Pin interrupts register interface.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="23" size="1" name="GROUP0INT" description="Enables clock to GPIO GROUP0 interrupt register interface.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="24" size="1" name="GROUP1INT" description="Enables clock to GPIO GROUP1 interrupt register interface.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="1" name="RAM1" description="Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="27" size="1" name="USBSRAM" description="Enables USB SRAM block located at 0x2000 4000 to 0x2000 4800.">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x094" size="4" name="SSP0CLKDIV" access="Read/Write" description="SSP0 clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="SPI0_PCLK clock divider values.  0: System clock disabled.  1: Divide by 1.  to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x098" size="4" name="UARTCLKDIV" access="Read/Write" description="UART clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="UART_PCLK clock divider values  0: Disable UART_PCLK.  1: Divide by 1.  to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x09C" size="4" name="SSP1CLKDIV" access="Read/Write" description="SSP1 clock divider" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="SSP1_PCLK clock divider values  0: Disable SSP1_PCLK.  1: Divide by 1.  to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0AC" size="4" name="TRACECLKDIV" access="Read/Write" description="ARM trace clock divider" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="ARM trace clock divider values.  0: Disable TRACE_CLK.  1: Divide by 1.  to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0B0" size="4" name="SYSTICKCLKDIV" access="Read/Write" description="SYSTICK clock divider" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="SYSTICK clock divider values.  0: Disable SYSTICK timer clock.  1: Divide by 1. to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C0" size="4" name="USBCLKSEL" access="Read/Write" description="USB clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SEL" description="USB clock source. Values 0x2 and 0x3 are reserved.">
+        <Enum name="USB_PLL_OUT" start="0x0" description="USB PLL out" />
+        <Enum name="MAIN_CLOCK" start="0x1" description="Main clock" />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8" size="4" name="USBCLKDIV" access="Read/Write" description="USB clock source divider" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="USB clock divider values  0: Disable USB clock.  1: Divide by 1. to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0E0" size="4" name="CLKOUTSEL" access="Read/Write" description="CLKOUT clock source select" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SEL" description="CLKOUT clock source">
+        <Enum name="IRC_OSCILLATOR" start="0x0" description="IRC oscillator" />
+        <Enum name="CRYSTAL_OSCILLATOR_" start="0x1" description="Crystal oscillator (SYSOSC)" />
+        <Enum name="WATCHDOG_OSCILLATOR" start="0x2" description="Watchdog oscillator" />
+        <Enum name="MAIN_CLOCK" start="0x3" description="Main clock" />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0E8" size="4" name="CLKOUTDIV" access="Read/Write" description="CLKOUT clock divider" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DIV" description="CLKOUT clock divider values  0: Disable CLKOUT clock divider.  1: Divide by 1. to 255: Divide by 255." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="PIOPORCAP0" access="ReadOnly" description="POR captured PIO status 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="24" name="PIOSTAT" description="State of P0_23 through P0_0 at power-on reset" />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="PIOPORCAP1" access="ReadOnly" description="POR captured PIO status 1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="PIOSTAT" description="State of P1_31 through P1_0 at power-on reset" />
+    </Register>
+    <Register start="+0x150" size="4" name="BODCTRL" access="Read/Write" description="Brown-Out Detect" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="BODRSTLEV" description="BOD reset level">
+        <Enum name="LEVEL_0_THE_RESET_A" start="0x0" description="Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V." />
+        <Enum name="LEVEL_1_THE_RESET_A" start="0x1" description="Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V." />
+        <Enum name="LEVEL_2_THE_RESET_A" start="0x2" description="Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V." />
+        <Enum name="LEVEL_3_THE_RESET_A" start="0x3" description="Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V." />
+      </BitField>
+      <BitField start="2" size="2" name="BODINTVAL" description="BOD interrupt level">
+        <Enum name="RESERVED_" start="0x0" description="Reserved." />
+        <Enum name="LEVEL_1THE_INTERRUP" start="0x1" description="Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V." />
+        <Enum name="LEVEL_2_THE_INTERRU" start="0x2" description="Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V." />
+        <Enum name="LEVEL_3_THE_INTERRU" start="0x3" description="Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V." />
+      </BitField>
+      <BitField start="4" size="1" name="BODRSTENA" description="BOD reset enable">
+        <Enum name="DISABLE_RESET_FUNCTI" start="0" description="Disable reset function." />
+        <Enum name="ENABLE_RESET_FUNCTIO" start="1" description="Enable reset function." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="SYSTCKCAL" access="Read/Write" description="System tick counter calibration" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="26" name="CAL" description="System tick timer calibration value" />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x170" size="4" name="IRQLATENCY" access="Read/Write" description="IQR delay. Allows trade-off between interrupt latency and determinism." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="LATENCY" description="8-bit latency value" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x174" size="4" name="NMISRC" access="Read/Write" description="NMI Source Control" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="IRQNO" description="The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1. See Table 53 for the list of interrupt sources and their IRQ numbers." />
+      <BitField start="5" size="26" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="NMIEN" description="Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0." />
+    </Register>
+    <Register start="+0x178+0" size="4" name="PINTSEL0" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+4" size="4" name="PINTSEL1" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+8" size="4" name="PINTSEL2" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+12" size="4" name="PINTSEL3" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+16" size="4" name="PINTSEL4" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+20" size="4" name="PINTSEL5" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+24" size="4" name="PINTSEL6" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178+28" size="4" name="PINTSEL7" access="Read/Write" description="GPIO Pin Interrupt Select register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN" description="Pin number within the port selected by the PORTSEL bit in this register." />
+      <BitField start="5" size="1" name="PORTSEL" description="Select the port for the pin number to be selected in the INTPIN bits of this register.">
+        <Enum name="PORT_0" start="0" description="Port 0" />
+        <Enum name="PORT_1" start="1" description="Port 1" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x198" size="4" name="USBCLKCTRL" access="Read/Write" description="USB clock control" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="AP_CLK" description="USB need_clock signal control">
+        <Enum name="UNDER_HARDWARE_CONTR" start="0" description="Under hardware control." />
+        <Enum name="FORCED_HIGH_" start="1" description="Forced HIGH." />
+      </BitField>
+      <BitField start="1" size="1" name="POL_CLK" description="USB need_clock polarity for triggering the USB wake-up interrupt">
+        <Enum name="FALLING_EDGE_OF_THE_" start="0" description="Falling edge of the USB need_clock triggers the USB wake-up (default)." />
+        <Enum name="RISING_EDGE_OF_THE_U" start="1" description="Rising edge of the USB need_clock triggers the USB wake-up." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x19C" size="4" name="USBCLKST" access="ReadOnly" description="USB clock status" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NEED_CLKST" description="USB need_clock signal status">
+        <Enum name="LOW" start="0" description="LOW" />
+        <Enum name="HIGH" start="1" description="HIGH" />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x204" size="4" name="STARTERP0" access="Read/Write" description="Start logic 0 interrupt wake-up enable register 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PINT0" description="Pin interrupt 0 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="1" size="1" name="PINT1" description="Pin interrupt 1 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="2" size="1" name="PINT2" description="Pin interrupt 2 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="3" size="1" name="PINT3" description="Pin interrupt 3 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="4" size="1" name="PINT4" description="Pin interrupt 4 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="5" size="1" name="PINT5" description="Pin interrupt 5 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="PINT6" description="Pin interrupt 6 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="7" size="1" name="PINT7" description="Pin interrupt 7 wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x214" size="4" name="STARTERP1" access="Read/Write" description="Start logic 1 interrupt wake-up enable register 1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="12" size="1" name="WWDTINT" description="WWDT interrupt wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="13" size="1" name="BODINT" description="Brown Out Detect (BOD) interrupt wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="14" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="19" size="1" name="USB_WAKEUP" description="USB need_clock signal wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="20" size="1" name="GPIOINT0" description="GPIO GROUP0 interrupt wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="21" size="1" name="GPIOINT1" description="GPIO GROUP1 interrupt wake-up">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+    </Register>
+    <Register start="+0x230" size="4" name="PDSLEEPCFG" access="Read/Write" description="Power-down states in deep-sleep mode" reset_value="0" reset_mask="0x00000000">
+      <BitField start="3" size="1" name="BOD_PD" description="BOD power-down control for Deep-sleep and Power-down mode">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down control for Deep-sleep and Power-down mode">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x234" size="4" name="PDAWAKECFG" access="Read/Write" description="Power-down states for wake-up from deep-sleep" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="2" size="1" name="FLASH_PD" description="Flash wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="3" size="1" name="BOD_PD" description="BOD wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="4" size="1" name="ADC_PD" description="ADC wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL wake-up configuration">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL wake-up configuration">
+        <Enum name="POWERED" start="0" description="Powered" />
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
+      <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver wake-up configuration">
+        <Enum name="USB_TRANSCEIVER_POWE" start="0" description="USB transceiver powered" />
+        <Enum name="USB_TRANSCEIVER_POWE" start="1" description="USB transceiver powered down" />
+      </BitField>
+      <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x238" size="4" name="PDRUNCFG" access="Read/Write" description="Power configuration register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="IRCOUT_PD" description="IRC oscillator output power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="1" size="1" name="IRC_PD" description="IRC oscillator power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="2" size="1" name="FLASH_PD" description="Flash power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="3" size="1" name="BOD_PD" description="BOD power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="4" size="1" name="ADC_PD" description="ADC power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="5" size="1" name="SYSOSC_PD" description="Crystal oscillator power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="6" size="1" name="WDTOSC_PD" description="Watchdog oscillator power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="7" size="1" name="SYSPLL_PD" description="System PLL power-down">
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+        <Enum name="POWERED" start="0" description="Powered" />
+      </BitField>
+      <BitField start="8" size="1" name="USBPLL_PD" description="USB PLL power-down">
+        <Enum name="POWERED" start="0" description="Powered" />
+        <Enum name="POWERED_DOWN" start="1" description="Powered down" />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
+      <BitField start="10" size="1" name="USBPAD_PD" description="USB transceiver power-down configuration">
+        <Enum name="USB_TRANSCEIVER_POWE" start="0" description="USB transceiver powered" />
+        <Enum name="USB_TRANSCEIVER_POWE" start="1" description="USB transceiver powered down (suspend mode)" />
+      </BitField>
+      <BitField start="11" size="1" name="RESERVED" description="Reserved. This bit must be set to one in Run mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="13" size="3" name="RESERVED" description="Reserved. Always write these bits as 111." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x3F8" size="4" name="DEVICE_ID" access="ReadOnly" description="Device ID" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="DEVICEID" description="LPC1345FHN33 = 0x2801 0541 LPC1345FBD48 = 0x2801 0541 LPC1346FHN33 = 0x0801 8542 LPC1346FBD48 = 0x0801 8542 LPC1347FHN33 = 0x0802 0543 LPC1347FBD48 = 0x0802 0543 LPC1347FBD64 = 0x0802 0543 LPC1315FHN33 = 0x3A01 0523 LPC1315FBD48 = 0x3A01 0523 LPC1316FHN33 = 0x1A01 8524 LPC1316FBD48 = 0x1A01 8524 LPC1317FHN33 = 0x1A02 0525 LPC1317FBD48 = 0x1A02 0525 LPC1317FBD64 = 0x1A02 0525" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_PIN_INT" start="0x4004C000" description="GPIO pin interrupt ">
+    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP1" start="0x40058000" description="SSP/SPI">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="RESERVED" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="LOW" start="0" description="SPI controller maintains the bus clock low between frames." />
+        <Enum name="HIGH" start="1" description="SPI controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRSTCLOCK" start="0" description="SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECONDCLOCK" start="1" description="SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="DURING_NORMAL_OPERAT" start="0" description="During normal operation." />
+        <Enum name="SERIAL_INPUT_IS_TAKE" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SPI Enable.">
+        <Enum name="DISABLED" start="0" description="The SPI controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP/SPI registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_GROUP_INT0" start="0x4005C000" description="GPIO group interrupt ">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
+        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
+        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
+      </BitField>
+      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
+        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
+        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
+      </BitField>
+      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
+        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
+        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40060000" description="GPIO group interrupt ">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
+        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
+        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
+      </BitField>
+      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
+        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
+        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
+      </BitField>
+      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
+        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
+        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port 0 polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1 . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port 0/1 pins for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port 0/1 enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port 0/1 pin for group interrupt. Bit n corresponds to pin P0/1_n of port 0/1. 0 = the port 0/1 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0/1 pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RITIMER" start="0x40064000" description="Repetitive Interrupt Timer (RI timer)">
+    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare value LSB register. Holds the 32 LSBs of the compare value." reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the 32 LSBs of the compare value which is compared to the counter." />
+    </Register>
+    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask LSB register. This register holds the 32 LSB s of the mask value. A one  written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32 LSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
+    </Register>
+    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
+        <Enum name="MASK" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
+        <Enum name="NO_MASK" start="0" description="The counter value does not equal the masked compare value." />
+      </BitField>
+      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
+        <Enum name="CLEAR_ON_O" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers. This will occur on the same clock that sets the interrupt flag." />
+        <Enum name="NOT_CLEAR_ON_0" start="0" description="The timer will not be cleared to 0." />
+      </BitField>
+      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
+        <Enum name="HALT_ON_DEBUG" start="1" description="The timer is halted when the processor is halted for debugging." />
+        <Enum name="NO_EFFECT_ON_DEBUG" start="0" description="Debug has no effect on the timer operation." />
+      </BitField>
+      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
+        <Enum name="TIMER_ENABLED" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
+        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="Counter LSB register. 32 LSBs of the counter." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RICOUNTER" description="32 LSBs of the up counter. Counts continuously unless RITEN bit in CTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
+    </Register>
+    <Register start="+0x010" size="4" name="COMPVAL_H" access="Read/Write" description="Compare value MSB register. Holds the 16 MSBs of the compare value." reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RICOMP" description="Compare value MSB register. Holds the 16 MSBs of the compare value which is compared to the counter." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="MASK_H" access="Read/Write" description="Mask MSB register. This register holds the 16 MSBs of the mask value. A one written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RIMASK" description="Mask register. This register holds the 16 MSBs of the mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018" size="4" name="COUNTER_H" access="Read/Write" description="Counter MSB register. 16 MSBs of the counter." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RICOUNTER" description="16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USB" start="0x40080000" description="USB2.0 device controller">
+    <Register start="+0x000" size="4" name="DEVCMDSTAT" access="Read/Write" description="USB Device Command/Status register" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="DEV_ADDR" description="USB device address. After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR. When receiving a SetAddress Control Request from the USB host, software must program the new address before completing the status phase of the SetAddress Control Request." />
+      <BitField start="7" size="1" name="DEV_EN" description="USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR." />
+      <BitField start="8" size="1" name="SETUP" description="SETUP token received. If a SETUP token is received and acknowledged by the device, this bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW." />
+      <BitField start="9" size="1" name="PLL_ON" description="Always PLL Clock on:">
+        <Enum name="USB_NEEDCLK_FUNCTION" start="0" description="USB_NeedClk functional" />
+        <Enum name="USB_NEEDCLK_ALWAYS_1" start="1" description="USB_NeedClk always 1. Clock will not be stopped in case of suspend." />
+      </BitField>
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="1" name="LPM_SUP" description="LPM Supported:">
+        <Enum name="LPM_NOT_SUPPORTED_" start="0" description="LPM not supported." />
+        <Enum name="LPM_SUPPORTED_" start="1" description="LPM supported." />
+      </BitField>
+      <BitField start="12" size="1" name="INTONNAK_AO" description="Interrupt on NAK for interrupt and bulk OUT EP">
+        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
+        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
+      </BitField>
+      <BitField start="13" size="1" name="INTONNAK_AI" description="Interrupt on NAK for interrupt and bulk IN EP">
+        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
+        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
+      </BitField>
+      <BitField start="14" size="1" name="INTONNAK_CO" description="Interrupt on NAK for control OUT EP">
+        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
+        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
+      </BitField>
+      <BitField start="15" size="1" name="INTONNAK_CI" description="Interrupt on NAK for control IN EP">
+        <Enum name="ACKNOW" start="0" description="Only acknowledged packets generate an interrupt" />
+        <Enum name="ACKNOW_NAK" start="1" description="Both acknowledged and NAKed packets generate interrupts." />
+      </BitField>
+      <BitField start="16" size="1" name="DCON" description="Device status - connect.  The connect bit must be set by SW to indicate that the device must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and the VbusDebounced bit is one." />
+      <BitField start="17" size="1" name="DSUS" description="Device status - suspend.  The suspend bit indicates the current suspend state. It is set to 1 when the device hasn't seen any activity on its upstream port for more than 3 milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and the software writes a 0 to it, the device will generate a remote wake-up. This will only happen when the device is connected (Connect bit = 1). When the device is not connected or not suspended, a writing a 0 has no effect. Writing a 1 never has an effect." />
+      <BitField start="18" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="LPM_SUS" description="Device status - LPM Suspend.  This bit represents the current LPM suspend state. It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed. When the device is in the LPM suspended state (LPM suspend bit = 1) and the software writes a zero to this bit, the device will generate a remote walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one." />
+      <BitField start="20" size="1" name="LPM_REWP" description="LPM Remote Wake-up Enabled by USB host.  HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset is received. Software can use this bit to check if the remote wake-up feature is enabled by the host for the LPM transaction." />
+      <BitField start="21" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="1" name="DCON_C" description="Device status - connect change.  The Connect Change bit is set when the device's pull-up resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it." />
+      <BitField start="25" size="1" name="DSUS_C" description="Device status - suspend change.  The suspend change bit is set to 1 when the suspend bit toggles. The suspend bit can toggle because: - The device goes in the suspended state  - The device is disconnected - The device receives resume signaling on its upstream port.  The bit is reset by writing a one to it." />
+      <BitField start="26" size="1" name="DRES_C" description="Device status - reset change.  This bit is set when the device received a bus reset. On a bus reset the device will automatically go to the default state (unconfigured and responding to address 0). The bit is reset by writing a one to it." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="28" size="1" name="VBUSDEBOUNCED" description="This bit indicates if Vbus is detected or not. The bit raises immediately when Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and the DCon bit is set, the HW will enable the pull-up resistor to signal a connect." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="INFO" access="Read/Write" description="USB Info register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="FRAME_NR" description="Frame number. This contains the frame number of the last successfully received SOF. In case no SOF was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC error, the frame number returned will be the corrupted frame number as received by the device." />
+      <BitField start="11" size="4" name="ERR_CODE" description="The error code which last occurred:">
+        <Enum name="NO_ERROR" start="0x0" description="No error" />
+        <Enum name="PID_ENCODING_ERROR" start="0x1" description="PID encoding error" />
+        <Enum name="PID_UNKNOWN" start="0x2" description="PID unknown" />
+        <Enum name="PACKET_UNEXPECTED" start="0x3" description="Packet unexpected" />
+        <Enum name="TOKEN_CRC_ERROR" start="0x4" description="Token CRC error" />
+        <Enum name="DATA_CRC_ERROR" start="0x5" description="Data CRC error" />
+        <Enum name="TIME_OUT" start="0x6" description="Time out" />
+        <Enum name="BABBLE" start="0x7" description="Babble" />
+        <Enum name="TRUNCATED_EOP" start="0x8" description="Truncated EOP" />
+        <Enum name="SENT_RECEIVED_NAK" start="0x9" description="Sent/Received NAK" />
+        <Enum name="SENT_STALL" start="0xA" description="Sent Stall" />
+        <Enum name="OVERRUN" start="0xB" description="Overrun" />
+        <Enum name="SENT_EMPTY_PACKET" start="0xC" description="Sent empty packet" />
+        <Enum name="BITSTUFF_ERROR" start="0xD" description="Bitstuff error" />
+        <Enum name="SYNC_ERROR" start="0xE" description="Sync error" />
+        <Enum name="WRONG_DATA_TOGGLE" start="0xF" description="Wrong data toggle" />
+      </BitField>
+      <BitField start="15" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="EPLISTSTART" access="Read/Write" description="USB EP Command/Status List start address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="24" name="EP_LIST" description="Start address of the USB EP Command/Status List." />
+    </Register>
+    <Register start="+0x00C" size="4" name="DATABUFSTART" access="Read/Write" description="USB Data buffer start address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="22" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="10" name="DA_BUF" description="Start address of the buffer pointer page where all endpoint data buffers are located." />
+    </Register>
+    <Register start="+0x010" size="4" name="LPM" access="Read/Write" description="Link Power Management register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="HIRD_HW" description="Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token" />
+      <BitField start="4" size="4" name="HIRD_SW" description="Host Initiated Resume Duration - SW. This is the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume." />
+      <BitField start="8" size="1" name="DATA_PENDING" description="As long as this bit is set to one and LPM supported bit is set to one, HW will return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has still data pending and LPM is supported, it must set this bit to 1." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="EPSKIP" access="Read/Write" description="USB Endpoint skip" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="30" name="SKIP" description="Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must deactivate the buffer assigned to this endpoint and return control back to software. When HW has deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit.  An interrupt will be generated when the Active bit goes from 1 to 0.  Note: In case of double-buffering, HW will only clear the Active bit of the buffer indicated by the EPINUSE bit." />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="EPINUSE" access="Read/Write" description="USB Endpoint Buffer in use" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
+      <BitField start="2" size="8" name="BUF" description="Buffer in use: This register has one bit per physical endpoint.  0: HW is accessing buffer 0.  1: HW is accessing buffer 1." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="EPBUFCFG" access="Read/Write" description="USB Endpoint Buffer Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Fixed to zero because the control endpoint zero is fixed to single-buffering for each physical endpoint." />
+      <BitField start="2" size="8" name="BUF_SB" description="Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer.  1: Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle the EPINUSE bit when it clears the Active bit for the buffer." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="INTSTAT" access="Read/Write" description="USB interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EP0OUT" description="Interrupt status register bit for the Control EP0 OUT direction.  This bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a NAK is transmitted for the Control EP0 OUT direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="1" size="1" name="EP0IN" description="Interrupt status register bit for the Control EP0 IN direction.  This bit will be set if NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for the Control EP0 IN direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="2" size="1" name="EP1OUT" description="Interrupt status register bit for the EP1 OUT direction. This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP1 OUT direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="3" size="1" name="EP1IN" description="Interrupt status register bit for the EP1 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP1 IN direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="4" size="1" name="EP2OUT" description="Interrupt status register bit for the EP2 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP2 OUT direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="5" size="1" name="EP2IN" description="Interrupt status register bit for the EP2 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP2 IN direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="6" size="1" name="EP3OUT" description="Interrupt status register bit for the EP3 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP3 OUT direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="7" size="1" name="EP3IN" description="Interrupt status register bit for the EP3 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP3 IN direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="8" size="1" name="EP4OUT" description="Interrupt status register bit for the EP4 OUT direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted for the EP4 OUT direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="9" size="1" name="EP4IN" description="Interrupt status register bit for the EP4 IN direction.  This bit will be set if the corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions to zero or the skip bit is set by software.  If the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted for the EP4 IN direction.  Software can clear this bit by writing a one to it." />
+      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="FRAME_INT" description="Frame interrupt.  This bit is set to one every millisecond when the VbusDebounced bit and the DCON bit are set. This bit can be used by software when handling isochronous endpoints.  Software can clear this bit by writing a one to it." />
+      <BitField start="31" size="1" name="DEV_INT" description="Device status interrupt. This bit is set by HW when one of the bits in the Device Status Change register are set. Software can clear this bit by writing a one to it." />
+    </Register>
+    <Register start="+0x024" size="4" name="INTEN" access="Read/Write" description="USB interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="EP_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
+      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="FRAME_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
+      <BitField start="31" size="1" name="DEV_INT_EN" description="If this bit is set and the corresponding USB interrupt status bit is set, a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit." />
+    </Register>
+    <Register start="+0x028" size="4" name="INTSETSTAT" access="Read/Write" description="USB set interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="EP_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
+      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="FRAME_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
+      <BitField start="31" size="1" name="DEV_SET_INT" description="If software writes a one to one of these bits, the corresponding USB interrupt status bit is set.  When this register is read, the same value as the USB interrupt status register is returned." />
+    </Register>
+    <Register start="+0x02C" size="4" name="INTROUTING" access="Read/Write" description="USB interrupt routing register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="ROUTE_INT9_0" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
+      <BitField start="10" size="20" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="ROUTE_INT30" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
+      <BitField start="31" size="1" name="ROUTE_INT31" description="This bit can control on which hardware interrupt line the interrupt will be generated:  0: IRQ interrupt line is selected for this interrupt bit 1: FIQ interrupt line is selected for this interrupt bit" />
+    </Register>
+    <Register start="+0x034" size="4" name="EPTOGGLE" access="ReadOnly" description="USB Endpoint toggle register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="TOGGLE" description="Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_PORT" start="0x50000000" description="GPIO port ">
+    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0/1; pins PIO0/1_0 to PIO0/1_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the pin P0/1_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin P0/1_n (bit 0 = P0/1_0, bit 1 = P0_1, ..., bit 31 = P0/1_31). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to P0/1_n are active in the P0/1 PIN register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Portpin register port 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Portpin register port 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = P0/1_0, bit 1 = P0/1_1, ..., bit 31 = P0/1_31). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port 0/1  Read: output bits for port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port 0/1  Read: output bits for port 0/1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port 0/1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port 0/1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port 0/1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port 0/1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
+    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="RIT" start="12" size="1" />
+      <BitField name="SSP1" start="14" size="1" />
+      <BitField name="I2C" start="15" size="1" />
+      <BitField name="CT16B0" start="16" size="1" />
+      <BitField name="CT16B1" start="17" size="1" />
+      <BitField name="CT32B0" start="18" size="1" />
+      <BitField name="CT32B1" start="19" size="1" />
+      <BitField name="SSP0" start="20" size="1" />
+      <BitField name="USART" start="21" size="1" />
+      <BitField name="USB" start="22" size="1" />
+      <BitField name="USB_FIQ" start="23" size="1" />
+      <BitField name="ADC" start="24" size="1" />
+      <BitField name="WWDT" start="25" size="1" />
+      <BitField name="BOD" start="26" size="1" />
+      <BitField name="FLASH" start="27" size="1" />
+      <BitField name="USBWAKEUP" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="RIT" start="12" size="1" />
+      <BitField name="SSP1" start="14" size="1" />
+      <BitField name="I2C" start="15" size="1" />
+      <BitField name="CT16B0" start="16" size="1" />
+      <BitField name="CT16B1" start="17" size="1" />
+      <BitField name="CT32B0" start="18" size="1" />
+      <BitField name="CT32B1" start="19" size="1" />
+      <BitField name="SSP0" start="20" size="1" />
+      <BitField name="USART" start="21" size="1" />
+      <BitField name="USB" start="22" size="1" />
+      <BitField name="USB_FIQ" start="23" size="1" />
+      <BitField name="ADC" start="24" size="1" />
+      <BitField name="WWDT" start="25" size="1" />
+      <BitField name="BOD" start="26" size="1" />
+      <BitField name="FLASH" start="27" size="1" />
+      <BitField name="USBWAKEUP" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="RIT" start="12" size="1" />
+      <BitField name="SSP1" start="14" size="1" />
+      <BitField name="I2C" start="15" size="1" />
+      <BitField name="CT16B0" start="16" size="1" />
+      <BitField name="CT16B1" start="17" size="1" />
+      <BitField name="CT32B0" start="18" size="1" />
+      <BitField name="CT32B1" start="19" size="1" />
+      <BitField name="SSP0" start="20" size="1" />
+      <BitField name="USART" start="21" size="1" />
+      <BitField name="USB" start="22" size="1" />
+      <BitField name="USB_FIQ" start="23" size="1" />
+      <BitField name="ADC" start="24" size="1" />
+      <BitField name="WWDT" start="25" size="1" />
+      <BitField name="BOD" start="26" size="1" />
+      <BitField name="FLASH" start="27" size="1" />
+      <BitField name="USBWAKEUP" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="RIT" start="12" size="1" />
+      <BitField name="SSP1" start="14" size="1" />
+      <BitField name="I2C" start="15" size="1" />
+      <BitField name="CT16B0" start="16" size="1" />
+      <BitField name="CT16B1" start="17" size="1" />
+      <BitField name="CT32B0" start="18" size="1" />
+      <BitField name="CT32B1" start="19" size="1" />
+      <BitField name="SSP0" start="20" size="1" />
+      <BitField name="USART" start="21" size="1" />
+      <BitField name="USB" start="22" size="1" />
+      <BitField name="USB_FIQ" start="23" size="1" />
+      <BitField name="ADC" start="24" size="1" />
+      <BitField name="WWDT" start="25" size="1" />
+      <BitField name="BOD" start="26" size="1" />
+      <BitField name="FLASH" start="27" size="1" />
+      <BitField name="USBWAKEUP" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="RIT" start="12" size="1" />
+      <BitField name="SSP1" start="14" size="1" />
+      <BitField name="I2C" start="15" size="1" />
+      <BitField name="CT16B0" start="16" size="1" />
+      <BitField name="CT16B1" start="17" size="1" />
+      <BitField name="CT32B0" start="18" size="1" />
+      <BitField name="CT32B1" start="19" size="1" />
+      <BitField name="SSP0" start="20" size="1" />
+      <BitField name="USART" start="21" size="1" />
+      <BitField name="USB" start="22" size="1" />
+      <BitField name="USB_FIQ" start="23" size="1" />
+      <BitField name="ADC" start="24" size="1" />
+      <BitField name="WWDT" start="25" size="1" />
+      <BitField name="BOD" start="26" size="1" />
+      <BitField name="FLASH" start="27" size="1" />
+      <BitField name="USBWAKEUP" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
+      <BitField name="PIN_INT0" start="4" size="4" />
+      <BitField name="PIN_INT1" start="12" size="4" />
+      <BitField name="PIN_INT2" start="20" size="4" />
+      <BitField name="PIN_INT3" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
+      <BitField name="PIN_INT4" start="4" size="4" />
+      <BitField name="PIN_INT5" start="12" size="4" />
+      <BitField name="PIN_INT6" start="20" size="4" />
+      <BitField name="PIN_INT7" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
+      <BitField name="GINT0" start="4" size="4" />
+      <BitField name="GINT1" start="12" size="4" />
+    </Register>
+    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
+      <BitField name="RIT" start="4" size="4" />
+      <BitField name="SSP1" start="20" size="4" />
+      <BitField name="I2C" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
+      <BitField name="CT16B0" start="4" size="4" />
+      <BitField name="CT16B1" start="12" size="4" />
+      <BitField name="CT32B0" start="20" size="4" />
+      <BitField name="CT32B1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
+      <BitField name="SSP0" start="4" size="4" />
+      <BitField name="USART" start="12" size="4" />
+      <BitField name="USB" start="20" size="4" />
+      <BitField name="USB_FIQ" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
+      <BitField name="ADC" start="4" size="4" />
+      <BitField name="WWDT" start="12" size="4" />
+      <BitField name="BOD" start="20" size="4" />
+      <BitField name="FLASH" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
+      <BitField name="USBWAKEUP" start="20" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
+    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
+      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
+      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
+      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
+    </Register>
+    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
+      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
+    </Register>
+    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
+      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
+    </Register>
+    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
+      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
+      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
+      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCB" start="" description="System Control Block">
+    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
+      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
+    </Register>
+    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
+      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
+      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
+      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
+      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
+    </Register>
+    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
+      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
+      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
+      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
+      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
+      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
+      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
+      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
+      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
+      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
+      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
+    </Register>
+    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
+      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
+    </Register>
+    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
+      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
+      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
+      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
+      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
+      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
+      <BitField name="VECTRESET" start="0" size="1" description="" />
+    </Register>
+    <Register name="SCR" start="0xE000ED10" description="System Control Register">
+      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
+      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
+      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
+    </Register>
+    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
+      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
+      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
+      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
+      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
+      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
+      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
+    </Register>
+    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
+      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
+      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
+      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
+    </Register>
+    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
+      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
+    </Register>
+    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
+      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
+      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
+    </Register>
+    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
+      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
+      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
+      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
+      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
+      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
+      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
+      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
+      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
+      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
+      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
+      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
+      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
+      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
+      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
+    </Register>
+    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
+      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
+      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
+      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
+      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
+      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
+    </Register>
+    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
+      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
+      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
+      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
+      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
+      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
+      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
+    </Register>
+    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
+      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
+      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
+      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
+      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
+      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
+      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
+    </Register>
+    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
+      <BitField name="DEBUGEVT" start="31" size="1" description="" />
+      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
+      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
+    </Register>
+    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
+      <BitField name="EXTERNAL" start="4" size="1" description="" />
+      <BitField name="VCATCH" start="3" size="1" description="" />
+      <BitField name="DWTTRAP" start="2" size="1" description="" />
+      <BitField name="BKPT" start="1" size="1" description="" />
+      <BitField name="HALTED" start="0" size="1" description="" />
+    </Register>
+    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
+    </Register>
+    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
+    </Register>
+    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
+      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
+    </Register>
+  </RegisterGroup>
+</Processor>
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s
new file mode 100644
index 000000000..1cbd4bb22
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/LPC13Uxx_Vectors.s
@@ -0,0 +1,342 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                         Preprocessor Definitions                          *
+ *                         ------------------------                          *
+ * VECTORS_IN_RAM                                                            *
+ *                                                                           *
+ *   If defined, an area of RAM will large enough to store the vector table  *
+ *   will be reserved.                                                       *
+ *                                                                           *
+ *****************************************************************************/
+
+  .syntax unified
+  .code 16
+
+  .section .init, "ax"
+  .align 0
+
+/*****************************************************************************
+ * Default Exception Handlers                                                *
+ *****************************************************************************/
+
+  .thumb_func
+  .weak NMI_Handler
+NMI_Handler:
+  b .
+
+  .thumb_func
+  .weak HardFault_Handler
+HardFault_Handler:
+  b .
+
+  .thumb_func
+  .weak SVC_Handler
+SVC_Handler:
+  b .
+
+  .thumb_func
+  .weak PendSV_Handler
+PendSV_Handler:
+  b .
+
+  .thumb_func
+  .weak SysTick_Handler
+SysTick_Handler:
+  b .
+
+  .thumb_func
+Dummy_Handler:
+  b .
+
+#if defined(__OPTIMIZATION_SMALL)
+
+  .weak PIN_INT0_IRQHandler
+  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT1_IRQHandler
+  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT2_IRQHandler
+  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT3_IRQHandler
+  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT4_IRQHandler
+  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT5_IRQHandler
+  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT6_IRQHandler
+  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT7_IRQHandler
+  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
+
+  .weak GINT0_IRQHandler
+  .thumb_set GINT0_IRQHandler,Dummy_Handler
+
+  .weak GINT1_IRQHandler
+  .thumb_set GINT1_IRQHandler,Dummy_Handler
+
+  .weak RIT_IRQHandler
+  .thumb_set RIT_IRQHandler,Dummy_Handler
+
+  .weak SSP1_IRQHandler
+  .thumb_set SSP1_IRQHandler,Dummy_Handler
+
+  .weak I2C_IRQHandler
+  .thumb_set I2C_IRQHandler,Dummy_Handler
+
+  .weak CT16B0_IRQHandler
+  .thumb_set CT16B0_IRQHandler,Dummy_Handler
+
+  .weak CT16B1_IRQHandler
+  .thumb_set CT16B1_IRQHandler,Dummy_Handler
+
+  .weak CT32B0_IRQHandler
+  .thumb_set CT32B0_IRQHandler,Dummy_Handler
+
+  .weak CT32B1_IRQHandler
+  .thumb_set CT32B1_IRQHandler,Dummy_Handler
+
+  .weak SSP0_IRQHandler
+  .thumb_set SSP0_IRQHandler,Dummy_Handler
+
+  .weak USART_IRQHandler
+  .thumb_set USART_IRQHandler,Dummy_Handler
+
+  .weak USB_IRQHandler
+  .thumb_set USB_IRQHandler,Dummy_Handler
+
+  .weak USB_FIQ_IRQHandler
+  .thumb_set USB_FIQ_IRQHandler,Dummy_Handler
+
+  .weak ADC_IRQHandler
+  .thumb_set ADC_IRQHandler,Dummy_Handler
+
+  .weak WWDT_IRQHandler
+  .thumb_set WWDT_IRQHandler,Dummy_Handler
+
+  .weak BOD_IRQHandler
+  .thumb_set BOD_IRQHandler,Dummy_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Dummy_Handler
+
+  .weak USBWAKEUP_IRQHandler
+  .thumb_set USBWAKEUP_IRQHandler,Dummy_Handler
+
+#else
+
+  .thumb_func
+  .weak PIN_INT0_IRQHandler
+PIN_INT0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT1_IRQHandler
+PIN_INT1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT2_IRQHandler
+PIN_INT2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT3_IRQHandler
+PIN_INT3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT4_IRQHandler
+PIN_INT4_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT5_IRQHandler
+PIN_INT5_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT6_IRQHandler
+PIN_INT6_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT7_IRQHandler
+PIN_INT7_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak GINT0_IRQHandler
+GINT0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak GINT1_IRQHandler
+GINT1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak RIT_IRQHandler
+RIT_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP1_IRQHandler
+SSP1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2C_IRQHandler
+I2C_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CT16B0_IRQHandler
+CT16B0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CT16B1_IRQHandler
+CT16B1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CT32B0_IRQHandler
+CT32B0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CT32B1_IRQHandler
+CT32B1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP0_IRQHandler
+SSP0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USART_IRQHandler
+USART_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USB_IRQHandler
+USB_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USB_FIQ_IRQHandler
+USB_FIQ_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ADC_IRQHandler
+ADC_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak WWDT_IRQHandler
+WWDT_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak BOD_IRQHandler
+BOD_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak FLASH_IRQHandler
+FLASH_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USBWAKEUP_IRQHandler
+USBWAKEUP_IRQHandler:
+  b .
+
+#endif
+
+/*****************************************************************************
+ * Vector Table                                                              *
+ *****************************************************************************/
+
+  .section .vectors, "ax"
+  .align 0
+  .global _vectors
+  .extern __stack_end__
+  .extern Reset_Handler
+
+_vectors:
+  .word __stack_end__
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word SVC_Handler
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word PIN_INT0_IRQHandler
+  .word PIN_INT1_IRQHandler
+  .word PIN_INT2_IRQHandler
+  .word PIN_INT3_IRQHandler
+  .word PIN_INT4_IRQHandler
+  .word PIN_INT5_IRQHandler
+  .word PIN_INT6_IRQHandler
+  .word PIN_INT7_IRQHandler
+  .word GINT0_IRQHandler
+  .word GINT1_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word Dummy_Handler /* Reserved */
+  .word RIT_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word SSP1_IRQHandler
+  .word I2C_IRQHandler
+  .word CT16B0_IRQHandler
+  .word CT16B1_IRQHandler
+  .word CT32B0_IRQHandler
+  .word CT32B1_IRQHandler
+  .word SSP0_IRQHandler
+  .word USART_IRQHandler
+  .word USB_IRQHandler
+  .word USB_FIQ_IRQHandler
+  .word ADC_IRQHandler
+  .word WWDT_IRQHandler
+  .word BOD_IRQHandler
+  .word FLASH_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word Dummy_Handler /* Reserved */
+  .word USBWAKEUP_IRQHandler
+_vectors_end:
+
+#ifdef VECTORS_IN_RAM
+  .section .vectors_ram, "ax"
+  .align 0
+  .global _vectors_ram
+
+_vectors_ram:
+  .space _vectors_end - _vectors, 0
+#endif
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml
new file mode 100644
index 000000000..79bedc537
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/flash_placement.xml
@@ -0,0 +1,37 @@
+<!DOCTYPE Linker_Placement_File>
+<Root name="Flash Section Placement">
+  <MemorySegment name="$(FLASH_NAME:FLASH)">
+    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
+    <ProgramSection alignment="4" load="Yes" name=".init" />
+    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
+    <ProgramSection alignment="4" load="Yes" name=".text" />
+    <ProgramSection alignment="4" load="Yes" name=".dtors" />
+    <ProgramSection alignment="4" load="Yes" name=".ctors" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata" />
+    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
+    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
+    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
+    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
+  </MemorySegment>
+  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
+    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
+    <ProgramSection alignment="4" load="No" name=".fast_run" />
+    <ProgramSection alignment="4" load="No" name=".data_run" />
+    <ProgramSection alignment="4" load="No" name=".bss" />
+    <ProgramSection alignment="4" load="No" name=".tbss" />
+    <ProgramSection alignment="4" load="No" name=".tdata_run" />
+    <ProgramSection alignment="4" load="No" name=".non_init" />
+    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
+    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
+    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
+  </MemorySegment>
+  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
+    <ProgramSection alignment="4" load="Yes" name=".text2" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
+    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
+  </MemorySegment>
+  <MemorySegment name="$(RAM2_NAME:RAM2)">
+    <ProgramSection alignment="4" load="No" name=".data2_run" />
+    <ProgramSection alignment="4" load="No" name=".bss2" />
+  </MemorySegment>
+</Root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject b/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
new file mode 100644
index 000000000..2e9a33d35
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
@@ -0,0 +1,105 @@
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="lpc13xx" target="8" version="2">
+  <project Name="lpc13xx">
+    <configuration
+      Name="Common"
+      Placement="Flash"
+      Target="LPC1347FBD64"
+      arm_architecture="v7M"
+      arm_core_type="Cortex-M3"
+      arm_endian="Little"
+      arm_fpu_type="None"
+      arm_interwork="No"
+      arm_linker_heap_size="256"
+      arm_linker_process_stack_size="0"
+      arm_linker_stack_size="256"
+      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00010000;RAM;0x10000000;0x00002000;RAM;0x20000000;0x00000800"
+      arm_target_debug_interface_type="ADIv5"
+      arm_target_device_name="LPC1347"
+      arm_target_interface_type="SWD"
+      c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX"
+      c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)"
+      debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml"
+      debug_target_connection="J-Link"
+      gcc_entry_point="Reset_Handler"
+      linker_memory_map_file="$(ProjectDir)/LPC1347FBD64_MemoryMap.xml"
+      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
+      macros="DeviceFamily=LPC1300;DeviceSubFamily=LPC134x;Target=LPC1347FBD64;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc13xx"
+      package_dependencies="LPC1300"
+      project_directory=""
+      project_type="Executable"
+      target_reset_script="Reset();"
+      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
+    <folder Name="System Files">
+      <file file_name="thumb_crt0.s" />
+      <file file_name="LPC1300_Startup.s" />
+      <file file_name="LPC13Uxx_Vectors.s">
+        <configuration Name="Common" file_type="Assembly" />
+      </file>
+      <file file_name="LPC1300_Target.js">
+        <configuration Name="Common" file_type="Reset Script" />
+      </file>
+      <file file_name="LPC1347FBD64_MemoryMap.xml" />
+      <file file_name="flash_placement.xml" />
+    </folder>
+    <configuration
+      Name="Debug"
+      link_use_linker_script_file="No"
+      linker_section_placement_file="flash_placement.xml" />
+    <folder Name="hw">
+      <folder Name="bsp">
+        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
+        <file file_name="../../../../../hw/bsp/board.h" />
+        <folder Name="lpcxpresso1769">
+          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" />
+          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h" />
+        </folder>
+      </folder>
+      <folder Name="mcu">
+        <folder Name="nxp">
+          <folder Name="lpc175x_6x">
+            <folder Name="CMSIS_CORE_LPC17xx">
+              <folder Name="inc">
+                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h" />
+              </folder>
+              <folder Name="src">
+                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c" />
+              </folder>
+            </folder>
+            <folder Name="LPC17xx_DriverLib">
+              <folder Name="include" />
+              <folder Name="source">
+                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_gpio.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_pinsel.c" />
+              </folder>
+            </folder>
+          </folder>
+        </folder>
+      </folder>
+    </folder>
+    <folder
+      Name="src"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../src"
+      recurse="Yes" />
+    <folder
+      Name="tinyusb"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../../../../src"
+      recurse="Yes" />
+    <folder
+      Name="segger_rtt"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../../../../lib/segger_rtt"
+      recurse="No" />
+  </project>
+  <configuration
+    Name="LPCXpresso 1347"
+    c_preprocessor_definitions="DEBUG"
+    gcc_debugging_level="Level 3"
+    gcc_optimization_level="None" />
+</solution>
diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s
new file mode 100644
index 000000000..17f88e0ca
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/thumb_crt0.s
@@ -0,0 +1,415 @@
+// **********************************************************************
+// *                    SEGGER Microcontroller GmbH                     *
+// *                        The Embedded Experts                        *
+// **********************************************************************
+// *                                                                    *
+// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
+// *            (c) 2001 - 2018 Rowley Associates Limited               *
+// *                                                                    *
+// *           www.segger.com     Support: support@segger.com           *
+// *                                                                    *
+// **********************************************************************
+// *                                                                    *
+// * All rights reserved.                                               *
+// *                                                                    *
+// * Redistribution and use in source and binary forms, with or         *
+// * without modification, are permitted provided that the following    *
+// * conditions are met:                                                *
+// *                                                                    *
+// * - Redistributions of source code must retain the above copyright   *
+// *   notice, this list of conditions and the following disclaimer.    *
+// *                                                                    *
+// * - Neither the name of SEGGER Microcontroller GmbH                  *
+// *   nor the names of its contributors may be used to endorse or      *
+// *   promote products derived from this software without specific     *
+// *   prior written permission.                                        *
+// *                                                                    *
+// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+// * DISCLAIMED.                                                        *
+// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
+// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+// * DAMAGE.                                                            *
+// *                                                                    *
+// **********************************************************************
+//
+//
+//                           Preprocessor Definitions
+//                           ------------------------
+// APP_ENTRY_POINT
+//
+//   Defines the application entry point function, if undefined this setting
+//   defaults to "main".
+//
+// INITIALIZE_STACK
+//
+//   If defined, the contents of the stack will be initialized to a the
+//   value 0xCC.
+//
+// INITIALIZE_SECONDARY_SECTIONS
+//
+//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
+//
+// INITIALIZE_TCM_SECTIONS
+//
+//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
+//   will be initialized.
+//
+// INITIALIZE_USER_SECTIONS
+//
+//   If defined, the function InitializeUserMemorySections will be called prior
+//   to entering main in order to allow the user to initialize any user defined
+//   memory sections.
+//
+// FULL_LIBRARY
+//
+//  If defined then 
+//    - argc, argv are setup by the debug_getargs.
+//    - the exit symbol is defined and executes on return from main.
+//    - the exit symbol calls destructors, atexit functions and then debug_exit.
+//  
+//  If not defined then
+//    - argc and argv are zero.
+//    - the exit symbol is defined, executes on return from main and loops
+//
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+  .syntax unified
+
+  .global _start
+  .extern APP_ENTRY_POINT
+  .global exit
+  .weak exit
+
+#ifdef INITIALIZE_USER_SECTIONS
+  .extern InitializeUserMemorySections
+#endif
+
+  .section .init, "ax"
+  .code 16
+  .balign 2
+  .thumb_func
+
+_start:
+  /* Set up main stack if size > 0 */
+  ldr r1, =__stack_end__
+  ldr r0, =__stack_start__
+  subs r2, r1, r0
+  beq 1f
+#ifdef __ARM_EABI__
+  movs r2, #0x7
+  bics r1, r2
+#endif
+  mov sp, r1
+#ifdef INITIALIZE_STACK
+  movs r2, #0xCC
+  ldr r0, =__stack_start__
+  bl memory_set
+#endif
+1:
+
+  /* Set up process stack if size > 0 */
+  ldr r1, =__stack_process_end__
+  ldr r0, =__stack_process_start__
+  subs r2, r1, r0
+  beq 1f
+#ifdef __ARM_EABI__
+  movs r2, #0x7
+  bics r1, r2
+#endif
+  msr psp, r1
+  movs r2, #2
+  msr control, r2
+#ifdef INITIALIZE_STACK
+  movs r2, #0xCC
+  bl memory_set
+#endif
+1:
+
+  /* Copy initialized memory sections into RAM (if necessary). */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  ldr r2, =__data_end__
+  bl memory_copy
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  ldr r2, =__text_end__
+  bl memory_copy
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  ldr r2, =__fast_end__
+  bl memory_copy
+  ldr r0, =__ctors_load_start__
+  ldr r1, =__ctors_start__
+  ldr r2, =__ctors_end__
+  bl memory_copy
+  ldr r0, =__dtors_load_start__
+  ldr r1, =__dtors_start__
+  ldr r2, =__dtors_end__
+  bl memory_copy
+  ldr r0, =__rodata_load_start__
+  ldr r1, =__rodata_start__
+  ldr r2, =__rodata_end__
+  bl memory_copy
+  ldr r0, =__tdata_load_start__
+  ldr r1, =__tdata_start__
+  ldr r2, =__tdata_end__
+  bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+  ldr r0, =__data2_load_start__
+  ldr r1, =__data2_start__
+  ldr r2, =__data2_end__
+  bl memory_copy
+  ldr r0, =__text2_load_start__
+  ldr r1, =__text2_start__
+  ldr r2, =__text2_end__
+  bl memory_copy
+  ldr r0, =__rodata2_load_start__
+  ldr r1, =__rodata2_start__
+  ldr r2, =__rodata2_end__
+  bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+#ifdef INITIALIZE_TCM_SECTIONS
+  ldr r0, =__data_tcm_load_start__
+  ldr r1, =__data_tcm_start__
+  ldr r2, =__data_tcm_end__
+  bl memory_copy
+  ldr r0, =__text_tcm_load_start__
+  ldr r1, =__text_tcm_start__
+  ldr r2, =__text_tcm_end__
+  bl memory_copy
+  ldr r0, =__rodata_tcm_load_start__
+  ldr r1, =__rodata_tcm_start__
+  ldr r2, =__rodata_tcm_end__
+  bl memory_copy
+#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
+
+  /* Zero the bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  movs r2, #0
+  bl memory_set
+  ldr r0, =__tbss_start__
+  ldr r1, =__tbss_end__
+  movs r2, #0
+  bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+  ldr r0, =__bss2_start__
+  ldr r1, =__bss2_end__
+  mov r2, #0
+  bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+#ifdef INITIALIZE_TCM_SECTIONS
+  ldr r0, =__bss_tcm_start__
+  ldr r1, =__bss_tcm_end__
+  mov r2, #0
+  bl memory_set
+#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
+
+  /* Initialize the heap */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  subs r1, r1, r0
+  cmp r1, #8
+  blt 1f
+  movs r2, #0
+  str r2, [r0]
+  adds r0, r0, #4
+  str r1, [r0]
+1:
+
+#ifdef INITIALIZE_USER_SECTIONS
+  ldr r2, =InitializeUserMemorySections
+  blx r2
+#endif
+
+  /* Call constructors */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+ctor_loop:
+  cmp r0, r1
+  beq ctor_end
+  ldr r2, [r0]
+  adds r0, #4
+  push {r0-r1}  
+  blx r2
+  pop {r0-r1}
+  b ctor_loop
+ctor_end:
+
+  /* Setup initial call frame */
+  movs r0, #0
+  mov lr, r0
+  mov r12, sp
+
+  .type start, function
+start:
+  /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+  movs r0, #ARGSSPACE
+  ldr r1, =args
+  ldr r2, =debug_getargs  
+  blx r2
+  ldr r1, =args
+#else
+  movs r0, #0
+  movs r1, #0
+#endif
+  ldr r2, =APP_ENTRY_POINT
+  blx r2
+
+  .thumb_func
+exit:
+#ifdef FULL_LIBRARY  
+  mov r5, r0 // save the exit parameter/return result
+
+  /* Call destructors */
+  ldr r0, =__dtors_start__
+  ldr r1, =__dtors_end__
+dtor_loop:
+  cmp r0, r1
+  beq dtor_end
+  ldr r2, [r0]
+  add r0, #4
+  push {r0-r1}
+  blx r2
+  pop {r0-r1}
+  b dtor_loop
+dtor_end:
+
+  /* Call atexit functions */
+  ldr r2, =_execute_at_exit_fns  
+  blx r2
+
+  /* Call debug_exit with return result/exit parameter */
+  mov r0, r5
+  ldr r2, =debug_exit  
+  blx r2
+#endif
+
+  /* Returned from application entry point, loop forever. */
+exit_loop:
+  b exit_loop
+
+  .thumb_func
+memory_copy:
+  cmp r0, r1
+  beq 2f
+  subs r2, r2, r1
+  beq 2f
+1:
+  ldrb r3, [r0]
+  adds r0, r0, #1
+  strb r3, [r1]
+  adds r1, r1, #1
+  subs r2, r2, #1
+  bne 1b
+2:
+  bx lr
+
+  .thumb_func
+memory_set:
+  cmp r0, r1
+  beq 1f
+  strb r2, [r0]
+  adds r0, r0, #1
+  b memory_set
+1:
+  bx lr
+
+  // default C/C++ library helpers
+
+.macro HELPER helper_name
+  .section .text.\helper_name, "ax", %progbits
+  .balign 2
+  .global \helper_name
+  .weak \helper_name  
+\helper_name:
+  .thumb_func
+.endm
+
+.macro JUMPTO name
+#if defined(__thumb__) && !defined(__thumb2__)
+  mov r12, r0
+  ldr r0, =\name
+  push {r0}
+  mov r0, r12
+  pop {pc}
+#else
+  b \name
+#endif
+.endm
+
+HELPER __aeabi_read_tp
+  ldr r0, =__tbss_start__-8
+  bx lr
+HELPER abort
+  b .
+HELPER __assert
+  b .
+HELPER __aeabi_assert
+  b .
+HELPER __sync_synchronize
+  bx lr
+HELPER __getchar
+  JUMPTO debug_getchar
+HELPER __putchar
+  JUMPTO debug_putchar
+HELPER __open
+  JUMPTO debug_fopen
+HELPER __close
+  JUMPTO debug_fclose
+HELPER __write   
+  mov r3, r0
+  mov r0, r1
+  movs r1, #1  
+  JUMPTO debug_fwrite
+HELPER __read  
+  mov r3, r0
+  mov r0, r1
+  movs r1, #1 
+  JUMPTO debug_fread
+HELPER __seek
+  push {r4, lr}
+  mov r4, r0
+  bl debug_fseek
+  cmp r0, #0
+  bne 1f
+  mov r0, r4
+  bl debug_ftell
+  pop {r4, pc}
+1:
+  ldr r0, =-1
+  pop {r4, pc}
+  // char __user_locale_name_buffer[];
+  .section .bss.__user_locale_name_buffer, "aw", %nobits
+  .global __user_locale_name_buffer
+  .weak __user_locale_name_buffer
+  __user_locale_name_buffer:
+  .word 0x0
+
+#ifdef FULL_LIBRARY
+  .bss
+args:
+  .space ARGSSPACE
+#endif
+
+  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
+  .section .stack, "wa", %nobits
+  .section .stack_process, "wa", %nobits
+  .section .heap, "wa", %nobits
+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index fa7bfde0c..1bcf6aa8d 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -92,7 +92,7 @@
 #define OPT_MODE_NONE         0x00 ///< Disabled
 #define OPT_MODE_DEVICE       0x01 ///< Device Mode
 #define OPT_MODE_HOST         0x02 ///< Host Mode
-#define OPT_MODE_HIGH_SPEED   0x10 ///< Highspeed
+#define OPT_MODE_HIGH_SPEED   0x10 ///< High speed
 /** @} */
 
 #ifndef CFG_TUSB_RHPORT0_MODE
@@ -236,7 +236,7 @@
 #endif
 
 #if CFG_TUD_ENDOINT0_SIZE > 64
-  #error Control Endpoint Max Package Size cannot larger than 64
+  #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
 #endif /* _TUSB_OPTION_H_ */
-- 
cgit v1.3.1


From d246cc2e6c9c7eed3b56693a6685a13381950ba2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Nov 2018 23:39:18 +0700
Subject: lpc13xx build ok (not work) with lpcopen

---
 .../cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject      |   63 +-
 hw/bsp/ea4357/startup/xpresso/cr_startup_lpc43xx.c |  509 ------
 hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c       |   58 +-
 hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h       |    8 +-
 .../startup/xpresso/cr_startup_lpc13u.c            |  354 -----
 hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c       |    1 -
 .../startup/xpresso/cr_startup_lpc176x.c           |  423 -----
 hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c         |   83 -
 hw/mcu/nxp/lpc13uxx/hal_mcu/hal_mcu.h              |   54 -
 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/history.txt |   25 -
 .../nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h |  760 ---------
 .../lpc13xx/CMSIS_CORE_LPC13Uxx/inc/power_api.h    |   88 --
 .../CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h      |   64 -
 .../nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/liblinks.xml   |   32 -
 .../CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c      |  437 ------
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/inc/clkconfig.h |   44 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/gpio.h   |   64 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/nmi.h    |   32 -
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/inc/power_api.h |   88 --
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer16.h   |   59 -
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer32.h   |   58 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/type.h   |   52 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/uart.h   |   72 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/usart.h  |   44 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/Serial.c |   33 -
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/src/clkconfig.c |   69 -
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/gpio.c   |  838 ----------
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/nmi.c    |   95 --
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer16.c   |  628 --------
 .../nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer32.c   |  646 --------
 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/uart.c   |  437 ------
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.cproject         |  191 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.project          |   26 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h    |  301 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h        |  243 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h  |  518 +++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h       |   56 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h  |  157 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h    | 1627 ++++++++++++++++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h |  636 ++++++++
 .../nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h   |  688 +++++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h       |  147 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h  |  541 +++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h    |  137 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h |  474 ++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h |  641 ++++++++
 .../nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h |  209 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h    |  539 +++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h   |  416 +++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h  |  287 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h   |  216 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h |  255 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h    |  238 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h |  188 +++
 .../nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h   |  197 +++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h |   79 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h    |  605 ++++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h   |  137 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h  |   41 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h |  702 +++++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h  |  445 ++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h   |  788 ++++++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h   |   77 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h   |  271 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/adc_13xx.c    |  287 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c   |   71 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c  |  261 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/flash_13xx.c  |   82 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c |  108 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_2.c |  140 ++
 .../nxp/lpc13xx/lpc_chip_13xx/src/gpiogroup_13xx.c |   52 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2c_13xx.c    |  548 +++++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2cm_13xx.c   |  259 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/iocon_13xx.c  |   59 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pinint_13xx.c |   53 +
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pmu_13xx.c    |  114 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ring_buffer.c |  167 ++
 .../nxp/lpc13xx/lpc_chip_13xx/src/ritimer_13xx.c   |   99 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ssp_13xx.c    |  496 ++++++
 .../nxp/lpc13xx/lpc_chip_13xx/src/stopwatch_13xx.c |  108 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c |  110 ++
 .../nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c   |  132 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/timer_13xx.c  |  115 ++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c   |  280 ++++
 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/wwdt_13xx.c   |   80 +
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c    |  292 ++--
 86 files changed, 15930 insertions(+), 6274 deletions(-)
 delete mode 100644 hw/bsp/ea4357/startup/xpresso/cr_startup_lpc43xx.c
 delete mode 100644 hw/bsp/lpcxpresso1347/startup/xpresso/cr_startup_lpc13u.c
 delete mode 100644 hw/bsp/lpcxpresso1769/startup/xpresso/cr_startup_lpc176x.c
 delete mode 100644 hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
 delete mode 100644 hw/mcu/nxp/lpc13uxx/hal_mcu/hal_mcu.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/history.txt
 delete mode 100644 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/power_api.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/liblinks.xml
 delete mode 100644 hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/clkconfig.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/gpio.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/nmi.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/power_api.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer16.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer32.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/type.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/uart.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/usart.h
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/Serial.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/clkconfig.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/gpio.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/nmi.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer16.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer32.c
 delete mode 100644 hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/uart.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.cproject
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.project
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/adc_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/flash_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_2.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpiogroup_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2c_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2cm_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/iocon_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pinint_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pmu_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ring_buffer.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ritimer_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ssp_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/stopwatch_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/timer_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c
 create mode 100644 hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/wwdt_13xx.c

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject b/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
index 2e9a33d35..affdd872a 100644
--- a/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
+++ b/examples/device/cdc_msc_hid/ses/lpc13xx/lpc13xx.emProject
@@ -10,15 +10,15 @@
       arm_endian="Little"
       arm_fpu_type="None"
       arm_interwork="No"
-      arm_linker_heap_size="256"
+      arm_linker_heap_size="0"
       arm_linker_process_stack_size="0"
       arm_linker_stack_size="256"
       arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00010000;RAM;0x10000000;0x00002000;RAM;0x20000000;0x00000800"
       arm_target_debug_interface_type="ADIv5"
       arm_target_device_name="LPC1347"
       arm_target_interface_type="SWD"
-      c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX"
-      c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)"
+      c_preprocessor_definitions="__LPC1347FBD64__;__LPC1300_FAMILY;__LPC134x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_LPCXPRESSO1347;CFG_TUSB_MCU=OPT_MCU_LPC13XX"
+      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/lpc_chip_13xx/inc"
       debug_register_definition_file="$(ProjectDir)/LPC13Uxx_Registers.xml"
       debug_target_connection="J-Link"
       gcc_entry_point="Reset_Handler"
@@ -50,28 +50,55 @@
       <folder Name="bsp">
         <file file_name="../../../../../hw/bsp/ansi_escape.h" />
         <file file_name="../../../../../hw/bsp/board.h" />
-        <folder Name="lpcxpresso1769">
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c" />
-          <file file_name="../../../../../hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h" />
+        <folder Name="lpcxpresso1347">
+          <file file_name="../../../../../hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c" />
+          <file file_name="../../../../../hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h" />
         </folder>
       </folder>
       <folder Name="mcu">
         <folder Name="nxp">
-          <folder Name="lpc175x_6x">
-            <folder Name="CMSIS_CORE_LPC17xx">
+          <folder Name="lpc13xx">
+            <folder Name="lpc_chip_13xx">
               <folder Name="inc">
-                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/LPC17xx.h" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/inc/system_LPC17xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h" />
               </folder>
               <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/CMSIS_CORE_LPC17xx/src/system_LPC17xx.c" />
-              </folder>
-            </folder>
-            <folder Name="LPC17xx_DriverLib">
-              <folder Name="include" />
-              <folder Name="source">
-                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_gpio.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc175x_6x/LPC17xx_DriverLib/source/lpc17xx_pinsel.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c" />
               </folder>
             </folder>
           </folder>
diff --git a/hw/bsp/ea4357/startup/xpresso/cr_startup_lpc43xx.c b/hw/bsp/ea4357/startup/xpresso/cr_startup_lpc43xx.c
deleted file mode 100644
index a5f06006a..000000000
--- a/hw/bsp/ea4357/startup/xpresso/cr_startup_lpc43xx.c
+++ /dev/null
@@ -1,509 +0,0 @@
-//*****************************************************************************
-// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
-//
-// Version : 150706
-//*****************************************************************************
-//
-// Copyright(C) NXP Semiconductors, 2013-2015
-// All rights reserved.
-//
-// Software that is described herein is for illustrative purposes only
-// which provides customers with programming information regarding the
-// LPC products.  This software is supplied "AS IS" without any warranties of
-// any kind, and NXP Semiconductors and its licensor disclaim any and
-// all warranties, express or implied, including all implied warranties of
-// merchantability, fitness for a particular purpose and non-infringement of
-// intellectual property rights.  NXP Semiconductors assumes no responsibility
-// or liability for the use of the software, conveys no license or rights under any
-// patent, copyright, mask work right, or any other intellectual property rights in
-// or to any products. NXP Semiconductors reserves the right to make changes
-// in the software without notification. NXP Semiconductors also makes no
-// representation or warranty that such application will be suitable for the
-// specified use without further testing or modification.
-//
-// Permission to use, copy, modify, and distribute this software and its
-// documentation is hereby granted, under NXP Semiconductors' and its
-// licensor's relevant copyrights in the software, without fee, provided that it
-// is used in conjunction with NXP Semiconductors microcontrollers.  This
-// copyright, permission, and disclaimer notice must appear in all copies of
-// this code.
-//*****************************************************************************
-
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-    extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
-// Declaration of external SystemInit function
-extern void SystemInit(void);
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will 
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-void ResetISR(void);
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void MemManage_Handler(void);
-WEAK void BusFault_Handler(void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void DebugMon_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take 
-// precedence over these weak definitions
-//
-//*****************************************************************************
-void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
-#if defined (__USE_LPCOPEN)
-void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
-#endif
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
-#if defined (__USE_LPCOPEN)
-void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
-#else
-void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
-#endif
-void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-//
-// External declaration for LPC MCU vector table checksum from  Linker Script
-//
-//*****************************************************************************
-WEAK extern void __valid_user_code_checksum();
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((used,section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-    // Core Level - CM4
-    &_vStackTop,                    // The initial stack pointer
-    ResetISR,                       // The reset handler
-    NMI_Handler,                    // The NMI handler
-    HardFault_Handler,              // The hard fault handler
-    MemManage_Handler,              // The MPU fault handler
-    BusFault_Handler,               // The bus fault handler
-    UsageFault_Handler,             // The usage fault handler
-    __valid_user_code_checksum,             // LPC MCU Checksum
-    0,                              // Reserved
-    0,                              // Reserved
-    0,                              // Reserved
-    SVC_Handler,                    // SVCall handler
-    DebugMon_Handler,               // Debug monitor handler
-    0,                              // Reserved
-    PendSV_Handler,                 // The PendSV handler
-    SysTick_Handler,                // The SysTick handler
-
-    // Chip Level - LPC43 (M4)
-    DAC_IRQHandler,           // 16
-#if defined (__USE_LPCOPEN)
-    M0APP_IRQHandler,         // 17 CortexM4/M0 (LPC43XX ONLY)
-#else
-    M0CORE_IRQHandler,        // 17
-#endif
-    DMA_IRQHandler,           // 18
-    0,           // 19
-    FLASH_EEPROM_IRQHandler,  // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
-    ETH_IRQHandler,           // 21
-    SDIO_IRQHandler,          // 22
-    LCD_IRQHandler,           // 23
-    USB0_IRQHandler,          // 24
-    USB1_IRQHandler,          // 25
-    SCT_IRQHandler,           // 26
-    RIT_IRQHandler,           // 27
-    TIMER0_IRQHandler,        // 28
-    TIMER1_IRQHandler,        // 29
-    TIMER2_IRQHandler,        // 30
-    TIMER3_IRQHandler,        // 31
-    MCPWM_IRQHandler,         // 32
-    ADC0_IRQHandler,          // 33
-    I2C0_IRQHandler,          // 34
-    I2C1_IRQHandler,          // 35
-    SPI_IRQHandler,           // 36
-    ADC1_IRQHandler,          // 37
-    SSP0_IRQHandler,          // 38
-    SSP1_IRQHandler,          // 39
-    UART0_IRQHandler,         // 40
-    UART1_IRQHandler,         // 41
-    UART2_IRQHandler,         // 42
-    UART3_IRQHandler,         // 43
-    I2S0_IRQHandler,          // 44
-    I2S1_IRQHandler,          // 45
-    SPIFI_IRQHandler,         // 46
-    SGPIO_IRQHandler,         // 47
-    GPIO0_IRQHandler,         // 48
-    GPIO1_IRQHandler,         // 49
-    GPIO2_IRQHandler,         // 50
-    GPIO3_IRQHandler,         // 51
-    GPIO4_IRQHandler,         // 52
-    GPIO5_IRQHandler,         // 53
-    GPIO6_IRQHandler,         // 54
-    GPIO7_IRQHandler,         // 55
-    GINT0_IRQHandler,         // 56
-    GINT1_IRQHandler,         // 57
-    EVRT_IRQHandler,          // 58
-    CAN1_IRQHandler,          // 59
-    0,                        // 60
-#if defined (__USE_LPCOPEN)
-    ADCHS_IRQHandler,         // 61 ADCHS combined interrupt
-#else
-    VADC_IRQHandler,          // 61
-#endif
-    ATIMER_IRQHandler,        // 62
-    RTC_IRQHandler,           // 63
-    0,                        // 64
-    WDT_IRQHandler,           // 65
-    M0SUB_IRQHandler,         // 66
-    CAN0_IRQHandler,          // 67
-    QEI_IRQHandler,           // 68
-};
-
-
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-        __attribute__((section(".after_vectors"
-)))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int *pulSrc = (unsigned int*) romstart;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4)
-        *pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4)
-        *pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//
-//*****************************************************************************
-void ResetISR(void) {
-
-// *************************************************************
-// The following conditional block of code manually resets as
-// much of the peripheral set of the LPC43 as possible. This is
-// done because the LPC43 does not provide a means of triggering
-// a full system reset under debugger control, which can cause
-// problems in certain circumstances when debugging.
-//
-// You can prevent this code block being included if you require
-// (for example when creating a final executable which you will
-// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
-//
-#ifndef DONT_RESET_ON_RESTART
-
-    // Disable interrupts
-    __asm volatile ("cpsid i");
-    // equivalent to CMSIS '__disable_irq()' function
-
-    unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
-    // LPC_RGU->RESET_CTRL0 @ 0x40053100
-    // LPC_RGU->RESET_CTRL1 @ 0x40053104
-    // Note that we do not use the CMSIS register access mechanism,
-    // as there is no guarantee that the project has been configured
-    // to use CMSIS.
-
-    // Write to LPC_RGU->RESET_CTRL0
-    *(RESET_CONTROL + 0) = 0x10DF1000;
-    // GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
-    // USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
-
-    // Write to LPC_RGU->RESET_CTRL1
-    *(RESET_CONTROL + 1) = 0x01DFF7FF;
-    // M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
-    // I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
-    // DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
-    // RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
-
-    // Clear all pending interrupts in the NVIC
-    volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
-    unsigned int irqpendloop;
-    for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
-        *(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
-    }
-
-    // Reenable interrupts
-    __asm volatile ("cpsie i");
-    // equivalent to CMSIS '__enable_irq()' function
-
-#endif  // ifndef DONT_RESET_ON_RESTART
-// *************************************************************
-
-#if defined (__USE_LPCOPEN)
-    SystemInit();
-#endif
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-    unsigned int LoadAddr, ExeAddr, SectionLen;
-    unsigned int *SectionTableAddr;
-
-    // Load base address of Global Section Table
-    SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-    while (SectionTableAddr < &__data_section_table_end) {
-        LoadAddr = *SectionTableAddr++;
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        data_init(LoadAddr, ExeAddr, SectionLen);
-    }
-    // At this point, SectionTableAddr = &__bss_section_table;
-    // Zero fill the bss segment
-    while (SectionTableAddr < &__bss_section_table_end) {
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        bss_init(ExeAddr, SectionLen);
-    }
-
-#if !defined (__USE_LPCOPEN)
-// LPCOpen init code deals with FP and VTOR initialisation
-#if defined (__VFP_FP__) && !defined (__SOFTFP__)
-    /*
-     * Code to enable the Cortex-M4 FPU only included
-     * if appropriate build options have been selected.
-     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
-     */
-    // CPACR is located at address 0xE000ED88
-    asm("LDR.W R0, =0xE000ED88");
-    // Read CPACR
-    asm("LDR R1, [R0]");
-    // Set bits 20-23 to enable CP10 and CP11 coprocessors
-    asm(" ORR R1, R1, #(0xF << 20)");
-    // Write back the modified value to the CPACR
-    asm("STR R1, [R0]");
-#endif // (__VFP_FP__) && !(__SOFTFP__)
-    // ******************************
-    // Check to see if we are running the code from a non-zero
-    // address (eg RAM, external flash), in which case we need
-    // to modify the VTOR register to tell the CPU that the
-    // vector table is located at a non-0x0 address.
-
-    // Note that we do not use the CMSIS register access mechanism,
-    // as there is no guarantee that the project has been configured
-    // to use CMSIS.
-    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
-    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
-        // CMSIS : SCB->VTOR = <address of vector table>
-        *pSCB_VTOR = (unsigned int) g_pfnVectors;
-    }
-#endif
-
-#if defined (__USE_CMSIS)
-    SystemInit();
-#endif
-
-#if defined (__cplusplus)
-    //
-    // Call C++ library initialisation
-    //
-    __libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-    // Call the Redlib library, which in turn calls main()
-    __main();
-#else
-    main();
-#endif
-
-    //
-    // main() shouldn't return, but if it does, we'll just enter an infinite loop
-    //
-    while (1) {
-        ;
-    }
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void NMI_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void HardFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void MemManage_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void BusFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void UsageFault_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SVC_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void DebugMon_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void PendSV_Handler(void) {
-    while (1) {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SysTick_Handler(void) {
-    while (1) {
-    }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void IntDefaultHandler(void) {
-    while (1) {
-    }
-}
diff --git a/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c b/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
index d72402d66..ef95b511e 100644
--- a/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
+++ b/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
@@ -36,10 +36,10 @@
 */
 /**************************************************************************/
 
-#include "../board.h"
-
 #ifdef BOARD_LPCXPRESSO1347
 
+#include "../board.h"
+
 #define LED_PORT                  (0)
 #define LED_PIN                   (7)
 #define LED_ON                    (1)
@@ -63,39 +63,67 @@ enum {
   BOARD_BUTTON_COUNT = sizeof(buttons) / sizeof(buttons[0])
 };
 
+// required by lpcopen chip layer
+uint32_t const OscRateIn = 0;
+uint32_t const ExtRateIn = 0;
+
+// required by startup
+void SystemInit(void)
+{
+  Chip_SystemInit();
+}
 
 void board_init(void)
 {
-  SystemInit();
+  Chip_SystemInit();
 
 #if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
   SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
 #endif
 
-  GPIOInit();
+  Chip_GPIO_Init(LPC_GPIO_PORT);
 
   //------------- LED -------------//
-  GPIOSetDir(LED_PORT, LED_PIN, 1);
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, BOARD_LED0);
 
   //------------- BUTTON -------------//
-  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
+//  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIOSetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
 
   //------------- UART -------------//
-  UARTInit(CFG_UART_BAUDRATE);
+  //UARTInit(CFG_UART_BAUDRATE);
 
 }
 
+/*------------------------------------------------------------------*/
+/* TUSB HAL MILLISECOND
+ *------------------------------------------------------------------*/
+#if CFG_TUSB_OS == OPT_OS_NONE
+
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t tusb_hal_millis(void)
+{
+  return board_tick2ms(system_ticks);
+}
+
+#endif
+
 //--------------------------------------------------------------------+
 // LEDS
 //--------------------------------------------------------------------+
-void board_leds(uint32_t on_mask, uint32_t off_mask)
+void board_led_control(uint32_t id, bool state)
 {
-  if (on_mask & BIT_(0))
+  if (state)
   {
-    GPIOSetBitValue(LED_PORT, LED_PIN, LED_ON);
-  }else if (off_mask & BIT_(0))
+    Chip_GPIO_SetValue(LPC_GPIO_PORT, 0, 1 << id);
+  }else
   {
-    GPIOSetBitValue(LED_PORT, LED_PIN, LED_OFF);
+    Chip_GPIO_ClearValue(LPC_GPIO_PORT, 0, 1 << id);
   }
 }
 
@@ -104,14 +132,14 @@ void board_leds(uint32_t on_mask, uint32_t off_mask)
 //--------------------------------------------------------------------+
 static bool button_read(uint8_t id)
 {
-  return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
+//  return !GPIOGetPinValue(buttons[id].port, buttons[id].pin); // button is active low
 }
 
 uint32_t board_buttons(void)
 {
   uint32_t result = 0;
 
-  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
+//  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
 
   return result;
 }
@@ -121,7 +149,7 @@ uint32_t board_buttons(void)
 //--------------------------------------------------------------------+
 void board_uart_putchar(uint8_t c)
 {
-  UARTSend(&c, 1);
+//  UARTSend(&c, 1);
 }
 
 uint8_t  board_uart_getchar(void)
diff --git a/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h b/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h
index 643aec7f3..f47a75beb 100644
--- a/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h
+++ b/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h
@@ -43,11 +43,11 @@
  extern "C" {
 #endif
 
-#include "LPC13Uxx.h"
-#include "gpio.h"
-#include "uart.h"
+//#include "LPC13Uxx.h"
 
-#define CFG_PRINTF_TARGET PRINTF_TARGET_UART
+#include "chip.h"
+
+#define BOARD_LED0      7
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/lpcxpresso1347/startup/xpresso/cr_startup_lpc13u.c b/hw/bsp/lpcxpresso1347/startup/xpresso/cr_startup_lpc13u.c
deleted file mode 100644
index 8b5d7eebb..000000000
--- a/hw/bsp/lpcxpresso1347/startup/xpresso/cr_startup_lpc13u.c
+++ /dev/null
@@ -1,354 +0,0 @@
-//*****************************************************************************
-//   +--+       
-//   | ++----+   
-//   +-++    |  
-//     |     |  
-//   +-+--+  |   
-//   | +--+--+  
-//   +----+    Copyright (c) 2012 Code Red Technologies Ltd.
-//
-// NXP LPC13U Microcontroller Startup code for use with Red Suite
-//
-// Version : 120202
-//
-// Software License Agreement
-// 
-// The software is owned by Code Red Technologies and/or its suppliers, and is 
-// protected under applicable copyright laws.  All rights are reserved.  Any 
-// use in violation of the foregoing restrictions may subject the user to criminal 
-// sanctions under applicable laws, as well as to civil liability for the breach 
-// of the terms and conditions of this license.
-// 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
-// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
-// CODE RED TECHNOLOGIES LTD. 
-//
-//*****************************************************************************
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-	extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-// Code Red - if CMSIS is being used, then SystemInit() routine
-// will be called by startup code rather than in application's main()
-#if defined (__USE_CMSIS)
-#include "LPC13Uxx.h"
-#endif
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will 
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-void ResetISR(void);
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void MemManage_Handler(void);
-WEAK void BusFault_Handler(void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void DebugMon_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take 
-// precedence over these weak definitions
-//
-//*****************************************************************************
-void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void OSTIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CT16B0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CT16B1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USART_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
-void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void OSCFAIL_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PVTCIRCUIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.  Note that the proper constructs must be placed on this to
-// ensure that it ends up at physical address 0x0000.0000.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-	// Core Level - CM3
-		&_vStackTop, // The initial stack pointer
-		ResetISR, // The reset handler
-		NMI_Handler, // The NMI handler
-		HardFault_Handler, // The hard fault handler
-		MemManage_Handler, // The MPU fault handler
-		BusFault_Handler, // The bus fault handler
-		UsageFault_Handler, // The usage fault handler
-		0, // Reserved
-		0, // Reserved
-		0, // Reserved
-		0, // Reserved
-		SVC_Handler, // SVCall handler
-		DebugMon_Handler, // Debug monitor handler
-		0, // Reserved
-		PendSV_Handler, // The PendSV handler
-		SysTick_Handler, // The SysTick handler
-
-        // LPC13U External Interrupts
-		PIN_INT0_IRQHandler,	// All GPIO pin can be routed to PIN_INTx
-		PIN_INT1_IRQHandler,
-		PIN_INT2_IRQHandler,
-		PIN_INT3_IRQHandler,
-		PIN_INT4_IRQHandler,
-		PIN_INT5_IRQHandler,
-		PIN_INT6_IRQHandler,
-		PIN_INT7_IRQHandler,
-		GINT0_IRQHandler,
-		GINT1_IRQHandler,		// PIO0 (0:7)
-		0,
-		0,
-		OSTIMER_IRQHandler,
-		0,
-		SSP1_IRQHandler,		// SSP1
-		I2C_IRQHandler,        	//  I2C
-		CT16B0_IRQHandler,		// 16-bit Timer0
-		CT16B1_IRQHandler,      // 16-bit Timer1
-		CT32B0_IRQHandler,      // 32-bit Timer0
-		CT32B1_IRQHandler,      // 32-bit Timer1
-		SSP0_IRQHandler,        // SSP0
-		USART_IRQHandler,       // USART
-		USB_IRQHandler,         // USB IRQ
-		USB_FIQHandler,         // USB FIQ
-		ADC_IRQHandler,         // A/D Converter
-		WDT_IRQHandler,         // Watchdog timer
-		BOD_IRQHandler,         // Brown Out Detect
-		FMC_IRQHandler,         // IP2111 Flash Memory Controller
-		OSCFAIL_IRQHandler,     // OSC FAIL
-		PVTCIRCUIT_IRQHandler,  // PVT CIRCUIT
-		USBWakeup_IRQHandler,   // USB wake up
-		0,
-	};
-
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-	unsigned int *pulDest = (unsigned int*) start;
-	unsigned int *pulSrc = (unsigned int*) romstart;
-	unsigned int loop;
-	for (loop = 0; loop < len; loop = loop + 4)
-		*pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-	unsigned int *pulDest = (unsigned int*) start;
-	unsigned int loop;
-	for (loop = 0; loop < len; loop = loop + 4)
-		*pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void
-ResetISR(void) {
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-	unsigned int LoadAddr, ExeAddr, SectionLen;
-	unsigned int *SectionTableAddr;
-
-	// Load base address of Global Section Table
-	SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-	while (SectionTableAddr < &__data_section_table_end) {
-		LoadAddr = *SectionTableAddr++;
-		ExeAddr = *SectionTableAddr++;
-		SectionLen = *SectionTableAddr++;
-		data_init(LoadAddr, ExeAddr, SectionLen);
-	}
-	// At this point, SectionTableAddr = &__bss_section_table;
-	// Zero fill the bss segment
-	while (SectionTableAddr < &__bss_section_table_end) {
-		ExeAddr = *SectionTableAddr++;
-		SectionLen = *SectionTableAddr++;
-		bss_init(ExeAddr, SectionLen);
-	}
-
-#ifdef __USE_CMSIS
-	SystemInit();
-#endif
-
-#if defined (__cplusplus)
-	//
-	// Call C++ library initialisation
-	//
-	__libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-	// Call the Redlib library, which in turn calls main()
-	__main() ;
-#else
-	main();
-#endif
-	//
-	// main() shouldn't return, but if it does, we'll just enter an infinite loop
-	//
-	while (1) {
-		;
-	}
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void NMI_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void HardFault_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void MemManage_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void BusFault_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void UsageFault_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void SVC_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void DebugMon_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void PendSV_Handler(void) {
-	while (1) {
-	}
-}
-__attribute__ ((section(".after_vectors")))
-void SysTick_Handler(void) {
-	while (1) {
-	}
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a handler
-// is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void IntDefaultHandler(void) {
-	//
-	// Go into an infinite loop.
-	//
-	while (1) {
-	}
-}
diff --git a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
index edbe7c8f0..40472174b 100644
--- a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
@@ -157,7 +157,6 @@ void board_led_control(uint32_t id, bool state)
   {
     GPIO_ClearValue(BOARD_LED0_PORT, BIT_(BOARD_LED0));
   }
-
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/lpcxpresso1769/startup/xpresso/cr_startup_lpc176x.c b/hw/bsp/lpcxpresso1769/startup/xpresso/cr_startup_lpc176x.c
deleted file mode 100644
index fc6bed580..000000000
--- a/hw/bsp/lpcxpresso1769/startup/xpresso/cr_startup_lpc176x.c
+++ /dev/null
@@ -1,423 +0,0 @@
-//*****************************************************************************
-//   +--+
-//   | ++----+
-//   +-++    |
-//     |     |
-//   +-+--+  |
-//   | +--+--+
-//   +----+    Copyright (c) 2009-10 Code Red Technologies Ltd.
-//
-// Microcontroller Startup code for use with Red Suite
-//
-// Version : 101130
-//
-// Software License Agreement
-//
-// The software is owned by Code Red Technologies and/or its suppliers, and is
-// protected under applicable copyright laws.  All rights are reserved.  Any
-// use in violation of the foregoing restrictions may subject the user to criminal
-// sanctions under applicable laws, as well as to civil liability for the breach
-// of the terms and conditions of this license.
-//
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
-// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
-// CODE RED TECHNOLOGIES LTD.
-//
-//*****************************************************************************
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-	extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-#define SVCall_Handler SVC_Handler
-
-// Code Red - if CMSIS is being used, then SystemInit() routine
-// will be called by startup code rather than in application's main()
-#if defined (__USE_CMSIS)
-#include "system_LPC17xx.h"
-#endif
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-     void ResetISR(void);
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void MemManage_Handler(void);
-WEAK void BusFault_Handler(void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVCall_Handler(void);
-WEAK void DebugMon_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take
-// precedence over these weak definitions
-//
-//*****************************************************************************
-void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-	// Core Level - CM3
-	&_vStackTop, // The initial stack pointer
-	ResetISR,								// The reset handler
-	NMI_Handler,							// The NMI handler
-	HardFault_Handler,						// The hard fault handler
-	MemManage_Handler,						// The MPU fault handler
-	BusFault_Handler,						// The bus fault handler
-	UsageFault_Handler,						// The usage fault handler
-	0,										// Reserved
-	0,										// Reserved
-	0,										// Reserved
-	0,										// Reserved
-	SVCall_Handler,							// SVCall handler
-	DebugMon_Handler,						// Debug monitor handler
-	0,										// Reserved
-	PendSV_Handler,							// The PendSV handler
-	SysTick_Handler,						// The SysTick handler
-
-	// Chip Level - LPC17
-	WDT_IRQHandler,							// 16, 0x40 - WDT
-	TIMER0_IRQHandler,						// 17, 0x44 - TIMER0
-	TIMER1_IRQHandler,						// 18, 0x48 - TIMER1
-	TIMER2_IRQHandler,						// 19, 0x4c - TIMER2
-	TIMER3_IRQHandler,						// 20, 0x50 - TIMER3
-	UART0_IRQHandler,						// 21, 0x54 - UART0
-	UART1_IRQHandler,						// 22, 0x58 - UART1
-	UART2_IRQHandler,						// 23, 0x5c - UART2
-	UART3_IRQHandler,						// 24, 0x60 - UART3
-	PWM1_IRQHandler,						// 25, 0x64 - PWM1
-	I2C0_IRQHandler,						// 26, 0x68 - I2C0
-	I2C1_IRQHandler,						// 27, 0x6c - I2C1
-	I2C2_IRQHandler,						// 28, 0x70 - I2C2
-	SPI_IRQHandler,							// 29, 0x74 - SPI
-	SSP0_IRQHandler,						// 30, 0x78 - SSP0
-	SSP1_IRQHandler,						// 31, 0x7c - SSP1
-	PLL0_IRQHandler,						// 32, 0x80 - PLL0 (Main PLL)
-	RTC_IRQHandler,							// 33, 0x84 - RTC
-	EINT0_IRQHandler,						// 34, 0x88 - EINT0
-	EINT1_IRQHandler,						// 35, 0x8c - EINT1
-	EINT2_IRQHandler,						// 36, 0x90 - EINT2
-	EINT3_IRQHandler,						// 37, 0x94 - EINT3
-	ADC_IRQHandler,							// 38, 0x98 - ADC
-	BOD_IRQHandler,							// 39, 0x9c - BOD
-	USB_IRQHandler,							// 40, 0xA0 - USB
-	CAN_IRQHandler,							// 41, 0xa4 - CAN
-	DMA_IRQHandler,							// 42, 0xa8 - GP DMA
-	I2S_IRQHandler,							// 43, 0xac - I2S
-	ENET_IRQHandler,						// 44, 0xb0 - Ethernet
-	RIT_IRQHandler,							// 45, 0xb4 - RITINT
-	MCPWM_IRQHandler,						// 46, 0xb8 - Motor Control PWM
-	QEI_IRQHandler,							// 47, 0xbc - Quadrature Encoder
-	PLL1_IRQHandler,						// 48, 0xc0 - PLL1 (USB PLL)
-	USBActivity_IRQHandler,					// 49, 0xc4 - USB Activity interrupt to wakeup
-	CANActivity_IRQHandler, 				// 50, 0xc8 - CAN Activity interrupt to wakeup
-};
-
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-	unsigned int *pulDest = (unsigned int*) start;
-	unsigned int *pulSrc = (unsigned int*) romstart;
-	unsigned int loop;
-	for (loop = 0; loop < len; loop = loop + 4)
-		*pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-	unsigned int *pulDest = (unsigned int*) start;
-	unsigned int loop;
-	for (loop = 0; loop < len; loop = loop + 4)
-		*pulDest++ = 0;
-}
-
-#ifndef USE_OLD_STYLE_DATA_BSS_INIT
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-#else
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the load address, execution address and length of the RW data section and
-// the execution and length of the BSS (zero initialized) section.
-// Note that these symbols are not normally used by the managed linker script
-// mechanism in Red Suite/LPCXpresso 3.6 (Windows) and LPCXpresso 3.8 (Linux).
-// They are provide here simply so this startup code can be used with earlier
-// versions of Red Suite which do not support the more advanced managed linker
-// script mechanism introduced in the above version. To enable their use,
-// define "USE_OLD_STYLE_DATA_BSS_INIT".
-//*****************************************************************************
-extern unsigned int _etext;
-extern unsigned int _data;
-extern unsigned int _edata;
-extern unsigned int _bss;
-extern unsigned int _ebss;
-#endif
-
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void
-ResetISR(void) {
-
-#ifndef USE_OLD_STYLE_DATA_BSS_INIT
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-	unsigned int LoadAddr, ExeAddr, SectionLen;
-	unsigned int *SectionTableAddr;
-
-	// Load base address of Global Section Table
-	SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-	while (SectionTableAddr < &__data_section_table_end) {
-		LoadAddr = *SectionTableAddr++;
-		ExeAddr = *SectionTableAddr++;
-		SectionLen = *SectionTableAddr++;
-		data_init(LoadAddr, ExeAddr, SectionLen);
-	}
-	// At this point, SectionTableAddr = &__bss_section_table;
-	// Zero fill the bss segment
-	while (SectionTableAddr < &__bss_section_table_end) {
-		ExeAddr = *SectionTableAddr++;
-		SectionLen = *SectionTableAddr++;
-		bss_init(ExeAddr, SectionLen);
-	}
-#else
-	// Use Old Style Data and BSS section initialization.
-	// This will only initialize a single RAM bank.
-	unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
-
-    // Copy the data segment from flash to SRAM.
-	LoadAddr = &_etext;
-	ExeAddr = &_data;
-	EndAddr = &_edata;
-	SectionLen = (void*)EndAddr - (void*)ExeAddr;
-	data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
-	// Zero fill the bss segment
-	ExeAddr = &_bss;
-	EndAddr = &_ebss;
-	SectionLen = (void*)EndAddr - (void*)ExeAddr;
-	bss_init ((unsigned int)ExeAddr, SectionLen);
-#endif
-
-#ifdef __USE_CMSIS
-	SystemInit();
-#endif
-
-#if defined (__cplusplus)
-	//
-	// Call C++ library initialisation
-	//
-	__libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-	// Call the Redlib library, which in turn calls main()
-	__main() ;
-#else
-	main();
-#endif
-
-	//
-	// main() shouldn't return, but if it does, we'll just enter an infinite loop
-	//
-	while (1) {
-		;
-	}
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void NMI_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void HardFault_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void MemManage_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void BusFault_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void UsageFault_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SVCall_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void DebugMon_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void PendSV_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SysTick_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void IntDefaultHandler(void)
-{
-    while(1)
-    {
-    }
-}
diff --git a/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c b/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
deleted file mode 100644
index 5c6c2e623..000000000
--- a/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_lpc13uxx.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_lpc13uxx.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "common/tusb_common.h"
-#include "hal.h"
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC13XX
-
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport; // discard compiler's warning
-  NVIC_EnableIRQ(USB_IRQ_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport; // discard compiler's warning
-  NVIC_DisableIRQ(USB_IRQ_IRQn);
-}
-
-bool tusb_hal_init(void)
-{
-	// TODO remove magic number
-  LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); /* Enable AHB clock to the USB block and USB RAM. */
-  LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
-
-  /* Pull-down is needed, or internally, VBUS will be floating. This is to
-  address the wrong status in VBUSDebouncing bit in CmdStatus register.  */
-  // set PIO0_3 as USB_VBUS
-  LPC_IOCON->PIO0_3   &= ~0x1F;
-  LPC_IOCON->PIO0_3   |= (0x01<<0) | (1 << 3);            /* Secondary function VBUS */
-
-  // set PIO0_6 as usb connect
-  LPC_IOCON->PIO0_6   &= ~0x07;
-  LPC_IOCON->PIO0_6   |= (0x01<<0);            /* Secondary function SoftConn */
-
-  return true;
-}
-
-void USB_IRQHandler(void)
-{
-  hal_dcd_isr(0);
-}
-
-
-
-
-#endif
diff --git a/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_mcu.h b/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_mcu.h
deleted file mode 100644
index e38b48199..000000000
--- a/hw/mcu/nxp/lpc13uxx/hal_mcu/hal_mcu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_lpc13uxx.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#ifndef _TUSB_HAL_MCU_H_
-#define _TUSB_HAL_MCU_H_
-
-#include "LPC13Uxx.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_HAL_MCU_H_ */
-
diff --git a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/history.txt b/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/history.txt
deleted file mode 100644
index f564aade7..000000000
--- a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/history.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-History of updates to CMSIS_CORE_LPC13Uxx
-===========================================
-
-18 July 2013
-------------
-CMSIS library project using ARM Cortex-M0 CMSIS files as
-supplied in ARM's CMSIS 3.20 March 2013 release, together
-with NXP's device specific files taken from old
-CMSISv2p10_LPC13Uxx project.
-
-Note files are built -Os for both Debug and Release
-
-
-History of updates to CMSISv2p10_LPC13Uxx
-=========================================
-
-17 February 2012
-----------------
-
-CMSIS 2.1 library project using ARM Cortex-M3 CMSIS 
-files as supplied in ARM's CMSIS 2.1 July 2011 release,
-together with device/board specific files from NXP for
-LPC1300 (12bit ADC) parts (ie LPC1315/16/17/45/46/47).
-
-
diff --git a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h b/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h
deleted file mode 100644
index 220c0f889..000000000
--- a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/LPC13Uxx.h
+++ /dev/null
@@ -1,760 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     LPC13Uxx.h
- *
- * 
- *
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
- *           default LPC13Uxx Device Series
- *
- * @version  V0.1
- * @date     18. Jan 2012
- *
- * @note     Generated with SFDGen V2.6 Build 4f  on Tuesday, 17.01.2012 13:39:52
- *
- *           from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
- *           created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
- *
- *******************************************************************************************************/
-
-/** @addtogroup NXP
-  * @{
-  */
-
-/** @addtogroup LPC13Uxx
-  * @{
-  */
-
-#ifndef __LPC13UXX_H__
-#define __LPC13UXX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-
-#if defined ( __CC_ARM   )
-  #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// -------------------------  Cortex-M3 Processor Exceptions Numbers  -----------------------------
-  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
-  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
-  MemoryManagement_IRQn             = -12,  /*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
-  BusFault_IRQn                     = -11,  /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
-  UsageFault_IRQn                   = -10,  /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
-  SVCall_IRQn                       = -5,   /*!<  11  System Service Call via SVC instruction */
-  DebugMonitor_IRQn                 = -4,   /*!<  12  Debug Monitor                    */
-  PendSV_IRQn                       = -2,   /*!<  14  Pendable request for system service */
-  SysTick_IRQn                      = -1,   /*!<  15  System Tick Timer                */
-// ----------------------------  LPC13Uxx Specific Interrupt Numbers  --------------------------------
-  PIN_INT0_IRQn                     = 0,    /*!<   0  PIN_INT0                         */
-  PIN_INT1_IRQn                     = 1,    /*!<   1  PIN_INT1                         */
-  PIN_INT2_IRQn                     = 2,    /*!<   2  PIN_INT2                         */
-  PIN_INT3_IRQn                     = 3,    /*!<   3  PIN_INT3                         */
-  PIN_INT4_IRQn                     = 4,    /*!<   4  PIN_INT4                         */
-  PIN_INT5_IRQn                     = 5,    /*!<   5  PIN_INT5                         */
-  PIN_INT6_IRQn                     = 6,    /*!<   6  PIN_INT6                         */
-  PIN_INT7_IRQn                     = 7,    /*!<   7  PIN_INT7                         */
-  GINT0_IRQn                        = 8,    /*!<   8  GINT0                            */
-  GINT1_IRQn                        = 9,    /*!<   9  GINT1                            */
-  Reserved0_IRQn                    = 10,   /*!<  10  Reserved Interrupt               */
-  Reserved1_IRQn                    = 11,   /*!<  11  Reserved Interrupt               */
-  RIT_IRQn                          = 12,   /*!<  12  Repetitive Interrupt Timer       */
-  Reserved2_IRQn                    = 13,   /*!<  13  Reserved Interrupt               */
-  SSP1_IRQn                         = 14,   /*!<  14  SSP1                             */
-  I2C_IRQn                          = 15,   /*!<  15  I2C                              */
-  CT16B0_IRQn                       = 16,   /*!<  16  CT16B0                           */
-  CT16B1_IRQn                       = 17,   /*!<  17  CT16B1                           */
-  CT32B0_IRQn                       = 18,   /*!<  18  CT32B0                           */
-  CT32B1_IRQn                       = 19,   /*!<  19  CT32B1                           */
-  SSP0_IRQn                         = 20,   /*!<  20  SSP0                             */
-  USART_IRQn                        = 21,   /*!<  21  USART                            */
-  USB_IRQ_IRQn                      = 22,   /*!<  22  USB_IRQ                          */
-  USB_FIQ_IRQn                      = 23,   /*!<  23  USB_FIQ                          */
-  ADC_IRQn                          = 24,   /*!<  24  ADC                              */
-  WDT_IRQn                          = 25,   /*!<  25  WDT                              */
-  BOD_IRQn                          = 26,   /*!<  26  BOD                              */
-  FMC_IRQn                          = 27,   /*!<  27  FMC                              */
-  Reserved3_IRQn                    = 28,   /*!<  28  Reserved Interrupt               */
-  Reserved4_IRQn                    = 29,   /*!<  29  Reserved Interrupt               */
-  USBWAKEUP_IRQn                    = 30,   /*!<  30  USBWAKEUP                        */
-  Reserved5_IRQn                    = 31,   /*!<  31  Reserved Interrupt               */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
-
-#define __CM3_REV              0x0000       /*!< Cortex-M3 Core Revision               */
-#define __MPU_PRESENT             0         /*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include <core_cm3.h>                       /*!< Cortex-M3 processor and core peripherals */
-#include "system_LPC13Uxx.h"                /*!< LPC13Uxx System                          */
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          I2C                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-
-typedef struct {                            /*!< (@ 0x40000000) I2C Structure          */
-  __IO uint32_t CONSET;                     /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-  __I  uint32_t STAT;                       /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
-  __IO uint32_t DAT;                        /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
-  __IO uint32_t ADR0;                       /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  __IO uint32_t SCLH;                       /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
-  __IO uint32_t SCLL;                       /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
-  __O  uint32_t CONCLR;                     /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
-  __IO uint32_t MMCTRL;                     /*!< (@ 0x4000001C) Monitor mode control register. */
-  union{
-  __IO uint32_t ADR[3];                     /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
-  struct{
-  __IO uint32_t ADR1;
-  __IO uint32_t ADR2;
-  __IO uint32_t ADR3;
-  };
-  };
-  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
-  union{
-  __IO uint32_t MASK[4];                    /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
-  struct{
-  __IO uint32_t MASK0;
-  __IO uint32_t MASK1;
-  __IO uint32_t MASK2;
-  __IO uint32_t MASK3;
-  };
-  };
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         WWDT                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-typedef struct {                            /*!< (@ 0x40004000) WWDT Structure         */
-  __IO uint32_t MOD;                        /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
-  __IO uint32_t TC;                         /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
-  __O  uint32_t FEED;                       /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
-  __I  uint32_t TV;                         /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
-  __IO uint32_t CLKSEL;                     /*!< (@ 0x40004010) Watchdog clock select register. */
-  __IO uint32_t WARNINT;                    /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
-  __IO uint32_t WINDOW;                     /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         USART                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-typedef struct {                            /*!< (@ 0x40008000) USART Structure        */
-  
-  union {
-    __IO uint32_t DLL;                      /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-    __O  uint32_t THR;                      /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
-    __I  uint32_t RBR;                      /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
-  };
-  
-  union {
-    __IO uint32_t IER;                      /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
-    __IO uint32_t DLM;                      /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-  };
-  
-  union {
-    __O  uint32_t FCR;                      /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
-    __I  uint32_t IIR;                      /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  };
-  __IO uint32_t LCR;                        /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40008010) Modem Control Register. */
-  __I  uint32_t LSR;                        /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t MSR;                        /*!< (@ 0x40008018) Modem Status Register. */
-  __IO uint32_t SCR;                        /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
-  __IO uint32_t ACR;                        /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __IO uint32_t ICR;                        /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
-  __IO uint32_t FDR;                        /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __IO uint32_t OSR;                        /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
-  __IO uint32_t TER;                        /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
-  __I  uint32_t RESERVED0[3];
-  __IO uint32_t HDEN;                       /*!< (@ 0x40008040) Half duplex enable register. */
-  __I  uint32_t RESERVED1;
-  __IO uint32_t SCICTRL;                    /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
-  __IO uint32_t RS485CTRL;                  /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-  __IO uint32_t RS485DLY;                   /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
-  __IO uint32_t SYNCCTRL;                   /*!< (@ 0x40008058) Synchronous mode control register. */
-} LPC_USART_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        CT16B0                                        -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x4000C000) CT16B0 Structure       */
-  __IO uint32_t IR;                         /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-  __IO uint32_t TCR;                        /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-  __IO uint32_t TC;                         /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-  __IO uint32_t PR;                         /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-  __IO uint32_t PC;                         /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-  __IO uint32_t MCR;                        /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x4000C018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x4000C01C) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x4000C020) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x4000C024) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
-    struct{
-  __I  uint32_t CR0;			            /*!< (@ 0x4000C02C) Capture Register. CR 0 */
-  __I  uint32_t CR1;			            /*!< (@ 0x4000C030) Capture Register. CR 1 */
-  __I  uint32_t CR2;			            /*!< (@ 0x4000C034) Capture Register. CR 2 */
-  __I  uint32_t CR3;			            /*!< (@ 0x4000C038) Capture Register. CR 3 */
-  };
-  };
-  __IO uint32_t EMR;                        /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins  */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-  __IO uint32_t PWMC;                       /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
-} LPC_CT16B0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        CT16B1                                        -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x40010000) CT16B1 Structure       */
-  __IO uint32_t IR;                         /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-  __IO uint32_t TCR;                        /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-  __IO uint32_t TC;                         /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-  __IO uint32_t PR;                         /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-  __IO uint32_t PC;                         /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x40010018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x4001001C) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x40010020) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x40010024) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
-    struct{
-  __I  uint32_t CR0;			            /*!< (@ 0x4001002C) Capture Register. CR 0 */
-  __I  uint32_t CR1;			            /*!< (@ 0x40010030) Capture Register. CR 1 */
-  __I  uint32_t CR2;			            /*!< (@ 0x40010034) Capture Register. CR 2 */
-  __I  uint32_t CR3;			            /*!< (@ 0x40010038) Capture Register. CR 3 */
-  };
-  };
-  __IO uint32_t EMR;                        /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins  */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-  __IO uint32_t PWMC;                       /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
-} LPC_CT16B1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        CT32B0                                        -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x40014000) CT32B0 Structure       */
-  __IO uint32_t IR;                         /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-  __IO uint32_t TCR;                        /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-  __IO uint32_t TC;                         /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-  __IO uint32_t PR;                         /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-  __IO uint32_t PC;                         /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x40014018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x4001401C) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x40014020) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x40014024) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
-    struct{
-  __I  uint32_t CR0;			            /*!< (@ 0x4001402C) Capture Register. CR 0 */
-  __I  uint32_t CR1;			            /*!< (@ 0x40014030) Capture Register. CR 1 */
-  __I  uint32_t CR2;			            /*!< (@ 0x40014034) Capture Register. CR 2 */
-  __I  uint32_t CR3;			            /*!< (@ 0x40014038) Capture Register. CR 3 */
-  };
-  };
-  __IO uint32_t EMR;                        /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-  __IO uint32_t PWMC;                       /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
-} LPC_CT32B0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        CT32B1                                        -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x40018000) CT32B1 Structure       */
-  __IO uint32_t IR;                         /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-  __IO uint32_t TCR;                        /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-  __IO uint32_t TC;                         /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
-  __IO uint32_t PR;                         /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
-  __IO uint32_t PC;                         /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x40018018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x4001801C) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x40018020) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x40018024) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
-    struct{
-  __I  uint32_t CR0;			            /*!< (@ 0x4001802C) Capture Register. CR 0 */
-  __I  uint32_t CR1;			            /*!< (@ 0x40018030) Capture Register. CR 1 */
-  __I  uint32_t CR2;			            /*!< (@ 0x40018034) Capture Register. CR 2 */
-  __I  uint32_t CR3;			            /*!< (@ 0x40018038) Capture Register. CR 3 */
-  };
-  };
-  __IO uint32_t EMR;                        /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-  __IO uint32_t PWMC;                       /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
-} LPC_CT32B1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          ADC                                         -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x4001C000) ADC Structure          */
-  __IO uint32_t CR;                         /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
-  __IO uint32_t GDR;                        /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
-  __I  uint32_t RESERVED0[1];
-  __IO uint32_t INTEN;                      /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
-  union{
-  __I  uint32_t DR[8];                      /*!< (@ 0x4001C010) A/D Channel Data Register*/
-    struct{
-  __I  uint32_t DR0;                      	/*!< (@ 0x4001C010) A/D Channel Data Register 0*/
-  __I  uint32_t DR1;                      	/*!< (@ 0x4001C014) A/D Channel Data Register 1*/
-  __I  uint32_t DR2;                      	/*!< (@ 0x4001C018) A/D Channel Data Register 2*/
-  __I  uint32_t DR3;                      	/*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
-  __I  uint32_t DR4;                      	/*!< (@ 0x4001C020) A/D Channel Data Register 4*/
-  __I  uint32_t DR5;                      	/*!< (@ 0x4001C024) A/D Channel Data Register 5*/
-  __I  uint32_t DR6;                      	/*!< (@ 0x4001C028) A/D Channel Data Register 6*/
-  __I  uint32_t DR7;                      	/*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
-  };
-  };
-  __I  uint32_t STAT;                       /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          PMU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x40038000) PMU Structure          */
-  __IO uint32_t PCON;                       /*!< (@ 0x40038000) Power control register */
-  union{
-  __IO uint32_t GPREG[4];                   /*!< (@ 0x40038004) General purpose register 0 */
-  struct{
-  __IO uint32_t GPREG0;                   	/*!< (@ 0x40038004) General purpose register 0 */
-  __IO uint32_t GPREG1;                   	/*!< (@ 0x40038008) General purpose register 1 */
-  __IO uint32_t GPREG2;                   	/*!< (@ 0x4003800C) General purpose register 2 */
-  __IO uint32_t GPREG3;                   	/*!< (@ 0x40038010) General purpose register 3 */
-  };
-  };
-  __IO uint32_t GPREG4;                     /*!< (@ 0x40038014) General purpose register 4 */
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       FLASHCTRL                                      -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x4003C000) FLASHCTRL Structure    */
-  __I  uint32_t RESERVED0[4];
-  __IO uint32_t FLASHCFG;                   /*!< (@ 0x4003C010) Flash memory access time configuration register */
-  __I  uint32_t RESERVED1[3];
-  __IO uint32_t FMSSTART;                   /*!< (@ 0x4003C020) Signature start address register */
-  __IO uint32_t FMSSTOP;                    /*!< (@ 0x4003C024) Signature stop-address register */
-  __I  uint32_t RESERVED2[1];
-  __I  uint32_t FMSW0;                      /*!< (@ 0x4003C02C) Word 0 [31:0]          */
-  __I  uint32_t FMSW1;                      /*!< (@ 0x4003C030) Word 1 [63:32]         */
-  __I  uint32_t FMSW2;                      /*!< (@ 0x4003C034) Word 2 [95:64]         */
-  __I  uint32_t FMSW3;                      /*!< (@ 0x4003C038) Word 3 [127:96]        */
-  __I  uint32_t RESERVED3[1001];
-  __I  uint32_t FMSTAT;                     /*!< (@ 0x4003CFE0) Signature generation status register */
-  __I  uint32_t RESERVED4[1];
-  __O  uint32_t FMSTATCLR;                  /*!< (@ 0x4003CFE8) Signature generation status clear register */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SSP0                                         -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x40040000) SSP0 Structure         */
-  __IO uint32_t CR0;                        /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
-  __IO uint32_t CR1;                        /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
-  __IO uint32_t DR;                         /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-  __I  uint32_t SR;                         /*!< (@ 0x4004000C) Status Register        */
-  __IO uint32_t CPSR;                       /*!< (@ 0x40040010) Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                        /*!< (@ 0x40040018) Raw Interrupt Status Register */
-  __I  uint32_t MIS;                        /*!< (@ 0x4004001C) Masked Interrupt Status Register */
-  __O  uint32_t ICR;                        /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-} LPC_SSP0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         IOCON                                        -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x40044000) IOCON Structure        */
-  __IO uint32_t RESET_PIO0_0;               /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
-  __IO uint32_t PIO0_1;                     /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
-  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
-  __IO uint32_t PIO0_3;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
-  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
-  __IO uint32_t PIO0_5;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
-  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
-  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
-  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
-  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
-  __IO uint32_t SWCLK_PIO0_10;              /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
-  __IO uint32_t TDI_PIO0_11;                /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
-  __IO uint32_t TMS_PIO0_12;                /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
-  __IO uint32_t TDO_PIO0_13;                /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
-  __IO uint32_t TRST_PIO0_14;               /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
-  __IO uint32_t SWDIO_PIO0_15;              /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
-  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
-  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
-  __IO uint32_t PIO0_18;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
-  __IO uint32_t PIO0_19;                    /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
-  __IO uint32_t PIO0_20;                    /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
-  __IO uint32_t PIO0_21;                    /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
-  __IO uint32_t PIO0_22;                    /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
-  __IO uint32_t PIO0_23;                    /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
-  __IO uint32_t PIO1_0;                     /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
-  __IO uint32_t PIO1_1;                     /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
-  __IO uint32_t PIO1_2;                     /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
-  __IO uint32_t PIO1_3;                     /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
-  __IO uint32_t PIO1_4;                     /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
-  __IO uint32_t PIO1_5;                     /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
-  __IO uint32_t PIO1_6;                     /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
-  __IO uint32_t PIO1_7;                     /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
-  __IO uint32_t PIO1_8;                     /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
-  __IO uint32_t PIO1_9;                     /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
-  __IO uint32_t PIO1_10;                    /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
-  __IO uint32_t PIO1_11;                    /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
-  __IO uint32_t PIO1_12;                    /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
-  __IO uint32_t PIO1_13;                    /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
-  __IO uint32_t PIO1_14;                    /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
-  __IO uint32_t PIO1_15;                    /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
-  __IO uint32_t PIO1_16;                    /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
-  __IO uint32_t PIO1_17;                    /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
-  __IO uint32_t PIO1_18;                    /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
-  __IO uint32_t PIO1_19;                    /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
-  __IO uint32_t PIO1_20;                    /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
-  __IO uint32_t PIO1_21;                    /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
-  __IO uint32_t PIO1_22;                    /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
-  __IO uint32_t PIO1_23;                    /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
-  __IO uint32_t PIO1_24;                    /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
-  __IO uint32_t PIO1_25;                    /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
-  __IO uint32_t PIO1_26;                    /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
-  __IO uint32_t PIO1_27;                    /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
-  __IO uint32_t PIO1_28;                    /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
-  __IO uint32_t PIO1_29;                    /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
-  __IO uint32_t PIO1_30;                    /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
-  __IO uint32_t PIO1_31;                    /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        SYSCON                                        -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x40048000) SYSCON Structure       */
-  __IO uint32_t SYSMEMREMAP;                /*!< (@ 0x40048000) System memory remap    */
-  __IO uint32_t PRESETCTRL;                 /*!< (@ 0x40048004) Peripheral reset control */
-  __IO uint32_t SYSPLLCTRL;                 /*!< (@ 0x40048008) System PLL control     */
-  __I  uint32_t SYSPLLSTAT;                 /*!< (@ 0x4004800C) System PLL status      */
-  __IO uint32_t USBPLLCTRL;                 /*!< (@ 0x40048010) USB PLL control        */
-  __I  uint32_t USBPLLSTAT;                 /*!< (@ 0x40048014) USB PLL status         */
-  __I  uint32_t RESERVED0[2];
-  __IO uint32_t SYSOSCCTRL;                 /*!< (@ 0x40048020) System oscillator control */
-  __IO uint32_t WDTOSCCTRL;                 /*!< (@ 0x40048024) Watchdog oscillator control */
-  __I  uint32_t RESERVED1[2];
-  __IO uint32_t SYSRSTSTAT;                 /*!< (@ 0x40048030) System reset status register */
-  __I  uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;               /*!< (@ 0x40048040) System PLL clock source select */
-  __I  uint32_t RESERVED3;
-  __IO uint32_t USBPLLCLKSEL;               /*!< (@ 0x40048048) USB PLL clock source select */
-  __I  uint32_t RESERVED4[9];
-  __IO uint32_t MAINCLKSEL;                 /*!< (@ 0x40048070) Main clock source select */
-  __I  uint32_t RESERVED5;
-  __IO uint32_t SYSAHBCLKDIV;               /*!< (@ 0x40048078) System clock divider   */
-  __I  uint32_t RESERVED6;
-  __IO uint32_t SYSAHBCLKCTRL;              /*!< (@ 0x40048080) System clock control   */
-  __I  uint32_t RESERVED7[4];
-  __IO uint32_t SSP0CLKDIV;                 /*!< (@ 0x40048094) SSP0 clock divider     */
-  __IO uint32_t UARTCLKDIV;                 /*!< (@ 0x40048098) UART clock divider     */
-  __IO uint32_t SSP1CLKDIV;                 /*!< (@ 0x4004809C) SSP1 clock divider     */
-  __I  uint32_t RESERVED8[3];
-  __IO uint32_t TRACECLKDIV;                /*!< (@ 0x400480AC) ARM trace clock divider */
-  __IO uint32_t SYSTICKCLKDIV;              /*!< (@ 0x400480B0) SYSTICK clock divder   */
-  __I  uint32_t RESERVED9[3];
-  __IO uint32_t USBCLKSEL;                  /*!< (@ 0x400480C0) USB clock source select */
-  __I  uint32_t RESERVED10;
-  __IO uint32_t USBCLKDIV;                  /*!< (@ 0x400480C8) USB clock source divider */
-  __I  uint32_t RESERVED11[5];
-  __IO uint32_t CLKOUTSEL;                  /*!< (@ 0x400480E0) CLKOUT clock source select */
-  __I  uint32_t RESERVED12;
-  __IO uint32_t CLKOUTDIV;                  /*!< (@ 0x400480E8) CLKOUT clock divider   */
-  __I  uint32_t RESERVED13[5];
-  __I  uint32_t PIOPORCAP0;                 /*!< (@ 0x40048100) POR captured PIO status 0 */
-  __I  uint32_t PIOPORCAP1;                 /*!< (@ 0x40048104) POR captured PIO status 1 */
-  __I  uint32_t RESERVED14[18];
-  __IO uint32_t BODCTRL;                    /*!< (@ 0x40048150) Brown-Out Detect       */
-  __IO uint32_t SYSTCKCAL;                  /*!< (@ 0x40048154) System tick counter calibration */
-  __I  uint32_t RESERVED15[6];
-  __IO uint32_t IRQLATENCY;                 /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
-  __IO uint32_t NMISRC;                     /*!< (@ 0x40048174) NMI Source Control     */
-  __IO uint32_t PINSEL[8];                  /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
-  __IO uint32_t USBCLKCTRL;                 /*!< (@ 0x40048198) USB clock control      */
-  __I  uint32_t USBCLKST;                   /*!< (@ 0x4004819C) USB clock status       */
-  __I  uint32_t RESERVED16[25];
-  __IO uint32_t STARTERP0;                  /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
-  __I  uint32_t RESERVED17[3];
-  __IO uint32_t STARTERP1;                  /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
-  __I  uint32_t RESERVED18[6];
-  __IO uint32_t PDSLEEPCFG;                 /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
-  __IO uint32_t PDAWAKECFG;                 /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
-  __IO uint32_t PDRUNCFG;                   /*!< (@ 0x40048238) Power configuration register */
-  __I  uint32_t RESERVED19[111];
-  __I  uint32_t DEVICE_ID;                  /*!< (@ 0x400483F8) Device ID              */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                     GPIO_PIN_INT                                     -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
-  __IO uint32_t ISEL;                       /*!< (@ 0x4004C000) Pin Interrupt Mode register */
-  __IO uint32_t IENR;                       /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
-  __O  uint32_t SIENR;                      /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
-  __O  uint32_t CIENR;                      /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
-  __IO uint32_t IENF;                       /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
-  __O  uint32_t SIENF;                      /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
-  __O  uint32_t CIENF;                      /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
-  __IO uint32_t RISE;                       /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
-  __IO uint32_t FALL;                       /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
-  __IO uint32_t IST;                        /*!< (@ 0x4004C024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SSP1                                         -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x40058000) SSP1 Structure         */
-  __IO uint32_t CR0;                        /*!< (@ 0x40058000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
-  __IO uint32_t CR1;                        /*!< (@ 0x40058004) Control Register 1. Selects master/slave and other modes. */
-  __IO uint32_t DR;                         /*!< (@ 0x40058008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-  __I  uint32_t SR;                         /*!< (@ 0x4005800C) Status Register        */
-  __IO uint32_t CPSR;                       /*!< (@ 0x40058010) Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< (@ 0x40058014) Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                        /*!< (@ 0x40058018) Raw Interrupt Status Register */
-  __I  uint32_t MIS;                        /*!< (@ 0x4005801C) Masked Interrupt Status Register */
-  __O  uint32_t ICR;                        /*!< (@ 0x40058020) SSPICR Interrupt Clear Register */
-} LPC_SSP1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                    GPIO_GROUP_INT0                                   -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
-  __IO uint32_t CTRL;                       /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
-  __I  uint32_t RESERVED0[7];
-  __IO uint32_t PORT_POL[2];                /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
-  __I  uint32_t RESERVED1[6];
-  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INT0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                    GPIO_GROUP_INT1                                   -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
-  __IO uint32_t CTRL;                       /*!< (@ 0x40060000) GPIO grouped interrupt control register */
-  __I  uint32_t RESERVED0[7];
-  __IO uint32_t PORT_POL[2];                /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
-  __I  uint32_t RESERVED1[6];
-  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INT1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                          Repetitive Interrupt Timer (RIT)                            -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x40064000) RITIMER Structure */
-  __IO uint32_t COMPVAL;                    /*!< (@ 0x40064000) RITIMER compare register */
-  __IO uint32_t MASK;                       /*!< (@ 0x40064004) RITIMER mask register */
-  __IO uint32_t CTRL;                       /*!< (@ 0x40064008) RITIMER control register */
-  __IO uint32_t COUNTER;                    /*!< (@ 0x4006400C) RITIMER counter register */
-  __IO uint32_t COMPVAL_H;                  /*!< (@ 0x40064010) RITIMER compare upper register */
-  __IO uint32_t MASK_H;                     /*!< (@ 0x40064014) RITIMER mask upper register */
-  __I  uint32_t RESERVED0[1];
-  __IO uint32_t COUNTER_H;                  /*!< (@ 0x4006401C) RITIMER counter upper register */
-} LPC_RITIMER_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          USB                                         -----
-// ------------------------------------------------------------------------------------------------
-typedef struct {                            /*!< (@ 0x40020000) USB Structure          */
-  __IO uint32_t DEVCMDSTAT;                 /*!< (@ 0x40020000) USB Device Command/Status register */
-  __IO uint32_t INFO;                       /*!< (@ 0x40020004) USB Info register      */
-  __IO uint32_t EPLISTSTART;                /*!< (@ 0x40020008) USB EP Command/Status List start address */
-  __IO uint32_t DATABUFSTART;               /*!< (@ 0x4002000C) USB Data buffer start address */
-  __IO uint32_t LPM;                        /*!< (@ 0x40020010) Link Power Management register */
-  __IO uint32_t EPSKIP;                     /*!< (@ 0x40020014) USB Endpoint skip      */
-  __IO uint32_t EPINUSE;                    /*!< (@ 0x40020018) USB Endpoint Buffer in use */
-  __IO uint32_t EPBUFCFG;                   /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
-  __IO uint32_t INTSTAT;                    /*!< (@ 0x40020020) USB interrupt status register */
-  __IO uint32_t INTEN;                      /*!< (@ 0x40020024) USB interrupt enable register */
-  __IO uint32_t INTSETSTAT;                 /*!< (@ 0x40020028) USB set interrupt status register */
-  __IO uint32_t INTROUTING;                 /*!< (@ 0x4002002C) USB interrupt routing register */
-  __I  uint32_t RESERVED0[1];
-  __I  uint32_t EPTOGGLE;                   /*!< (@ 0x40020034) USB Endpoint toggle register */
-} LPC_USB_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       GPIO_PORT                                      -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct {                            /*!< (@ 0x50000000) GPIO_PORT Structure    */
-  union {
-    struct {
-      __IO uint8_t B0[32];                  /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
-      __IO uint8_t B1[32];                  /*!< (@ 0x50000020) Byte pin registers port 1 */
-    };
-    __IO uint8_t B[64];                     /*!< (@ 0x50000000) Byte pin registers port 0/1 */
-  };
-  __I  uint32_t RESERVED0[1008];
-  union {
-    struct {
-      __IO uint32_t W0[32];                 /*!< (@ 0x50001000) Word pin registers port 0 */
-      __IO uint32_t W1[32];                 /*!< (@ 0x50001080) Word pin registers port 1 */
-    };
-    __IO uint32_t W[64];                    /*!< (@ 0x50001000) Word pin registers port 0/1 */
-  };
-  __I  uint32_t RESERVED1[960];
-  __IO uint32_t DIR[2];                     /*!< (@ 0x50002000) Direction registers port 0/1 */
-  __I  uint32_t RESERVED2[30];
-  __IO uint32_t MASK[2];                    /*!< (@ 0x50002080) Mask register port 0/1 */
-  __I  uint32_t RESERVED3[30];
-  __IO uint32_t PIN[2];                     /*!< (@ 0x50002100) Portpin register port 0 */
-  __I  uint32_t RESERVED4[30];
-  __IO uint32_t MPIN[2];                    /*!< (@ 0x50002180) Masked port register port 0/1 */
-  __I  uint32_t RESERVED5[30];
-  __IO uint32_t SET[2];                     /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
-  __I  uint32_t RESERVED6[30];
-  __O  uint32_t CLR[2];                     /*!< (@ 0x50002280) Clear port 0/1         */
-  __I  uint32_t RESERVED7[30];
-  __O  uint32_t NOT[2];                     /*!< (@ 0x50002300) Toggle port 0/1        */
-} LPC_GPIO_Type;
-
-
-#if defined ( __CC_ARM   )
-  #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 Peripheral memory map                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE              (0x40000000)
-#define LPC_WWDT_BASE             (0x40004000)
-#define LPC_USART_BASE            (0x40008000)
-#define LPC_CT16B0_BASE           (0x4000C000)
-#define LPC_CT16B1_BASE           (0x40010000)
-#define LPC_CT32B0_BASE           (0x40014000)
-#define LPC_CT32B1_BASE           (0x40018000)
-#define LPC_ADC_BASE              (0x4001C000)
-#define LPC_PMU_BASE              (0x40038000)
-#define LPC_FLASHCTRL_BASE        (0x4003C000)
-#define LPC_SSP0_BASE             (0x40040000)
-#define LPC_IOCON_BASE            (0x40044000)
-#define LPC_SYSCON_BASE           (0x40048000)
-#define LPC_GPIO_PIN_INT_BASE     (0x4004C000)
-#define LPC_SSP1_BASE             (0x40058000)
-#define LPC_GPIO_GROUP_INT0_BASE  (0x4005C000)
-#define LPC_GPIO_GROUP_INT1_BASE  (0x40060000)
-#define LPC_RITIMER_BASE          (0x40064000)
-#define LPC_USB_BASE              (0x40080000)
-#define LPC_GPIO_BASE             (0x50000000)
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                Peripheral declaration                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C                   ((LPC_I2C_Type            *) LPC_I2C_BASE)
-#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
-#define LPC_USART                 ((LPC_USART_Type          *) LPC_USART_BASE)
-#define LPC_CT16B0                ((LPC_CT16B0_Type         *) LPC_CT16B0_BASE)
-#define LPC_CT16B1                ((LPC_CT16B1_Type         *) LPC_CT16B1_BASE)
-#define LPC_CT32B0                ((LPC_CT32B0_Type         *) LPC_CT32B0_BASE)
-#define LPC_CT32B1                ((LPC_CT32B1_Type         *) LPC_CT32B1_BASE)
-#define LPC_ADC                   ((LPC_ADC_Type            *) LPC_ADC_BASE)
-#define LPC_PMU                   ((LPC_PMU_Type            *) LPC_PMU_BASE)
-#define LPC_FLASHCTRL             ((LPC_FLASHCTRL_Type      *) LPC_FLASHCTRL_BASE)
-#define LPC_SSP0                  ((LPC_SSP0_Type           *) LPC_SSP0_BASE)
-#define LPC_SSP1                  ((LPC_SSP1_Type           *) LPC_SSP1_BASE)
-#define LPC_IOCON                 ((LPC_IOCON_Type          *) LPC_IOCON_BASE)
-#define LPC_SYSCON                ((LPC_SYSCON_Type         *) LPC_SYSCON_BASE)
-#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
-#define LPC_USB                   ((LPC_USB_Type            *) LPC_USB_BASE)
-#define LPC_GPIO                  ((LPC_GPIO_Type           *) LPC_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group h1usf */
-
-#ifdef __cplusplus
-}
-#endif 
-
-
-#endif  // __LPC13UXX_H__
diff --git a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/power_api.h b/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/power_api.h
deleted file mode 100644
index f95021774..000000000
--- a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/power_api.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/****************************************************************************
- *   $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267                   $
- *   Project: NXP LPC13Uxx software example  
- *
- *   Description:
- *     Power API Header File for NXP LPC13Uxx Device Series 
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __LPC13UXX_POWER_API_H__
-#define __LPC13UXX_POWER_API_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define PWRROMD_PRESENT
-
-#define USBROMD_PRESENT
-
-#ifdef USBROMD_PRESENT
-#include "mw_usbd_rom_api.h"
-#endif
-
-typedef	struct _PWRD {
-  void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
-  void (*set_power)(unsigned int cmd[], unsigned int resp[]);
-}  PWRD;
-
-typedef	struct _ROM {
-#ifdef USBROMD_PRESENT
-   const USBD_API_T * pUSBD;
-#else
-   const unsigned p_usbd;
-#endif /* USBROMD_PRESENT */
-   const unsigned p_clib;
-   const unsigned p_cand;
-#ifdef PWRROMD_PRESENT
-   const PWRD * pPWRD;
-#else
-   const unsigned p_pwrd;
-#endif /* PWRROMD_PRESENT */
-   const unsigned p_dev1;
-   const unsigned p_dev2;
-   const unsigned p_dev3;
-   const unsigned p_dev4; 
-}  ROM;
-
-//PLL setup related definitions
-#define	CPU_FREQ_EQU  		0       //main PLL freq must be equal to the specified 
-#define	CPU_FREQ_LTE		1       //main PLL freq must be less than or equal the specified
-#define	CPU_FREQ_GTE		2       //main PLL freq must be greater than or equal the specified
-#define	CPU_FREQ_APPROX		3       //main PLL freq must be as close as possible the specified
-
-#define	PLL_CMD_SUCCESS		0       //PLL setup successfully found
-#define	PLL_INVALID_FREQ	1       //specified freq out of range (either input or output)
-#define	PLL_INVALID_MODE	2       //invalid mode (see above for valid) specified
-#define	PLL_FREQ_NOT_FOUND	3       //specified freq not found under specified conditions
-#define	PLL_NOT_LOCKED		4       //PLL not locked => no changes to the PLL setup
-
-//power setup elated definitions
-#define	PARAM_DEFAULT			0   //default power settings (voltage regulator, flash interface)
-#define	PARAM_CPU_PERFORMANCE	1   //setup for maximum CPU performance (higher current, more computation)
-#define	PARAM_EFFICIENCY		2   //balanced setting (power vs CPU performance)
-#define	PARAM_LOW_CURRENT		3   //lowest active current, lowest CPU performance
-
-#define	PARAM_CMD_SUCCESS		0   //power setting successfully found
-#define	PARAM_INVALID_FREQ		1   //specified freq out of range (=0 or > 50 MHz)
-#define	PARAM_INVALID_MODE		2   //specified mode not valid (see above for valid)
-
-#define MAX_CLOCK_KHZ_PARAM                50000
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC13UXX_POWER_API_H__ */
-
diff --git a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h b/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h
deleted file mode 100644
index 615a5e23c..000000000
--- a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/inc/system_LPC13Uxx.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC13Uxx.h
- * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- *           for the NXP LPC13Uxx Device Series
- * @version  V1.10
- * @date     24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC13Uxx_H
-#define __SYSTEM_LPC13Uxx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC13Uxx_H */
diff --git a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/liblinks.xml b/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/liblinks.xml
deleted file mode 100644
index 80eb9b85d..000000000
--- a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/liblinks.xml
+++ /dev/null
@@ -1,32 +0,0 @@
-<!-- liblinks.xml
-
-     LPCXpresso "Smart update wizard" script file
-     When executed on a particular application project, will
-     add appropriate links to the specified library project.
-
-     Note that this script assumes that the application project
-     contains the standard 'Debug' and 'Release' build 
-     configurations.
--->
-
-<project name="" update="true">
-	<setting id="all.compiler.inc">
-		<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/inc}</value>
-        </setting>
-    <setting id="all.compiler.def">
-		<value>__USE_CMSIS=CMSIS_CORE_LPC13Uxx</value>
-    </setting>
-	<setting id="linker.libs">
-		<value>CMSIS_CORE_LPC13Uxx</value>
-	</setting>
-	<setting id="linker.paths" buildType="Debug">
-		<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Debug}</value>
-	</setting>
-	<setting id="linker.paths" buildType="Release">
-		<value>${workspace_loc:/CMSIS_CORE_LPC13Uxx/Release}</value>
-	</setting>
-	<requires msg="Library project `CMSIS_CORE_LPC13Uxx` not found">
-		<value>CMSIS_CORE_LPC13Uxx</value>
-	</requires>
-</project>
-
diff --git a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c b/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c
deleted file mode 100644
index fbdef8a92..000000000
--- a/hw/mcu/nxp/lpc13xx/CMSIS_CORE_LPC13Uxx/src/system_LPC13Uxx.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/******************************************************************************
- * @file     system_LPC13Uxx.c
- * @purpose  CMSIS Cortex-M3 Device Peripheral Access Layer Source File
- *           for the NXP LPC13xx Device Series
- * @version  V1.10
- * @date     24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-#include "LPC13Uxx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Oscillator Control Register (SYSOSCCTRL)
-//     <o1.0>      BYPASS: System Oscillator Bypass Enable
-//                     <i> If enabled then PLL input (sys_osc_clk) is fed
-//                     <i> directly from XTALIN and XTALOUT pins.
-//     <o1.9>      FREQRANGE: System Oscillator Frequency Range
-//                     <i> Determines frequency range for Low-power oscillator.
-//                   <0=> 1 - 20 MHz
-//                   <1=> 15 - 25 MHz
-//   </h>
-//
-//   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
-//     <o2.0..4>   DIVSEL: Select Divider for Fclkana
-//                     <i> wdt_osc_clk = Fclkana/ (2 � (1 + DIVSEL))
-//                   <0-31>
-//     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
-//                   <0=> Undefined
-//                   <1=> 0.5 MHz
-//                   <2=> 0.8 MHz
-//                   <3=> 1.1 MHz
-//                   <4=> 1.4 MHz
-//                   <5=> 1.6 MHz
-//                   <6=> 1.8 MHz
-//                   <7=> 2.0 MHz
-//                   <8=> 2.2 MHz
-//                   <9=> 2.4 MHz
-//                   <10=> 2.6 MHz
-//                   <11=> 2.7 MHz
-//                   <12=> 2.9 MHz
-//                   <13=> 3.1 MHz
-//                   <14=> 3.2 MHz
-//                   <15=> 3.4 MHz
-//   </h>
-//
-//   <h> System PLL Control Register (SYSPLLCTRL)
-//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
-//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
-//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
-//     <o3.0..4>   MSEL: Feedback Divider Selection
-//                     <i> M = MSEL + 1
-//                   <0-31>
-//     <o3.5..6>   PSEL: Post Divider Selection
-//                   <0=> P = 1
-//                   <1=> P = 2
-//                   <2=> P = 4
-//                   <3=> P = 8
-//   </h>
-//
-//   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
-//     <o4.0..1>   SEL: System PLL Clock Source
-//                   <0=> IRC Oscillator
-//                   <1=> System Oscillator
-//                   <2=> Reserved
-//                   <3=> Reserved
-//   </h>
-//
-//   <h> Main Clock Source Select Register (MAINCLKSEL)
-//     <o5.0..1>   SEL: Clock Source for Main Clock
-//                   <0=> IRC Oscillator
-//                   <1=> Input Clock to System PLL
-//                   <2=> WDT Oscillator
-//                   <3=> System PLL Clock Out
-//   </h>
-//
-//   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
-//     <o6.0..7>   DIV: System AHB Clock Divider
-//                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
-//                     <i> 0 = is disabled
-//                   <0-255>
-//   </h>
-//
-//   <h> USB PLL Control Register (USBPLLCTRL)
-//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
-//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
-//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
-//     <o7.0..4>   MSEL: Feedback Divider Selection
-//                     <i> M = MSEL + 1
-//                   <0-31>
-//     <o7.5..6>   PSEL: Post Divider Selection
-//                   <0=> P = 1
-//                   <1=> P = 2
-//                   <2=> P = 4
-//                   <3=> P = 8
-//   </h>
-//
-//   <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
-//     <o8.0..1>   SEL: USB PLL Clock Source
-//                     <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
-//                   <0=> IRC Oscillator
-//                   <1=> System Oscillator
-//                   <2=> Reserved
-//                   <3=> Reserved
-//   </h>
-//
-//   <h> USB Clock Source Select Register (USBCLKSEL)
-//     <o9.0..1>   SEL: System PLL Clock Source
-//                   <0=> USB PLL out
-//                   <1=> Main clock
-//                   <2=> Reserved
-//                   <3=> Reserved
-//   </h>
-//
-//   <h> USB Clock Divider Register (USBCLKDIV)
-//     <o10.0..7>  DIV: USB Clock Divider
-//                     <i> Divides USB clock to 48 MHz.
-//                     <i> 0 = is disabled
-//                   <0-255>
-//   </h>
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define SYSPLLCTRL_Val        0x00000025              // Reset: 0x000
-#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
-#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
-#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
-#define USBPLLCTRL_Val        0x00000023              // Reset: 0x000
-#define USBPLLCLKSEL_Val      0x00000001              // Reset: 0x000
-#define USBCLKSEL_Val         0x00000000              // Reset: 0x000
-#define USBCLKDIV_Val         0x00000001              // Reset: 0x001
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
-   #error "SYSOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
-   #error "WDTOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
-   #error "SYSPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
-   #error "SYSPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
-   #error "MAINCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
-   #error "SYSAHBCLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
-   #error "USBPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((USBPLLCTRL_Val),  ~0x000001FF))
-   #error "USBPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
-   #error "USBCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
-   #error "USBCLKDIV: Value out of range!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-    
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define __XTAL            (12000000UL)    /* Oscillator frequency             */
-#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
-#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
-
-
-#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
-#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
-
-#if (CLOCK_SETUP)                         /* Clock Setup              */
-  #if  (__FREQSEL ==  0)
-    #define __WDT_OSC_CLK        ( 0)                  /* undefined */
-  #elif (__FREQSEL ==  1)
-    #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
-  #elif (__FREQSEL ==  2)
-    #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
-  #elif (__FREQSEL ==  3)
-    #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
-  #elif (__FREQSEL ==  4)
-    #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
-  #elif (__FREQSEL ==  5)
-    #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
-  #elif (__FREQSEL ==  6)
-    #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
-  #elif (__FREQSEL ==  7)
-    #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
-  #elif (__FREQSEL ==  8)
-    #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
-  #elif (__FREQSEL ==  9)
-    #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
-  #elif (__FREQSEL == 10)
-    #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
-  #elif (__FREQSEL == 11)
-    #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
-  #elif (__FREQSEL == 12)
-    #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
-  #elif (__FREQSEL == 13)
-    #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
-  #elif (__FREQSEL == 14)
-    #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
-  #else
-    #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
-  #endif
-
-  /* sys_pllclkin calculation */
-  #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
-    #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
-  #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
-    #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
-  #else
-    #define __SYS_PLLCLKIN           (0)
-  #endif
-
-  #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
-
-  /* main clock calculation */
-  #if   ((MAINCLKSEL_Val & 0x03) == 0)
-    #define __MAIN_CLOCK             (__IRC_OSC_CLK)
-  #elif ((MAINCLKSEL_Val & 0x03) == 1)
-    #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
-  #elif ((MAINCLKSEL_Val & 0x03) == 2)
-    #if (__FREQSEL ==  0)
-      #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
-    #else
-      #define __MAIN_CLOCK           (__WDT_OSC_CLK)
-    #endif
-  #elif ((MAINCLKSEL_Val & 0x03) == 3)
-    #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
-  #else
-    #define __MAIN_CLOCK             (0)
-  #endif
-
-  #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)         
-
-#else
-  #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
-#endif  // CLOCK_SETUP 
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  uint32_t wdt_osc = 0;
-
-  /* Determine clock frequency according to clock register values             */
-  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
-    case 0:  wdt_osc =       0; break;
-    case 1:  wdt_osc =  500000; break;
-    case 2:  wdt_osc =  800000; break;
-    case 3:  wdt_osc = 1100000; break;
-    case 4:  wdt_osc = 1400000; break;
-    case 5:  wdt_osc = 1600000; break;
-    case 6:  wdt_osc = 1800000; break;
-    case 7:  wdt_osc = 2000000; break;
-    case 8:  wdt_osc = 2200000; break;
-    case 9:  wdt_osc = 2400000; break;
-    case 10: wdt_osc = 2600000; break;
-    case 11: wdt_osc = 2700000; break;
-    case 12: wdt_osc = 2900000; break;
-    case 13: wdt_osc = 3100000; break;
-    case 14: wdt_osc = 3200000; break;
-    case 15: wdt_osc = 3400000; break;
-  }
-  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
- 
-  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
-    case 0:                             /* Internal RC oscillator             */
-      SystemCoreClock = __IRC_OSC_CLK;
-      break;
-    case 1:                             /* Input Clock to System PLL          */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK;
-            break;
-          case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK;
-            break;
-          case 2:                       /* Reserved                           */
-          case 3:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-      }
-      break;
-    case 2:                             /* WDT Oscillator                     */
-      SystemCoreClock = wdt_osc;
-      break;
-    case 3:                             /* System PLL Clock Out               */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = __IRC_OSC_CLK;
-            } else {
-              SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 1:                       /* System oscillator                  */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = __SYS_OSC_CLK;
-            } else {
-              SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 2:                       /* Reserved                           */
-          case 3:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-      }
-      break;
-  }
-
-  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;  
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void) {
-  volatile uint32_t i;
-
-#if (CLOCK_SETUP)                                 /* Clock Setup              */
-
-#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 5);          /* Power-up System Osc      */
-  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-
-  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
-#if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
-  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 7);          /* Power-up SYSPLL          */
-  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
-#endif
-
-#if (((MAINCLKSEL_Val & 0x03) == 2) )
-  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 6);          /* Power-up WDT Clock       */
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-
-  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
-
-  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
-
-#if ((USBCLKDIV_Val & 0x1FF) != 0)                /* USB clock is used        */
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 10);         /* Power-up USB PHY         */
-
-  /* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
-  LPC_SYSCON->PDRUNCFG     &= ~(1 <<  8);         /* Power-up USB PLL         */
-  LPC_SYSCON->USBPLLCLKSEL  = USBPLLCLKSEL_Val;   /* Select PLL Input         */
-  LPC_SYSCON->USBPLLCTRL    = USBPLLCTRL_Val;
-  while (!(LPC_SYSCON->USBPLLSTAT   & 0x01));     /* Wait Until PLL Locked    */
-
-  LPC_SYSCON->USBCLKSEL     = USBCLKSEL_Val;      /* Select USB Clock         */
-  LPC_SYSCON->USBCLKDIV     = USBCLKDIV_Val;      /* Set USB clock divider    */
-
-#else                                             /* USB clock is not used    */                        
-  LPC_SYSCON->PDRUNCFG     |=  (1 << 10);         /* Power-down USB PHY       */
-  LPC_SYSCON->PDRUNCFG     |=  (1 <<  8);         /* Power-down USB PLL       */
-#endif
-
-#endif
-
-  /* System clock to the IOCON needs to be enabled or
-  most of the I/O related peripherals won't work. */
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
-
-}
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/clkconfig.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/clkconfig.h
deleted file mode 100644
index 50876a097..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/clkconfig.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/****************************************************************************
- *   $Id:: clkconfig.h 6172 2011-01-13 18:22:51Z usb00423                   $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains definition and prototype for clock configuration.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __CLKCONFIG_H 
-#define __CLKCONFIG_H
-
-#define SYSPLL_SRC_IRC_OSC          0
-#define SYSPLL_SRC_SYS_OSC          1
-
-#define MAINCLK_SRC_IRC_OSC         0
-#define MAINCLK_SRC_SYSPLL_IN       1
-#define MAINCLK_SRC_WDT_OSC         2
-#define MAINCLK_SRC_SYS_PLL         3
-
-#define WDTCLK_SRC_IRC_OSC          0
-#define WDTCLK_SRC_WDT_OSC          1
-
-#define CLKOUTCLK_SRC_IRC_OSC       0
-#define CLKOUTCLK_SRC_SYS_OSC       1
-#define CLKOUTCLK_SRC_WDT_OSC       2
-#define CLKOUTCLK_SRC_MAIN_CLK      3
-
-void WDT_CLK_Setup(uint32_t timer_num);
-void CLKOUT_Setup(uint32_t timer_num);
-#endif /* end __CLKCONFIG_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/gpio.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/gpio.h
deleted file mode 100644
index 35d17f112..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/gpio.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/****************************************************************************
- *   $Id:: gpio.h 6172 2011-01-13 18:22:51Z usb00423                        $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains definition and prototype for GPIO.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __GPIO_H
-#define __GPIO_H
-
-#define CHANNEL0	0
-#define CHANNEL1	1
-#define CHANNEL2	2
-#define CHANNEL3	3
-#define CHANNEL4	4
-#define CHANNEL5	5
-#define CHANNEL6	6
-#define CHANNEL7	7
-
-#define PORT0		0
-#define PORT1		1
-
-#define GROUP0		0
-#define GROUP1		1
-
-void PIN_INT0_IRQHandler(void);
-void PIN_INT1_IRQHandler(void);
-void PIN_INT2_IRQHandler(void);
-void PIN_INT3_IRQHandler(void);
-void PIN_INT4_IRQHandler(void);
-void PIN_INT5_IRQHandler(void);
-void PIN_INT6_IRQHandler(void);
-void PIN_INT7_IRQHandler(void);
-void GINT0_IRQHandler(void);
-void GINT1_IRQHandler(void);
-void GPIOInit( void );
-void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
-		uint32_t sense, uint32_t event );
-void GPIOPinIntEnable( uint32_t channelNum, uint32_t event );
-void GPIOPinIntDisable( uint32_t channelNum, uint32_t event );
-uint32_t GPIOPinIntStatus( uint32_t channelNum );
-void GPIOPinIntClear( uint32_t channelNum );
-void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
-		uint32_t sense, uint32_t *eventPattern );
-uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
-void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
-void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
-
-#endif /* end __GPIO_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/nmi.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/nmi.h
deleted file mode 100644
index 498e4fd38..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/nmi.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/****************************************************************************
- *   $Id:: nmi.h 6172 2011-01-13 18:22:51Z usb00423                         $
- *   Project: NXP LPC13Uxx NMI software example
- *
- *   Description:
- *     This file contains definition and prototype for NMI interrupt.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __NMI_H 
-#define __NMI_H
-
-#define NMI_ENABLED          1
-
-#define MAX_NMI_NUM          32
-
-void NMI_Init( uint32_t NMI_num );
-void NMI_Handler(void);
-#endif /* end __NMI_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/power_api.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/power_api.h
deleted file mode 100644
index f95021774..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/power_api.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/****************************************************************************
- *   $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267                   $
- *   Project: NXP LPC13Uxx software example  
- *
- *   Description:
- *     Power API Header File for NXP LPC13Uxx Device Series 
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __LPC13UXX_POWER_API_H__
-#define __LPC13UXX_POWER_API_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define PWRROMD_PRESENT
-
-#define USBROMD_PRESENT
-
-#ifdef USBROMD_PRESENT
-#include "mw_usbd_rom_api.h"
-#endif
-
-typedef	struct _PWRD {
-  void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
-  void (*set_power)(unsigned int cmd[], unsigned int resp[]);
-}  PWRD;
-
-typedef	struct _ROM {
-#ifdef USBROMD_PRESENT
-   const USBD_API_T * pUSBD;
-#else
-   const unsigned p_usbd;
-#endif /* USBROMD_PRESENT */
-   const unsigned p_clib;
-   const unsigned p_cand;
-#ifdef PWRROMD_PRESENT
-   const PWRD * pPWRD;
-#else
-   const unsigned p_pwrd;
-#endif /* PWRROMD_PRESENT */
-   const unsigned p_dev1;
-   const unsigned p_dev2;
-   const unsigned p_dev3;
-   const unsigned p_dev4; 
-}  ROM;
-
-//PLL setup related definitions
-#define	CPU_FREQ_EQU  		0       //main PLL freq must be equal to the specified 
-#define	CPU_FREQ_LTE		1       //main PLL freq must be less than or equal the specified
-#define	CPU_FREQ_GTE		2       //main PLL freq must be greater than or equal the specified
-#define	CPU_FREQ_APPROX		3       //main PLL freq must be as close as possible the specified
-
-#define	PLL_CMD_SUCCESS		0       //PLL setup successfully found
-#define	PLL_INVALID_FREQ	1       //specified freq out of range (either input or output)
-#define	PLL_INVALID_MODE	2       //invalid mode (see above for valid) specified
-#define	PLL_FREQ_NOT_FOUND	3       //specified freq not found under specified conditions
-#define	PLL_NOT_LOCKED		4       //PLL not locked => no changes to the PLL setup
-
-//power setup elated definitions
-#define	PARAM_DEFAULT			0   //default power settings (voltage regulator, flash interface)
-#define	PARAM_CPU_PERFORMANCE	1   //setup for maximum CPU performance (higher current, more computation)
-#define	PARAM_EFFICIENCY		2   //balanced setting (power vs CPU performance)
-#define	PARAM_LOW_CURRENT		3   //lowest active current, lowest CPU performance
-
-#define	PARAM_CMD_SUCCESS		0   //power setting successfully found
-#define	PARAM_INVALID_FREQ		1   //specified freq out of range (=0 or > 50 MHz)
-#define	PARAM_INVALID_MODE		2   //specified mode not valid (see above for valid)
-
-#define MAX_CLOCK_KHZ_PARAM                50000
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC13UXX_POWER_API_H__ */
-
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer16.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer16.h
deleted file mode 100644
index 64355554c..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer16.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/****************************************************************************
- *   $Id:: timer16.h 6956 2011-03-23 23:03:25Z usb00423                     $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains definition and prototype for 16-bit timer 
- *     configuration.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __TIMER16_H 
-#define __TIMER16_H
-
-/* The test is either MAT_OUT or CAP_IN. Default is MAT_OUT. */
-#define TIMER_MATCH		0
-
-
-#define EMC0	4
-#define EMC1	6
-#define EMC2	8
-#define EMC3	10
-
-#define MATCH0	(1<<0)
-#define MATCH1	(1<<1)
-#define MATCH2	(1<<2)
-#define MATCH3	(1<<3)
-
-///* For 16-bit timer, make sure that TIME_INTERVAL should be no
-//greater than 0xFFFF. */
-#ifndef TIME_INTERVAL
-#define TIME_INTERVAL	(SystemCoreClock/1000 - 1)
-#endif
-
-void delayMs(uint8_t timer_num, uint32_t delayInMs);
-void CT16B0_IRQHandler(void);
-void CT16B1_IRQHandler(void);
-void enable_timer16(uint8_t timer_num);
-void disable_timer16(uint8_t timer_num);
-void reset_timer16(uint8_t timer_num);
-void set_timer16_capture(uint8_t timer_num, uint8_t location );
-void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
-void init_timer16(uint8_t timer_num, uint32_t timerInterval);
-void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled);
-void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
-
-#endif /* end __TIMER16_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer32.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer32.h
deleted file mode 100644
index ff0ad3846..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/timer32.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/****************************************************************************
- *   $Id:: timer32.h 7146 2011-04-19 19:48:01Z nxp28548                     $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains definition and prototype for 32-bit timer 
- *     configuration.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __TIMER32_H 
-#define __TIMER32_H
-
-/* The test is either MAT_OUT or CAP_IN. Default is CAP_IN. */
-#ifndef TIMER_MATCH
-#define TIMER_MATCH		0
-#endif//TIMER_MATCH
-
-#define EMC0	4
-#define EMC1	6
-#define EMC2	8
-#define EMC3	10
-
-#define MATCH0	(1<<0)
-#define MATCH1	(1<<1)
-#define MATCH2	(1<<2)
-#define MATCH3	(1<<3)
-
-#ifndef TIME_INTERVAL
-#define TIME_INTERVAL	(SystemCoreClock/100 - 1)
-#endif
-
-void delay32Ms(uint8_t timer_num, uint32_t delayInMs);
-void CT32B0_IRQHandler(void);
-void CT32B1_IRQHandler(void);
-void enable_timer32(uint8_t timer_num);
-void disable_timer32(uint8_t timer_num);
-void reset_timer32(uint8_t timer_num);
-void set_timer32_capture(uint8_t timer_num, uint8_t location );
-void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location);
-void init_timer32(uint8_t timer_num, uint32_t timerInterval);
-void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable);
-void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value);
-
-#endif /* end __TIMER32_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/type.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/type.h
deleted file mode 100644
index b45e97b53..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/type.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/****************************************************************************
- *   $Id:: type.h 6172 2011-01-13 18:22:51Z usb00423                        $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains different type definition.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __TYPE_H__
-#define __TYPE_H__
-
-#if defined (__GNUC__)
-#include <stdint.h>
-
-#else
-/* exact-width signed integer types */
-typedef   signed          char int8_t;
-typedef   signed short     int int16_t;
-typedef   signed           int int32_t;
-//typedef   signed       __int64 int64_t;
-
-     /* exact-width unsigned integer types */
-typedef unsigned          char uint8_t;
-typedef unsigned short     int uint16_t;
-typedef unsigned           int uint32_t;
-//typedef unsigned       __int64 uint64_t;
-#endif
-
-#ifndef NULL
-#define NULL    ((void *)0)
-#endif
-
-#ifndef FALSE
-#define FALSE   (0)
-#endif
-
-#ifndef TRUE
-#define TRUE    (1)
-#endif
-
-#endif  /* __TYPE_H__ */
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/uart.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/uart.h
deleted file mode 100644
index 2beccaf6c..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/uart.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/****************************************************************************
- *   $Id:: uart.h 6172 2011-01-13 18:22:51Z usb00423                        $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains definition and prototype for UART configuration.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __UART_H
-#define __UART_H
-
-#define AUTOBAUD_ENABLE 0
-#define FDR_CALIBRATION 0
-#define RS485_ENABLED   0
-#define TX_INTERRUPT    0		/* 0 if TX uses polling, 1 interrupt driven. */
-#define MODEM_TEST      0
-
-#define IER_RBR         (0x01<<0)
-#define IER_THRE        (0x01<<1)
-#define IER_RLS         (0x01<<2)
-#define IER_ABEO        (0x01<<8)
-#define IER_ABTO        (0x01<<9)
-
-#define IIR_PEND        0x01
-#define IIR_RLS         0x03
-#define IIR_RDA         0x02
-#define IIR_CTI         0x06
-#define IIR_THRE        0x01
-#define IIR_ABEO        (0x01<<8)
-#define IIR_ABTO        (0x01<<9)
-
-#define LSR_RDR         (0x01<<0)
-#define LSR_OE          (0x01<<1)
-#define LSR_PE          (0x01<<2)
-#define LSR_FE          (0x01<<3)
-#define LSR_BI          (0x01<<4)
-#define LSR_THRE        (0x01<<5)
-#define LSR_TEMT        (0x01<<6)
-#define LSR_RXFE        (0x01<<7)
-
-#define BUFSIZE         0x40
-
-/* RS485 mode definition. */
-#define RS485_NMMEN		(0x1<<0)
-#define RS485_RXDIS		(0x1<<1)
-#define RS485_AADEN		(0x1<<2)
-#define RS485_SEL             (0x1<<3)
-#define RS485_DCTRL		(0x1<<4)
-#define RS485_OINV		(0x1<<5)
-
-void ModemInit( void );
-void UARTInit(uint32_t Baudrate);
-void USART_IRQHandler(void);
-void UARTSend(uint8_t *BufferPtr, uint32_t Length);
-void print_string( uint8_t *str_ptr );
-uint8_t get_key( void );
-
-#endif /* end __UART_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/usart.h b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/usart.h
deleted file mode 100644
index b81474541..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/inc/usart.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/****************************************************************************
- *   $Id:: usart.h 6172 2011-01-13 18:22:51Z usb00423                       $
- *   Project: NXP LPC13Uxx software example
- *
- *   Description:
- *     This file contains definition and prototype for UART configuration.
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __USART_H 
-#define __USART_H
-
-/* Synchronous mode control register definition. */
-#define SYNC_ON             (0x1<<0)
-#define SYNC_OFF            (0x0<<0)
-
-#define SYNC_MASTER         (0x1<<1)
-#define SYNC_SLAVE          (0x0<<1)
-
-#define SYNC_RE             (0x0<<2)
-#define SYNC_FE             (0x1<<2)
-
-#define SYNC_CONT_CLK_EN    (0x1<<4)
-#define SYNC_CONT_CLK_DIS   (0x0<<4)
-
-#define SYNC_STARTSTOPOFF   (0x1<<5)
-#define SYNC_STARTSTOPON    (0x0<<5)
-
-#define SYNC_CON_CLK_CLR    (0x1<<6)
-
-#endif /* end __USART_H */
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/Serial.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/Serial.c
deleted file mode 100644
index 3f8b97d74..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/Serial.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/******************************************************************************/
-/* SERIAL.C: Low Level Serial Routines                                        */
-/******************************************************************************/
-/* This file is part of the uVision/ARM development tools.                    */
-/* Copyright (c) 2005-2006 Keil Software. All rights reserved.                */
-/* This software may only be used under the terms of a valid, current,        */
-/* end user licence from KEIL for a compatible version of KEIL software       */
-/* development tools. Nothing else gives you the right to use this software.  */
-/******************************************************************************/
-
-#include "LPC13Uxx.h"                     /* LPC13Uxx definitions              */
-#include "uart.h"
-
-#define CR     0x0D
-
-/* implementation of putchar (also used by printf function to output data)    */
-int sendchar (int ch)  {                 /* Write character to Serial Port    */
-
-
-  if (ch == '\n')  {
-    while (!(LPC_USART->LSR & 0x20));
-    LPC_USART->THR = CR;                          /* output CR */
-  }
-  while (!(LPC_USART->LSR & 0x20));
-  return (LPC_USART->THR = ch);
-}
-
-
-int getkey (void)  {                     /* Read character from Serial Port   */
-
-  while (!(LPC_USART->LSR & 0x01));
-  return (LPC_USART->RBR);
-}
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/clkconfig.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/clkconfig.c
deleted file mode 100644
index 488472206..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/clkconfig.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/****************************************************************************
- *   $Id:: clkconfig.c 6874 2011-03-22 01:58:31Z usb00423                   $
- *   Project: NXP LPC13Uxx Clock Configuration example
- *
- *   Description:
- *     This file contains clock configuration code example which include 
- *     watchdog setup and debug clock out setup.
- *
- ****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-****************************************************************************/
-#include "LPC13Uxx.h"
-#include "clkconfig.h"
-
-
-/*****************************************************************************
-** Function name:		WDT_CLK_Setup
-**
-** Descriptions:		Configure WDT clock.
-** parameters:			clock source: irc_osc(0), main_clk(1), wdt_osc(2).			 
-** 						
-** Returned value:		None
-** 
-*****************************************************************************/
-void WDT_CLK_Setup ( uint32_t clksrc )
-{
-  /* Freq = 0.5Mhz, div_sel is 0x1F, divided by 64. WDT_OSC should be 7.8125khz */
-  LPC_SYSCON->WDTOSCCTRL = (0x1<<5)|0x1F;
-  LPC_SYSCON->PDRUNCFG &= ~(0x1<<6);    /* Let WDT clock run */
-
-  /* Enables clock for WDT */
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15);
-  LPC_WWDT->CLKSEL = clksrc;        /* Select clock source */
-  return;
-}
-
-/*****************************************************************************
-** Function name:		CLKOUT_Setup
-**
-** Descriptions:		Configure CLKOUT for reference clock check.
-** parameters:			clock source: irc_osc(0), sys_osc(1), wdt_osc(2),
-**						main_clk(3).			 
-** 						
-** Returned value:		None
-** 
-*****************************************************************************/
-void CLKOUT_Setup ( uint32_t clksrc )
-{
-  /* debug PLL after configuration. */
-  LPC_SYSCON->CLKOUTSEL = clksrc;	/* Select Main clock */
-  LPC_SYSCON->CLKOUTDIV = 1;			/* Divided by 1 */
-  return;
-}
-
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/gpio.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/gpio.c
deleted file mode 100644
index 602bca572..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/gpio.c
+++ /dev/null
@@ -1,838 +0,0 @@
-/****************************************************************************
- *   $Id:: gpio.c 6874 2011-03-22 01:58:31Z usb00423                        $
- *   Project: NXP LPC13Uxx GPIO example
- *
- *   Description:
- *     This file contains GPIO code example which include GPIO
- *     initialization, GPIO interrupt handler, and related APIs for
- *     GPIO access.
- *
- ****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-****************************************************************************/
-#include "LPC13Uxx.h"			/* LPC13Uxx Peripheral Registers */
-#include "gpio.h"
-
-volatile uint32_t pin_int0_counter = 0;
-volatile uint32_t pin_int1_counter = 0;
-volatile uint32_t pin_int2_counter = 0;
-volatile uint32_t pin_int3_counter = 0;
-volatile uint32_t pin_int4_counter = 0;
-volatile uint32_t pin_int5_counter = 0;
-volatile uint32_t pin_int6_counter = 0;
-volatile uint32_t pin_int7_counter = 0;
-volatile uint32_t gint0_counter = 0;
-volatile uint32_t gint1_counter = 0;
-volatile uint32_t pin_int0_level_counter = 0;
-volatile uint32_t pin_int0_rising_edge_counter = 0;
-volatile uint32_t pin_int0_falling_edge_counter = 0;
-volatile uint32_t pin_int1_level_counter = 0;
-volatile uint32_t pin_int1_rising_edge_counter = 0;
-volatile uint32_t pin_int1_falling_edge_counter = 0;
-volatile uint32_t pin_int2_level_counter = 0;
-volatile uint32_t pin_int2_rising_edge_counter = 0;
-volatile uint32_t pin_int2_falling_edge_counter = 0;
-volatile uint32_t pin_int3_level_counter = 0;
-volatile uint32_t pin_int3_rising_edge_counter = 0;
-volatile uint32_t pin_int3_falling_edge_counter = 0;
-volatile uint32_t pin_int4_level_counter = 0;
-volatile uint32_t pin_int4_rising_edge_counter = 0;
-volatile uint32_t pin_int4_falling_edge_counter = 0;
-volatile uint32_t pin_int5_level_counter = 0;
-volatile uint32_t pin_int5_rising_edge_counter = 0;
-volatile uint32_t pin_int5_falling_edge_counter = 0;
-volatile uint32_t pin_int6_level_counter = 0;
-volatile uint32_t pin_int6_rising_edge_counter = 0;
-volatile uint32_t pin_int6_falling_edge_counter = 0;
-volatile uint32_t pin_int7_level_counter = 0;
-volatile uint32_t pin_int7_rising_edge_counter = 0;
-volatile uint32_t pin_int7_falling_edge_counter = 0;
-volatile uint32_t gint0_level_counter = 0;
-volatile uint32_t gint0_edge_counter = 0;
-volatile uint32_t gint1_level_counter = 0;
-volatile uint32_t gint1_edge_counter = 0;
-
-/*****************************************************************************
-** Function name:		PIN_INT0_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT0_IRQHandler(void)
-{
-  pin_int0_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) )
-	{
-	  pin_int0_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<0) ) )
-	  {
-		pin_int0_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<0;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<0) ) )
-	  {
-		pin_int0_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<0;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<0;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT1_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT1_IRQHandler(void)
-{
-  pin_int1_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) )
-	{
-	  pin_int1_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<1) ) )
-	  {
-		pin_int1_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<1;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<1) ) )
-	  {
-		pin_int1_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<1;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<1;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT2_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT2_IRQHandler(void)
-{
-  pin_int2_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) )
-	{
-	  pin_int2_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<2) ) )
-	  {
-		pin_int2_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<2;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<2) ) )
-	  {
-		pin_int2_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<2;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<2;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT3_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT3_IRQHandler(void)
-{
-  pin_int3_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) )
-	{
-	  pin_int3_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<3) ) )
-	  {
-		pin_int3_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<3;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<3) ) )
-	  {
-		pin_int3_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<3;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<3;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT4_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT4_IRQHandler(void)
-{
-  pin_int4_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) )
-	{
-	  pin_int4_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<4) ) )
-	  {
-		pin_int4_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<4;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<4) ) )
-	  {
-		pin_int4_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<4;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<4;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT5_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT5_IRQHandler(void)
-{
-  pin_int5_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) )
-	{
-	  pin_int5_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<5) ) )
-	  {
-		pin_int5_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<5;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<5) ) )
-	  {
-		pin_int5_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<5;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<5;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT6_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT6_IRQHandler(void)
-{
-  pin_int6_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) )
-	{
-	  pin_int6_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<6) ) )
-	  {
-		pin_int6_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<6;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<6) ) )
-	  {
-		pin_int6_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<6;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<6;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		PIN_INT7_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void PIN_INT7_IRQHandler(void)
-{
-  pin_int7_counter++;
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) )
-  {
-	if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) )
-	{
-	  pin_int7_level_counter++;
-	}
-	else
-	{
-	  if ( ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENR & (0x1<<7) ) )
-	  {
-		pin_int7_rising_edge_counter++;
-		LPC_GPIO_PIN_INT->RISE = 0x1<<7;
-	  }
-	  if ( ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) && ( LPC_GPIO_PIN_INT->IENF & (0x1<<7) ) )
-	  {
-		pin_int7_falling_edge_counter++;
-		LPC_GPIO_PIN_INT->FALL = 0x1<<7;
-	  }
-	  LPC_GPIO_PIN_INT->IST = 0x1<<7;
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GINT0_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GINT0_IRQHandler(void)
-{
-  gint0_counter++;
-  if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<0) )
-  {
-	if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<2) )
-	{
-	  gint0_level_counter++;
-	}
-	else
-	{
-	  gint0_edge_counter++;
-	}
-	LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<0);
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GINT1_IRQHandler
-**
-** Descriptions:		Use one GPIO pin as interrupt source
-**
-** parameters:			None
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GINT1_IRQHandler(void)
-{
-  gint1_counter++;
-  if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<0) )
-  {
-	if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<2) )
-	{
-	  gint1_level_counter++;
-	}
-	else
-	{
-	  gint1_edge_counter++;
-	}
-	LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<0);
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOInit
-**
-** Descriptions:		Initialize GPIO, install the
-**						GPIO interrupt handler
-**
-** parameters:			None
-**
-** Returned value:		true or false, return false if the VIC table
-**						is full and GPIO interrupt handler can be
-**						installed.
-**
-*****************************************************************************/
-void GPIOInit( void )
-{
-  /* Enable AHB clock to the GPIO domain. */
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
-
-  /* Enable AHB clock to the PinInt, GroupedInt domain. */
-  LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
-
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOSetPinInterrupt
-**
-** Descriptions:		Set interrupt sense, event, etc.
-**						sense: edge or level, 0 is edge, 1 is level
-**						event/polarity: 0 is active low/falling, 1 is high/rising.
-**
-** parameters:			channel #, port #, bit position, sense, event(polarity)
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOSetPinInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi,
-		uint32_t sense, uint32_t event )
-{
-  switch ( channelNum )
-  {
-	case CHANNEL0:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[0] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[0] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT0_IRQn);
-	break;
-	case CHANNEL1:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[1] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[1] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT1_IRQn);
-	break;
-	case CHANNEL2:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[2] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[2] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT2_IRQn);
-	break;
-	case CHANNEL3:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[3] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[3] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT3_IRQn);
-	break;
-	case CHANNEL4:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[4] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[4] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT4_IRQn);
-	break;
-	case CHANNEL5:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[5] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[5] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT5_IRQn);
-	break;
-	case CHANNEL6:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[6] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[6] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT6_IRQn);
-	break;
-	case CHANNEL7:
-	  if ( portNum )
-	  {
-		LPC_SYSCON->PINSEL[7] = bitPosi + 24;
-	  }
-	  else
-	  {
-		LPC_SYSCON->PINSEL[7] = bitPosi;
-	  }
-	  NVIC_EnableIRQ(PIN_INT7_IRQn);
-	break;
-	default:
-	  break;
-  }
-  if ( sense == 0 )
-  {
-	LPC_GPIO_PIN_INT->ISEL &= ~(0x1<<channelNum);	/* Edge trigger */
-	if ( event == 0 )
-	{
-	  LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum);	/* faling edge */
-	}
-	else
-	{
-	  LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum);	/* Rising edge */
-	}
-  }
-  else
-  {
-	LPC_GPIO_PIN_INT->ISEL |= (0x1<<channelNum);	/* Level trigger. */
-	LPC_GPIO_PIN_INT->IENR |= (0x1<<channelNum);	/* Level enable */
-	if ( event == 0 )
-	{
-	  LPC_GPIO_PIN_INT->IENF &= ~(0x1<<channelNum);	/* active-low */
-	}
-	else
-	{
-	  LPC_GPIO_PIN_INT->IENF |= (0x1<<channelNum);	/* active-high */
-	}
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOPinIntEnable
-**
-** Descriptions:		Enable Interrupt
-**
-** parameters:			channel num, event(0 is falling edge, 1 is rising edge)
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOPinIntEnable( uint32_t channelNum, uint32_t event )
-{
-  if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
-  {
-	if ( event == 0 )
-	{
-	  LPC_GPIO_PIN_INT->SIENF |= (0x1<<channelNum);	/* faling edge */
-	}
-	else
-	{
-	  LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum);	/* Rising edge */
-	}
-  }
-  else
-  {
-	LPC_GPIO_PIN_INT->SIENR |= (0x1<<channelNum);	/* Level */
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOPinIntDisable
-**
-** Descriptions:		Disable Interrupt
-**
-** parameters:			channel num, event(0 is falling edge, 1 is rising edge)
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOPinIntDisable( uint32_t channelNum, uint32_t event )
-{
-  if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
-  {
-	if ( event == 0 )
-	{
-	  LPC_GPIO_PIN_INT->CIENF |= (0x1<<channelNum);	/* faling edge */
-	}
-	else
-	{
-	  LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum);	/* Rising edge */
-	}
-  }
-  else
-  {
-	LPC_GPIO_PIN_INT->CIENR |= (0x1<<channelNum);	/* Level */
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOPinIntStatus
-**
-** Descriptions:		Get Interrupt status
-**
-** parameters:			channel num
-**
-** Returned value:		None
-**
-*****************************************************************************/
-uint32_t GPIOPinIntStatus( uint32_t channelNum )
-{
-  if ( LPC_GPIO_PIN_INT->IST & (0x1<<channelNum) )
-  {
-	return( 1 );
-  }
-  else
-  {
-	return( 0 );
-  }
-}
-
-/*****************************************************************************
-** Function name:		GPIOPinIntClear
-**
-** Descriptions:		Clear Interrupt
-**
-** parameters:			channel num
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOPinIntClear( uint32_t channelNum )
-{
-  if ( !( LPC_GPIO_PIN_INT->ISEL & (0x1<<channelNum) ) )
-  {
-	LPC_GPIO_PIN_INT->IST = (1<<channelNum);
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOSetGroupedInterrupt
-**
-** Descriptions:		Set interrupt logic, sense, eventPattern, etc.
-**						logic: AND or OR, 0 is OR, 1 is AND
-**						sensePattern: edge or level, 0 is edge, 1 is level
-**						event/polarity: 0 is active low/falling, 1 is high/rising.
-**
-** parameters:			group #, bit pattern, logic, sense, event(polarity) pattern
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOSetGroupedInterrupt( uint32_t groupNum, uint32_t *bitPattern, uint32_t logic,
-		uint32_t sense, uint32_t *eventPattern )
-{
-  switch ( groupNum )
-  {
-	case GROUP0:
-	  if ( sense == 0 )
-	  {
-		LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<2);	/* Edge trigger */
-	  }
-	  else
-	  {
-		LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2);	/* Level trigger. */
-	  }
-	  if ( logic == 0 )
-	  {
-		LPC_GPIO_GROUP_INT0->CTRL &= ~(0x1<<1);	/* OR */
-	  }
-	  else
-	  {
-		LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<1);	/* AND */
-	  }
-	  LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
-	  LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
-	  LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
-	  LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
-      /* as soon as enabled, an edge may be generated       */
-	  /* clear interrupt flag and NVIC pending interrupt to */
-	  /* workaround the potential edge generated as enabled */
-	  LPC_GPIO_GROUP_INT0->CTRL |= (1<<0);
-	  NVIC_ClearPendingIRQ(GINT0_IRQn);
-	  NVIC_EnableIRQ(GINT0_IRQn);
-	break;
-	case GROUP1:
-	  if ( sense == 0 )
-	  {
-		LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2);	/* Edge trigger */
-	  }
-	  else
-	  {
-		LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2);	/* Level trigger. */
-	  }
-	  if ( logic == 0 )
-	  {
-		LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<1);	/* OR */
-	  }
-	  else
-	  {
-		LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<1);	/* AND */
-	  }
-	  LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0));
-	  LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1));
-	  LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0));
-	  LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1));
-      /* as soon as enabled, an edge may be generated       */
-	  /* clear interrupt flag and NVIC pending interrupt to */
-	  /* workaround the potential edge generated as enabled */
-	  LPC_GPIO_GROUP_INT1->CTRL |= (1<<0);
-	  NVIC_ClearPendingIRQ(GINT1_IRQn);
-	  NVIC_EnableIRQ(GINT1_IRQn);
-	break;
-	default:
-	  break;
-  }
-
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOGetPinValue
-**
-** Descriptions:		Read Current state of port pin, PIN register value
-**
-** parameters:			port num, bit position
-** Returned value:		None
-**
-*****************************************************************************/
-uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi )
-{
-  uint32_t regVal = 0;
-
-  if( bitPosi < 0x20 )
-  {
-	if ( LPC_GPIO->PIN[portNum] & (0x1<<bitPosi) )
-	{
-	  regVal = 1;
-	}
-  }
-  else if( bitPosi == 0xFF )
-  {
-	regVal = LPC_GPIO->PIN[portNum];
-  }
-  return ( regVal );
-}
-
-/*****************************************************************************
-** Function name:		GPIOSetBitValue
-**
-** Descriptions:		Set/clear a bit in a specific position
-**
-** parameters:			port num, bit position, bit value
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal )
-{
-  if ( bitVal )
-  {
-	LPC_GPIO->SET[portNum] = 1<<bitPosi;
-  }
-  else
-  {
-	LPC_GPIO->CLR[portNum] = 1<<bitPosi;
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		GPIOSetDir
-**
-** Descriptions:		Set the direction in GPIO port
-**
-** parameters:			portNum, bit position, direction (1 out, 0 input)
-**
-** Returned value:		None
-**
-*****************************************************************************/
-void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir )
-{
-  if( dir )
-  {
-	LPC_GPIO->DIR[portNum] |= (1<<bitPosi);
-  }
-  else
-  {
-	LPC_GPIO->DIR[portNum] &= ~(1<<bitPosi);
-  }
-  return;
-}
-
-/******************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/nmi.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/nmi.c
deleted file mode 100644
index d4225b60f..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/nmi.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/****************************************************************************
- *   $Id:: nmi.c 7227 2011-04-27 20:20:38Z usb01267                         $
- *   Project: NXP LPC13Uxx NMI interrupt example
- *
- *   Description:
- *     This file contains NMI interrupt handler code example.
- *
- ****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-****************************************************************************/
-#include "LPC13Uxx.h"
-#include "nmi.h"
-
-#if NMI_ENABLED
-volatile uint32_t NMI_Counter[MAX_NMI_NUM];
-
-/*****************************************************************************
-** Function name:		NMI_Handler
-**
-** Descriptions:		NMI interrupt handler
-** parameters:		None			 
-** 						
-** Returned value:	None
-** 
-*****************************************************************************/
-void NMI_Handler( void )
-{
-  uint32_t regVal;
-
-  regVal = LPC_SYSCON->NMISRC;
-  regVal &=	~0x80000000;
-  if ( regVal < MAX_NMI_NUM )
-  {
-    if ( regVal == CT16B0_IRQn )
-	{
-	  /* Use TIMER16_0_IRQHandler as example for real application. */ 	
-	  LPC_CT16B0->IR = 0xFF;	/* Clear timer16_0 interrupt */
-	}
-	else if ( regVal == CT16B1_IRQn )
-	{
-	  /* Use TIMER16_1_IRQHandler as example for real application. */	
-	  LPC_CT16B1->IR = 0xFF;	/* Clear timer16_1 interrupt */
-	}
-    else if ( regVal == CT32B0_IRQn )
-	{
-	  /* Use TIMER32_0_IRQHandler as example for real application. */ 	
-	  LPC_CT32B0->IR = 0xFF;	/* Clear timer32_0 interrupt */
-	}
-	else if ( regVal == CT32B1_IRQn )
-	{
-	  /* Use TIMER32_0_IRQHandler as example for real application. */ 	
-	  LPC_CT32B1->IR = 0xFF;	/* Clear timer32_1 interrupt */
-	}
-	NMI_Counter[regVal]++; 
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		NMI_Init
-**
-** Descriptions:		NMI initialization
-** parameters:			NMI number			 
-** 						
-** Returned value:		None
-** 
-*****************************************************************************/
-void NMI_Init( uint32_t NMI_num )
-{
-  uint32_t i;
-
-  for ( i = 0; i < MAX_NMI_NUM; i++ )
-  {
-    NMI_Counter[i] = 0x0;
-  }
-  LPC_SYSCON->NMISRC = 0x80000000|NMI_num;
-  return;
-}
-
-#endif
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer16.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer16.c
deleted file mode 100644
index a599ec326..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer16.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/****************************************************************************
- *   $Id:: timer16.c 6950 2011-03-23 22:09:44Z usb00423                     $
- *   Project: NXP LPC13Uxx 16-bit timer example
- *
- *   Description:
- *     This file contains 16-bit timer code example which include timer 
- *     initialization, timer interrupt handler, and related APIs for 
- *     timer setup.
- *
- ****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-****************************************************************************/
-#include "LPC13Uxx.h"
-#include "timer16.h"
-#include "nmi.h"
-
-volatile uint32_t timer16_0_counter[4] = {0,0,0,0};
-volatile uint32_t timer16_1_counter[4] = {0,0,0,0};
-volatile uint32_t timer16_0_capture[4] = {0,0,0,0};
-volatile uint32_t timer16_1_capture[4] = {0,0,0,0};
-volatile uint32_t timer16_0_period = 0;
-volatile uint32_t timer16_1_period = 0;
-
-/*****************************************************************************
-** Function name:		delayMs
-**
-** Descriptions:		Start the timer delay in milo seconds
-**						until elapsed
-**
-** parameters:			timer number, Delay value in milo second			 
-** 						
-** Returned value:		None
-** 
-*****************************************************************************/
-void delayMs(uint8_t timer_num, uint32_t delayInMs)
-{
-  if (timer_num == 0)
-  {
-    /*
-    * setup timer #0 for delay
-    */
-    LPC_CT16B0->TCR = 0x02;		/* reset timer */
-    LPC_CT16B0->PR  = 0x00;		/* set prescaler to zero */
-    LPC_CT16B0->MR0 = delayInMs * (SystemCoreClock / 1000);
-    LPC_CT16B0->IR  = 0xff;		/* reset all interrrupts */
-    LPC_CT16B0->MCR = 0x04;		/* stop timer on match */
-    LPC_CT16B0->TCR = 0x01;		/* start timer */
-    /* wait until delay time has elapsed */
-    while (LPC_CT16B0->TCR & 0x01);
-  }
-  else if (timer_num == 1)
-  {
-    /*
-    * setup timer #1 for delay
-    */
-    LPC_CT16B1->TCR = 0x02;		/* reset timer */
-    LPC_CT16B1->PR  = 0x00;		/* set prescaler to zero */
-    LPC_CT16B1->MR0 = delayInMs * (SystemCoreClock / 1000);
-    LPC_CT16B1->IR  = 0xff;		/* reset all interrrupts */
-    LPC_CT16B1->MCR = 0x04;		/* stop timer on match */
-    LPC_CT16B1->TCR = 0x01;		/* start timer */
-    /* wait until delay time has elapsed */
-    while (LPC_CT16B1->TCR & 0x01);
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		CT16B0_IRQHandler
-**
-** Descriptions:		Timer/CounterX and CaptureX interrupt handler
-**
-** parameters:			None
-** Returned value:		None
-** 
-******************************************************************************/
-void CT16B0_IRQHandler(void)
-{
-  if ( LPC_CT16B0->IR & (0x1<<0) )
-  {
-	LPC_CT16B0->IR = 0x1<<0;			/* clear interrupt flag */
-	timer16_0_counter[0]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<1) )
-  {
-	LPC_CT16B0->IR = 0x1<<1;			/* clear interrupt flag */
-	timer16_0_counter[1]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<2) )
-  {
-	LPC_CT16B0->IR = 0x1<<2;			/* clear interrupt flag */
-	timer16_0_counter[2]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<3) )
-  {
-	LPC_CT16B0->IR = 0x1<<3;			/* clear interrupt flag */
-	timer16_0_counter[3]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<4) )
-  {
-	LPC_CT16B0->IR = 0x1<<4;		/* clear interrupt flag */
-	timer16_0_capture[0]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<5) )
-  {
-	LPC_CT16B0->IR = 0x1<<5;		/* clear interrupt flag */
-	timer16_0_capture[1]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<6) )
-  {
-	LPC_CT16B0->IR = 0x1<<6;		/* clear interrupt flag */
-	timer16_0_capture[2]++;
-  }
-  if ( LPC_CT16B0->IR & (0x1<<7) )
-  {
-	LPC_CT16B0->IR = 0x1<<7;		/* clear interrupt flag */
-	timer16_0_capture[3]++;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		CT16B1_IRQHandler
-**
-** Descriptions:		Timer/CounterX and CaptureX interrupt handler
-**
-** parameters:			None
-** Returned value:		None
-** 
-******************************************************************************/
-void CT16B1_IRQHandler(void)
-{
-  if ( LPC_CT16B1->IR & (0x1<<0) )
-  {  
-	LPC_CT16B1->IR = 0x1<<0;			/* clear interrupt flag */
-	timer16_1_counter[0]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<1) )
-  {  
-	LPC_CT16B1->IR = 0x1<<1;			/* clear interrupt flag */
-	timer16_1_counter[1]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<2) )
-  {  
-	LPC_CT16B1->IR = 0x1<<2;			/* clear interrupt flag */
-	timer16_1_counter[2]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<3) )
-  {  
-	LPC_CT16B1->IR = 0x1<<3;			/* clear interrupt flag */
-	timer16_1_counter[3]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<4) )
-  {
-	LPC_CT16B1->IR = 0x1<<4;		/* clear interrupt flag */
-	timer16_1_capture[0]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<5) )
-  {
-	LPC_CT16B1->IR = 0x1<<5;		/* clear interrupt flag */
-	timer16_1_capture[1]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<6) )
-  {
-	LPC_CT16B1->IR = 0x1<<6;		/* clear interrupt flag */
-	timer16_1_capture[2]++;
-  }
-  if ( LPC_CT16B1->IR & (0x1<<7) )
-  {
-	LPC_CT16B1->IR = 0x1<<7;		/* clear interrupt flag */
-	timer16_1_capture[3]++;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		enable_timer
-**
-** Descriptions:		Enable timer
-**
-** parameters:			timer number: 0 or 1
-** Returned value:		None
-** 
-******************************************************************************/
-void enable_timer16(uint8_t timer_num)
-{
-  if ( timer_num == 0 )
-  {
-    LPC_CT16B0->TCR = 1;
-  }
-  else
-  {
-    LPC_CT16B1->TCR = 1;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		disable_timer
-**
-** Descriptions:		Disable timer
-**
-** parameters:			timer number: 0 or 1
-** Returned value:		None
-** 
-******************************************************************************/
-void disable_timer16(uint8_t timer_num)
-{
-  if ( timer_num == 0 )
-  {
-    LPC_CT16B0->TCR = 0;
-  }
-  else
-  {
-    LPC_CT16B1->TCR = 0;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		reset_timer
-**
-** Descriptions:		Reset timer
-**
-** parameters:			timer number: 0 or 1
-** Returned value:		None
-** 
-******************************************************************************/
-void reset_timer16(uint8_t timer_num)
-{
-  uint32_t regVal;
-
-  if ( timer_num == 0 )
-  {
-    regVal = LPC_CT16B0->TCR;
-    regVal |= 0x02;
-    LPC_CT16B0->TCR = regVal;
-  }
-  else
-  {
-    regVal = LPC_CT16B1->TCR;
-    regVal |= 0x02;
-    LPC_CT16B1->TCR = regVal;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		Set_timer_capture
-**
-** Descriptions:		set timer capture based on LOC number.
-**
-** parameters:			timer number and location number
-** Returned value:		None
-** 
-******************************************************************************/
-void set_timer16_capture(uint8_t timer_num, uint8_t location )
-{
-  if ( timer_num == 0 )
-  {
-	/*  Timer0_16 I/O config */
-	if ( location == 0 )
-	{
-	  LPC_IOCON->PIO1_16           &= ~0x07;
-	  LPC_IOCON->PIO1_16           |= 0x02;		/* Timer0_16 CAP0 */
-	  LPC_IOCON->PIO1_17           &= ~0x07;
-	  LPC_IOCON->PIO1_17           |= 0x01;		/* Timer0_16 CAP2 */
-	}
-	else if ( location == 1 )
-	{
-	  LPC_IOCON->PIO0_2            &= ~0x07;
-	  LPC_IOCON->PIO0_2            |= 0x02;		/* Timer0_16 CAP0 */
-	}
-	else
-	{
-	  while ( 1 );				/* Fatal location number error */
-	}
-  }
-  else
-  {
-	/*  Timer1_16 I/O config */
-	if ( location == 0 )
-	{
-	  LPC_IOCON->PIO0_20           &= ~0x07;	/*  Timer1_16 I/O config */
-	  LPC_IOCON->PIO0_20           |= 0x01;		/* Timer1_16 CAP0 */
-	  LPC_IOCON->PIO1_18           &= ~0x07;
-	  LPC_IOCON->PIO1_18           |= 0x01;		/* Timer1_16 CAP1 */
-	}
-	else
-	{
-	  while ( 1 );				/* Fatal location number error */
-	}
-  }	
-  return;
-}
-
-/******************************************************************************
-** Function name:		Set_timer_match
-**
-** Descriptions:		set timer match based on LOC number.
-**
-** parameters:			timer number, match enable, and location number 
-** Returned value:		None
-** 
-******************************************************************************/
-void set_timer16_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
-{
-  if ( timer_num == 0 )
-  {
-	if ( match_enable & 0x01 )
-	{
-	  /*  Timer0_16 I/O config */
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_8           &= ~0x07;	
-		LPC_IOCON->PIO0_8           |= 0x02;		/* Timer0_16 MAT0 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_13           &= ~0x07;
-		LPC_IOCON->PIO1_13           |= 0x02;		/* Timer0_16 MAT0 */
-	  }
-	}
-	if ( match_enable & 0x02 )
-	{
-	  /*  Timer0_16 I/O config */
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_9           &= ~0x07;
-		LPC_IOCON->PIO0_9           |= 0x02;		/* Timer0_16 MAT1 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_14           &= ~0x07;
-		LPC_IOCON->PIO1_14           |= 0x02;		/* Timer0_16 MAT1 */
-	  }
-	}
-	if ( match_enable & 0x04 )
-	{
-	  /*  Timer0_16 I/O config */
-	  if ( location == 0 )
-	  {
-#ifdef __SWD_DISABLED
-		LPC_IOCON->SWCLK_PIO0_10    &= ~0x07;
-		LPC_IOCON->SWCLK_PIO0_10    |= 0x03;		/* Timer0_16 MAT2 */
-#endif	
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_15           &= ~0x07;
-		LPC_IOCON->PIO1_15           |= 0x02;		/* Timer0_16 MAT2 */
-	  }
-	}
-  }
-  else if ( timer_num == 1 )
-  {
-	if ( match_enable & 0x01 )
-	{
-	  /*  Timer1_16 I/O config */
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_21           &= ~0x07;
-		LPC_IOCON->PIO0_21           |= 0x01;		/* Timer1_16 MAT0 */
-	  }
-	}
-	if ( match_enable & 0x02 )
-	{
-	  /*  Timer1_16 I/O config */
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_22           &= ~0x07;
-		LPC_IOCON->PIO0_22           |= 0x02;		/* Timer1_16 MAT1 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_23           &= ~0x07;
-		LPC_IOCON->PIO1_23           |= 0x01;		/* Timer1_16 MAT1 */
-	  }
-	}
-  }
-  return;		
-}
-
-/******************************************************************************
-** Function name:		init_timer
-**
-** Descriptions:		Initialize timer, set timer interval, reset timer,
-**						install timer interrupt handler
-**
-** parameters:			timer number and timer interval
-** Returned value:		None
-** 
-******************************************************************************/
-void init_timer16(uint8_t timer_num, uint32_t TimerInterval) 
-{
-  uint32_t i;
-
-  if ( timer_num == 0 )
-  {
-    /* Some of the I/O pins need to be clearfully planned if
-    you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
-
-    LPC_CT16B0->MR0 = TimerInterval;
-    LPC_CT16B0->MR1 = TimerInterval;
-#if TIMER_MATCH
-    for ( i = 0; i < 4; i++ )
-    {
-      timer16_0_counter[i] = 0;
-    }
-    set_timer16_match(timer_num, 0x07, 0);
-    LPC_CT16B0->EMR &= ~(0xFF<<4);
-    LPC_CT16B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
-#else
-    for ( i = 0; i < 4; i++ )
-    {
-      timer16_0_capture[i] = 0;
-    }
-    set_timer16_capture(timer_num, 0);
-    /* Capture 0 and 2 on rising edge, interrupt enable. */
-    LPC_CT16B0->CCR = (0x5<<0)|(0x5<<6);
-#endif
-    LPC_CT16B0->MCR = (0x3<<0)|(0x3<<3);  /* Interrupt and Reset on MR0 and MR1 */
-		
-    /* Enable the TIMER0 Interrupt */
-#if NMI_ENABLED
-    NVIC_DisableIRQ(CT16B0_IRQn);
-    NMI_Init( CT16B0_IRQn );
-#else
-    NVIC_EnableIRQ(CT16B0_IRQn);
-#endif
-  }
-  else if ( timer_num == 1 )
-  {
-    /* Some of the I/O pins need to be clearfully planned if
-    you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
-    LPC_CT16B1->MR0 = TimerInterval;
-    LPC_CT16B1->MR1 = TimerInterval;
-#if TIMER_MATCH
-    for ( i = 0; i < 4; i++ )
-    {
-      timer16_1_counter[i] = 0;
-    }
-    set_timer16_match(timer_num, 0x07, 0);
-    LPC_CT16B1->EMR &= ~(0xFF<<4);
-    LPC_CT16B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8));
-#else
-    for ( i = 0; i < 4; i++ )
-    {
-      timer16_1_capture[i] = 0;
-    }
-    set_timer16_capture(timer_num, 0);
-    /* Capture 0 and 1 on rising edge, interrupt enable. */
-    LPC_CT16B1->CCR = (0x5<<0)|(0x5<<3);
-#endif
-    LPC_CT16B1->MCR = (0x3<<0)|(0x3<<3);  /* Interrupt and Reset on MR0 and MR1 */
-
-    /* Enable the TIMER1 Interrupt */
-#if NMI_ENABLED
-    NVIC_DisableIRQ(CT16B1_IRQn);
-    NMI_Init( CT16B1_IRQn );
-#else
-    NVIC_EnableIRQ(CT16B1_IRQn);
-#endif
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		init_timer16PWM
-**
-** Descriptions:		Initialize timer as PWM
-**
-** parameters:			timer number, period and match enable:
-**						match_enable[0] = PWM for MAT0 
-**						match_enable[1] = PWM for MAT1
-**						match_enable[2] = PWM for MAT2
-**			
-** Returned value:	None
-** 
-******************************************************************************/
-void init_timer16PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable, uint8_t cap_enabled)
-{	
-  disable_timer16(timer_num);
-
-  if (timer_num == 1)
-  {
-    /* Some of the I/O pins need to be clearfully planned if
-    you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<8);
-		
-    /* Setup the external match register */
-    LPC_CT16B1->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(2<<EMC0)|(1<<3)|(match_enable);
-		
-    /* Setup the outputs */
-    /* If match0 is enabled, set the output */
-    set_timer16_match(timer_num, match_enable, 0 );
-		
-    /* Enable the selected PWMs and enable Match3 */
-    LPC_CT16B1->PWMC = (1<<3)|(match_enable);
-		
-    /* Setup the match registers */
-    /* set the period value to a global variable */
-    timer16_1_period 	= period;
-    LPC_CT16B1->MR3 	= timer16_1_period;
-    LPC_CT16B1->MR0	= timer16_1_period/2;
-    LPC_CT16B1->MR1	= timer16_1_period/2;
-    LPC_CT16B1->MR2	= timer16_1_period/2;
-		
-    /* Set match control register */
-    LPC_CT16B1->MCR = 1<<10;// | 1<<9;				/* Reset on MR3 */
-		
-    if (cap_enabled)
-    {
-	  /* Use location 0 for test. */
-	  set_timer16_capture( timer_num, 0 );
-      LPC_CT16B1->IR = 0xF;							/* clear interrupt flag */
-			
-      /* Set the capture control register */
-      LPC_CT16B1->CCR = 7;
-			
-    }
-    /* Enable the TIMER1 Interrupt */
-    NVIC_EnableIRQ(CT16B1_IRQn);
-  }
-  else
-  {
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<7);
-		
-    /* Setup the external match register */
-    LPC_CT16B0->EMR = (1<<EMC3)|(1<<EMC2)|(1<<EMC1)|(1<<EMC0)|(1<<3)|(match_enable);
-		
-    /* Setup the outputs */
-    /* If match0 is enabled, set the output */
-    set_timer16_match(timer_num, match_enable, 0 );
-			
-    /* Enable the selected PWMs and enable Match3 */
-    LPC_CT16B0->PWMC = (1<<3)|(match_enable);
-		
-    /* Setup the match registers */
-    /* set the period value to a global variable */
-    timer16_0_period = period;
-    LPC_CT16B0->MR3 = timer16_0_period;
-    LPC_CT16B0->MR0 = timer16_0_period/2;
-    LPC_CT16B0->MR1 = timer16_0_period/2;
-    LPC_CT16B0->MR2 = timer16_0_period/2;
-		
-    /* Set the match control register */
-    LPC_CT16B0->MCR = 1<<10;				/* Reset on MR3 */
-		
-    /* Enable the TIMER1 Interrupt */
-    NVIC_EnableIRQ(CT16B0_IRQn);
-  }
-}
-
-/******************************************************************************
-** Function name:		pwm16_setMatch
-**
-** Descriptions:		Set the pwm16 match values
-**
-** parameters:			timer number, match numner and the value
-**
-** Returned value:		None
-** 
-******************************************************************************/
-void setMatch_timer16PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
-{
-  if (timer_num)
-  {
-    switch (match_nr)
-    {
-      case 0:
-        LPC_CT16B1->MR0 = value;
-      break;
-      case 1: 
-        LPC_CT16B1->MR1 = value;
-      break;
-      case 2:
-        LPC_CT16B1->MR2 = value;
-      break;
-      case 3: 
-        LPC_CT16B1->MR3 = value;
-      break;
-      default:
-        break;
-    }	
-  }
-  else 
-  {
-    switch (match_nr)
-    {
-      case 0:
-        LPC_CT16B0->MR0 = value;
-      break;
-      case 1: 
-        LPC_CT16B0->MR1 = value;
-      break;
-      case 2:
-        LPC_CT16B0->MR2 = value;
-      break;
-      case 3: 
-        LPC_CT16B0->MR3 = value;
-      break;
-      default:
-      break;
-    }	
-  }
-}
-
-/******************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer32.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer32.c
deleted file mode 100644
index d201a8b96..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/timer32.c
+++ /dev/null
@@ -1,646 +0,0 @@
-/****************************************************************************
- *   $Id:: timer32.c 6951 2011-03-23 22:11:07Z usb00423                     $
- *   Project: NXP LPC13Uxx 32-bit timer example
- *
- *   Description:
- *     This file contains 32-bit timer code example which include timer 
- *     initialization, timer interrupt handler, and related APIs for 
- *     timer setup.
- *
- ****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-****************************************************************************/
-#include "LPC13Uxx.h"
-#include "timer32.h"
-#include "nmi.h"
-
-volatile uint32_t timer32_0_counter[4] = {0,0,0,0};
-volatile uint32_t timer32_1_counter[4] = {0,0,0,0};
-volatile uint32_t timer32_0_capture[4] = {0,0,0,0};
-volatile uint32_t timer32_1_capture[4] = {0,0,0,0};
-volatile uint32_t timer32_0_period = 0;
-volatile uint32_t timer32_1_period = 0;
-
-/*****************************************************************************
-** Function name:		delay32Ms
-**
-** Descriptions:		Start the timer delay in milo seconds
-**						until elapsed
-**
-** parameters:			timer number, Delay value in milo second			 
-** 						
-** Returned value:		None
-** 
-*****************************************************************************/
-void delay32Ms(uint8_t timer_num, uint32_t delayInMs)
-{
-  if (timer_num == 0)
-  {
-    /* setup timer #0 for delay */
-    LPC_CT32B0->TCR = 0x02;		/* reset timer */
-    LPC_CT32B0->PR  = 0x00;		/* set prescaler to zero */
-    LPC_CT32B0->MR0 = delayInMs * (SystemCoreClock / 1000);
-    LPC_CT32B0->IR  = 0xff;		/* reset all interrrupts */
-    LPC_CT32B0->MCR = 0x04;		/* stop timer on match */
-    LPC_CT32B0->TCR = 0x01;		/* start timer */
-  
-    /* wait until delay time has elapsed */
-    while (LPC_CT32B0->TCR & 0x01);
-  }
-  else if (timer_num == 1)
-  {
-    /* setup timer #1 for delay */
-    LPC_CT32B1->TCR = 0x02;		/* reset timer */
-    LPC_CT32B1->PR  = 0x00;		/* set prescaler to zero */
-    LPC_CT32B1->MR0 = delayInMs * (SystemCoreClock / 1000);
-    LPC_CT32B1->IR  = 0xff;		/* reset all interrrupts */
-    LPC_CT32B1->MCR = 0x04;		/* stop timer on match */
-    LPC_CT32B1->TCR = 0x01;		/* start timer */
-  
-    /* wait until delay time has elapsed */
-    while (LPC_CT32B1->TCR & 0x01);
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		CT32B0_IRQHandler
-**
-** Descriptions:		Timer/CounterX and captureX interrupt handler
-**
-** parameters:			None
-** Returned value:		None
-** 
-******************************************************************************/
-void CT32B0_IRQHandler(void)
-{
-  if ( LPC_CT32B0->IR & (0x01<<0) )
-  {  
-	LPC_CT32B0->IR = 0x1<<0;			/* clear interrupt flag */
-	timer32_0_counter[0]++;
-  }
-  if ( LPC_CT32B0->IR & (0x01<<1) )
-  {  
-	LPC_CT32B0->IR = 0x1<<1;			/* clear interrupt flag */
-	timer32_0_counter[1]++;
-  }
-  if ( LPC_CT32B0->IR & (0x01<<2) )
-  {  
-	LPC_CT32B0->IR = 0x1<<2;			/* clear interrupt flag */
-	timer32_0_counter[2]++;
-  }
-  if ( LPC_CT32B0->IR & (0x01<<3) )
-  {  
-	LPC_CT32B0->IR = 0x1<<3;			/* clear interrupt flag */
-	timer32_0_counter[3]++;
-  }
-  if ( LPC_CT32B0->IR & (0x1<<4) )
-  {  
-	LPC_CT32B0->IR = 0x1<<4;			/* clear interrupt flag */
-	timer32_0_capture[0]++;
-  }
-  if ( LPC_CT32B0->IR & (0x1<<5) )
-  {  
-	LPC_CT32B0->IR = 0x1<<5;			/* clear interrupt flag */
-	timer32_0_capture[1]++;
-  }
-  if ( LPC_CT32B0->IR & (0x1<<6) )
-  {  
-	LPC_CT32B0->IR = 0x1<<6;			/* clear interrupt flag */
-	timer32_0_capture[2]++;
-  }
-  if ( LPC_CT32B0->IR & (0x1<<7) )
-  {  
-	LPC_CT32B0->IR = 0x1<<7;			/* clear interrupt flag */
-	timer32_0_capture[3]++;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		CT32B1_IRQHandler
-**
-** Descriptions:		Timer/CounterX and captureX interrupt handler
-**
-** parameters:			None
-** Returned value:		None
-** 
-******************************************************************************/
-void CT32B1_IRQHandler(void)
-{
-  if ( LPC_CT32B1->IR & (0x01<<0) )
-  {  
-	LPC_CT32B1->IR = 0x1<<0;			/* clear interrupt flag */
-	timer32_1_counter[0]++;
-  }
-  if ( LPC_CT32B1->IR & (0x01<<1) )
-  {  
-	LPC_CT32B1->IR = 0x1<<1;			/* clear interrupt flag */
-	timer32_1_counter[1]++;
-  }
-  if ( LPC_CT32B1->IR & (0x01<<2) )
-  {  
-	LPC_CT32B1->IR = 0x1<<2;			/* clear interrupt flag */
-	timer32_1_counter[2]++;
-  }
-  if ( LPC_CT32B1->IR & (0x01<<3) )
-  {  
-	LPC_CT32B1->IR = 0x1<<3;			/* clear interrupt flag */
-	timer32_1_counter[3]++;
-  }
-  if ( LPC_CT32B1->IR & (0x1<<4) )
-  {  
-	LPC_CT32B1->IR = 0x1<<4;			/* clear interrupt flag */
-	timer32_1_capture[0]++;
-  }
-  if ( LPC_CT32B1->IR & (0x1<<5) )
-  {  
-	LPC_CT32B1->IR = 0x1<<5;			/* clear interrupt flag */
-	timer32_1_capture[1]++;
-  }
-  if ( LPC_CT32B1->IR & (0x1<<6) )
-  {  
-	LPC_CT32B1->IR = 0x1<<6;			/* clear interrupt flag */
-	timer32_1_capture[2]++;
-  }
-  if ( LPC_CT32B1->IR & (0x1<<7) )
-  {  
-	LPC_CT32B1->IR = 0x1<<7;			/* clear interrupt flag */
-	timer32_1_capture[3]++;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		enable_timer
-**
-** Descriptions:		Enable timer
-**
-** parameters:			timer number: 0 or 1
-** Returned value:		None
-** 
-******************************************************************************/
-void enable_timer32(uint8_t timer_num)
-{
-  if ( timer_num == 0 )
-  {
-    LPC_CT32B0->TCR = 1;
-  }
-  else
-  {
-    LPC_CT32B1->TCR = 1;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		disable_timer
-**
-** Descriptions:		Disable timer
-**
-** parameters:			timer number: 0 or 1
-** Returned value:		None
-** 
-******************************************************************************/
-void disable_timer32(uint8_t timer_num)
-{
-  if ( timer_num == 0 )
-  {
-    LPC_CT32B0->TCR = 0;
-  }
-  else
-  {
-    LPC_CT32B1->TCR = 0;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		reset_timer
-**
-** Descriptions:		Reset timer
-**
-** parameters:			timer number: 0 or 1
-** Returned value:		None
-** 
-******************************************************************************/
-void reset_timer32(uint8_t timer_num)
-{
-  uint32_t regVal;
-
-  if ( timer_num == 0 )
-  {
-    regVal = LPC_CT32B0->TCR;
-    regVal |= 0x02;
-    LPC_CT32B0->TCR = regVal;
-  }
-  else
-  {
-    regVal = LPC_CT32B1->TCR;
-    regVal |= 0x02;
-    LPC_CT32B1->TCR = regVal;
-  }
-  return;
-}
-
-/******************************************************************************
-** Function name:		set_timer_capture
-**
-** Descriptions:		Set timer capture based on location
-**
-** parameters:			timer number: 0~1, location 0~2
-** Returned value:		None
-** 
-******************************************************************************/
-void set_timer32_capture(uint8_t timer_num, uint8_t location )
-{
-  if ( timer_num == 0 )
-  {
-	/*  Timer0_32 I/O config */
-	if ( location == 0 )
-	{
-	  LPC_IOCON->PIO1_28          &= ~0x07;
-	  LPC_IOCON->PIO1_28          |= 0x01;		/* Timer0_32 CAP0 */
-	  LPC_IOCON->PIO1_29          &= ~0x07;
-	  LPC_IOCON->PIO1_29          |= 0x02;		/* Timer0_32 CAP2 */
-	}
-	else if ( location == 1 )
-	{
-	  LPC_IOCON->PIO0_17          &= ~0x07;
-	  LPC_IOCON->PIO0_17          |= 0x02;		/* Timer0_32 CAP0 */
-	}
-	else
-	{
-	  while ( 1 );				/* Fatal location number error */
-	}
-  }
-  else
-  {
-	/*  Timer1_32 I/O config */
-	if ( location == 0 )
-	{
-	  LPC_IOCON->PIO1_4           &= ~0x07;		/*  Timer1_32 I/O config */
-	  LPC_IOCON->PIO1_4           |= 0x01;		/* Timer1_32 CAP0 */
-	  LPC_IOCON->PIO1_5           &= ~0x07;
-	  LPC_IOCON->PIO1_5           |= 0x01;		/* Timer1_32 CAP1 */
-	}
-	else if ( location == 1 )
-	{
-	  LPC_IOCON->TMS_PIO0_12        &= ~0x07;
-	  LPC_IOCON->TMS_PIO0_12        |= 0x03;		/* Timer1_32 CAP0 */
-	}
-	else
-	{
-	  while ( 1 );				/* Fatal location number error */
-	}
-  }	
-  return;
-}
-
-/******************************************************************************
-** Function name:		set_timer_match
-**
-** Descriptions:		Set timer match based on location
-**
-** parameters:			timer number: 0~1, location 0~2
-** Returned value:		None
-** 
-******************************************************************************/
-void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location)
-{
-  if ( timer_num == 0 )
-  {
-	if ( match_enable & 0x01 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_18           &= ~0x07;	
-		LPC_IOCON->PIO0_18           |= 0x02;		/* Timer0_32 MAT0 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_24           &= ~0x07;
-		LPC_IOCON->PIO1_24           |= 0x01;		/* Timer0_32 MAT0 */
-	  }
-	}
-	if ( match_enable & 0x02 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_19           &= ~0x07;
-		LPC_IOCON->PIO0_19           |= 0x02;		/* Timer0_32 MAT1 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_25           &= ~0x07;
-		LPC_IOCON->PIO1_25           |= 0x01;		/* Timer0_32 MAT1 */
-	  }
-	}
-	if ( match_enable & 0x04 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO0_1            &= ~0x07;
-		LPC_IOCON->PIO0_1            |= 0x02;		/* Timer0_32 MAT2 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_26           &= ~0x07;
-		LPC_IOCON->PIO1_26           |= 0x01;		/* Timer0_32 MAT2 */
-	  }
-	}
-	if ( match_enable & 0x08 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->TDI_PIO0_11       &= ~0x07;
-		LPC_IOCON->TDI_PIO0_11       |= 0x03;		/* Timer0_32 MAT3 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO1_27           &= ~0x07;
-		LPC_IOCON->PIO1_27           |= 0x01;		/* Timer0_32 MAT3 */
-	  }
-	}
-  }
-  else if ( timer_num == 1 )
-  {
-	if ( match_enable & 0x01 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO1_0            &= ~0x07;
-		LPC_IOCON->PIO1_0            |= 0x01;		/* Timer1_32 MAT0 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->TDO_PIO0_13       &= ~0x07;
-		LPC_IOCON->TDO_PIO0_13       |= 0x03;		/* Timer1_32 MAT0 */
-	  }
-	}
-	if ( match_enable & 0x02 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO1_1            &= ~0x07;
-		LPC_IOCON->PIO1_1            |= 0x01;		/* Timer1_32 MAT1 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->TRST_PIO0_14      &= ~0x07;
-		LPC_IOCON->TRST_PIO0_14      |= 0x03;		/* Timer1_32 MAT1 */
-	  }
-	}
-	if ( match_enable & 0x04 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO1_2            &= ~0x07;
-		LPC_IOCON->PIO1_2            |= 0x01;		/* Timer1_32 MAT2 */
-	  }
-	  else if ( location == 1 )
-	  {
-#if __SWD_DISABLED
-		LPC_IOCON->SWDIO_PIO0_15     &= ~0x07;
-		LPC_IOCON->SWDIO_PIO0_15     |= 0x03;		/* Timer1_32 MAT2 */
-#endif
-	  }
-	}
-	if ( match_enable & 0x08 )
-	{
-	  if ( location == 0 )
-	  {
-		LPC_IOCON->PIO1_3            &= ~0x07;
-		LPC_IOCON->PIO1_3            |= 0x01;		/* Timer1_32 MAT3 */
-	  }
-	  else if ( location == 1 )
-	  {
-		LPC_IOCON->PIO0_16           &= ~0x07;
-		LPC_IOCON->PIO0_16           |= 0x02;		/* Timer1_32 MAT3 */
-	  }
-	}
-  }
-  return;		
-}
-
-/******************************************************************************
-** Function name:		init_timer
-**
-** Descriptions:		Initialize timer, set timer interval, reset timer,
-**				install timer interrupt handler
-**
-** parameters:		timer number and timer interval
-** Returned value:	None
-** 
-******************************************************************************/
-void init_timer32(uint8_t timer_num, uint32_t TimerInterval) 
-{
-  uint32_t i;
-
-  if ( timer_num == 0 )
-  {
-    /* Some of the I/O pins need to be clearfully planned if
-    you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
-
-    LPC_CT32B0->MR0 = TimerInterval;
-#if TIMER_MATCH
-  	for ( i = 0; i < 4; i++ )
-	{
-      timer32_0_counter[i] = 0;
-	}
-    set_timer32_match(timer_num, 0x0F, 0);
-	LPC_CT32B0->EMR &= ~(0xFF<<4);
-	LPC_CT32B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10));	/* MR0/1/2/3 Toggle */
-#else
-  	for ( i = 0; i < 4; i++ )
-	{
-      timer32_0_capture[i] = 0;
-	}
-	set_timer32_capture(timer_num, 0 );
-	/* Capture 0 on rising edge, interrupt enable. */
-	LPC_CT32B0->CCR = (0x5<<0)|(0x5<<6);
-#endif
- 	LPC_CT32B0->MCR = 3;			/* Interrupt and Reset on MR0 */
-
-    /* Enable the TIMER0 Interrupt */
-#if NMI_ENABLED
-    NVIC_DisableIRQ( CT32B0_IRQn );
-	NMI_Init( CT32B0_IRQn );
-#else
-    NVIC_EnableIRQ(CT32B0_IRQn);
-#endif
-  }
-  else if ( timer_num == 1 )
-  {
-    /* Some of the I/O pins need to be clearfully planned if
-    you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
-
-    LPC_CT32B1->MR0 = TimerInterval;
-#if TIMER_MATCH
-    for ( i = 0; i < 4; i++ )
-	{
-      timer32_1_counter[i] = 0;
-	}
-	set_timer32_match(timer_num, 0x0F, 0);
-	LPC_CT32B1->EMR &= ~(0xFF<<4);
-	LPC_CT32B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10));	/* MR0/1/2 Toggle */
-#else
-  	for ( i = 0; i < 4; i++ )
-	{
-      timer32_1_capture[i] = 0;
-	}
-	set_timer32_capture(timer_num, 0 );
-	/* Capture 0 on rising edge, interrupt enable. */
-	LPC_CT32B1->CCR = (0x5<<0)|(0x5<<3);
-#endif
-    LPC_CT32B1->MCR = 3;			/* Interrupt and Reset on MR0 */
-
-    /* Enable the TIMER1 Interrupt */
-#if NMI_ENABLED
-    NVIC_DisableIRQ( CT32B1_IRQn );
-	NMI_Init( CT32B1_IRQn );
-#else
-    NVIC_EnableIRQ(CT32B1_IRQn);
-#endif
-  }
-  return;
-}
-/******************************************************************************
-** Function name:		init_timer32PWM
-**
-** Descriptions:		Initialize timer as PWM
-**
-** parameters:			timer number, period and match enable:
-**						match_enable[0] = PWM for MAT0 
-**						match_enable[1] = PWM for MAT1
-**						match_enable[2] = PWM for MAT2
-** Returned value:		None
-** 
-******************************************************************************/
-void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable)
-{
-  disable_timer32(timer_num);
-  if (timer_num == 1)
-  {
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
-
-    /* Setup the external match register */
-    LPC_CT32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
-
-    /* Setup the outputs */
-    /* If match0 is enabled, set the output, use location 0 for test. */
-	set_timer32_match( timer_num, match_enable, 0 );
-
-    /* Enable the selected PWMs and enable Match3 */
-    LPC_CT32B1->PWMC = MATCH3|(match_enable);
- 
-    /* Setup the match registers */
-    /* set the period value to a global variable */
-    timer32_1_period = period;
-    LPC_CT32B1->MR3 = timer32_1_period;
-    LPC_CT32B1->MR0 = timer32_1_period/2;
-    LPC_CT32B1->MR1 = timer32_1_period/2;
-    LPC_CT32B1->MR2 = timer32_1_period/2;
-    LPC_CT32B1->MCR = 1<<10;				/* Reset on MR3 */
-  }
-  else
-  {
-    /* Some of the I/O pins need to be clearfully planned if
-    you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
-
-    /* Setup the external match register */
-    LPC_CT32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
- 
-    /* Setup the outputs */
-    /* If match0 is enabled, set the output, use location 0 for test. */
-	set_timer32_match( timer_num, match_enable, 0 );
-
-    /* Enable the selected PWMs and enable Match3 */
-    LPC_CT32B0->PWMC = MATCH3|(match_enable);
-
-    /* Setup the match registers */
-    /* set the period value to a global variable */
-    timer32_0_period = period;
-    LPC_CT32B0->MR3 = timer32_0_period;
-    LPC_CT32B0->MR0 = timer32_0_period/2;
-    LPC_CT32B0->MR1 = timer32_0_period/2;
-    LPC_CT32B0->MR2 = timer32_0_period/2;
-    LPC_CT32B0->MCR = 1<<10;				/* Reset on MR3 */
-  }
-}
-
-/******************************************************************************
-** Function name:		pwm32_setMatch
-**
-** Descriptions:		Set the pwm32 match values
-**
-** parameters:			timer number, match numner and the value
-**
-** Returned value:		None
-** 
-******************************************************************************/
-void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value)
-{
-  if (timer_num)
-  {
-    switch (match_nr)
-    {
-      case 0:
-        LPC_CT32B1->MR0 = value;
-      break;
-      case 1: 
-        LPC_CT32B1->MR1 = value;
-      break;
-      case 2:
-        LPC_CT32B1->MR2 = value;
-      break;
-      case 3: 
-        LPC_CT32B1->MR3 = value;
-      break;
-      default:
-      break;
-    }	
-  }
-  else 
-  {
-    switch (match_nr)
-    {
-      case 0:
-        LPC_CT32B0->MR0 = value;
-      break;
-      case 1: 
-        LPC_CT32B0->MR1 = value;
-      break;
-      case 2:
-        LPC_CT32B0->MR2 = value;
-      break;
-      case 3: 
-        LPC_CT32B0->MR3 = value;
-      break;
-      default:
-      break;
-    }	
-  }
-}
-
-/******************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/uart.c b/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/uart.c
deleted file mode 100644
index 80e32ab7a..000000000
--- a/hw/mcu/nxp/lpc13xx/LPC13Uxx_DriverLib/src/uart.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/****************************************************************************
- *   $Id:: uart.c 7125 2011-04-15 00:22:12Z usb01267                        $
- *   Project: NXP LPC13Uxx UART example
- *
- *   Description:
- *     This file contains UART code example which include UART
- *     initialization, UART interrupt handler, and related APIs for
- *     UART access.
- *
- ****************************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-****************************************************************************/
-#include "LPC13Uxx.h"
-#include "type.h"
-#include "uart.h"
-
-volatile uint32_t UARTStatus;
-volatile uint8_t  UARTTxEmpty = 1;
-volatile uint8_t  UARTBuffer[BUFSIZE];
-volatile uint32_t UARTCount = 0;
-
-#if AUTOBAUD_ENABLE
-volatile uint32_t UARTAutoBaud = 0, AutoBaudTimeout = 0;
-#endif
-
-/*****************************************************************************
-** Function name:		USART_IRQHandler
-**
-** Descriptions:		USART interrupt handler
-**
-** parameters:			None
-** Returned value:		None
-**
-*****************************************************************************/
-void USART_IRQHandler(void)
-{
-  uint8_t IIRValue, LSRValue;
-  uint8_t Dummy = Dummy;
-
-  IIRValue = LPC_USART->IIR;
-
-  IIRValue >>= 1;			/* skip pending bit in IIR */
-  IIRValue &= 0x07;			/* check bit 1~3, interrupt identification */
-  if (IIRValue == IIR_RLS)		/* Receive Line Status */
-  {
-    LSRValue = LPC_USART->LSR;
-    /* Receive Line Status */
-    if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI))
-    {
-      /* There are errors or break interrupt */
-      /* Read LSR will clear the interrupt */
-      UARTStatus = LSRValue;
-      Dummy = LPC_USART->RBR;	/* Dummy read on RX to clear
-								interrupt, then bail out */
-      return;
-    }
-    if (LSRValue & LSR_RDR)	/* Receive Data Ready */
-    {
-      /* If no error on RLS, normal ready, save into the data buffer. */
-      /* Note: read RBR will clear the interrupt */
-      UARTBuffer[UARTCount++] = LPC_USART->RBR;
-      if (UARTCount == BUFSIZE)
-      {
-        UARTCount = 0;		/* buffer overflow */
-      }
-    }
-  }
-  else if (IIRValue == IIR_RDA)	/* Receive Data Available */
-  {
-    /* Receive Data Available */
-    UARTBuffer[UARTCount++] = LPC_USART->RBR;
-    if (UARTCount == BUFSIZE)
-    {
-      UARTCount = 0;		/* buffer overflow */
-    }
-  }
-  else if (IIRValue == IIR_CTI)	/* Character timeout indicator */
-  {
-    /* Character Time-out indicator */
-    UARTStatus |= 0x100;		/* Bit 9 as the CTI error */
-  }
-  else if (IIRValue == IIR_THRE)	/* THRE, transmit holding register empty */
-  {
-    /* THRE interrupt */
-    LSRValue = LPC_USART->LSR;		/* Check status in the LSR to see if
-								valid data in U0THR or not */
-    if (LSRValue & LSR_THRE)
-    {
-      UARTTxEmpty = 1;
-    }
-    else
-    {
-      UARTTxEmpty = 0;
-    }
-  }
-#if AUTOBAUD_ENABLE
-  if (LPC_USART->IIR & IIR_ABEO) /* End of Auto baud */
-  {
-	LPC_USART->IER &= ~IIR_ABEO;
-	/* clear bit ABEOInt in the IIR by set ABEOIntClr in the ACR register */
-	LPC_USART->ACR |= IIR_ABEO;
-	UARTAutoBaud = 1;
-  }
-  else if (LPC_USART->IIR & IIR_ABTO)/* Auto baud time out */
-  {
-	LPC_USART->IER &= ~IIR_ABTO;
-	AutoBaudTimeout = 1;
-	/* clear bit ABTOInt in the IIR by set ABTOIntClr in the ACR register */
-	LPC_USART->ACR |= IIR_ABTO;
-  }
-#endif
-  return;
-}
-
-#if MODEM_TEST
-/*****************************************************************************
-** Function name:		ModemInit
-**
-** Descriptions:		Initialize UART0 port as modem, setup pin select.
-**
-** parameters:			None
-** Returned value:		None
-**
-*****************************************************************************/
-void ModemInit( void )
-{
-
-  LPC_IOCON->PIO0_7 &= ~0x07;     /* UART I/O config */
-  LPC_IOCON->PIO0_7 |= 0x01;      /* UART CTS */
-  LPC_IOCON->PIO0_17 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO0_17 |= 0x01;     /* UART RTS */
-#if 1
-  LPC_IOCON->PIO1_13 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_13 |= 0x01;     /* UART DTR */
-  LPC_IOCON->PIO1_14 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_14 |= 0x01;     /* UART DSR */
-  LPC_IOCON->PIO1_15 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_15 |= 0x01;     /* UART DCD */
-  LPC_IOCON->PIO1_16 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_16 |= 0x01;     /* UART RI */
-
-#else
-  LPC_IOCON->PIO1_19 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_19 |= 0x01;     /* UART DTR */
-  LPC_IOCON->PIO1_20 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_20 |= 0x01;     /* UART DSR */
-  LPC_IOCON->PIO1_21 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_21 |= 0x01;     /* UART DCD */
-  LPC_IOCON->PIO1_22 &= ~0x07;    /* UART I/O config */
-  LPC_IOCON->PIO1_22 |= 0x01;     /* UART RI */
-#endif
-  LPC_USART->MCR = 0xC0;          /* Enable Auto RTS and Auto CTS. */
-  return;
-}
-#endif
-
-/***********************************************************************
- *
- * Function: uart_set_divisors
- *
- * Purpose: Determines best dividers to get a target clock rate
- *
- * Processing:
- *     See function.
- *
- * Parameters:
- *     UARTClk    : UART clock
- *     baudrate   : Desired UART baud rate
- *
- * Outputs:
- *	  baudrate : Sets the estimated buadrate value in DLL, DLM, and FDR.
- *
- * Returns: Error status.
- *
- * Notes: None
- *
- **********************************************************************/
-uint32_t uart_set_divisors(uint32_t UARTClk, uint32_t baudrate)
-{
-  uint32_t uClk;
-  uint32_t calcBaudrate = 0;
-  uint32_t temp = 0;
-
-  uint32_t mulFracDiv, dividerAddFracDiv;
-  uint32_t diviser = 0 ;
-  uint32_t mulFracDivOptimal = 1;
-  uint32_t dividerAddOptimal = 0;
-  uint32_t diviserOptimal = 0;
-
-  uint32_t relativeError = 0;
-  uint32_t relativeOptimalError = 100000;
-
-  /* get UART block clock */
-  uClk = UARTClk >> 4; /* div by 16 */
-  /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
-   * The formula is :
-   * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
-   * It involves floating point calculations. That's the reason the formulae are adjusted with
-   * Multiply and divide method.*/
-  /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
-   * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
-  for (mulFracDiv = 1; mulFracDiv <= 15; mulFracDiv++)
-  {
-    for (dividerAddFracDiv = 0; dividerAddFracDiv <= 15; dividerAddFracDiv++)
-    {
-      temp = (mulFracDiv * uClk) / ((mulFracDiv + dividerAddFracDiv));
-      diviser = temp / baudrate;
-      if ((temp % baudrate) > (baudrate / 2))
-        diviser++;
-
-      if (diviser > 2 && diviser < 65536)
-      {
-        calcBaudrate = temp / diviser;
-
-        if (calcBaudrate <= baudrate)
-          relativeError = baudrate - calcBaudrate;
-        else
-          relativeError = calcBaudrate - baudrate;
-
-        if ((relativeError < relativeOptimalError))
-        {
-          mulFracDivOptimal = mulFracDiv ;
-          dividerAddOptimal = dividerAddFracDiv;
-          diviserOptimal = diviser;
-          relativeOptimalError = relativeError;
-          if (relativeError == 0)
-            break;
-        }
-      } /* End of if */
-    } /* end of inner for loop */
-    if (relativeError == 0)
-      break;
-  } /* end of outer for loop  */
-
-  if (relativeOptimalError < (baudrate / 30))
-  {
-    /* Set the `Divisor Latch Access Bit` and enable so the DLL/DLM access*/
-    /* Initialise the `Divisor latch LSB` and `Divisor latch MSB` registers */
-    LPC_USART->DLM = (diviserOptimal >> 8) & 0xFF;
-    LPC_USART->DLL = diviserOptimal & 0xFF;
-
-    /* Initialise the Fractional Divider Register */
-    LPC_USART->FDR = ((mulFracDivOptimal & 0xF) << 4) | (dividerAddOptimal & 0xF);
-    return( TRUE );
-  }
-  return ( FALSE );
-}
-
-/*****************************************************************************
-** Function name:		UARTInit
-**
-** Descriptions:		Initialize UART0 port, setup pin select,
-**				clock, parity, stop bits, FIFO, etc.
-**
-** parameters:			UART baudrate
-** Returned value:		None
-**
-*****************************************************************************/
-void UARTInit(uint32_t baudrate)
-{
-#if !AUTOBAUD_ENABLE
-  uint32_t Fdiv;
-#endif
-  volatile uint32_t regVal;
-
-  UARTTxEmpty = 1;
-  UARTCount = 0;
-
-  NVIC_DisableIRQ(USART_IRQn);
-  /* Select only one location from below. */
-#if 1
-  LPC_IOCON->PIO0_18 &= ~0x07;    /*  UART I/O config */
-  LPC_IOCON->PIO0_18 |= 0x01;     /* UART RXD */
-  LPC_IOCON->PIO0_19 &= ~0x07;
-  LPC_IOCON->PIO0_19 |= 0x01;     /* UART TXD */
-#endif
-#if 0
-  LPC_IOCON->PIO1_14 &= ~0x07;    /*  UART I/O config */
-  LPC_IOCON->PIO1_14 |= 0x03;     /* UART RXD */
-  LPC_IOCON->PIO1_13 &= ~0x07;
-  LPC_IOCON->PIO1_13 |= 0x03;     /* UART TXD */
-#endif
-#if 0
-  LPC_IOCON->PIO1_17 &= ~0x07;    /*  UART I/O config */
-  LPC_IOCON->PIO1_17 |= 0x02;     /* UART RXD */
-  LPC_IOCON->PIO1_18 &= ~0x07;
-  LPC_IOCON->PIO1_18 |= 0x02;     /* UART TXD */
-#endif
-#if 0
-  LPC_IOCON->PIO1_26 &= ~0x07;    /*  UART I/O config */
-  LPC_IOCON->PIO1_26 |= 0x02;     /* UART RXD */
-  LPC_IOCON->PIO1_27 &= ~0x07;
-  LPC_IOCON->PIO1_27 |= 0x02;     /* UART TXD */
-#endif
-
-  /* Enable UART clock */
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
-  LPC_SYSCON->UARTCLKDIV = 0x1;     /* divided by 1 */
-
-  LPC_USART->LCR = 0x83;            /* 8 bits, no Parity, 1 Stop bit */
-#if !AUTOBAUD_ENABLE
-#if FDR_CALIBRATION
-	if ( uart_set_divisors(SystemCoreClock/LPC_SYSCON->UARTCLKDIV, baudrate) != TRUE )
-	{
-      Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ;	/*baud rate */
-      LPC_USART->DLM = Fdiv / 256;
-      LPC_USART->DLL = Fdiv % 256;
-	  LPC_USART->FDR = 0x10;		/* Default */
-	}
-#else
-    Fdiv = ((SystemCoreClock/LPC_SYSCON->UARTCLKDIV)/16)/baudrate ;	/*baud rate */
-    LPC_USART->DLM = Fdiv / 256;
-    LPC_USART->DLL = Fdiv % 256;
-	LPC_USART->FDR = 0x10;		/* Default */
-#endif
-#endif
-  LPC_USART->LCR = 0x03;		/* DLAB = 0 */
-  LPC_USART->FCR = 0x07;		/* Enable and reset TX and RX FIFO. */
-
-  /* Read to clear the line status. */
-  regVal = LPC_USART->LSR;
-
-  /* Ensure a clean start, no data in either TX or RX FIFO. */
-  while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
-  while ( LPC_USART->LSR & LSR_RDR )
-  {
-	regVal = LPC_USART->RBR;	/* Dump data from RX FIFO */
-  }
-
-  /* Enable the UART Interrupt */
-  NVIC_EnableIRQ(USART_IRQn);
-
-#if TX_INTERRUPT
-  LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS;	/* Enable UART interrupt */
-#else
-  LPC_USART->IER = IER_RBR | IER_RLS;	/* Enable UART interrupt */
-#endif
-#if AUTOBAUD_ENABLE
-    LPC_USART->IER |= IER_ABEO | IER_ABTO;
-#endif
-  return;
-}
-
-/*****************************************************************************
-** Function name:		UARTSend
-**
-** Descriptions:		Send a block of data to the UART 0 port based
-**				on the data length
-**
-** parameters:		buffer pointer, and data length
-** Returned value:	None
-**
-*****************************************************************************/
-void UARTSend(uint8_t *BufferPtr, uint32_t Length)
-{
-
-  while ( Length != 0 )
-  {
-	  /* THRE status, contain valid data */
-#if !TX_INTERRUPT
-	  while ( !(LPC_USART->LSR & LSR_THRE) );
-	  LPC_USART->THR = *BufferPtr;
-#else
-	  /* Below flag is set inside the interrupt handler when THRE occurs. */
-      while ( !(UARTTxEmpty & 0x01) );
-	  LPC_USART->THR = *BufferPtr;
-      UARTTxEmpty = 0;	/* not empty in the THR until it shifts out */
-#endif
-      BufferPtr++;
-      Length--;
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		print_string
-**
-** Descriptions:		print out string on the terminal
-**
-** parameters:			pointer to the string end with NULL char.
-** Returned value:		none.
-**
-*****************************************************************************/
-void print_string( uint8_t *str_ptr )
-{
-  while(*str_ptr != 0x00)
-  {
-    while((LPC_USART->LSR & 0x60) != 0x60);
-    LPC_USART->THR = *str_ptr;
-    str_ptr++;
-  }
-  return;
-}
-
-/*****************************************************************************
-** Function name:		get_key
-**
-** Descriptions:		Get a character from the terminal
-**
-** parameters:			None
-** Returned value:		character, zero is none.
-**
-*****************************************************************************/
-uint8_t get_key( void )
-{
-  uint8_t dummy;
-
-  while ( !(LPC_USART->LSR & 0x01) );
-  dummy = LPC_USART->RBR;
-  if ((dummy>=65) && (dummy<=90))
-  {
-	/* convert capital to non-capital character, A2a, B2b, C2c. */
-	dummy +=32;
-  }
-  /* echo */
-  LPC_USART->THR = dummy;
-  return(dummy);
-}
-
-/******************************************************************************
-**                            End Of File
-******************************************************************************/
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.cproject b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.cproject
new file mode 100644
index 000000000..238c3e381
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.cproject
@@ -0,0 +1,191 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.crt.advproject.config.lib.debug.1695642511">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.lib.debug.1695642511" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/lpc_chip_13xx"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/lpc_chip_13xx/Debug"/>
+						<entry flags="RESOLVED" kind="libraryFile" name="lpc_chip_13xx" srcPrefixMapping="" srcRootPath=""/>
+					</externalSetting>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.lib.debug.1695642511" name="Debug" parent="com.crt.advproject.config.lib.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;lib${BuildArtifactFileName}&quot; ; # arm-none-eabi-objdump -h -S &quot;lib${BuildArtifactFileName}&quot; &gt;&quot;${BuildArtifactFileBaseName}.lss&quot;">
+					<folderInfo id="com.crt.advproject.config.lib.debug.1695642511." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.lib.debug.120581011" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.lib.debug">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.lib.debug.473621100" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.lib.debug"/>
+							<builder buildPath="${workspace_loc:/lpc_chip_13xx}/Debug" id="com.crt.advproject.builder.lib.debug.1315764688" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.lib.debug"/>
+							<tool id="com.crt.advproject.cpp.lib.debug.449530115" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.lib.debug"/>
+							<tool id="com.crt.advproject.gcc.lib.debug.1623980226" name="MCU C Compiler" superClass="com.crt.advproject.gcc.lib.debug">
+								<option id="com.crt.advproject.gcc.arch.389138896" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.thumb.61656502" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.gcc.hdrlib.1861262547" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.codered" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.552339960" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="__REDLIB__"/>
+									<listOptionValue builtIn="false" value="DEBUG"/>
+									<listOptionValue builtIn="false" value="__CODE_RED"/>
+									<listOptionValue builtIn="false" value="CORE_M3"/>
+								</option>
+								<option id="gnu.c.compiler.option.misc.other.1707277877" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections" valueType="string"/>
+								<option id="gnu.c.compiler.option.include.paths.934680239" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc}&quot;"/>
+								</option>
+								<inputType id="com.crt.advproject.compiler.input.1297500374" superClass="com.crt.advproject.compiler.input"/>
+							</tool>
+							<tool id="com.crt.advproject.gas.lib.debug.1213759179" name="MCU Assembler" superClass="com.crt.advproject.gas.lib.debug">
+								<option id="com.crt.advproject.gas.arch.2101888144" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm3" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.thumb.1092766685" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+								<option id="gnu.both.asm.option.flags.crt.1713070977" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
+								<option id="com.crt.advproject.gas.hdrlib.1580292679" name="Use headers for C library" superClass="com.crt.advproject.gas.hdrlib" value="com.crt.advproject.gas.hdrlib.codered" valueType="enumerated"/>
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.50165465" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+								<inputType id="com.crt.advproject.assembler.input.190511374" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+							</tool>
+							<tool id="com.crt.advproject.ar.lib.debug.1850004878" name="MCU Archiver" superClass="com.crt.advproject.ar.lib.debug"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="inc"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="usbd_rom"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.crt.advproject.config.lib.release.1609757260">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.lib.release.1609757260" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings>
+					<externalSetting>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/lpc_chip_13xx"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/lpc_chip_13xx/Release"/>
+						<entry flags="RESOLVED" kind="libraryFile" name="lpc_chip_13xx" srcPrefixMapping="" srcRootPath=""/>
+					</externalSetting>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="Release build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.lib.release.1609757260" name="Release" parent="com.crt.advproject.config.lib.release" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;lib${BuildArtifactFileName}&quot; ; # arm-none-eabi-objdump -h -S &quot;lib${BuildArtifactFileName}&quot; &gt;&quot;${BuildArtifactFileBaseName}.lss&quot;">
+					<folderInfo id="com.crt.advproject.config.lib.release.1609757260." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.lib.release.746798763" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.lib.release">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.lib.release.1300324823" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.lib.release"/>
+							<builder buildPath="${workspace_loc:/lpc_chip_13xx}/Release" id="com.crt.advproject.builder.lib.release.1753777091" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.lib.release"/>
+							<tool id="com.crt.advproject.cpp.lib.release.471884019" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.lib.release"/>
+							<tool id="com.crt.advproject.gcc.lib.release.362523454" name="MCU C Compiler" superClass="com.crt.advproject.gcc.lib.release">
+								<option id="com.crt.advproject.gcc.arch.302225597" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm3" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.thumb.337603171" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.gcc.hdrlib.1493675834" name="Use headers for C library" superClass="com.crt.advproject.gcc.hdrlib" value="com.crt.advproject.gcc.hdrlib.codered" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.1776219671" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="__REDLIB__"/>
+									<listOptionValue builtIn="false" value="NDEBUG"/>
+									<listOptionValue builtIn="false" value="__CODE_RED"/>
+									<listOptionValue builtIn="false" value="CORE_M3"/>
+								</option>
+								<option id="gnu.c.compiler.option.misc.other.596897297" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections" valueType="string"/>
+								<option id="gnu.c.compiler.option.include.paths.1557813074" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc}&quot;"/>
+								</option>
+								<option id="com.crt.advproject.gcc.lib.release.option.optimization.level.523992986" superClass="com.crt.advproject.gcc.lib.release.option.optimization.level" value="gnu.c.optimization.level.size" valueType="enumerated"/>
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+							</tool>
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+								<option id="com.crt.advproject.gas.thumb.2146598429" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+								<option id="gnu.both.asm.option.flags.crt.293768223" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DNDEBUG -D__CODE_RED" valueType="string"/>
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+							<tool id="com.crt.advproject.ar.lib.release.157189512" name="MCU Archiver" superClass="com.crt.advproject.ar.lib.release"/>
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+					</folderInfo>
+					<sourceEntries>
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+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="usbd_rom"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="lpc_chip_13xx.com.crt.advproject.projecttype.lib.547521942" name="Static Library" projectType="com.crt.advproject.projecttype.lib"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_3="NXP" property_4="LPC1347" property_count="5" version="60100"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC1347" flash_driver="LPC11_12_13_64K_8K.cfx" match_id="0x08020543" name="LPC1347" stub="crt_emu_lpc11_13_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC1347&lt;/name&gt;&#13;
+&lt;family&gt;LPC13xx (12bit ADC)&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
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+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash64" location="0x0" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RITIMER" determined="infoFile" id="RITIMER" location="0x40064000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc13Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+	</storageModule>
+</cproject>
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.project b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.project
new file mode 100644
index 000000000..4c3403c4c
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>lpc_chip_13xx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h
new file mode 100644
index 000000000..423581458
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/adc_13xx.h
@@ -0,0 +1,301 @@
+/*
+ * @brief  LPC13xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_13XX_H_
+#define __ADC_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ADC_13XX CHIP:  LPC13xx A/D conversion driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+#define ADC_ACC_12BITS
+#define ADC_TRIM_SUPPORT
+#else
+#define ADC_ACC_10BITS
+#endif
+
+#if defined(CHIP_LPC1347)
+#define ADC_MAX_SAMPLE_RATE 500000
+#else
+#define ADC_MAX_SAMPLE_RATE 400000
+#endif
+
+/**
+ * @brief 10 or 12-bit ADC register block structure
+ */
+typedef struct {					/*!< ADCn Structure */
+	__IO uint32_t CR;				/*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+	__I  uint32_t GDR;				/*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+	__I  uint32_t RESERVED0;
+	__IO uint32_t INTEN;			/*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+	__I  uint32_t DR[8];			/*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+	__I  uint32_t STAT;				/*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+#if defined(ADC_TRIM_SUPPORT)
+	__IO uint32_t ADTRM;
+#endif
+} LPC_ADC_T;
+
+/**
+ * @brief ADC register support bitfields and mask
+ */
+#if defined(ADC_ACC_12BITS)
+ #define ADC_DR_RESULT(n)        ((((n) >> 4) & 0xFFF))	/*!< Mask for getting the 12 bits ADC data read value */
+#else
+ #define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF))	/*!< Mask for getting the 10 bits ADC data read value */
+ #define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))	/*!< Number of ADC accuracy bits */
+#endif
+
+#define ADC_DR_DONE(n)          (((n) >> 31))			/*!< Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL)))	/*!< Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n)        ((1UL << (n)))			/*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))	/*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST            ((1UL << 16))			/*!< Repeated conversions A/D enable bit */
+#if defined(CHIP_LPC1347)
+#define ADC_CR_LPWRMODE         ((1UL << 22))			/*!<Enable the low-power ADC mode */
+#define ADC_CR_MODE10BIT        ((1UL << 23))			/*!<Enable the 10-bit conversion rate mode with high conversion rate. */
+#else
+#define ADC_CR_PDN              ((1UL << 21))			/*!< ADC convert is operational */
+#endif
+#define ADC_CR_START_MASK       ((7UL << 24))			/*!< ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))		/*!< Select Start Mode */
+#define ADC_CR_START_NOW        ((1UL << 24))			/*!< Start conversion now */
+#define ADC_CR_START_CTOUT15    ((2UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8     ((3UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0   ((4UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1   ((5UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2      ((6UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE             ((1UL << 27))			/*!< Start conversion on a falling edge on the selected CAP/MAT signal */
+#if defined(CHIP_LPC1347)
+#define ADC_SAMPLE_RATE_CONFIG_MASK         (ADC_CR_CLKDIV(0xFF) | ADC_CR_MODE10BIT)
+#else
+#define ADC_SAMPLE_RATE_CONFIG_MASK         (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
+#endif
+
+/**
+ * @brief	ADC status register used for IP drivers
+ */
+typedef enum IP_ADC_STATUS {
+	ADC_DR_DONE_STAT,	/*!< ADC data register staus */
+	ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
+	ADC_DR_ADINT_STAT	/*!< ADC interrupt status */
+} ADC_STATUS_T;
+
+/** The channels on one ADC peripheral*/
+typedef enum CHIP_ADC_CHANNEL {
+	ADC_CH0 = 0,	/**< ADC channel 0 */
+	ADC_CH1,		/**< ADC channel 1 */
+	ADC_CH2,		/**< ADC channel 2 */
+	ADC_CH3,		/**< ADC channel 3 */
+	ADC_CH4,		/**< ADC channel 4 */
+	ADC_CH5,		/**< ADC channel 5 */
+	ADC_CH6,		/**< ADC channel 6 */
+	ADC_CH7,		/**< ADC channel 7 */
+} ADC_CHANNEL_T;
+
+#if defined(CHIP_LPC1347)
+/** LPC1347 chip */
+typedef enum CHIP_ADC_RESOLUTION {
+	ADC_12BITS = 0,		/**< ADC 12 bits */
+	ADC_10BITS = 1,		/**< ADC 10 bits  */
+} ADC_RESOLUTION_T;
+#else
+/** The number of bits of accuracy of the result in the LS bits of ADDR*/
+typedef enum CHIP_ADC_RESOLUTION {
+	ADC_10BITS = 0,		/**< ADC 10 bits */
+	ADC_9BITS,			/**< ADC 9 bits  */
+	ADC_8BITS,			/**< ADC 8 bits  */
+	ADC_7BITS,			/**< ADC 7 bits  */
+	ADC_6BITS,			/**< ADC 6 bits  */
+	ADC_5BITS,			/**< ADC 5 bits  */
+	ADC_4BITS,			/**< ADC 4 bits  */
+	ADC_3BITS,			/**< ADC 3 bits  */
+} ADC_RESOLUTION_T;
+#endif
+
+/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
+typedef enum CHIP_ADC_EDGE_CFG {
+	ADC_TRIGGERMODE_RISING = 0,		/**< Trigger event: rising edge */
+	ADC_TRIGGERMODE_FALLING,		/**< Trigger event: falling edge */
+} ADC_EDGE_CFG_T;
+
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum CHIP_ADC_START_MODE {
+	ADC_NO_START = 0,
+	ADC_START_NOW,			/*!< Start conversion now */
+	ADC_START_ON_CTOUT15,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+	ADC_START_ON_CTOUT8,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+	ADC_START_ON_ADCTRIG0,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+	ADC_START_ON_ADCTRIG1,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+	ADC_START_ON_MCOA2		/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_START_MODE_T;
+
+/** Clock setup structure for ADC controller passed to the initialize function */
+typedef struct {
+	uint32_t adcRate;		/*!< ADC rate */
+	uint8_t  bitsAccuracy;	/*!< ADC bit accuracy */
+	bool     burstMode;		/*!< ADC Burt Mode */
+} ADC_CLOCK_SETUP_T;
+
+/**
+ * @brief	Initialize the ADC peripheral and the ADC setup structure to default value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be set
+ * @return	Nothing
+ * @note	Default setting for ADC is 400kHz - 10bits
+ */
+void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
+
+/**
+ * @brief	Shutdown ADC
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_ADC_DeInit(LPC_ADC_T *pADC);
+
+/**
+ * @brief	Read the ADC value from a channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	data		: Pointer to where to put data
+ * @return	SUCCESS or ERROR if no conversion is ready
+ */
+Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
+
+/**
+ * @brief	Read the ADC value and convert it to 8bits value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel:	selected channel
+ * @param	data		: Storage for data
+ * @return	Status	: ERROR or SUCCESS
+ */
+Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
+
+/**
+ * @brief	Read the ADC channel status
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	StatusType	: Status type of ADC_DR_*
+ * @return	SET or RESET
+ */
+FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
+
+/**
+ * @brief	Enable/Disable interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	SET or RESET
+ */
+void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
+
+/**
+ * @brief	Enable/Disable global interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
+{
+	Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
+}
+
+/**
+ * @brief	Select the mode starting the AD conversion
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	mode		: Stating mode, should be :
+ *							- ADC_NO_START				: Must be set for Burst mode
+ *							- ADC_START_NOW				: Start conversion now
+ *							- ADC_START_ON_CTOUT15		: Start conversion when the edge selected by bit 27 occurs on CTOUT_15
+ *							- ADC_START_ON_CTOUT8		: Start conversion when the edge selected by bit 27 occurs on CTOUT_8
+ *							- ADC_START_ON_ADCTRIG0		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
+ *							- ADC_START_ON_ADCTRIG1		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
+ *							- ADC_START_ON_MCOA2		: Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
+ * @param	EdgeOption	: Stating Edge Condition, should be :
+ *							- ADC_TRIGGERMODE_RISING	: Trigger event on rising edge
+ *							- ADC_TRIGGERMODE_FALLING	: Trigger event on falling edge
+ * @return	Nothing
+ */
+void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
+
+/**
+ * @brief	Set the ADC Sample rate
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	rate		: Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
+ * @return	Nothing
+ */
+void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
+
+/**
+ * @brief	Set the ADC accuracy bits
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	resolution	: The resolution, should be ADC_10BITS -> ADC_3BITS
+ * @return	Nothing
+ */
+void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution);
+
+/**
+ * @brief	Enable or disable the ADC channel on ADC peripheral
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel to be enable or disable
+ * @param	NewState	: New state, should be:
+ *								- ENABLE
+ *								- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
+
+/**
+ * @brief	Enable burst mode
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, should be:
+ *							- ENABLE
+ *							- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h
new file mode 100644
index 000000000..002cbef6b
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/chip.h
@@ -0,0 +1,243 @@
+/*
+ * @brief LPC13xx basic chip inclusion file
+ *
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef CORE_M3
+#error CORE_M3 is not defined for the LPC13xx architecture
+#error CORE_M3 should be defined as part of your compiler define list
+#endif
+
+#if !defined(CHIP_LPC1343) && !defined(CHIP_LPC1347)
+#error CHIP_LPC1343 or CHIP_LPC1347 is not defined!
+#endif
+
+/* Peripheral mapping per device
+   Peripheral					Device(s)
+   ----------------------------	------------------------------------------------------------------------------
+   I2C(40000000)				CHIP_LPC1343/CHIP_LPC1347
+   WDT(40004000)				CHIP_LPC1343/CHIP_LPC1347
+   TIMER0_16(4000C000)			CHIP_LPC1343/CHIP_LPC1347
+   TIMER1_16(40010000)			CHIP_LPC1343/CHIP_LPC1347
+   TIMER0_32(40014000)			CHIP_LPC1343/CHIP_LPC1347
+   TIMER1_32(40018000)			CHIP_LPC1343/CHIP_LPC1347
+   PMU(40038000)				CHIP_LPC1343/CHIP_LPC1347
+   FLASH_CTRL(4003C000)			CHIP_LPC1343/CHIP_LPC1347
+   SSP0(40040000)				CHIP_LPC1343/CHIP_LPC1347
+   IOCONF(40044000)				CHIP_LPC1343/CHIP_LPC1347
+   SYSCTL(40048000)				CHIP_LPC1343/CHIP_LPC1347
+   SSP1(40058000)				CHIP_LPC1347
+   ADC(4001C000)				CHIP_LPC1343/CHIP_LPC1347
+   UART(40008000)				CHIP_LPC1343 only
+   USB(40020000)				CHIP_LPC1343 only
+   GPIO_PORT(50000000)			CHIP_LPC1343 only
+   GPIO_PIO0(50000000)			CHIP_LPC1343 only
+   GPIO_PIO1(50010000)			CHIP_LPC1343 only
+   GPIO_PIO2(50020000)			CHIP_LPC1343 only
+   GPIO_PIO3(50030000)			CHIP_LPC1343 only
+   USART/SMARTCARD(40008000)	CHIP_LPC1347 only
+   FLASH_EEPROM(4003C000)		CHIP_LPC1347 only
+   GPIO_INT(4004C000)			CHIP_LPC1347 only
+   GPIO_GRP0_INT(4005C000)		CHIP_LPC1347 only
+   GPIO_GRP1_INT(40060000)		CHIP_LPC1347 only
+   RITIMER(40064000)			CHIP_LPC1347 only
+ */
+
+/** @defgroup PERIPH_13XX_BASE CHIP: LPC13xx Peripheral addresses and register set declarations
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#define LPC_I2C_BASE              0x40000000
+#define LPC_WWDT_BASE             0x40004000
+#define LPC_USART_BASE            0x40008000
+#define LPC_TIMER16_0_BASE        0x4000C000
+#define LPC_TIMER16_1_BASE        0x40010000
+#define LPC_TIMER32_0_BASE        0x40014000
+#define LPC_TIMER32_1_BASE        0x40018000
+#define LPC_ADC_BASE              0x4001C000
+#define LPC_PMU_BASE              0x40038000
+#define LPC_FLASH_BASE            0x4003C000
+#define LPC_SSP0_BASE             0x40040000
+#define LPC_SSP1_BASE             0x40058000
+#define LPC_IOCON_BASE            0x40044000
+#define LPC_SYSCTL_BASE           0x40048000
+#if defined(CHIP_LPC1347)
+#define LPC_GPIO_PIN_INT_BASE     0x4004C000
+#define LPC_GPIO_GROUP_INT0_BASE  0x4005C000
+#define LPC_GPIO_GROUP_INT1_BASE  0x40060000
+#define LPC_GPIO_PORT_BASE        0x50000000
+#define LPC_USB0_BASE             0x40080000
+#define LPC_RITIMER_BASE          0x40064000
+#define IAP_ENTRY_LOCATION        0X1FFF1FF1
+#define LPC_ROM_API_BASE_LOC      0x1FFF1FF8
+#else /*CHIP_LPC1343*/
+#define LPC_GPIO_PORT0_BASE       0x50000000
+#define LPC_GPIO_PORT1_BASE       0x50010000
+#define LPC_GPIO_PORT2_BASE       0x50020000
+#define LPC_GPIO_PORT3_BASE       0x50030000
+#define LPC_USB0_BASE             0x40020000
+#endif
+
+#define LPC_ADC                   ((LPC_ADC_T              *) LPC_ADC_BASE)
+#define LPC_I2C                   ((LPC_I2C_T              *) LPC_I2C_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_T             *) LPC_WWDT_BASE)
+#define LPC_USART                 ((LPC_USART_T            *) LPC_USART_BASE)
+#define LPC_TIMER16_0             ((LPC_TIMER_T            *) LPC_TIMER16_0_BASE)
+#define LPC_TIMER16_1             ((LPC_TIMER_T            *) LPC_TIMER16_1_BASE)
+#define LPC_TIMER32_0             ((LPC_TIMER_T            *) LPC_TIMER32_0_BASE)
+#define LPC_TIMER32_1             ((LPC_TIMER_T            *) LPC_TIMER32_1_BASE)
+#define LPC_PMU                   ((LPC_PMU_T              *) LPC_PMU_BASE)
+#define LPC_FMC                   ((LPC_FMC_T              *) LPC_FLASH_BASE)
+#define LPC_SSP0                  ((LPC_SSP_T              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSP_T              *) LPC_SSP1_BASE)
+#define LPC_IOCON                 ((LPC_IOCON_T            *) LPC_IOCON_BASE)
+#define LPC_SYSCTL                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE)
+#if defined(CHIP_LPC1347)
+#define LPC_PININT                ((LPC_PIN_INT_T          *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((LPC_GPIOGROUPINT_T     *) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((LPC_GPIOGROUPINT_T     *) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_GPIO_PORT             ((LPC_GPIO_T             *) LPC_GPIO_PORT_BASE)
+#define LPC_RITIMER               ((LPC_RITIMER_T          *) LPC_RITIMER_BASE)
+#define LPC_USB                   ((LPC_USB_T              *) LPC_USB0_BASE)
+#define LPC_ROM_API               (*((LPC_ROM_API_T        * *) LPC_ROM_API_BASE_LOC))
+#else
+#define LPC_GPIO_PORT             ((LPC_GPIO_T             *) LPC_GPIO_PORT0_BASE)
+#endif
+
+/**
+ * @}
+ */
+
+/** @ingroup CHIP_13XX_DRIVER_OPTIONS
+ * @{
+ */
+ 
+/**
+ * @brief	System oscillator rate
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the external oscillator for the board. If using the
+ * internal oscillator, this rate can be 0.
+ */
+extern const uint32_t OscRateIn;
+
+/**
+ * @brief	Clock rate on the CLKIN pin
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the CLKIN pin for the board. If this pin isn't used,
+ * this rate can be 0.
+ */
+extern const uint32_t ExtRateIn;
+
+/**
+ * @}
+ */
+
+#include "sysctl_13xx.h"
+#include "clock_13xx.h"
+#include "fmc_13xx.h"
+#include "iocon_13xx.h"
+#include "adc_13xx.h"
+#include "i2c_13xx.h"
+#include "i2cm_13xx.h"
+#include "pmu_13xx.h"
+#include "ssp_13xx.h"
+#include "timer_13xx.h"
+#include "uart_13xx.h"
+#include "wwdt_13xx.h"
+#include "flash_13xx.h"
+#if defined(CHIP_LPC1347)
+#include "gpio_13xx_1.h"
+#include "gpiogroup_13xx.h"
+#include "ritimer_13xx.h"
+#include "usbd_13xx.h"
+#include "romapi_13xx.h"
+#include "pinint_13xx.h"
+#else
+#include "gpio_13xx_2.h"
+#endif
+
+/** @defgroup SUPPORT_13XX_FUNC CHIP: LPC13xx support functions
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Current system clock rate, mainly used for sysTick
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	USB Pin and clock initialization
+ * Calling this function will initialize the USB pins and the clock
+ * @return	None
+ * @note	This function will assume that the chip is clocked by an
+ * external crystal oscillator of frequency 12MHz and the Oscillator
+ * is running.
+ */
+void Chip_USB_Init(void);
+
+/**
+* @brief	Clock and PLL initialization based on the external oscillator
+* @return	None
+* @note	This function assumes an external crystal oscillator
+* frequency of 12MHz.
+*/
+void Chip_SetupXtalClocking(void);
+
+/**
+* @brief	Clock and PLL initialization based on the internal oscillator
+* @return	None
+*/
+void Chip_SetupIrcClocking(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h
new file mode 100644
index 000000000..06fff25ca
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/clock_13xx.h
@@ -0,0 +1,518 @@
+/*
+ * @brief LPC13XX Clock control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CLOCK_13XX_H_
+#define __CLOCK_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CLOCK_13XX CHIP: LPC13xx Clock Control block driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+  
+/** @defgroup CLOCK_13XX_OPTIONS CHIP: LPC13xx Clock Control driver options
+ * @ingroup CHIP_13XX_DRIVER_OPTIONS CLOCK_13XX
+ * The clock driver has options that configure it's operation at build-time.<br>
+ *
+ * <b>CRYSTAL_MAIN_FREQ_IN</b><br>
+ * This define is the external crystal frequency used for the main oscillator.<br>
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** Internal oscillator frequency */
+#define SYSCTL_IRC_FREQ (12000000)
+
+/**
+ * @brief	Set System PLL divider values
+ * @param	msel    : PLL feedback divider value. M = msel + 1.
+ * @param	psel    : PLL post divider value. P =  (1<<psel).
+ * @return	Nothing
+ * @note	See the user manual for how to setup the PLL.
+ */
+STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
+{
+	LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
+}
+
+/**
+ * @brief	Read System PLL lock status
+ * @return	true of the PLL is locked. false if not locked
+ */
+STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
+{
+	return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
+}
+
+/**
+ * Clock sources for system and USB PLLs
+ */
+typedef enum CHIP_SYSCTL_PLLCLKSRC {
+	SYSCTL_PLLCLKSRC_IRC = 0,		/*!< Internal oscillator in */
+	SYSCTL_PLLCLKSRC_SYSOSC,		/*!< Crystal (main) oscillator in */
+	SYSCTL_PLLCLKSRC_RESERVED1,	/*!< Reserved */
+	SYSCTL_PLLCLKSRC_RESERVED2,	/*!< Reserved */
+} CHIP_SYSCTL_PLLCLKSRC_T;
+
+/**
+ * @brief	Set System PLL clock source
+ * @param	src	: Clock source for system PLL
+ * @return	Nothing
+ * @note	This function will also toggle the clock source update register
+ * to update the clock source.
+ */
+void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
+
+/**
+ * @brief	Set USB PLL divider values
+ * @param	msel    : PLL feedback divider value. M = msel + 1.
+ * @param	psel    : PLL post divider value. P = (1<<psel).
+ * @return	Nothing
+ * @note	See the user manual for how to setup the PLL.
+ */
+STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
+{
+	LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
+}
+
+/**
+ * @brief	Read USB PLL lock status
+ * @return	true of the PLL is locked. false if not locked
+ */
+STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
+{
+	return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
+}
+
+/**
+ * @brief	Set USB PLL clock source
+ * @param	src	: Clock source for USB PLL
+ * @return	Nothing
+ * @note	This function will also toggle the clock source update register
+ * to update the clock source.
+ */
+void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
+
+/**
+ * @brief	Bypass System Oscillator and set oscillator frequency range
+ * @param	bypass	: Flag to bypass oscillator
+ * @param	highfr	: Flag to set oscillator range from 15-25 MHz
+ * @return	Nothing
+ * @note	Sets the PLL input to bypass the oscillator. This would be
+ * used if an external clock that is not an oscillator is attached
+ * to the XTALIN pin.
+ */
+void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
+
+/**
+ * Watchdog and low frequency oscillator frequencies plus or minus 40%
+ */
+typedef enum CHIP_WDTLFO_OSC {
+	WDTLFO_OSC_ILLEGAL,
+	WDTLFO_OSC_0_60,	/*!< 0.6 MHz watchdog/LFO rate */
+	WDTLFO_OSC_1_05,	/*!< 1.05 MHz watchdog/LFO rate */
+	WDTLFO_OSC_1_40,	/*!< 1.4 MHz watchdog/LFO rate */
+	WDTLFO_OSC_1_75,	/*!< 1.75 MHz watchdog/LFO rate */
+	WDTLFO_OSC_2_10,	/*!< 2.1 MHz watchdog/LFO rate */
+	WDTLFO_OSC_2_40,	/*!< 2.4 MHz watchdog/LFO rate */
+	WDTLFO_OSC_2_70,	/*!< 2.7 MHz watchdog/LFO rate */
+	WDTLFO_OSC_3_00,	/*!< 3.0 MHz watchdog/LFO rate */
+	WDTLFO_OSC_3_25,	/*!< 3.25 MHz watchdog/LFO rate */
+	WDTLFO_OSC_3_50,	/*!< 3.5 MHz watchdog/LFO rate */
+	WDTLFO_OSC_3_75,	/*!< 3.75 MHz watchdog/LFO rate */
+	WDTLFO_OSC_4_00,	/*!< 4.0 MHz watchdog/LFO rate */
+	WDTLFO_OSC_4_20,	/*!< 4.2 MHz watchdog/LFO rate */
+	WDTLFO_OSC_4_40,	/*!< 4.4 MHz watchdog/LFO rate */
+	WDTLFO_OSC_4_60		/*!< 4.6 MHz watchdog/LFO rate */
+} CHIP_WDTLFO_OSC_T;
+
+/**
+ * @brief	Setup Watchdog oscillator rate and divider
+ * @param	wdtclk	: Selected watchdog clock rate
+ * @param	div		: Watchdog divider value, even value between 2 and 64
+ * @return	Nothing
+ * @note	Watchdog rate = selected rate divided by divider rate
+ */
+STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
+{
+	LPC_SYSCTL->WDTOSCCTRL  = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
+}
+
+/**
+ * Clock sources for main system clock
+ */
+typedef enum CHIP_SYSCTL_MAINCLKSRC {
+	SYSCTL_MAINCLKSRC_IRC = 0,		/*!< Internal oscillator */
+	SYSCTL_MAINCLKSRC_PLLIN,		/*!< System PLL input */
+	SYSCTL_MAINCLKSRC_WDTOSC,		/*!< Watchdog oscillator rate */
+	SYSCTL_MAINCLKSRC_PLLOUT,		/*!< System PLL output */
+} CHIP_SYSCTL_MAINCLKSRC_T;
+
+/**
+ * @brief	Set main system clock source
+ * @param	src	: Clock source for main system
+ * @return	Nothing
+ * @note	This function will also toggle the clock source update register
+ * to update the clock source.
+ */
+void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
+
+/**
+ * @brief   Returns the main clock source
+ * @return	Which clock is used for the core clock source?
+ */
+STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
+{
+	return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
+}
+
+/**
+ * @brief	Set system clock divider
+ * @param	div	: divider for system clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The system clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->SYSAHBCLKDIV  = div;
+}
+
+/**
+ * System and peripheral clocks
+ */
+typedef enum CHIP_SYSCTL_CLOCK {
+	SYSCTL_CLOCK_SYS = 0,				/*!< 0: System clock */
+	SYSCTL_CLOCK_ROM,					/*!<1:  ROM clock */
+	SYSCTL_CLOCK_RAM,					/*!< 2: RAM clock */
+	SYSCTL_CLOCK_FLASHREG,				/*!< 3: FLASH register interface clock */
+	SYSCTL_CLOCK_FLASHARRAY,			/*!< 4: FLASH array access clock */
+	SYSCTL_CLOCK_I2C,					/*!< 5: I2C clock */
+	SYSCTL_CLOCK_GPIO,					/*!< 6: GPIO clock */
+	SYSCTL_CLOCK_CT16B0,				/*!< 7: 16-bit Counter/timer 0 clock */
+	SYSCTL_CLOCK_CT16B1,				/*!< 8: 16-bit Counter/timer 1 clock */
+	SYSCTL_CLOCK_CT32B0,				/*!< 9: 32-bit Counter/timer 0 clock */
+	SYSCTL_CLOCK_CT32B1,				/*!< 10: 32-bit Counter/timer 1 clock */
+	SYSCTL_CLOCK_SSP0,					/*!< 11: SSP0 clock */
+	SYSCTL_CLOCK_UART0,					/*!< 12: UART0 clock */
+	SYSCTL_CLOCK_ADC,					/*!< 13: ADC clock */
+	SYSCTL_CLOCK_USB,					/*!< 14: USBREG clock */
+	SYSCTL_CLOCK_WDT,					/*!< 15: Watchdog timer clock */
+	SYSCTL_CLOCK_IOCON,					/*!< 16: IOCON block clock */
+	SYSCTL_CLOCK_RESERVED17,			/*!< 17: Reserved */
+	SYSCTL_CLOCK_SSP1,					/*!< 18: SSP1 clock */
+#if defined(CHIP_LPC1347)
+	SYSCTL_CLOCK_PINT,					/*!< 19: GPIO Pin interrupts register clock */
+	SYSCTL_CLOCK_RESERVED20,			/*!< 20: Reserved */
+	SYSCTL_CLOCK_RESERVED21,			/*!< 21: Reserved */
+	SYSCTL_CLOCK_RESERVED22,			/*!< 22: Reserved */
+	SYSCTL_CLOCK_GROUP0INT,				/*!< 23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only */
+	SYSCTL_CLOCK_GROUP1INT,				/*!< 24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only */
+	SYSCTL_CLOCK_RESERVED25,			/*!< 25: Reserved */
+	SYSCTL_CLOCK_RAM1,					/*!< 26: SRAM block (0x20000000) clock, LPC11E/Uxx only */
+	SYSCTL_CLOCK_USBRAM,				/*!< 27: USB SRAM block clock, LPC11Uxx only */
+#endif
+} CHIP_SYSCTL_CLOCK_T;
+
+/**
+ * @brief	Enable a system or peripheral clock
+ * @param	clk	: Clock to enable
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
+{
+	LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
+}
+
+/**
+ * @brief	Disable a system or peripheral clock
+ * @param	clk	: Clock to disable
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
+{
+	LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
+}
+
+/**
+ * @brief	Set SSP0 divider
+ * @param	div	: divider for SSP0 clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->SSP0CLKDIV  = div;
+}
+
+/**
+ * @brief	Return SSP0 divider
+ * @return	divider for SSP0 clock
+ * @note	A value of 0 means the clock is disabled.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
+{
+	return LPC_SYSCTL->SSP0CLKDIV;
+}
+
+/**
+ * @brief	Set UART divider clock
+ * @param	div	: divider for UART clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The UART clock
+ * rate is the main system clock divided by this value. <br>
+ *		For the LPC1311/13/42/43, the UART pins must be configured in the
+ * IOCON block before the UART clock can be enabled
+ */
+STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->USARTCLKDIV  = div;
+}
+
+/**
+ * @brief	Return UART divider
+ * @return	divider for UART clock
+ * @note	A value of 0 means the clock is disabled.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
+{
+	return LPC_SYSCTL->USARTCLKDIV;
+}
+
+/**
+ * @brief	Set SSP1 divider clock
+ * @param	div	: divider for SSP1 clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->SSP1CLKDIV  = div;
+}
+
+/**
+ * @brief	Return SSP1 divider
+ * @return	divider for SSP1 clock
+ * @note	A value of 0 means the clock is disabled.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
+{
+	return LPC_SYSCTL->SSP1CLKDIV;
+}
+
+/**
+ * @brief	Set ARM trace clock divider
+ * @param	div	: divider for ARM trace clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The ARM trace clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetTraceClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->TRACECLKDIV  = div;
+}
+
+/**
+ * @brief	Return ARM trace clock divider
+ * @return	divider for ARM trace clock
+ * @note	A value of 0 means the clock is disabled.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetTraceClockDiv(void)
+{
+	return LPC_SYSCTL->TRACECLKDIV;
+}
+
+/**
+ * @brief	Set SYSTICK clock divider
+ * @param	div	: divider for SYSTICK clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The SYSTICK clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetSystickClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->SYSTICKCLKDIV  = div;
+}
+
+/**
+ * @brief	Return SYSTICK clock divider
+ * @return	divider for SYSTICK clock
+ * @note	A value of 0 means the clock is disabled.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetSystickClockDiv(void)
+{
+	return LPC_SYSCTL->SYSTICKCLKDIV;
+}
+
+/**
+ * Clock sources for USB
+ */
+typedef enum CHIP_SYSCTL_USBCLKSRC {
+	SYSCTL_USBCLKSRC_PLLOUT = 0,	/*!< USB PLL out */
+	SYSCTL_USBCLKSRC_MAINSYSCLK,	/*!< Main system clock */
+} CHIP_SYSCTL_USBCLKSRC_T;
+
+/**
+ * @brief	Set USB clock source and divider
+ * @param	src	: Clock source for USB
+ * @param	div	: divider for USB clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The USB clock
+ * rate is either the main system clock or USB PLL output clock divided
+ * by this value. This function will also toggle the clock source
+ * update register to update the clock source.
+ */
+void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
+
+#if defined(CHIP_LPC1343)
+/**
+ * Clock sources for WDT
+ */
+typedef enum CHIP_SYSCTL_WDTCLKSRC {
+	SYSCTL_WDTCLKSRC_IRC = 0,		/*!< Internal oscillator for watchdog clock */
+	SYSCTL_WDTCLKSRC_MAINSYSCLK,	/*!< Main system clock for watchdog clock */
+	SYSCTL_WDTCLKSRC_WDTOSC,		/*!< Watchdog oscillator for watchdog clock */
+} CHIP_SYSCTL_WDTCLKSRC_T;
+
+/**
+ * @brief	Set WDT clock source and divider
+ * @param	src	: Clock source for WDT
+ * @param	div	: divider for WDT clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The WDT clock
+ * rate is the clock source divided by the divider. This function will
+ * also toggle the clock source update register to update the clock
+ * source.
+ */
+void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);
+
+#endif
+
+/**
+ * Clock sources for CLKOUT
+ */
+typedef enum CHIP_SYSCTL_CLKOUTSRC {
+	SYSCTL_CLKOUTSRC_IRC = 0,		/*!< Internal oscillator for CLKOUT */
+	SYSCTL_CLKOUTSRC_SYSOSC,		/*!< Main oscillator for CLKOUT */
+	SYSCTL_CLKOUTSRC_WDTOSC,		/*!< Watchdog oscillator for CLKOUT */
+	SYSCTL_CLKOUTSRC_MAINSYSCLK,	/*!< Main system clock for CLKOUT */
+} CHIP_SYSCTL_CLKOUTSRC_T;
+
+/**
+ * @brief	Set CLKOUT clock source and divider
+ * @param	src	: Clock source for CLKOUT
+ * @param	div	: divider for CLKOUT clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
+ * rate is the clock source divided by the divider. This function will
+ * also toggle the clock source update register to update the clock
+ * source.
+ */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
+
+/**
+ * @brief	Returns the main oscillator clock rate
+ * @return	main oscillator clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
+{
+	return OscRateIn;
+}
+
+/**
+ * @brief	Returns the internal oscillator (IRC) clock rate
+ * @return	internal oscillator (IRC) clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
+{
+	return SYSCTL_IRC_FREQ;
+}
+
+/**
+ * @brief	Return estimated watchdog oscillator rate
+ * @return	Estimated watchdog oscillator rate
+ * @note	This rate is accurate to plus or minus 40%.
+ */
+uint32_t Chip_Clock_GetWDTOSCRate(void);
+
+/**
+ * @brief	Return System PLL input clock rate
+ * @return	System PLL input clock rate
+ */
+uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
+
+/**
+ * @brief	Return System PLL output clock rate
+ * @return	System PLL output clock rate
+ */
+uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
+
+/**
+ * @brief	Return USB PLL input clock rate
+ * @return	USB PLL input clock rate
+ */
+uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
+
+/**
+ * @brief	Return USB PLL output clock rate
+ * @return	USB PLL output clock rate
+ */
+uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
+
+/**
+ * @brief	Return main clock rate
+ * @return	main clock rate
+ */
+uint32_t Chip_Clock_GetMainClockRate(void);
+
+/**
+ * @brief	Return system clock rate
+ * @return	system clock rate
+ */
+uint32_t Chip_Clock_GetSystemClockRate(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLOCK_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h
new file mode 100644
index 000000000..08ca1e962
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis.h
@@ -0,0 +1,56 @@
+/*
+ * @brief Basic CMSIS include file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_H_
+#define __CMSIS_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+/* Select correct CMSIS include file based on CHIP_* definition */
+#if defined(CHIP_LPC1343)
+#include "cmsis_1343.h"
+typedef LPC1343_IRQn_Type IRQn_Type;
+#elif defined(CHIP_LPC1347)
+#include "cmsis_1347.h"
+typedef LPC1347_IRQn_Type IRQn_Type;
+#else
+#error "No CHIP_* definition is defined"
+#endif
+
+/* Cortex-M3 processor and core peripherals */
+#include "core_cm3.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h
new file mode 100644
index 000000000..c9cf1d79d
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/cmsis_1347.h
@@ -0,0 +1,157 @@
+/*
+ * @brief Basic CMSIS include file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_1347_H_
+#define __CMSIS_1347_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMSIS_1347 CHIP: LPC1347 CMSIS include file
+ * @ingroup CHIP_13XX_CMSIS_Drivers
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+  #pragma diag_suppress 2525
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+//  #pragma push // FIXME not usable for IAR
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+ 
+#if !defined(CHIP_LPC1347)
+#error Incorrect or missing device variant (CHIP_LPC1347)
+#endif
+
+/** @defgroup CMSIS_1347_IRQ CHIP_1347: LPC1315/LPC1316/LPC1317/LPC1345/LPC1346/LPC1347 peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum LPC1347_IRQn {
+	Reset_IRQn                    = -15,/*!< 1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn           = -14,/*!< 2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                = -13,/*!< 3  Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn         = -12,/*!< 4  Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                 = -11,/*!< 5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn               = -10,/*!< 6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+	SVCall_IRQn                   = -5,	/*!< 11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn             = -4,	/*!< 12  Debug Monitor                    */
+	PendSV_IRQn                   = -2,	/*!< 14  Pendable request for system service */
+	SysTick_IRQn                  = -1,	/*!< 15  System Tick Timer                */
+
+	/******  LPC1347 Specific Interrupt Numbers *******************************************************/
+	PIN_INT0_IRQn                 = 0,	/*!< 0  PIN_INT0                         */
+	PIN_INT1_IRQn                 = 1,	/*!< 1  PIN_INT1                         */
+	PIN_INT2_IRQn                 = 2,	/*!< 2  PIN_INT2                         */
+	PIN_INT3_IRQn                 = 3,	/*!< 3  PIN_INT3                         */
+	PIN_INT4_IRQn                 = 4,	/*!< 4  PIN_INT4                         */
+	PIN_INT5_IRQn                 = 5,	/*!< 5  PIN_INT5                         */
+	PIN_INT6_IRQn                 = 6,	/*!< 6  PIN_INT6                         */
+	PIN_INT7_IRQn                 = 7,	/*!< 7  PIN_INT7                         */
+	GINT0_IRQn                    = 8,	/*!< 8  GINT0                            */
+	GINT1_IRQn                    = 9,	/*!< 9  GINT1                            */
+	Reserved0_IRQn                = 10,	/*!< 10  Reserved Interrupt               */
+	Reserved1_IRQn                = 11,	/*!< 11  Reserved Interrupt               */
+	RIT_IRQn                      = 12,	/*!< 12  Repetitive Interrupt Timer       */
+	Reserved2_IRQn                = 13,	/*!< 13  Reserved Interrupt               */
+	SSP1_IRQn                     = 14,	/*!< 14  SSP1                             */
+	I2C0_IRQn                     = 15,	/*!< 15  I2C                              */
+	TIMER_16_0_IRQn               = 16,	/*!< 16-bit Timer0 Interrupt                          */
+	TIMER_16_1_IRQn               = 17,	/*!< 16-bit Timer1 Interrupt                          */
+	TIMER_32_0_IRQn               = 18,	/*!< 32-bit Timer0 Interrupt                          */
+	TIMER_32_1_IRQn               = 19,	/*!< 32-bit Timer1 Interrupt                          */
+	SSP0_IRQn                     = 20,	/*!< 20  SSP0                             */
+	UART0_IRQn                    = 21,	/*!< 21  USART                            */
+	USB0_IRQn                     = 22,	/*!< 22  USB_IRQ                          */
+	USB0_FIQ_IRQn                 = 23,	/*!< 23  USB_FIQ                          */
+	ADC_IRQn                      = 24,	/*!< 24  ADC                              */
+	WDT_IRQn                      = 25,	/*!< 25  WDT                              */
+	BOD_IRQn                      = 26,	/*!< 26  BOD                              */
+	FMC_IRQn                      = 27,	/*!< 27  FMC                              */
+	Reserved3_IRQn                = 28,	/*!< 28  Reserved Interrupt               */
+	Reserved4_IRQn                = 29,	/*!< 29  Reserved Interrupt               */
+	USB_WAKEUP_IRQn               = 30,	/*!< 30  USBWAKEUP                        */
+	Reserved5_IRQn                = 31,	/*!< 31  Reserved Interrupt               */
+} LPC1347_IRQn_Type;
+
+/**
+ * @}
+ */
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/** @defgroup CMSIS_1347_COMMON CHIP: Common LPC1347 Cortex CMSIS definitions
+ * @{
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __CM3_REV              0x0201		/*!< Cortex-M3 Core Revision               */
+#define __MPU_PRESENT             0			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_1347_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h
new file mode 100644
index 000000000..122c9aa4a
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cm3.h
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h
new file mode 100644
index 000000000..0a18fafc3
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h
new file mode 100644
index 000000000..d213f0eed
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h
new file mode 100644
index 000000000..2da862163
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/error.h
@@ -0,0 +1,147 @@
+/*
+ * @brief Error code returned by Boot ROM drivers/library functions
+ *  @ingroup Common
+ *
+ *  This file contains unified error codes to be used across driver,
+ *  middleware, applications, hal and demo software.
+ *
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_ERROR_H__
+#define __LPC_ERROR_H__
+
+/** Error code returned by Boot ROM drivers/library functions
+ *
+ *  Error codes are a 32-bit value with :
+ *      - The 16 MSB contains the peripheral code number
+ *      - The 16 LSB contains an error code number associated to that peripheral
+ *
+ */
+typedef enum {
+	/**\b 0x00000000*/ LPC_OK = 0,	/**< enum value returned on Success */
+	/**\b 0xFFFFFFFF*/ ERR_FAILED = -1,	/**< enum value returned on general failure */
+	/**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2,	/**< enum value returned on general timeout */
+	/**\b 0xFFFFFFFD*/ ERR_BUSY = -3,	/**< enum value returned when resource is busy */
+
+	/* ISP related errors */
+	ERR_ISP_BASE = 0x00000000,
+	/*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
+	/*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR,	/* Source address not on word boundary */
+	/*0x00000003*/ ERR_ISP_DST_ADDR_ERROR,	/* Destination address not on word or 256 byte boundary */
+	/*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
+	/*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
+	/*0x00000006*/ ERR_ISP_COUNT_ERROR,	/* Byte count is not multiple of 4 or is not a permitted value */
+	/*0x00000007*/ ERR_ISP_INVALID_SECTOR,
+	/*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
+	/*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
+	/*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
+	/*0x0000000B*/ ERR_ISP_BUSY,/* Flash programming hardware interface is busy */
+	/*0x0000000C*/ ERR_ISP_PARAM_ERROR,	/* Insufficient number of parameters */
+	/*0x0000000D*/ ERR_ISP_ADDR_ERROR,	/* Address not on word boundary */
+	/*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
+	/*0x0000000F*/ ERR_ISP_CMD_LOCKED,	/* Command is locked */
+	/*0x00000010*/ ERR_ISP_INVALID_CODE,/* Unlock code is invalid */
+	/*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
+	/*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
+	/*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
+
+	/* ROM API related errors */
+	ERR_API_BASE = 0x00010000,
+	/**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1,	/**< Invalid parameters*/
+	/**\b 0x00010002*/ ERR_API_INVALID_PARAM1,	/**< PARAM1 is invalid */
+	/**\b 0x00010003*/ ERR_API_INVALID_PARAM2,	/**< PARAM2 is invalid */
+	/**\b 0x00010004*/ ERR_API_INVALID_PARAM3,	/**< PARAM3 is invalid */
+	/**\b 0x00010005*/ ERR_API_MOD_INIT,/**< API is called before module init */
+
+	/* SPIFI API related errors */
+	ERR_SPIFI_BASE = 0x00020000,
+	/*0x00020001*/ ERR_SPIFI_DEVICE_ERROR = ERR_SPIFI_BASE + 1,
+	/*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
+	/*0x00020003*/ ERR_SPIFI_TIMEOUT,
+	/*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
+	/*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
+	/*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
+	/*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
+	/*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
+	/*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
+
+	/* Security API related errors */
+	ERR_SEC_BASE = 0x00030000,
+	/*0x00030001*/ ERR_SEC_AES_WRONG_CMD = ERR_SEC_BASE + 1,
+	/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
+	/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
+
+	/* USB device stack related errors */
+	ERR_USBD_BASE = 0x00040000,
+	/**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1,/**< invalid request */
+	/**\b 0x00040002*/ ERR_USBD_UNHANDLED,	/**< Callback did not process the event */
+	/**\b 0x00040003*/ ERR_USBD_STALL,	/**< Stall the endpoint on which the call back is called */
+	/**\b 0x00040004*/ ERR_USBD_SEND_ZLP,	/**< Send ZLP packet on the endpoint on which the call back is called */
+	/**\b 0x00040005*/ ERR_USBD_SEND_DATA,	/**< Send data packet on the endpoint on which the call back is called */
+	/**\b 0x00040006*/ ERR_USBD_BAD_DESC,	/**< Bad descriptor*/
+	/**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,	/**< Bad config descriptor*/
+	/**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,	/**< Bad interface descriptor*/
+	/**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
+	/**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF,/**< Bad alignment of buffer passed. */
+	/**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR,/**< Too many class handlers. */
+
+	/* CGU  related errors */
+	ERR_CGU_BASE = 0x00050000,
+	/*0x00050001*/ ERR_CGU_NOT_IMPL = ERR_CGU_BASE + 1,
+	/*0x00050002*/ ERR_CGU_INVALID_PARAM,
+	/*0x00050003*/ ERR_CGU_INVALID_SLICE,
+	/*0x00050004*/ ERR_CGU_OUTPUT_GEN,
+	/*0x00050005*/ ERR_CGU_DIV_SRC,
+	/*0x00050006*/ ERR_CGU_DIV_VAL,
+	/*0x00050007*/ ERR_CGU_SRC,
+
+	/* I2C related errors */
+	ERR_I2C_BASE = 0x00060000,
+	/*0x00060001*/ ERR_I2C_NAK = ERR_I2C_BASE + 1,
+	/*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW,
+	/*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR,
+	/*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION,
+	/*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED,
+	/*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT,
+	/*0x00060007*/ ERR_I2C_GENERAL_FAILURE,
+	/*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT,
+	/*0x00060009*/ ERR_I2C_TIMEOUT,
+	/*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW
+} ErrorCode_t;
+
+#ifndef offsetof
+#define offsetof(s, m)   (int) &(((s *) 0)->m)
+#endif
+
+#define COMPILE_TIME_ASSERT(pred)    switch (0) { \
+	case 0:	\
+	case pred:; }
+
+#endif /* __LPC_ERROR_H__ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h
new file mode 100644
index 000000000..0a1799ece
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/flash_13xx.h
@@ -0,0 +1,541 @@
+/*
+ * @brief LPC13xx Flash/EEPROM programming driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FLASH_EEPROM_13XX_H_
+#define __FLASH_EEPROM_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup FLASH_EEPROM_13XX CHIP: LPC13xx FLASH/EEPROM Programming driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+#define ERASE_PAGE_SUPPORT
+#define EEPROM_RW_SUPPORT
+#endif
+
+/** Flash Programming Entry Location */
+#define FLASH_ENTRY_LOCATION    (0x1fff1ff1)
+
+/** The maximum number of flash programing parameters */
+#define FLASH_PARAMETER_NUM     (5)
+
+/** The maximum number of flash programing results */
+#define FLASH_RESULT_NUM        (4)
+
+/** Flash programming function type */
+typedef void (*FLASH_ENTRY_T)(unsigned int[], unsigned int[]);
+
+/**
+ * @brief Flash command code definitions
+ */
+typedef enum {
+	FLASH_PREPARE = 50,				/*!< Prepare sector(s) for write operation */
+	FLASH_COPY_RAM_TO_FLASH = 51,	/*!< Copy RAM to Flash */
+	FLASH_ERASE = 52,				/*!< Erase sector(s) */
+	FLASH_BLANK_CHECK = 53,			/*!< Blank check sector(s) */
+	FLASH_READ_PART_ID = 54,		/*!< Read chip part ID */
+	FLASH_READ_BOOT_VER = 55,		/*!< Read chip boot code version */
+	FLASH_COMPARE = 56,				/*!< Compare memory areas */
+	FLASH_REINVOKE_ISP = 57,		/*!< Reinvoke ISP */
+	FLASH_READ_UID = 58,			/*!< Read UID */
+#if defined(ERASE_PAGE_SUPPORT)
+	FLASH_ERASE_PAGE = 59,			/*!< Erase page */
+#endif
+#if defined(EEPROM_RW_SUPPORT)
+	FLASH_EEPROM_WRITE = 61,		/*!< EEPROM Write */
+	FLASH_EEPROM_READ = 62,			/*!< EEPROM Read */
+#endif
+}  FLASH_CMD_CODE_T;
+
+/**
+ * @brief Flash status code definitions
+ */
+typedef enum {
+	CMD_SUCCESS,				/*!< Command is executed successfully. */
+	INVALID_COMMAND,			/*!< Invalid command. */
+	SRC_ADDR_ERROR,				/*!< Source address is not on a word boundary. */
+	DST_ADDR_ERROR,				/*!< Destination address is not on a correct boundary. */
+	SRC_ADDR_NOT_MAPPED,		/*!< Source address is not mapped in the memory map. */
+	DST_ADDR_NOT_MAPPED,		/*!< Destination address is not mapped in the memory map. */
+	COUNT_ERROR,				/*!< Byte count is not multiple of 4 or is not a permitted value. */
+	INVALID_SECTOR,				/*!< Sector number is invalid. */
+	SECTOR_NOT_BLANK,				/*!< Sector is not blank. */
+	SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,	/*!< Command to prepare sector for write operation was not executed. */
+	COMPARE_ERROR,				/*!< Source and destination data is not same. */
+	BUSY,						/*!< Flash programming hardware interface is busy. */
+} FLASH_STATUS_CODE_T;
+
+#if defined(EEPROM_RW_SUPPORT)
+/** EEPROM size */
+#define EEPROM_SIZE                 (4 << 10)
+#endif
+
+/**
+ * @brief Command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;			/*!< Command code */
+	uint32_t pParams[FLASH_PARAMETER_NUM];	/*!< Parameters*/
+} FLASH_COMMAND_T;
+
+/**
+ * @brief Command result table structure
+ */
+typedef struct {
+	uint32_t status;		/*!< Status code */
+	uint32_t pResult[FLASH_RESULT_NUM];		/*!< Results*/
+} FLASH_OUTPUT_T;
+
+/* Flash Programming Command Description
+   Command                  Parameters              Return Code                                 Result
+   ----------------------------------------------------------------------------------------------------------
+   FLASH_PREPARE            Start Sector Number     CMD_SUCCESS                                 None
+                            End Sector Number       BUSY
+                                                    INVALID_SECTOR
+   FLASH_COPY_RAM2FLASH     Destination Flash Addr  CMD_SUCCESS                                 None
+                            Source RAM Addr         SRC_ADDR_ERROR
+                            Number of bytes written SRC_ADDR_NOT_MAPPED
+                            CCLK in kHz             DST_ADDR_NOT_MAPPED
+                                                    COUNT_ERROR
+                                                    SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+                                                    BUSY
+   FLASH_ERASE              Start Sector Number     CMD_SUCCESS                                 None
+                            Emd Sector Number       BUSY
+                            CCLK in kHz             SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+                                                    INVALID_SECTOR
+   FLASH_BLANK_CHECK        Start Sector Number     CMD_SUCCESS                                 Non Blank Sector Offset(if Status code is SECTOR_NOT_BLANK)
+                            End Sector Number       BUSY                                        Content of non blank word location
+                                                    SECTOR_NOT_BLANK
+                                                    INVALID_SECTOR
+   FLASH_READ_PART_ID       None                    CMD_SUCCESS                                 Part ID
+   FLASH_READ_BOOT_VER      None                    CMD_SUCCESS                                 <byte1(Major)>.<byte0(Minor)>
+   FLASH_COMPARE            Destination Addr        CMD_SUCCESS                                 Offset of the first mismatch
+                            Source Address          COMPARE_ERROR
+                            Number of bytes compared COUNT_ERROR
+                                                    ADDR_ERROR
+                                                    ADDR_NOT_MAPPED
+   FLASH_REINVOKE_ISP       None                    None                                        None
+   FLASH_READ_UID           None                    CMD_SUCCESS                                 The first 32-bit word
+                                                                                                The second 32-bit word.
+                                                                                                The third 32-bit word.
+                                                                                                The fourth 32-bit word
+   FLASH_ERASE_PAGE         Start Page Number       CMD_SUCCESS                                 None
+                            End Page Number         BUSY
+                            CCLK in kHz             SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+                                                    INVALID_SECTOR
+   FLASH_EEPROM_WRITE       EEPROM Addr             CMD_SUCCESS                                 None
+                            RAM Addr                SRC_ADDR_NOT_MAPPED
+                            Number of bytes written DST_ADDR_NOT_MAPPED
+                            CCLK in kHz
+   FLASH_EEPROM_READ        EEPROM Addr             CMD_SUCCESS                                 None
+                            RAM Addr                SRC_ADDR_NOT_MAPPED
+                            Number of bytes read    DST_ADDR_NOT_MAPPED
+                            CCLK in kHz
+ */
+
+/**
+ * @brief [Prepare sectors] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t start;		/*!< Start Sector Number */
+	uint32_t end;		/*!<End Sector Number (should be greater than or equal to start sector number).*/
+} FLASH_PREPARE_SECTORS_COMMAND_T;
+
+/**
+ * @brief [Prepare sectors] command result table structure
+ */
+typedef struct {
+	uint32_t status;			/*!< Status code */
+} FLASH_PREPARE_SECTORS_OUTPUT_T;
+
+/**
+ * @brief [Copy Ram to Flash] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t dst;		/*!< Destination flash address where data bytes are to be written (256 byte boundary) */
+	uint32_t src;		/*!<Source RAM address from which data bytes are to be read (a word boudary).*/
+	uint32_t byteNum;	/*!<Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.*/
+	uint32_t cclk;		/*!<System Clock Frequency (CCLK) in kHz.*/
+} FLASH_COPY_RAM_TO_FLASH_COMMAND_T;
+
+/**
+ * @brief [Copy Ram to Flash] command result table structure
+ */
+typedef struct {
+	uint32_t status;			/*!< Status code */
+} FLASH_COPY_RAM_TO_FLASH_OUTPUT_T;
+
+/**
+ * @brief [Erase Sector(s)] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t start;		/*!< Start Sector Number */
+	uint32_t end;		/*!<End Sector Number (should be greater than or equal to start sector number).*/
+	uint32_t cclk;		/*!<System Clock Frequency (CCLK) in kHz.*/
+} FLASH_ERASE_SECTORS_COMMAND_T;
+
+/**
+ * @brief [Erase Sector(s)] command result table structure
+ */
+typedef struct {
+	uint32_t status;			/*!< Status code */
+} FLASH_ERASE_SECTORS_OUTPUT_T;
+
+/**
+ * @brief [Blank check sector(s)] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t start;		/*!< Start Sector Number */
+	uint32_t end;		/*!<End Sector Number (should be greater than or equal to start sector number).*/
+} FLASH_BLANK_CHECK_SECTORS_COMMAND_T;
+
+/**
+ * @brief [Blank check sector(s)] command result table structure
+ */
+typedef struct {
+	uint32_t status;			/*!< Status code */
+	uint32_t firstNonBlankLoc;	/*!< Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK.*/
+	uint32_t firstNonBlankVal;	/*!<Contents of non blank word location.*/
+} FLASH_BLANK_CHECK_SECTORS_OUTPUT_T;
+
+/**
+ * @brief [Read Part Identification number] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+} FLASH_READ_PART_ID_COMMAND_T;
+
+/**
+ * @brief [Read Part Identification number] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+	uint32_t partID;	/*!< Part Identification Number*/
+} FLASH_READ_PART_ID_OUTPUT_T;
+
+/**
+ * @brief [Read Boot code version number] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+} FLASH_READ_BOOTCODE_VER_COMMAND_T;
+
+/**
+ * @brief [Read Boot code version number] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+	uint8_t minor;		/*!< Minor*/
+	uint8_t major;		/*!< Major*/
+} FLASH_READ_BOOTCODE_VER_OUTPUT_T;
+
+/**
+ * @brief [Compare memory] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t dst;		/*!<Starting flash or RAM address of data bytes to be compared (a word boundary) */
+	uint32_t src;		/*!<Starting flash or RAM address of data bytes to be compared (a word boudary).*/
+	uint32_t byteNum;	/*!<Number of bytes to be compared; should be a multiple of 4.*/
+} FLASH_COMPARE_MEM_COMMAND_T;
+
+/**
+ * @brief [Compare memory] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+	uint32_t offset;	/*!< Offset of the first mismatch if the Status Code is COMPARE_ERROR.*/
+} FLASH_COMPARE_MEM_OUTPUT_T;
+
+/**
+ * @brief [Reinvoke ISP] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+} FLASH_REINVOKE_ISP_COMMAND_T;
+
+/**
+ * @brief [Reinvoke ISP] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+} FLASH_REINVOKE_ISP_OUTPUT_T;
+
+/**
+ * @brief [ReadUID] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+} FLASH_READ_UID_COMMAND_T;
+
+/**
+ * @brief [ReadUID] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+	uint32_t id[4];		/*!< UID*/
+} FLASH_READ_UID_OUTPUT_T;
+
+#if defined(ERASE_PAGE_SUPPORT)
+/**
+ * @brief [Erase page(s)] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t start;		/*!< Start Page Number */
+	uint32_t end;		/*!<End Page Number (should be greater than or equal to start page number).*/
+	uint32_t cclk;		/*!<System Clock Frequency (CCLK) in kHz.*/
+} FLASH_ERASE_PAGES_COMMAND_T;
+
+/**
+ * @brief [Erase page(s)] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+} FLASH_ERASE_PAGES_OUTPUT_T;
+
+#endif /* defined(ERASE_PAGE_SUPPORT) */
+
+#if defined(EEPROM_RW_SUPPORT)
+/**
+ * @brief [Write EEPROM] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;			/*!< Command code */
+	uint32_t eepromAddr;	/*!< EEPROM address.*/
+	uint32_t ramAddr;		/*!< RAM address.*/
+	uint32_t byteNum;		/*!<Number of bytes to be written.*/
+	uint32_t cclk;			/*!<System Clock Frequency (CCLK) in kHz.*/
+} EEPROM_WRITE_COMMAND_T;
+
+/**
+ * @brief [Write EEPROM] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+} EEPROM_WRITE_OUTPUT_T;
+
+/**
+ * @brief [Read EEPROM] command parameter table structure
+ */
+typedef struct {
+	uint32_t cmd;		/*!< Command code */
+	uint32_t eepromAddr;	/*!< EEPROM address.*/
+	uint32_t ramAddr;		/*!< RAM address.*/
+	uint32_t byteNum;		/*!<Number of bytes to be written.*/
+	uint32_t cclk;			/*!<System Clock Frequency (CCLK) in kHz.*/
+} EEPROM_READ_COMMAND_T;
+
+/**
+ * @brief [Read EEPROM] command result table structure
+ */
+typedef struct {
+	uint32_t status;	/*!< Status code */
+} EEPROM_READ_OUTPUT_T;
+
+#endif /* defined(EEPROM_RW_SUPPORT) */
+
+/**
+ * @brief	Get sector number of the specified address
+ * @param	adr		: flash address.
+ * @return	sector number
+ */
+STATIC INLINE uint32_t Chip_FLASH_GetSecNum(uint32_t adr)
+{
+	return adr >> 12;
+}
+
+/**
+ * @brief	Execute flash programming command
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_FLASH_Execute(FLASH_COMMAND_T *pCommand, FLASH_OUTPUT_T *pOutput)
+{
+	((FLASH_ENTRY_T) FLASH_ENTRY_LOCATION)((unsigned int *) pCommand, (unsigned int *) pOutput);
+}
+
+/**
+ * @brief	Prepare sector(s) for write operation
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ * @note	This command must be executed before executing "Copy RAM to flash" or "Erase Sector(s)" command. <br>
+ *			The boot sector can not be prepared by this command.
+ */
+STATIC INLINE void Chip_FLASH_PrepareSectors(FLASH_PREPARE_SECTORS_COMMAND_T *pCommand,
+											 FLASH_PREPARE_SECTORS_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/**
+ * @brief	Copy RAM to flash
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ * @note	The affected sectors should be prepared first by calling "Prepare Sector for Write Operation" command.<br>
+ *		The boot sector can not be written by this command.
+ */
+STATIC INLINE void Chip_FLASH_CopyRamToFlash(FLASH_COPY_RAM_TO_FLASH_COMMAND_T *pCommand,
+											 FLASH_COPY_RAM_TO_FLASH_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/**
+ * @brief	Erase Sector(s)
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ * @note	 The boot sector can not be erased by this command.
+ */
+STATIC INLINE void Chip_FLASH_EraseSectors(FLASH_ERASE_SECTORS_COMMAND_T *pCommand,
+										   FLASH_ERASE_SECTORS_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/**
+ * @brief	Blank check sector(s)
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_FLASH_BlankCheckSectors(FLASH_BLANK_CHECK_SECTORS_COMMAND_T *pCommand,
+												FLASH_BLANK_CHECK_SECTORS_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/**
+ * @brief	Read Part Identification number
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+void Chip_FLASH_ReadPartID(FLASH_READ_PART_ID_OUTPUT_T *pOutput);
+
+/**
+ * @brief	Read Boot code version number
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+void Chip_FLASH_ReadBootCodeVersion(FLASH_READ_BOOTCODE_VER_OUTPUT_T *pOutput);
+
+/**
+ * @brief	Compare memory
+ * @param	pCommand	: parameters
+ * @param	pOutput	: results
+ * @return	Nothing
+ * @note	The result may not be correct when the source or destination includes any
+ * of the first 512 bytes starting from address zero. The first 512 bytes can be re-mapped to RAM.
+ */
+STATIC INLINE void Chip_FLASH_CompareMem(FLASH_COMPARE_MEM_COMMAND_T *pCommand,
+										 FLASH_COMPARE_MEM_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/**
+ * @brief	Reinvoke ISP
+ * @return	Nothing
+ */
+void Chip_FLASH_ReInvokeISP(void);
+
+/**
+ * @brief	Read UID
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+void Chip_FLASH_ReadUID(FLASH_READ_UID_OUTPUT_T *pOutput);
+
+#if defined(ERASE_PAGE_SUPPORT)
+/**
+ * @brief	Erase Page(s)
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_FLASH_ErasePages(FLASH_ERASE_PAGES_COMMAND_T *pCommand,
+										 FLASH_ERASE_PAGES_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+#endif /* defined(ERASE_PAGE_SUPPORT) */
+
+#if defined(EEPROM_RW_SUPPORT)
+/**
+ * @brief	Write EEPROM
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ * @note		The top 64 bytes of the EEPROM memory are reserved and cannot be written to.
+ */
+STATIC INLINE void Chip_EEPROM_Write(EEPROM_WRITE_COMMAND_T *pCommand,
+									 EEPROM_WRITE_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/**
+ * @brief	Read EEPROM
+ * @param	pCommand	: Command information
+ * @param	pOutput	: Output information
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_Read(EEPROM_READ_COMMAND_T *pCommand,
+									EEPROM_READ_OUTPUT_T *pOutput)
+{
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) pCommand, (FLASH_OUTPUT_T *) pOutput);
+}
+
+#endif /*defined(EEPROM_RW_SUPPORT)*/
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FLASH_EEPROM_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h
new file mode 100644
index 000000000..6c5bff034
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/fmc_13xx.h
@@ -0,0 +1,137 @@
+/*
+ * @brief LPC13xx FLASH Memory Controller (FMC) registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FMC_13XX_H_
+#define __FMC_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup FMC_13XX CHIP: LPC13xx FLASH Memory Controller driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief FLASH Memory Controller Unit register block structure
+ */
+typedef struct {/*!< FMC Structure */
+	__I  uint32_t  RESERVED1[4];
+	__IO uint32_t  FLASHCFG;
+	__I  uint32_t  RESERVED2[3];
+	__IO uint32_t  FMSSTART;
+	__IO uint32_t  FMSSTOP;
+	__I  uint32_t  RESERVED3;
+	__I  uint32_t  FMSW[4];
+	__I  uint32_t  RESERVED4[28];
+	__I  uint32_t  RESERVED5[974];
+	__I  uint32_t  FMSTAT;
+	__I  uint32_t  RESERVED6;
+	__O  uint32_t  FMSTATCLR;
+} LPC_FMC_T;
+
+/**
+ * @brief FLASH Access time definitions
+ */
+typedef enum {
+	FLASHTIM_20MHZ_CPU = 0,		/*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock*/
+	FLASHTIM_40MHZ_CPU = 1, 	/*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock*/
+	FLASHTIM_72MHZ_CPU = 2, 	/*!< Flash accesses use 3 CPU clocks. Use for up to 72 MHz CPU clock*/
+} FMC_FLASHTIM_T;
+
+/**
+ * @brief	Set FLASH access time in clocks
+ * @param	clks	: Clock cycles for FLASH access (minus 1)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_FMC_SetFLASHAccess(FMC_FLASHTIM_T clks)
+{
+	uint32_t tmp = LPC_FMC->FLASHCFG & (~(0x3));
+
+	/* Don't alter upper bits */
+	LPC_FMC->FLASHCFG = tmp | clks;
+}
+
+/**
+ * @brief	Start computation of a signature for a FLASH memory range
+ * @param	start	: Starting FLASH address for computation
+ * @param	stop	: Ending FLASH address for computation
+ * @return	Nothing
+ * @note	Only bits 20..4 are used for the FLASH signature computation.
+ *			Use the Chip_FMC_IsSignatureBusy() function to determine when the
+ *			signature computation operation is complete and use the
+ *			Chip_FMC_GetSignature() function to get the computed signature.
+ */
+STATIC INLINE void Chip_FMC_ComputeSignature(uint32_t start, uint32_t stop)
+{
+	LPC_FMC->FMSSTART = (start >> 4);
+	LPC_FMC->FMSTATCLR = (1 << 2);
+	LPC_FMC->FMSSTOP = (stop >> 4) | (1 << 17);
+}
+
+/**
+ * @brief	Clear signature generation completion flag
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_FMC_ClearSignatureBusy(void)
+{
+	LPC_FMC->FMSTATCLR = (1 << 2);
+}
+
+/**
+ * @brief	Check for signature generation completion
+ * @return	true if the signature computation is running, false if finished
+ */
+STATIC INLINE bool Chip_FMC_IsSignatureBusy(void)
+{
+	return (bool) ((LPC_FMC->FMSTAT & (1 << 2)) != 0);
+}
+
+/**
+ * @brief	Returns the generated FLASH signature value
+ * @param	index	: Signature index to get - use 0 to FMSW0, 1 to FMSW1, etc.
+ * @return	the generated FLASH signature value
+ */
+STATIC INLINE uint32_t Chip_FMC_GetSignature(int index)
+{
+	return LPC_FMC->FMSW[index];
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FMC_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h
new file mode 100644
index 000000000..4ff70b4ee
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_1.h
@@ -0,0 +1,474 @@
+/*
+ * @brief LPC13xx GPIO chip driver for LPC13(15/16/17/45/46/47) families
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIO_13XX_1_H_
+#define __GPIO_13XX_1_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIO_13XX_1 CHIP: LPC13xx GPIO chip driver for LPC13(15/16/17/45/46/47) families
+ * @ingroup CHIP_13XX_Drivers
+ * For device familes identified with CHIP definitions CHIP_LPC1315, CHIP_LPC1316, CHIP_LPC1317,
+ * CHIP_LPC1345, CHIP_LPC1346 and CHIP_LPC1347 only.
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+
+/**
+ * @brief  GPIO port register block structure
+ */
+typedef struct {				/*!< GPIO_PORT Structure */
+	__IO uint8_t B[128][32];	/*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
+	__IO uint32_t W[32][32];	/*!< Offset 0x1000: Word pin registers port 0 to n */
+	__IO uint32_t DIR[32];		/*!< Offset 0x2000: Direction registers port n */
+	__IO uint32_t MASK[32];		/*!< Offset 0x2080: Mask register port n */
+	__IO uint32_t PIN[32];		/*!< Offset 0x2100: Portpin register port n */
+	__IO uint32_t MPIN[32];		/*!< Offset 0x2180: Masked port register port n */
+	__IO uint32_t SET[32];		/*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */
+	__O  uint32_t CLR[32];		/*!< Offset 0x2280: Clear port n */
+	__O  uint32_t NOT[32];		/*!< Offset 0x2300: Toggle port n */
+} LPC_GPIO_T;
+
+/**
+ * @brief	Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_GPIO_Init(LPC_GPIO_T *pGPIO);
+
+/**
+ * @brief	De-Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO);
+
+/**
+ * @brief	Set a GPIO port/bit state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
+{
+	pGPIO->B[port][pin] = setting;
+}
+
+/**
+ * @brief	Set a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param port  : GPIO Port number where @a pin is located
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ * @note	This function replaces Chip_GPIO_WritePortBit()
+ */
+STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
+{
+	pGPIO->B[port][pin] = setting;
+}
+
+/**
+ * @brief	Read a GPIO state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	pin		: GPIO pin to read
+ * @return	true of the GPIO is high, false if low
+ * @note	It is recommended to use the Chip_GPIO_GetPinState() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin)
+{
+	return (bool) pGPIO->B[port][pin];
+}
+
+/**
+ * @brief	Get a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: GPIO pin to get state for
+ * @return	true if the GPIO is high, false if low
+ * @note	This function replaces Chip_GPIO_ReadPortBit()
+ */
+STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (bool) pGPIO->B[port][pin];
+}
+
+/**
+ * @brief	Set a GPIO direction
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	bit		: GPIO bit to set
+ * @param	setting	: true for output, false for input
+ * @return	Nothing
+ * @note	It is recommended to use the Chip_GPIO_SetPinDIROutput(),
+ * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
+ * of this function.
+ */
+void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting);
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: GPIO pin to set direction on as output
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->DIR[port] |= 1UL << pin;
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: GPIO pin to set direction on as input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->DIR[port] &= ~(1UL << pin);
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: GPIO pin to set direction for
+ * @param	output	: true for output, false for input
+ * @return	Nothing
+ */
+void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output);
+
+/**
+ * @brief	Read a GPIO direction (out or in)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	bit		: GPIO bit to read
+ * @return	true of the GPIO is an output, false if input
+ * @note	It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
+{
+	return (bool) (((pGPIO->DIR[port]) >> bit) & 1);
+}
+
+/**
+ * @brief	Get GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: GPIO pin to get direction for
+ * @return	true if the GPIO is an output, false if input
+ */
+STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (bool) (((pGPIO->DIR[port]) >> pin) & 1);
+}
+
+/**
+ * @brief	Set Direction for a GPIO port
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port Number
+ * @param	bitValue	: GPIO bit to set
+ * @param	out			: Direction value, 0 = input, !0 = output
+ * @return	None
+ * @note	Bits set to '0' are not altered. It is recommended to use the
+ * Chip_GPIO_SetPortDIR() function instead.
+ */
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out);
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pinMask	: GPIO pin mask to set direction on as output (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the output direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask)
+{
+	pGPIO->DIR[port] |= pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pinMask	: GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask)
+{
+	pGPIO->DIR[port] &= ~pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input or output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pinMask	: GPIO pin mask to set direction on (bits 0..b for pins 0..n)
+ * @param	outSet	: Direction value, false = set as inputs, true = set as outputs
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet);
+
+/**
+ * @brief	Get GPIO direction for a all GPIO pins
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @return	a bitfield containing the input and output states for each pin
+ * @note	For pins 0..n, a high state in a bit corresponds to an output state for the
+ * same pin, while a low  state corresponds to an input state.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->DIR[port];
+}
+
+/**
+ * @brief	Set GPIO port mask value for GPIO masked read and write
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	mask	: Mask value for read and write
+ * @return	Nothing
+ * @note	Controls which bits corresponding to PIO0_n are active in the P0MPORT
+ * register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17).
+ */
+STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint32_t port, uint32_t mask)
+{
+	pGPIO->MASK[port] = mask;
+}
+
+/**
+ * @brief	Get GPIO port mask value used for GPIO masked read and write
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @return	Returns value set with the Chip_GPIO_SetPortMask() function.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->MASK[port];
+}
+
+/**
+ * @brief	Set all GPIO raw pin states (regardless of masking)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	pGPIO->PIN[port] = value;
+}
+
+/**
+ * @brief	Get all GPIO raw pin states (regardless of masking)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @return	Current (raw) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->PIN[port];
+}
+
+/**
+ * @brief	Set all GPIO pin states, but mask via the MASKP0 register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	pGPIO->MPIN[port] = value;
+}
+
+/**
+ * @brief	Get all GPIO pin statesm but mask via the MASKP0 register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @return	Current (masked) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->MPIN[port];
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the high state
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port number
+ * @param	bitValue	: bit(s) in the port to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output. It is recommended to use the
+ * Chip_GPIO_SetPortOutHigh() function instead.
+ */
+STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
+{
+	pGPIO->SET[portNum] = bitValue;
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pins	: pins (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO->SET[port] = pins;
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip'
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: pin number (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->SET[port] = (1 << pin);
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the low state
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port number
+ * @param	bitValue	: bit(s) in the port to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
+{
+	pGPIO->CLR[portNum] = bitValue;
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pins	: pins (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO->CLR[port] = pins;
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: pin number (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->CLR[port] = (1 << pin);
+}
+
+/**
+ * @brief	Toggle selected GPIO output pins to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pins	: pins (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO->NOT[port] = pins;
+}
+
+/**
+ * @brief	Toggle an individual GPIO output pin to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: pin number (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->NOT[port] = (1 << pin);
+}
+
+/**
+ * @brief	Read current bit states for the selected port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	portNum	: port number to read
+ * @return	Current value of GPIO port
+ * @note	The current states of the bits for the port are read, regardless of
+ * whether the GPIO port bits are input or output.
+ */
+STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
+{
+	return pGPIO->PIN[portNum];
+}
+
+#endif /* defined(CHIP_LPC1347) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_13XX_1_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h
new file mode 100644
index 000000000..d877bbf50
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpio_13xx_2.h
@@ -0,0 +1,641 @@
+/*
+ * @brief LPC13xx GPIO chip driver for LPC13(11/13/42/43) families
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIO_13XX_2_H_
+#define __GPIO_13XX_2_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIO_13XX_2 CHIP: LPC13xx GPIO chip driver for LPC13(11/13/42/43) families
+ * @ingroup CHIP_13XX_Drivers
+ * For device familes identified with CHIP definitions CHIP_LPC1311, CHIP_LPC1313
+ * CHIP_LPC1342 and CHIP_LPC1343 only.
+ * @{
+ */
+
+#if defined(CHIP_LPC1343)
+    
+/**
+ * @brief  GPIO port register block structure
+ */
+typedef struct {				/*!< GPIO_PORT Structure */
+	__IO uint32_t DATA[4096];			/*!< Offset: 0x0000 to 0x3FFC Data address masking register (R/W) */
+	uint32_t RESERVED1[4096];
+	__IO uint32_t DIR;					/*!< Offset: 0x8000 Data direction register (R/W) */
+	__IO uint32_t IS;					/*!< Offset: 0x8004 Interrupt sense register (R/W) */
+	__IO uint32_t IBE;					/*!< Offset: 0x8008 Interrupt both edges register (R/W) */
+	__IO uint32_t IEV;					/*!< Offset: 0x800C Interrupt event register  (R/W) */
+	__IO uint32_t IE;					/*!< Offset: 0x8010 Interrupt mask register (R/W) */
+	__I  uint32_t RIS;					/*!< Offset: 0x8014 Raw interrupt status register (R/ ) */
+	__I  uint32_t MIS;					/*!< Offset: 0x8018 Masked interrupt status register (R/ ) */
+	__O  uint32_t IC;					/*!< Offset: 0x801C Interrupt clear register (W) */
+	uint32_t RESERVED2[8184];			/* Padding added for aligning contiguous GPIO blocks */
+} LPC_GPIO_T;
+
+/**
+ * @brief	Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_GPIO_Init(LPC_GPIO_T *pGPIO);
+
+/**
+ * @brief	De-Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO);
+
+/**
+ * @brief	Set a GPIO port/bit state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	bit		: GPIO bit to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
+{
+	pGPIO[port].DATA[1 << bit] = setting << bit;
+}
+
+/**
+ * @brief	Set a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ * @note	This function replaces Chip_GPIO_WritePortBit()
+ */
+STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
+{
+	pGPIO[port].DATA[1 << pin] = setting << pin;
+}
+
+/**
+ * @brief	Read a GPIO state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	bit		: GPIO bit to read
+ * @return	true of the GPIO is high, false if low
+ * @note	It is recommended to use the Chip_GPIO_GetPinState() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
+{
+	return (bool) ((pGPIO[port].DATA[1 << bit] >> bit) & 1);
+}
+
+/**
+ * @brief	Get a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: GPIO pin to get state for
+ * @return	true if the GPIO is high, false if low
+ * @note	This function replaces Chip_GPIO_ReadPortBit()
+ */
+STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (pGPIO[port].DATA[1 << pin]) != 0;
+}
+
+/**
+ * @brief	Seta GPIO direction
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	bit		: GPIO bit to set
+ * @param	setting	: true for output, false for input
+ * @return	Nothing
+ * @note	It is recommended to use the Chip_GPIO_SetPinDIROutput(),
+ * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
+ * of this function.
+ */
+void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting);
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: GPIO pin to set direction on as output
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DIR |= (1UL << pin);
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: GPIO pin to set direction on as input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DIR &= ~(1UL << pin);
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: GPIO pin to set direction for
+ * @param	output	: true for output, false for input
+ * @return	Nothing
+ */
+void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output);
+
+/**
+ * @brief	Read a GPIO direction (out or in)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	bit		: GPIO bit to read
+ * @return	true of the GPIO is an output, false if input
+ * @note	It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
+{
+	return (bool) (((pGPIO[port].DIR) >> bit) & 1);
+}
+
+/**
+ * @brief	Get GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: GPIO pin to get direction for
+ * @return	true if the GPIO is an output, false if input
+ */
+STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (bool) (pGPIO[port].DIR >> pin) & 1;
+}
+
+/**
+ * @brief	Set Direction for a GPIO port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port Number
+ * @param	bit		: GPIO bit to set
+ * @param	out		: Direction value, 0 = input, !0 = output
+ * @return	None
+ * @note	Bits set to '0' are not altered. It is recommended to use the
+ * Chip_GPIO_SetPortDIR() function instead.
+ */
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit, uint8_t out);
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinMask	: GPIO pin mask to set direction on as output (bits 0..n for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the output direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
+{
+	pGPIO[port].DIR |= pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinMask	: GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
+{
+	pGPIO[port].DIR &= ~pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input or output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinMask	: GPIO pin mask to set direction on (bits 0..b for pins 0..n)
+ * @param	outSet	: Direction value, false = set as inputs, true = set as outputs
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet);
+
+/**
+ * @brief	Get GPIO direction for a all GPIO pins
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	a bitfield containing the input and output states for each pin
+ * @note	For pins 0..n, a high state in a bit corresponds to an output state for the
+ * same pin, while a low  state corresponds to an input state.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].DIR;
+}
+
+/**
+ * @brief	Set all GPIO raw pin states (regardless of masking)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	pGPIO[port].DATA[0xFFF] = value;
+}
+
+/**
+ * @brief	Get all GPIO raw pin states (regardless of masking)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	Current (raw) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].DATA[0xFFF];
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	bit		: Bit(s) in the port to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output. It is recommended to use the
+ * Chip_GPIO_SetPortOutHigh() function instead.
+ */
+STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit)
+{
+	pGPIO[port].DATA[bit] = bit;
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pins	: pins (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO[port].DATA[pins] = 0xFFF;
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: pin number (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DATA[1 << pin] = (1 << pin);
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	bit		: Bit(s) in the port to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit)
+{
+	pGPIO[port].DATA[bit] = ~bit;
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pins	: pins (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO[port].DATA[pins] = 0;
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: pin number (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DATA[1 << pin] = 0;
+}
+
+/**
+ * @brief	Toggle selected GPIO output pins to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pins	: pins (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO[port].DATA[pins] ^= 0xFFF;
+}
+
+/**
+ * @brief	Toggle an individual GPIO output pin to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pin		: pin number (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DATA[1 << pin] ^= (1 << pin);
+}
+
+/**
+ * @brief	Read current bit states for the selected port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number to read
+ * @return	Current value of GPIO port
+ * @note	The current states of the bits for the port are read, regardless of
+ * whether the GPIO port bits are input or output.
+ */
+STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].DATA[4095];
+}
+
+/**
+ * @brief	Configure the pins as edge sensitive for interrupts
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to set to edge mode (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinModeEdge(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IS &= ~pinmask;
+}
+
+/**
+ * @brief	Configure the pins as level sensitive for interrupts
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to set to level mode (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinModeLevel(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IS |= pinmask;
+}
+
+/**
+ * @brief	Returns current GPIO edge or high level interrupt configuration for all pins for a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	A bifield containing the edge/level interrupt configuration for each
+ * pin for the selected port. Bit 0 = pin 0, 1 = pin 1.
+ * For each bit, a 0 means the edge interrupt is configured, while a 1 means a level
+ * interrupt is configured. Mask with this return value to determine the
+ * edge/level configuration for each pin in a port.
+ */
+STATIC INLINE uint32_t Chip_GPIO_IsLevelEnabled(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].IS;
+}
+
+/**
+ * @brief	Sets GPIO interrupt configuration for both edges for selected pins
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to set to dual edge mode (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetEdgeModeBoth(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IBE |= pinmask;
+}
+
+/**
+ * @brief	Sets GPIO interrupt configuration for a single edge for selected pins
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to set to single edge mode (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetEdgeModeSingle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IBE &= ~pinmask;
+}
+
+/**
+ * @brief	Returns current GPIO interrupt dual or single edge configuration for all pins for a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	A bifield containing the single/dual interrupt configuration for each
+ * pin for the selected port. Bit 0 = pin 0, 1 = pin 1.
+ * For each bit, a 0 means the interrupt triggers on a single edge (use the
+ * Chip_GPIO_SetEdgeModeHigh() and Chip_GPIO_SetEdgeModeLow() functions to configure
+ * selected edge), while a 1 means the interrupt triggers on both edges. Mask
+ * with this return value to determine the edge/level configuration for each pin in
+ * a port.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetEdgeModeDir(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].IBE;
+}
+
+/**
+ * @brief	Sets GPIO interrupt configuration when in single edge or level mode to high edge trigger or high level
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to set to high mode (ORed value of bits 0..11)
+ * @return	Nothing
+ * @note	Use this function to select high level or high edge interrupt mode
+ * for the selected pins on the selected port when not in dual edge mode.
+ */
+STATIC INLINE void Chip_GPIO_SetModeHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IEV |= pinmask;
+}
+
+/**
+ * @brief	Sets GPIO interrupt configuration when in single edge or level mode to low edge trigger or low level
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to set to low mode (ORed value of bits 0..11)
+ * @return	Nothing
+ * @note	Use this function to select low level or low edge interrupt mode
+ * for the selected pins on the selected port when not in dual edge mode.
+ */
+STATIC INLINE void Chip_GPIO_SetModeLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IEV &= ~pinmask;
+}
+
+/**
+ * @brief	Returns current GPIO interrupt edge direction or level mode
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	A bifield containing the low or high direction of the interrupt
+ * configuration for each pin for the selected port. Bit 0 = pin 0, 1 = pin 1.
+ * For each bit, a 0 means the interrupt triggers on a low level or edge, while a
+ * 1 means the interrupt triggers on a high level or edge. Mask with this
+ * return value to determine the high/low configuration for each pin in a port.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetModeHighLow(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].IEV;
+}
+
+/**
+ * @brief	Enables interrupts for selected pins on a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to enable interrupts for (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_EnableInt(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IE |= pinmask;
+}
+
+/**
+ * @brief	Disables interrupts for selected pins on a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to disable interrupts for (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_DisableInt(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IE &= ~pinmask;
+}
+
+/**
+ * @brief	Returns current enable pin interrupts for a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	A bifield containing the enabled pin interrupts (0..11)
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetEnabledInts(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].IE;
+}
+
+/**
+ * @brief	Returns raw interrupt pending status for pin interrupts for a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	A bifield containing the raw pending interrupt states for each pin (0..11) on the port
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetRawInts(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].RIS;
+}
+
+/**
+ * @brief	Returns masked interrupt pending status for pin interrupts for a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @return	A bifield containing the masked pending interrupt states for each pin (0..11) on the port
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetMaskedInts(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].MIS;
+}
+
+/**
+ * @brief	Clears pending interrupts for selected pins for a port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: Port number
+ * @param	pinmask	: Pins to clear interrupts for (ORed value of bits 0..11)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_ClearInts(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinmask)
+{
+	pGPIO[port].IC = pinmask;
+}
+
+/**
+ * @brief  GPIO interrupt mode definitions
+ */
+typedef enum {
+	GPIO_INT_ACTIVE_LOW_LEVEL  = 0x0,		/*!< Selects interrupt on pin to be triggered on LOW level */
+	GPIO_INT_ACTIVE_HIGH_LEVEL = 0x1,		/*!< Selects interrupt on pin to be triggered on HIGH level */
+	GPIO_INT_FALLING_EDGE      = 0x2,		/*!< Selects interrupt on pin to be triggered on FALLING level */
+	GPIO_INT_RISING_EDGE       = 0x3,		/*!< Selects interrupt on pin to be triggered on RISING level */
+	GPIO_INT_BOTH_EDGES        = 0x6		/*!< Selects interrupt on pin to be triggered on both edges */
+} GPIO_INT_MODE_T;
+
+/**
+ * @brief	Composite function for setting up a full interrupt configuration for a single pin
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	port		: Port number
+ * @param	pin			: Pin number (0..11)
+ * @param	modeFlags	: GPIO interrupt mode selection
+ * @return	Nothing
+ */
+void Chip_GPIO_SetupPinInt(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, GPIO_INT_MODE_T mode);
+
+#endif /* defined(CHIP_LPC1343) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_13XX_2_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h
new file mode 100644
index 000000000..2b99c0bef
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/gpiogroup_13xx.h
@@ -0,0 +1,209 @@
+/*
+ * @brief LPC13xx GPIO group driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIOGROUP_13XX_H_
+#define __GPIOGROUP_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIOGP_13XX CHIP: LPC13xx GPIO group driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+
+/**
+ * @brief GPIO grouped interrupt register block structure
+ */
+typedef struct {					/*!< GPIO_GROUP_INTn Structure */
+	__IO uint32_t  CTRL;			/*!< GPIO grouped interrupt control register */
+	__I  uint32_t  RESERVED0[7];
+	__IO uint32_t  PORT_POL[8];		/*!< GPIO grouped interrupt port polarity register */
+	__IO uint32_t  PORT_ENA[8];		/*!< GPIO grouped interrupt port m enable register */
+	uint32_t       RESERVED1[1000];
+} LPC_GPIOGROUPINT_T;
+
+/**
+ * LPC13xx GPIO group bit definitions
+ */
+#define GPIOGR_INT      (1 << 0)	/*!< GPIO interrupt pending/clear bit */
+#define GPIOGR_COMB     (1 << 1)	/*!< GPIO interrupt OR(0)/AND(1) mode bit */
+#define GPIOGR_TRIG     (1 << 2)	/*!< GPIO interrupt edge(0)/level(1) mode bit */
+
+/**
+ * @brief	Clear interrupt pending status for the selected group
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	uint32_t temp;
+
+	temp = pGPIOGPINT[group].CTRL;
+	pGPIOGPINT[group].CTRL = temp | GPIOGR_INT;
+}
+
+/**
+ * @brief	Returns current GPIO group inetrrupt pending status
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	true if the group interrupt is pending, otherwise false.
+ */
+STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
+}
+
+/**
+ * @brief	Selected GPIO group functionality for trigger on any pin in group (OR mode)
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL &= ~GPIOGR_COMB;
+}
+
+/**
+ * @brief	Selected GPIO group functionality for trigger on all matching pins in group (AND mode)
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL |= GPIOGR_COMB;
+}
+
+/**
+ * @brief	Selected GPIO group functionality edge trigger mode
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL &= ~GPIOGR_TRIG;
+}
+
+/**
+ * @brief	Selected GPIO group functionality level trigger mode
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL |= GPIOGR_TRIG;
+}
+
+/**
+ * @brief	Set selected pins for the group and port to low level trigger
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+											  uint8_t group,
+											  uint8_t port,
+											  uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_POL[port] &= ~pinMask;
+}
+
+/**
+ * @brief	Set selected pins for the group and port to high level trigger
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+											   uint8_t group,
+											   uint8_t port,
+											   uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_POL[port] |= pinMask;
+}
+
+/**
+ * @brief	Disabled selected pins for the group interrupt
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ * @note	Disabled pins do not contrinute to the group interrupt.
+ */
+STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+												uint8_t group,
+												uint8_t port,
+												uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask;
+}
+
+/**
+ * @brief	Enable selected pins for the group interrupt
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ * @note	Enabled pins contribute to the group interrupt.
+ */
+STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+											   uint8_t group,
+											   uint8_t port,
+											   uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_ENA[port] |= pinMask;
+}
+
+#endif /* defined(CHIP_LPC1347) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIOGROUP_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h
new file mode 100644
index 000000000..a515d3331
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2c_13xx.h
@@ -0,0 +1,539 @@
+/*
+ * @brief LPC13xx I2C driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __I2C_13XX_H_
+#define __I2C_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup I2C_13XX CHIP: LPC13xx I2C driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief I2C register block structure
+ */
+typedef struct {				/* I2C0 Structure         */
+	__IO uint32_t CONSET;		/*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+	__I  uint32_t STAT;			/*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+	__IO uint32_t DAT;			/*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+	__IO uint32_t ADR0;			/*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__IO uint32_t SCLH;			/*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+	__IO uint32_t SCLL;			/*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+	__O  uint32_t CONCLR;		/*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+	__IO uint32_t MMCTRL;		/*!< Monitor mode control register. */
+	__IO uint32_t ADR1;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__IO uint32_t ADR2;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__IO uint32_t ADR3;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__I  uint32_t DATA_BUFFER;	/*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+	__IO uint32_t MASK[4];		/*!< I2C Slave address mask register */
+} LPC_I2C_T;
+
+/**
+ * @brief	Return values for SLAVE handler
+ * @note
+ * Chip drivers will usally be designed to match their events with this value
+ */
+#define RET_SLAVE_TX    6	/**< Return value, when 1 byte TX'd successfully */
+#define RET_SLAVE_RX    5	/**< Return value, when 1 byte RX'd successfully */
+#define RET_SLAVE_IDLE  2	/**< Return value, when slave enter idle mode */
+#define RET_SLAVE_BUSY  0	/**< Return value, when slave is busy */
+
+/**
+ * @brief I2C state handle return values
+ */
+#define I2C_STA_STO_RECV            0x20
+
+/*
+ * @brief I2C Control Set register description
+ */
+#define I2C_I2CONSET_AA             ((0x04))/*!< Assert acknowledge flag */
+#define I2C_I2CONSET_SI             ((0x08))/*!< I2C interrupt flag */
+#define I2C_I2CONSET_STO            ((0x10))/*!< STOP flag */
+#define I2C_I2CONSET_STA            ((0x20))/*!< START flag */
+#define I2C_I2CONSET_I2EN           ((0x40))/*!< I2C interface enable */
+
+/*
+ * @brief I2C Control Clear register description
+ */
+#define I2C_I2CONCLR_AAC            ((1 << 2))	/*!< Assert acknowledge Clear bit */
+#define I2C_I2CONCLR_SIC            ((1 << 3))	/*!< I2C interrupt Clear bit */
+#define I2C_I2CONCLR_STOC           ((1 << 4))	/*!< I2C STOP Clear bit */
+#define I2C_I2CONCLR_STAC           ((1 << 5))	/*!< START flag Clear bit */
+#define I2C_I2CONCLR_I2ENC          ((1 << 6))	/*!< I2C interface Disable bit */
+
+/*
+ * @brief	I2C Common Control register description
+ */
+#define I2C_CON_AA            (1UL << 2)	/*!< Assert acknowledge bit */
+#define I2C_CON_SI            (1UL << 3)	/*!< I2C interrupt bit */
+#define I2C_CON_STO           (1UL << 4)	/*!< I2C STOP bit */
+#define I2C_CON_STA           (1UL << 5)	/*!< START flag bit */
+#define I2C_CON_I2EN          (1UL << 6)	/*!< I2C interface bit */
+
+/*
+ * @brief I2C Status Code definition (I2C Status register)
+ */
+#define I2C_STAT_CODE_BITMASK       ((0xF8))/*!< Return Code mask in I2C status register */
+#define I2C_STAT_CODE_ERROR         ((0xFF))/*!< Return Code error mask in I2C status register */
+
+/*
+ * @brief I2C return status code definitions
+ */
+#define I2C_I2STAT_NO_INF                       ((0xF8))/*!< No relevant information */
+#define I2C_I2STAT_BUS_ERROR                    ((0x00))/*!< Bus Error */
+
+/*
+ * @brief I2C Master transmit mode
+ */
+#define I2C_I2STAT_M_TX_START                   ((0x08))/*!< A start condition has been transmitted */
+#define I2C_I2STAT_M_TX_RESTART                 ((0x10))/*!< A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_NACK               ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_DAT_ACK                 ((0x28))/*!< Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))/*!< Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
+
+/*
+ * @brief I2C Master receive mode
+ */
+#define I2C_I2STAT_M_RX_START                   ((0x08))/*!< A start condition has been transmitted */
+#define I2C_I2STAT_M_RX_RESTART                 ((0x10))/*!< A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))/*!< Arbitration lost */
+#define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_NACK               ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_RX_DAT_ACK                 ((0x50))/*!< Data has been received, ACK has been returned */
+#define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))/*!< Data has been received, NACK has been returned */
+
+/*
+ * @brief I2C Slave receive mode
+ */
+#define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))/*!< Own slave address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA          ((0x68))/*!< Arbitration lost in SLA+R/W as master */
+// #define I2C_I2STAT_S_RX_SLAW_ACK				((0x68)) /*!< Own SLA+W has been received, ACK returned */
+#define I2C_I2STAT_S_RX_GENCALL_ACK             ((0x70))/*!< General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL      ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
+// #define I2C_I2STAT_S_RX_GENCALL_ACK				((0x78)) /*!< General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK         ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK     ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX   ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
+														   SLV/TRX (Slave Transmit) */
+
+/*
+ * @brief I2C Slave transmit mode
+ */
+#define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA          ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
+// #define I2C_I2STAT_S_TX_SLAR_ACK				((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_DAT_ACK                 ((0xB8))/*!< Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))/*!< Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
+#define I2C_SLAVE_TIME_OUT                      0x10000000UL/*!< Time out in case of using I2C slave mode */
+
+/*
+ * @brief I2C Data register definition
+ */
+#define I2C_I2DAT_BITMASK           ((0xFF))/*!< Mask for I2DAT register */
+#define I2C_I2DAT_IDLE_CHAR         (0xFF)	/*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
+											     its sending data length that can be supported */
+
+/*
+ * @brief I2C Monitor mode control register description
+ */
+#define I2C_I2MMCTRL_MM_ENA         ((1 << 0))			/**< Monitor mode enable */
+#define I2C_I2MMCTRL_ENA_SCL        ((1 << 1))			/**< SCL output enable */
+#define I2C_I2MMCTRL_MATCH_ALL      ((1 << 2))			/**< Select interrupt register match */
+#define I2C_I2MMCTRL_BITMASK        ((0x07))		/**< Mask for I2MMCTRL register */
+
+/*
+ * @brief I2C Data buffer register description
+ */
+#define I2DATA_BUFFER_BITMASK       ((0xFF))/*!< I2C Data buffer register bit mask */
+
+/*
+ * @brief I2C Slave Address registers definition
+ */
+#define I2C_I2ADR_GC                ((1 << 0))	/*!< General Call enable bit */
+#define I2C_I2ADR_BITMASK           ((0xFF))/*!< I2C Slave Address registers bit mask */
+
+/*
+ * @brief I2C Mask Register definition
+ */
+#define I2C_I2MASK_MASK(n)          ((n & 0xFE))/*!< I2C Mask Register mask field */
+
+/*
+ * @brief I2C SCL HIGH duty cycle Register definition
+ */
+#define I2C_I2SCLH_BITMASK          ((0xFFFF))	/*!< I2C SCL HIGH duty cycle Register bit mask */
+
+/*
+ * @brief I2C SCL LOW duty cycle Register definition
+ */
+#define I2C_I2SCLL_BITMASK          ((0xFFFF))	/*!< I2C SCL LOW duty cycle Register bit mask */
+
+/*
+ * @brief I2C status values
+ */
+#define I2C_SETUP_STATUS_ARBF   (1 << 8)	/**< Arbitration false */
+#define I2C_SETUP_STATUS_NOACKF (1 << 9)	/**< No ACK returned */
+#define I2C_SETUP_STATUS_DONE   (1 << 10)	/**< Status DONE */
+
+/*
+ * @brief I2C state handle return values
+ */
+#define I2C_OK                      0x00
+#define I2C_BYTE_SENT               0x01
+#define I2C_BYTE_RECV               0x02
+#define I2C_LAST_BYTE_RECV          0x04
+#define I2C_SEND_END                0x08
+#define I2C_RECV_END                0x10
+#define I2C_STA_STO_RECV            0x20
+
+#define I2C_ERR                     (0x10000000)
+#define I2C_NAK_RECV                (0x10000000 | 0x01)
+
+#define I2C_CheckError(ErrorCode)   (ErrorCode & 0x10000000)
+
+/*
+ * @brief I2C monitor control configuration defines
+ */
+#define I2C_MONITOR_CFG_SCL_OUTPUT  I2C_I2MMCTRL_ENA_SCL		/**< SCL output enable */
+#define I2C_MONITOR_CFG_MATCHALL    I2C_I2MMCTRL_MATCH_ALL		/**< Select interrupt register match */
+
+/**
+ * @brief	I2C Slave Identifiers
+ */
+typedef enum {
+	I2C_SLAVE_GENERAL,	/**< Slave ID for general calls */
+	I2C_SLAVE_0,		/**< Slave ID fo Slave Address 0 */
+	I2C_SLAVE_1,		/**< Slave ID fo Slave Address 1 */
+	I2C_SLAVE_2,		/**< Slave ID fo Slave Address 2 */
+	I2C_SLAVE_3,		/**< Slave ID fo Slave Address 3 */
+	I2C_SLAVE_NUM_INTERFACE	/**< Number of slave interfaces */
+} I2C_SLAVE_ID;
+
+/**
+ * @brief	I2C transfer status
+ */
+typedef enum {
+	I2C_STATUS_DONE,	/**< Transfer done successfully */
+	I2C_STATUS_NAK,		/**< NAK received during transfer */
+	I2C_STATUS_ARBLOST,	/**< Aribitration lost during transfer */
+	I2C_STATUS_BUSERR,	/**< Bus error in I2C transfer */
+	I2C_STATUS_BUSY,	/**< I2C is busy doing transfer */
+} I2C_STATUS_T;
+
+/**
+ * @brief Master transfer data structure definitions
+ */
+typedef struct {
+	uint8_t slaveAddr;		/**< 7-bit I2C Slave address */
+	const uint8_t *txBuff;	/**< Pointer to array of bytes to be transmitted */
+	int     txSz;			/**< Number of bytes in transmit array,
+							   if 0 only receive transfer will be carried on */
+	uint8_t *rxBuff;		/**< Pointer memory where bytes received from I2C be stored */
+	int     rxSz;			/**< Number of bytes to received,
+							   if 0 only transmission we be carried on */
+	I2C_STATUS_T status;	/**< Status of the current I2C transfer */
+} I2C_XFER_T;
+
+/**
+ * @brief	I2C interface IDs
+ * @note
+ * All Chip functions will take this as the first parameter,
+ * I2C_NUM_INTERFACE must never be used for calling any Chip
+ * functions, it is only used to find the number of interfaces
+ * available in the Chip.
+ */
+typedef enum I2C_ID {
+	I2C0,				/**< ID I2C0 */
+	I2C_NUM_INTERFACE	/**< Number of I2C interfaces in the chip */
+} I2C_ID_T;
+
+/**
+ * @brief	I2C master events
+ */
+typedef enum {
+	I2C_EVENT_WAIT = 1,	/**< I2C Wait event */
+	I2C_EVENT_DONE,		/**< Done event that wakes up Wait event */
+	I2C_EVENT_LOCK,		/**< Re-entrency lock event for I2C transfer */
+	I2C_EVENT_UNLOCK,	/**< Re-entrency unlock event for I2C transfer */
+	I2C_EVENT_SLAVE_RX,	/**< Slave receive event */
+	I2C_EVENT_SLAVE_TX,	/**< Slave transmit event */
+} I2C_EVENT_T;
+
+/**
+ * @brief	Event handler function type
+ */
+typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);
+
+/**
+ * @brief	Initializes the LPC_I2C peripheral with specified parameter.
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_Init(I2C_ID_T id);
+
+/**
+ * @brief	De-initializes the I2C peripheral registers to their default reset values
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_DeInit(I2C_ID_T id);
+
+/**
+ * @brief	Set up clock rate for LPC_I2C peripheral.
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	clockrate	: Target clock rate value to initialized I2C peripheral (Hz)
+ * @return	Nothing
+ * @note
+ * Parameter @a clockrate for I2C0 should be from 1000 up to 1000000
+ * (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. If the @a clockrate
+ * is more than 400 KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()
+ * must be called prior to calling this function.
+ */
+void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);
+
+/**
+ * @brief	Get current clock rate for LPC_I2C peripheral.
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	The current I2C peripheral clock rate
+ */
+uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);
+
+/**
+ * @brief	Transmit and Receive data in master mode
+ * @param	id		: I2C peripheral selected (I2C0, I2C1 etc)
+ * @param	xfer	: Pointer to a I2C_XFER_T structure see notes below
+ * @return
+ * Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes
+ * not sent due to error, xfer->rxSz will have the number of bytes yet
+ * to be received.
+ * @note
+ * The parameter @a xfer should have its member @a slaveAddr initialized
+ * to the 7-Bit slave address to which the master will do the xfer, Bit0
+ * to bit6 should have the address and Bit8 is ignored. During the transfer
+ * no code (like event handler) must change the content of the memory
+ * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
+ * initialized to the memory from which the I2C must pick the data to be
+ * transfered to slave and the number of bytes to send respectively, similarly
+ * @a rxBuff and @a rxSz must have pointer to memroy where data received
+ * from slave be stored and the number of data to get from slave respectilvely.
+ */
+int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);
+
+/**
+ * @brief	Transmit data to I2C slave using I2C Master mode
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 .. etc)
+ * @param	slaveAddr	: Slave address to which the data be written
+ * @param	buff		: Pointer to buffer having the array of data
+ * @param	len			: Number of bytes to be transfered from @a buff
+ * @return	Number of bytes successfully transfered
+ */
+int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);
+
+/**
+ * @brief	Transfer a command to slave and receive data from slave after a repeated start
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	slaveAddr	: Slave address of the I2C device
+ * @param	cmd			: Command (Address/Register) to be written
+ * @param	buff		: Pointer to memory that will hold the data received
+ * @param	len			: Number of bytes to receive
+ * @return	Number of bytes successfully received
+ */
+int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);
+
+/**
+ * @brief	Get pointer to current function handling the events
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Pointer to function handing events of I2C
+ */
+I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);
+
+/**
+ * @brief	Set function that must handle I2C events
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	event		: Pointer to function that will handle the event (Should not be NULL)
+ * @return	1 when successful, 0 when a transfer is on going with its own event handler
+ */
+int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);
+
+/**
+ * @brief	Set function that must handle I2C events
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	slaveAddr	: Slave address from which data be read
+ * @param	buff		: Pointer to memory where data read be stored
+ * @param	len			: Number of bytes to read from slave
+ * @return	Number of bytes read successfully
+ */
+int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);
+
+/**
+ * @brief	Default event handler for polling operation
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	event	: Event ID of the event that called the function
+ * @return	Nothing
+ */
+void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);
+
+/**
+ * @brief	Default event handler for interrupt base operation
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	event	: Event ID of the event that called the function
+ * @return	Nothing
+ */
+void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);
+
+/**
+ * @brief	I2C Master transfer state change handler
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ * @note	Usually called from the appropriate Interrupt handler
+ */
+void Chip_I2C_MasterStateHandler(I2C_ID_T id);
+
+/**
+ * @brief	Disable I2C peripheral's operation
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_Disable(I2C_ID_T id);
+
+/**
+ * @brief	Checks if master xfer in progress
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	1 if master xfer in progress 0 otherwise
+ * @note
+ * This API is generally used in interrupt handler
+ * of the application to decide whether to call
+ * master state handler or to call slave state handler
+ */
+int Chip_I2C_IsMasterActive(I2C_ID_T id);
+
+/**
+ * @brief	Setup a slave I2C device
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	sid			: I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)
+ * @param	xfer		: Pointer to transfer structure (see note below for more info)
+ * @param	event		: Event handler for slave transfers
+ * @param	addrMask	: Address mask to use along with slave address (see notes below for more info)
+ * @return	Nothing
+ * @note
+ * Parameter @a xfer should point to a valid I2C_XFER_T structure object
+ * and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),
+ * Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will
+ * be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers
+ * where slave can receive or send the data from, size of which will be provided by
+ * @a rxSz and @a txSz respectively. Function pointed to by @a event will be called
+ * for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully
+ * from the master and stored inside memory pointed by xfer->rxBuff, incremented
+ * the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of
+ * data from xfer->txBuff was sent to master successfully, incremented the pointer
+ * and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers
+ * with the slave).<br>
+ * <br>Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1
+ * to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as
+ * don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then
+ * 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered
+ * slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual
+ * address which was received from master.<br>
+ * <br><b>General Call Handling</b><br>
+ * Slave can receive data from master using general call address (0x00). General call
+ * handling must be setup as given below
+ *      - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL
+ *          - xfer->slaveAddr ignored, argument @a addrMask ignored
+ *          - function provided by @a event will registered to be called when slave received data using addr 0x00
+ *          - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer
+ *      - To handle General Call only (No other slaves are configured)
+ *          - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
+ *          - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL
+ *          - provide @a addrMask (typically 0, if not you better be knowing what you are doing)
+ *      - To handler General Call when other slave is active
+ *          - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
+ *          - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]
+ *          - Set Bit0 of @a xfer->slaveAddr as 1
+ *          - Provide appropriate @a addrMask
+ *          - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC
+ * @warning
+ * If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler
+ * will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer
+ * then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be
+ * called to notify this. For more info see section below<br>
+ * <br><b> Last data handling in slave </b><br>
+ * If the user wants to implement a slave which will read a byte from a specific location over and over
+ * again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read
+ * the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from
+ * xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another
+ * byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will
+ * occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte
+ * event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer
+ * and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte
+ * in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and
+ * the process repeats.
+ */
+void Chip_I2C_SlaveSetup(I2C_ID_T id,
+						 I2C_SLAVE_ID sid,
+						 I2C_XFER_T *xfer,
+						 I2C_EVENTHANDLER_T event,
+						 uint8_t addrMask);
+
+/**
+ * @brief	I2C Slave event handler
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_SlaveStateHandler(I2C_ID_T id);
+
+/**
+ * @brief	I2C peripheral state change checking
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	1 if I2C peripheral @a id has changed its state,
+ *          0 if there is no state change
+ * @note
+ * This function must be used by the application when
+ * the polling has to be done based on state change.
+ */
+int Chip_I2C_IsStateChanged(I2C_ID_T id);
+
+/**
+ * @}
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2C_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h
new file mode 100644
index 000000000..2576444a9
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/i2cm_13xx.h
@@ -0,0 +1,416 @@
+/*
+ * @brief LPC13XX I2C master driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __I2CM_13XX_H_
+#define __I2CM_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup I2CM_13XX CHIP: LPC13xx I2C master-only driver
+ * @ingroup I2C_13XX
+ * This driver only works in master mode. To describe the I2C transactions
+ * following symbols are used in driver documentation.
+ *
+ * Key to symbols
+ * ==============
+ * S     (1 bit) : Start bit
+ * P     (1 bit) : Stop bit
+ * Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
+ * A, NA (1 bit) : Acknowledge and Not-Acknowledge bit.
+ * Addr  (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
+ *                 get a 10 bit I2C address.
+ * Data  (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
+ *                 for 16 bit data.
+ * [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
+ * @{
+ */
+
+/** I2CM_13XX_OPTIONS_TYPES I2C master transfer options
+ * @{
+ */
+
+/** Ignore NACK during data transfer. By default transfer is aborted. */
+#define I2CM_XFER_OPTION_IGNORE_NACK     0x01
+/** ACK last byte received. By default we NACK last byte we receive per I2C spec. */
+#define I2CM_XFER_OPTION_LAST_RX_ACK     0x02
+
+/**
+ * @}
+ */
+
+/** I2CM_13XX_STATUS_TYPES I2C master transfer status types
+ * @{
+ */
+
+#define I2CM_STATUS_OK              0x00		/*!< Requested Request was executed successfully. */
+#define I2CM_STATUS_ERROR           0x01		/*!< Unknown error condition. */
+#define I2CM_STATUS_NAK             0x02		/*!< No acknowledgement received from slave. */
+#define I2CM_STATUS_BUS_ERROR       0x03		/*!< I2C bus error */
+#define I2CM_STATUS_SLAVE_NAK       0x04		/*!< No device responded for given slave address during SLA+W or SLA+R */
+#define I2CM_STATUS_ARBLOST         0x05		/*!< Arbitration lost. */
+#define I2CM_STATUS_BUSY            0xFF		/*!< I2C transmistter is busy. */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Master transfer data structure definitions
+ */
+typedef struct {
+	uint8_t slaveAddr;		/*!< 7-bit I2C Slave address */
+	uint8_t options;		/*!< Options for transfer*/
+	uint16_t status;		/*!< Status of the current I2C transfer */
+	uint16_t txSz;			/*!< Number of bytes in transmit array,
+							   if 0 only receive transfer will be carried on */
+	uint16_t rxSz;			/*!< Number of bytes to received,
+							   if 0 only transmission we be carried on */
+	const uint8_t *txBuff;	/*!< Pointer to array of bytes to be transmitted */
+	uint8_t *rxBuff;		/*!< Pointer memory where bytes received from I2C be stored */
+} I2CM_XFER_T;
+
+/**
+ * @brief	Initialize I2C Interface
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function enables the I2C clock.
+ */
+void Chip_I2CM_Init(LPC_I2C_T *pI2C);
+
+/**
+ * @brief	Shutdown I2C Interface
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function disables the I2C clock.
+ */
+void Chip_I2CM_DeInit(LPC_I2C_T *pI2C);
+
+/**
+ * @brief	Sets HIGH and LOW duty cycle registers
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	sclH	: Number of I2C_PCLK cycles for the SCL HIGH time.
+ * @param	sclL	: Number of I2C_PCLK cycles for the SCL LOW time.
+ * @return	Nothing
+ * @note	The frequency is determined by the following formula (I2C_PCLK
+ *          is the frequency of the peripheral I2C clock): <br>
+ *              I2C_bitFrequency = (I2C_PCLK)/(sclH + sclL);
+ */
+static INLINE void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
+{
+	pI2C->SCLH = (uint32_t) sclH;
+	pI2C->SCLL = (uint32_t) sclL;
+}
+
+/**
+ * @brief	Set up bus speed for LPC_I2C controller
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	busSpeed	: I2C bus clock rate
+ * @return	Nothing
+ * @note	Per I2C specification the busSpeed should be
+ *          @li 100000 for Standard mode
+ *          @li 400000 for Fast mode
+ *          @li 1000000 for Fast mode plus
+ *          IOCON registers corresponding to I2C pads should be updated
+ *          according to the bus mode.
+ */
+void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed);
+
+/**
+ * @brief	Transmit START or Repeat-START signal on I2C bus
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function sets the controller to transmit START condition when
+ *          the bus becomes free.
+ */
+static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C)
+{
+	pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
+}
+
+/**
+ * @brief	Reset I2C controller state
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function clears all control/status flags.
+ */
+static INLINE void Chip_I2CM_ResetControl(LPC_I2C_T *pI2C)
+{
+	/* Reset STA, STO, SI */
+	pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
+
+}
+
+/**
+ * @brief	Transmit a single data byte through the I2C peripheral
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	data	: Byte to transmit
+ * @return	Nothing
+ * @note	This function attempts to place a byte into the UART transmit
+ *			FIFO or transmit hold register regard regardless of UART state
+ *
+ */
+static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data)
+{
+	pI2C->DAT = (uint32_t) data;
+}
+
+/**
+ * @brief	Read a single byte data from the I2C peripheral
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	A single byte of data read
+ * @note	This function reads a byte from the I2C receive hold register
+ *			regardless of I2C state. The I2C status should be read first prior
+ *			to using this function.
+ */
+static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C)
+{
+	return (uint8_t) (pI2C->DAT & I2C_I2DAT_BITMASK);
+}
+
+/**
+ * @brief	Generate NACK after receiving next byte
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function sets the controller to NACK after receiving next
+ *          byte from slave transmitter. Used before receiving last byte.
+ */
+static INLINE void Chip_I2CM_NackNextByte(LPC_I2C_T *pI2C)
+{
+	pI2C->CONCLR = I2C_CON_AA;
+}
+
+/**
+ * @brief	Transmit STOP signal on I2C bus
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function sets the controller to transmit STOP condition.
+ */
+static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C)
+{
+	pI2C->CONSET = I2C_CON_STO;
+}
+
+/**
+ * @brief	Force start I2C transmit
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function force I2C state machine to start transmitting.
+ *			If an uncontrolled source generates a superfluous START or masks
+ *          a STOP condition, then the I2C-bus stays busy indefinitely. If
+ *          the STA flag is set and bus access is not obtained within a
+ *          reasonable amount of time, then a forced access to the I2C-bus is
+ *          possible. This is achieved by setting the STO flag while the STA
+ *          flag is still set. No STOP condition is transmitted.
+ */
+static INLINE void Chip_I2CM_ForceStart(LPC_I2C_T *pI2C)
+{
+	/* check if we are pending on start */
+	if (pI2C->CONSET & I2C_CON_STA) {
+		pI2C->CONSET = I2C_CON_STO;
+	}
+	else {
+		Chip_I2CM_SendStart(pI2C);
+	}
+}
+
+/**
+ * @brief	Transmit STOP+START signal on I2C bus
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note	This function sets the controller to transmit STOP condition
+ *          followed by a START condition.
+ */
+static INLINE void Chip_I2CM_SendStartAfterStop(LPC_I2C_T *pI2C)
+{
+	pI2C->CONSET = I2C_CON_STO | I2C_CON_STA;
+}
+
+/**
+ * @brief	Check if I2C controller state changed
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Returns 0 if state didn't change
+ * @note
+ */
+static INLINE uint32_t Chip_I2CM_StateChanged(LPC_I2C_T *pI2C)
+{
+	return pI2C->CONSET & I2C_CON_SI;
+}
+
+/**
+ * @brief	Clear state change interrupt flag
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note
+ */
+static INLINE void Chip_I2CM_ClearSI(LPC_I2C_T *pI2C)
+{
+	pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
+}
+
+/**
+ * @brief	Check if I2C bus is free per our controller
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Returns 0 if busy else a non-zero value.
+ * @note	I2C controller clears STO bit when it sees STOP
+ *          condition after a START condition on the bus.
+ */
+static INLINE uint32_t Chip_I2CM_BusFree(LPC_I2C_T *pI2C)
+{
+	return !(pI2C->CONSET & I2C_CON_STO);
+}
+
+/**
+ * @brief	Get current state of the I2C controller
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Returns 0 if busy else a non-zero value.
+ * @note	I2C controller clears STO bit when it sees STOP
+ *          condition after a START condition on the bus.
+ */
+static INLINE uint32_t Chip_I2CM_GetCurState(LPC_I2C_T *pI2C)
+{
+	return pI2C->STAT & I2C_STAT_CODE_BITMASK;
+}
+
+/**
+ * @brief	Disable I2C interface
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @return	Nothing
+ * @note
+ */
+static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C)
+{
+	pI2C->CONCLR = I2C_CON_I2EN;
+}
+
+/**
+ * @brief	Transfer state change handler handler
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	xfer	: Pointer to a I2CM_XFER_T structure see notes below
+ * @return Returns non-zero value on completion of transfer. The @a status
+ *         member of @a xfer structure contains the current status of the
+ *         transfer at the end of the call.
+ * @note
+ * The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer()
+ * routine.
+ */
+uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
+
+/**
+ * @brief	Transmit and Receive data in master mode
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	xfer	: Pointer to a I2CM_XFER_T structure see notes below
+ * @return Nothing.
+ * @note
+ * The parameter @a xfer should have its member @a slaveAddr initialized
+ * to the 7-Bit slave address to which the master will do the xfer, Bit0
+ * to bit6 should have the address and Bit8 is ignored. During the transfer
+ * no code (like event handler) must change the content of the memory
+ * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
+ * initialized to the memory from which the I2C must pick the data to be
+ * transfered to slave and the number of bytes to send respectively, similarly
+ * @a rxBuff and @a rxSz must have pointer to memroy where data received
+ * from slave be stored and the number of data to get from slave respectilvely.
+ * Following types of transfers are possible:
+ * - Write-only transfer: When @a rxSz member of @a xfer is set to 0.
+ *
+ *          S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P
+ *
+ *      - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options memeber
+ *
+ *          S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P
+ *
+ * - Read-only transfer: When @a txSz member of @a xfer is set to 0.
+ *
+ *          S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
+ *
+ *      - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options memeber
+ *
+ *          S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P
+ *
+ * - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero.
+ *
+ *          S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A]
+ *              S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
+ *
+ */
+void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
+
+/**
+ * @brief	Transmit and Receive data in master mode
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	xfer	: Pointer to a I2CM_XFER_T structure see notes below
+ * @return Returns non-zero value on succesful completion of transfer.
+ * @note
+ * This function operates same as Chip_I2CM_Xfer(), but is a blocking call.
+ */
+uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
+
+/**
+ * @brief	Write given buffer of data to I2C interface
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	buff	: Pointer to buffer to be transmitted
+ * @param	len     : Length of the buffer
+ * @return	Returns number of bytes written.
+ * @note	This function is a blocking call. The function generates
+ *          START/repeat-START condition on bus and starts transmitting
+ *          data untill transfer finishes or a NACK is received. No
+ *          STOP condition is transmitted on the bus.
+ *
+ *          S Data0 [A] Data1 [A] ... DataN [A]
+ */
+uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len);
+
+/**
+ * @brief	Read data from I2C slave to given buffer
+ * @param	pI2C	: Pointer to selected I2C peripheral
+ * @param	buff	:   Pointer to buffer for data received from I2C slave
+ * @param	len     : Length of the buffer
+ * @return	Returns number of bytes read.
+ * @note	This function is a blocking call. The function generates
+ *          START/repeat-START condition on bus and starts reading
+ *          data untill requested number of bytes are read. No
+ *          STOP condition is transmitted on the bus.
+ *
+ *          S [Data0] A [Data1] A ... [DataN] A
+ */
+uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len);
+
+/**
+ * @}
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2C_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h
new file mode 100644
index 000000000..09e941d5f
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/iocon_13xx.h
@@ -0,0 +1,287 @@
+/*
+ * @brief LPC13xx IOCON registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __IOCON_13XX_H_
+#define __IOCON_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IOCON_13XX CHIP: LPC13xx IO Control driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/** 
+ * @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format 
+ */ 
+typedef struct {
+#if defined(CHIP_LPC1347)
+	uint32_t port:8;		/* Pin port */
+	uint32_t pin:8;			/* Pin number */
+	uint32_t modefunc:16;	/* Function and mode */
+#else
+	uint32_t pin:8;			/* Pin number */
+	uint32_t modefunc:24;	/* Function and mode */
+#endif
+} PINMUX_GRP_T;
+
+
+/**
+ * @brief IO Configuration Unit register block structure
+ */
+#if defined(CHIP_LPC1347)
+typedef struct {						/*!< LPC1347 IOCON Structure */
+	__IO uint32_t  PIO0[24];
+	__IO uint32_t  PIO1[32];
+} LPC_IOCON_T;
+
+#else
+/**
+ * @brief LPC13XX I/O Configuration register offset
+ */
+typedef enum CHIP_IOCON_PIO {
+	IOCON_PIO0_0 = (0x00C >> 2),
+	IOCON_PIO0_1 = (0x010 >> 2),
+	IOCON_PIO0_2 = (0x01C >> 2),
+	IOCON_PIO0_3 = (0x02C >> 2),
+	IOCON_PIO0_4 = (0x030 >> 2),
+	IOCON_PIO0_5 = (0x034 >> 2),
+	IOCON_PIO0_6 = (0x04C >> 2),
+	IOCON_PIO0_7 = (0x050 >> 2),
+	IOCON_PIO0_8 = (0x060 >> 2),
+	IOCON_PIO0_9 = (0x064 >> 2),
+	IOCON_PIO0_11 = (0x074 >> 2),
+
+	IOCON_PIO1_0 = (0x078 >> 2),
+	IOCON_PIO1_1 = (0x07C >> 2),
+	IOCON_PIO1_2 = (0x080 >> 2),
+	IOCON_PIO1_3 = (0x090 >> 2),
+	IOCON_PIO1_4 = (0x094 >> 2),
+	IOCON_PIO1_5 = (0x0A0 >> 2),
+	IOCON_PIO1_6 = (0x0A4 >> 2),
+	IOCON_PIO1_7 = (0x0A8 >> 2),
+	IOCON_PIO1_8 = (0x014 >> 2),
+	IOCON_PIO1_9 = (0x038 >> 2),
+	IOCON_PIO1_10 = (0x06C >> 2),
+	IOCON_PIO1_11 = (0x098 >> 2),
+
+	IOCON_PIO2_0 = (0x008 >> 2),
+	IOCON_PIO2_1 = (0x028 >> 2),
+	IOCON_PIO2_2 = (0x05C >> 2),
+	IOCON_PIO2_3 = (0x08C >> 2),
+	IOCON_PIO2_4 = (0x040 >> 2),
+	IOCON_PIO2_5 = (0x044 >> 2),
+	IOCON_PIO2_6 = (0x000 >> 2),
+	IOCON_PIO2_7 = (0x020 >> 2),
+	IOCON_PIO2_8 = (0x024 >> 2),
+	IOCON_PIO2_9 = (0x054 >> 2),
+	IOCON_PIO2_10 = (0x058 >> 2),
+	IOCON_PIO2_11 = (0x070 >> 2),
+
+	IOCON_PIO3_0 = (0x084 >> 2),
+	IOCON_PIO3_1 = (0x088 >> 2),
+	IOCON_PIO3_2 = (0x09C >> 2),
+	IOCON_PIO3_3 = (0x0AC >> 2),
+	IOCON_PIO3_4 = (0x03C >> 2),
+	IOCON_PIO3_5 = (0x048 >> 2),
+} CHIP_IOCON_PIO_T;
+
+/**
+ * @brief LPC13XX Pin location select
+ */
+typedef enum CHIP_IOCON_PIN_LOC {
+	IOCON_SCKLOC_PIO0_10        = (0xB0),		/*!< Selects SCK0 function in pin location PIO0_10 */
+	IOCON_SCKLOC_PIO2_11        = (0xB0 | 1),	/*!< Selects SCK0 function in pin location PIO2_11 */
+	IOCON_SCKLOC_PIO0_6         = (0xB0 | 2),	/*!< Selects SCK0 function in pin location PIO0_6 */
+	IOCON_DSRLOC_PIO2_1         = (0xB4),		/*!< Selects DSR function in pin location PIO2_1 */
+	IOCON_DSRLOC_PIO3_1         = (0xB4 | 1),	/*!< Selects DSR function in pin location PIO3_1 */
+	IOCON_DCDLOC_PIO2_2         = (0xB8),		/*!< Selects DCD function in pin location PIO2_2 */
+	IOCON_DCDLOC_PIO3_2         = (0xB8 | 1),	/*!< Selects DCD function in pin location PIO3_2 */
+	IOCON_RILOC_PIO2_3          = (0xBC),		/*!< Selects RI function in pin location PIO2_3 */
+	IOCON_RILOC_PIO3_3          = (0xBC | 1),	/*!< Selects Ri function in pin location PIO3_3 */
+} CHIP_IOCON_PIN_LOC_T;
+
+typedef struct {						/*!< LPC1343 IOCON Structure */
+	__IO uint32_t  REG[48];
+} LPC_IOCON_T;
+#endif
+
+/**
+ * IOCON function and mode selection definitions
+ * See the User Manual for specific modes and functions supoprted by the
+ * various LPC13xx devices. Functionality can vary per device.
+ */
+#define IOCON_FUNC0             0x0				/*!< Selects pin function 0 */
+#define IOCON_FUNC1             0x1				/*!< Selects pin function 1 */
+#define IOCON_FUNC2             0x2				/*!< Selects pin function 2 */
+#define IOCON_FUNC3             0x3				/*!< Selects pin function 3 */
+#define IOCON_FUNC4             0x4				/*!< Selects pin function 4 */
+#define IOCON_FUNC5             0x5				/*!< Selects pin function 5 */
+#define IOCON_FUNC6             0x6				/*!< Selects pin function 6 */
+#define IOCON_FUNC7             0x7				/*!< Selects pin function 7 */
+#define IOCON_MODE_INACT        (0x0 << 3)		/*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN     (0x1 << 3)		/*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP       (0x2 << 3)		/*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER     (0x3 << 3)		/*!< Selects pin repeater function */
+#define IOCON_HYS_EN            (0x1 << 5)		/*!< Enables hysteresis */
+#define IOCON_INV_EN            (0x1 << 6)		/*!< Enables invert function on input */
+#define IOCON_RESERVED_BIT_6    (0x1 << 6)		/*!< Reserved, must be set. */
+#define IOCON_RESERVED_BIT_7    (0x1 << 7)		/*!< Reserved, must be set. */
+#define IOCON_ADMODE_EN         (0x0 << 7)		/*!< Enables analog input function (analog pins only) */
+#define IOCON_DIGMODE_EN        (0x1 << 7)		/*!< Enables digital function (analog pins only) */
+#define IOCON_SFI2C_EN          (0x0 << 8)		/*!< I2C standard mode/fast-mode */
+#define IOCON_STDI2C_EN         (0x1 << 8)		/*!< I2C standard I/O functionality */
+#define IOCON_FASTI2C_EN        (0x2 << 8)		/*!< I2C Fast-mode Plus */
+#define IOCON_FILT_DIS          (0x1 << 8)		/*!< Disables noise pulses filtering (10nS glitch filter) */
+#define IOCON_OPENDRAIN_EN      (0x1 << 10)		/*!< Enables open-drain function */
+
+/**
+ * IOCON function and mode selection definitions (old)
+ * For backwards compatibility.
+ */
+#define MD_PLN					(0x0 << 3)		/*!< Disable pull-down and pull-up resistor at resistor at pad */
+#define MD_PDN					(0x1 << 3)		/*!< Enable pull-down resistor at pad */
+#define MD_PUP					(0x2 << 3)		/*!< Enable pull-up resistor at pad */
+#define MD_BUK					(0x3 << 3)		/*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
+#define MD_HYS					(0x1 << 5)		/*!< Enable hysteresis */
+#define MD_INV					(0x1 << 6)		/*!< Invert enable */
+#define MD_ADMODE				(0x0 << 7)		/*!< Select analog mode */
+#define MD_DIGMODE				(0x1 << 7)		/*!< Select digitial mode */
+#define MD_DISFIL				(0x0 << 8)		/*!< Disable 10nS input glitch filter */
+#define MD_ENFIL				(0x1 << 8)		/*!< Enable 10nS input glitch filter */
+#define MD_SFI2C				(0x0 << 8)		/*!< I2C standard mode/fast-mode */
+#define MD_STDI2C				(0x1 << 8)		/*!< I2C standard I/O functionality */
+#define MD_FASTI2C				(0x2 << 8)		/*!< I2C Fast-mode Plus */
+#define MD_OPENDRAIN			(0x1 << 10)		/*!< Open drain mode bit */
+#define FUNC0 0x0
+#define FUNC1 0x1
+#define FUNC2 0x2
+#define FUNC3 0x3
+#define FUNC4 0x4
+#define FUNC5 0x5
+#define FUNC6 0x6
+#define FUNC7 0x7
+
+#if defined(CHIP_LPC1347)
+/**
+ * @brief	Sets I/O Control pin mux
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port		: GPIO port to mux
+ * @param	pin			: GPIO pin to mux
+ * @param	modefunc	: OR'ed values or type IOCON_*
+ * @return	Nothing
+ */
+void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc);
+
+/**
+ * @brief	I/O Control pin mux
+ * @param	pIOCON	: The base of IOCON peripheral on the chip
+ * @param	port	: GPIO port to mux
+ * @param	pin		: GPIO pin to mux
+ * @param	mode	: OR'ed values or type IOCON_*
+ * @param	func	: Pin function, value of type IOCON_FUNC?
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
+{
+	Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func));
+}
+
+#else
+
+/**
+ * @brief	Sets I/O Control pin mux
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	pin			: GPIO pin to mux
+ * @param	modefunc	: OR'ed values or type IOCON_*
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint32_t modefunc)
+{
+	pIOCON->REG[pin] = modefunc;
+}
+
+/**
+ * @brief	I/O Control pin mux
+ * @param	pIOCON	: The base of IOCON peripheral on the chip
+ * @param	pin		: GPIO pin to mux
+ * @param	mode	: OR'ed values or type IOCON_*
+ * @param	func	: Pin function, value of type IOCON_FUNC?
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint16_t mode, uint8_t func)
+{
+	Chip_IOCON_PinMuxSet(pIOCON, pin, (uint32_t) (mode | func));
+}
+
+/**
+ * @brief	Select pin location
+ * @param	pIOCON	: The base of IOCON peripheral on the chip
+ * @param	sel		: location selection
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_PinLocSel(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIN_LOC_T sel)
+{
+	pIOCON->REG[sel >> 2] = sel & 0x03;
+}
+
+#endif /* defined(CHIP_LPC1347) */
+
+/**
+ * @brief	Set all I/O Control pin muxing
+ * @param	pIOCON	    : The base of IOCON peripheral on the chip
+ * @param	pinArray    : Pointer to array of pin mux selections
+ * @param	arrayLength : Number of entries in pinArray
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength)
+{
+	uint32_t ix;
+	for (ix = 0; ix < arrayLength; ix++ ) {
+#if defined(CHIP_LPC1347)
+		Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].port, pinArray[ix].pin, pinArray[ix].modefunc);
+#else
+		Chip_IOCON_PinMuxSet(pIOCON, (CHIP_IOCON_PIO_T) pinArray[ix].pin, pinArray[ix].modefunc);
+#endif
+	}
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IOCON_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h
new file mode 100644
index 000000000..14c7b6050
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/lpc_types.h
@@ -0,0 +1,216 @@
+/*
+ * @brief Common types used in LPC functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_TYPES_H_
+#define __LPC_TYPES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @defgroup LPC_Types CHIP: LPC Common Types
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/** @defgroup LPC_Types_Public_Types LPC Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Boolean Type definition
+ */
+#if !defined(__cplusplus)
+// typedef enum {false = 0, true = !false} bool;
+#endif
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum {
+	NONE_BLOCKING = 0,		/**< None Blocking type */
+	BLOCKING,				/**< Blocking type */
+} TRANSFER_BLOCK_T;
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t (*PFI)();
+
+/**
+ * @}
+ */
+
+/** @defgroup LPC_Types_Public_Macros  LPC Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1 << (n))
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f, v) ((v) << (f))
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void *) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array)  (sizeof(array) / sizeof(array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/**
+ * @}
+ */
+
+/* Old Type Definition compatibility */
+/** @addtogroup LPC_Types_Public_Types
+ * @{
+ */
+
+/** LPC type for character type */
+typedef char CHAR;
+
+/** LPC type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** LPC type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** LPC type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** LPC type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** LPC type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** LPC type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** LPC type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** LPC type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+#ifdef __CODE_RED
+#define BOOL_32 bool
+#define BOOL_16 bool
+#define BOOL_8  bool
+#else
+/** 32 bit boolean type */
+typedef bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef bool BOOL_8;
+#endif
+
+#ifdef __CC_ARM
+#define INLINE  __inline
+#else
+#define INLINE inline
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* __LPC_TYPES_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h
new file mode 100644
index 000000000..25b771743
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pinint_13xx.h
@@ -0,0 +1,255 @@
+/*
+ * @brief LPC13XX Pin Interrupt and Pattern Match Registers and driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __PININT_13XX_H_
+#define __PININT_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup PININT_13XX CHIP: LPC13xx Pin Interrupt and Pattern Match driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+
+/**
+ * @brief LPC13xx Pin Interrupt and Pattern Match register block structure
+ */
+typedef struct {			/*!< PIN_INT Structure */
+	__IO uint32_t ISEL;		/*!< Pin Interrupt Mode register */
+	__IO uint32_t IENR;		/*!< Pin Interrupt Enable (Rising) register */
+	__IO uint32_t SIENR;	/*!< Set Pin Interrupt Enable (Rising) register */
+	__IO uint32_t CIENR;	/*!< Clear Pin Interrupt Enable (Rising) register */
+	__IO uint32_t IENF;		/*!< Pin Interrupt Enable Falling Edge / Active Level register */
+	__IO uint32_t SIENF;	/*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
+	__IO uint32_t CIENF;	/*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
+	__IO uint32_t RISE;		/*!< Pin Interrupt Rising Edge register */
+	__IO uint32_t FALL;		/*!< Pin Interrupt Falling Edge register */
+	__IO uint32_t IST;		/*!< Pin Interrupt Status register */
+} LPC_PIN_INT_T;
+
+/**
+ * LPC13xx Pin Interrupt channel values
+ */
+#define PININTCH0         (1 << 0)
+#define PININTCH1         (1 << 1)
+#define PININTCH2         (1 << 2)
+#define PININTCH3         (1 << 3)
+#define PININTCH4         (1 << 4)
+#define PININTCH5         (1 << 5)
+#define PININTCH6         (1 << 6)
+#define PININTCH7         (1 << 7)
+#define PININTCH(ch)      (1 << (ch))
+
+/**
+ * @brief	Initialize Pin interrupt block
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	Nothing
+ * @note	This function should be used after the Chip_GPIO_Init() function.
+ */
+STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {}
+
+/**
+ * @brief	De-Initialize Pin interrupt block
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {}
+
+/**
+ * @brief	Configure the pins as edge sensitive in Pin interrupt block
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->ISEL &= ~pins;
+}
+
+/**
+ * @brief	Configure the pins as level sensitive in Pin interrupt block
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->ISEL |= pins;
+}
+
+/**
+ * @brief	Return current PININT rising edge or high level interrupt enable state
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	A bifield containing the high edge/level interrupt enables for each
+ * interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
+ * For each bit, a 0 means the high edge/level interrupt is disabled, while a 1
+ * means it's enabled.
+ */
+STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT)
+{
+	return pPININT->IENR;
+}
+
+/**
+ * @brief	Enable high edge/level PININT interrupts for pins
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins to enable (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->SIENR = pins;
+}
+
+/**
+ * @brief	Disable high edge/level PININT interrupts for pins
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins to disable (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->CIENR = pins;
+}
+
+/**
+ * @brief	Return current PININT falling edge or low level interrupt enable state
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	A bifield containing the low edge/level interrupt enables for each
+ * interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
+ * For each bit, a 0 means the low edge/level interrupt is disabled, while a 1
+ * means it's enabled.
+ */
+STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT)
+{
+	return pPININT->IENF;
+}
+
+/**
+ * @brief	Enable low edge/level PININT interrupts for pins
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins to enable (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->SIENF = pins;
+}
+
+/**
+ * @brief	Disable low edge/level PININT interrupts for pins
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins to disable (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->CIENF = pins;
+}
+
+/**
+ * @brief	Return pin states that have a detected latched high edge (RISE) state
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	PININT states (bit n = high) with a latched rise state detected
+ */
+STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT)
+{
+	return pPININT->RISE;
+}
+
+/**
+ * @brief	Clears pin states that had a latched high edge (RISE) state
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins with latched states to clear
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->RISE = pins;
+}
+
+/**
+ * @brief	Return pin states that have a detected latched falling edge (FALL) state
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	PININT states (bit n = high) with a latched rise state detected
+ */
+STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT)
+{
+	return pPININT->FALL;
+}
+
+/**
+ * @brief	Clears pin states that had a latched falling edge (FALL) state
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pins with latched states to clear
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->FALL = pins;
+}
+
+/**
+ * @brief	Get interrupt status from Pin interrupt block
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @return	Interrupt status (bit n for PININTn = high means interrupt ie pending)
+ */
+STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT)
+{
+	return pPININT->IST;
+}
+
+/**
+ * @brief	Clear interrupt status in Pin interrupt block
+ * @param	pPININT	: The base address of Pin interrupt block
+ * @param	pins	: Pin interrupts to clear (ORed value of PININTCH*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins)
+{
+	pPININT->IST = pins;
+}
+
+#endif /* if defined(CHIP_LPC1347) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PININT_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h
new file mode 100644
index 000000000..44232df88
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/pmu_13xx.h
@@ -0,0 +1,238 @@
+/*
+ * @brief LPC13xx PMU chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __PMU_13XX_H_
+#define __PMU_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup PMU_13XX CHIP: LPC13xx Power Management Unit block driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief LPC13xx Power Management Unit register block structure
+ */
+typedef struct {
+	__IO uint32_t PCON;		/*!< Offset: 0x000 Power control Register (R/W) */
+	__IO uint32_t GPREG[4];	/*!< Offset: 0x004 General purpose Registers 0..3 (R/W) */
+	__IO uint32_t DPDCTRL;	/*!< Offset: 0x014 Deep power-down control register (R/W) */
+} LPC_PMU_T;
+
+/**
+ * @brief LPC13xx low power mode type definitions
+ */
+typedef enum CHIP_PMU_MCUPOWER {
+	PMU_MCU_SLEEP = 0,		/*!< Sleep mode */
+	PMU_MCU_DEEP_SLEEP,		/*!< Deep Sleep mode */
+#if defined(CHIP_LPC1347)
+	PMU_MCU_POWER_DOWN,		/*!< Power down mode */
+#endif
+	PMU_MCU_DEEP_PWRDOWN	/*!< Deep power down mode */
+} CHIP_PMU_MCUPOWER_T;
+
+/**
+ * PMU PCON register bit fields & masks
+ */
+#define PMU_PCON_PM_SLEEP           (0x0)		/*!< ARM WFI enter sleep mode */
+#if defined(CHIP_LPC1347)
+#define PMU_PCON_PM_DEEPSLEEP       (0x1)		/*!< ARM WFI enter Deep-sleep mode */
+#define PMU_PCON_PM_POWERDOWN       (0x2)		/*!< ARM WFI enter Power-down mode */
+#define PMU_PCON_PM_DEEPPOWERDOWN   (0x3)		/*!< ARM WFI enter Deep Power-down mode */
+#elif defined(CHIP_LPC1343)
+#define PMU_PCON_PM_DEEPPOWERDOWN   (0x2)		/*!< ARM WFI enter Deep Power-down mode */
+#endif 
+#define PMU_PCON_NODPD              (1 << 3)	/*!< Disable deep power-down mode */
+#define PMU_PCON_SLEEPFLAG          (1 << 8)	/*!< Sleep mode flag */
+#define PMU_PCON_DPDFLAG            (1 << 11)	/*!< Deep power-down flag */
+
+/**
+ * PMU DPDCTRL register bit fields & masks
+ */
+#define PMU_DPDCTRL_WAKEUPPHYS      (1 << 10)	/** Enable wake-up pin hysteresis */
+
+/**
+ * @brief	Write a value to a GPREG register
+ * @param	pPMU		: Pointer to PMU register block
+ * @param	regIndex	: Register index to write to, must be 0..3
+ * @param	value		: Value to write
+ * @return	None
+ */
+STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
+{
+	pPMU->GPREG[regIndex] = value;
+}
+
+/**
+ * @brief	Read a value to a GPREG register
+ * @param	pPMU		: Pointer to PMU register block
+ * @param	regIndex	: Register index to read from, must be 0..3
+ * @return	Value read from the GPREG register
+ */
+STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
+{
+	return pPMU->GPREG[regIndex];
+}
+
+/**
+ * @brief	Enter MCU Sleep mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
+ * and memories are active.
+ */
+void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Enter MCU Deep Sleep mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	In Deep-sleep mode, the peripherals receive no internal clocks.
+ * The flash is in stand-by mode. The SRAM memory and all peripheral registers
+ * as well as the processor maintain their internal states. The WWDT, WKT,
+ * and BOD can remain active to wake up the system on an interrupt.
+ */
+void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Enter MCU Power down mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	In Power-down mode, the peripherals receive no internal clocks.
+ * The internal SRAM memory and all peripheral registers as well as the
+ * processor maintain their internal states. The flash memory is powered
+ * down. The WWDT, WKT, and BOD can remain active to wake up the system
+ * on an interrupt.
+ */
+#if defined(CHIP_LPC1347)
+void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
+#endif
+
+/**
+ * @brief	Enter MCU Deep Power down mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	For maximal power savings, the entire system is shut down
+ * except for the general purpose registers in the PMU and the self
+ * wake-up timer. Only the general purpose registers in the PMU maintain
+ * their internal states. The part can wake up on a pulse on the WAKEUP
+ * pin or when the self wake-up timer times out. On wake-up, the part
+ * reboots.
+ */
+void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Place the MCU in a low power state
+ * @param	pPMU		: Pointer to PMU register block
+ * @param	SleepMode	: Sleep mode
+ * @return	None
+ */
+void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
+
+/**
+ * @brief	Disables deep power-down mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	Calling this functions prevents entry to Deep power-down
+ * mode. Once set, this can only be cleared by power-on reset.
+ */
+STATIC INLINE void Chip_PMU_DisableDeepPowerDown(LPC_PMU_T *pPMU)
+{
+	pPMU->PCON |= PMU_PCON_NODPD;
+}
+
+/**
+ * @brief	Returns sleep/power-down flags
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	Or'ed values of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
+ * @note	These indicate that the PMU is setup for entry into a low
+ * power state on the next WFI() instruction.
+ */
+STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU)
+{
+	return pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG);
+}
+
+/**
+ * @brief	Clears sleep/power-down flags
+ * @param	pPMU	: Pointer to PMU register block
+ * @param	flags	: Or'ed value of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
+ * @return	Nothing
+ * @note	Use this function to clear a low power state prior to calling
+ * WFI().
+ */
+STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
+{
+	pPMU->PCON &= ~flags;
+}
+
+/**
+ * @brief	Sets deep power-down functions
+ * @param	pPMU	: Pointer to PMU register block
+ * @param	flags	: Or'ed value of PMU_DPDCTRL_* values
+ * @return	Nothing
+ * @note	Some of these functions may need to be set prior to going
+ * into a low power mode. Note that some calls to this function enable
+ * functions while others disable it based on the PMU_DPDCTRL_*
+ * definitions.
+ */
+STATIC INLINE void Chip_PMU_SetPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags)
+{
+	pPMU->DPDCTRL |= flags;
+}
+
+/**
+ * @brief	Cleats deep power-down functions
+ * @param	pPMU	: Pointer to PMU register block
+ * @param	flags	: Or'ed value of PMU_DPDCTRL_* values
+ * @return	Nothing
+ * @note	Some of these functions may need to be cleared prior to going
+ * into a low power mode. Note that some calls to this function enable
+ * functions while others disable it based on the PMU_DPDCTRL_*
+ * definitions.
+ */
+STATIC INLINE void Chip_PMU_ClearPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags)
+{
+	pPMU->DPDCTRL &= ~flags;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PMU_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h
new file mode 100644
index 000000000..8c205fd3a
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ring_buffer.h
@@ -0,0 +1,188 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RING_BUFFER_H_
+#define __RING_BUFFER_H_
+
+#include "lpc_types.h"
+
+/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief Ring buffer structure
+ */
+typedef struct {
+	void *data;
+	int count;
+	int itemSz;
+	uint32_t head;
+	uint32_t tail;
+} RINGBUFF_T;
+
+/**
+ * @def		RB_VHEAD(rb)
+ * volatile typecasted head index
+ */
+#define RB_VHEAD(rb)              (*(volatile uint32_t *) &(rb)->head)
+
+/**
+ * @def		RB_VTAIL(rb)
+ * volatile typecasted tail index
+ */
+#define RB_VTAIL(rb)              (*(volatile uint32_t *) &(rb)->tail)
+
+/**
+ * @brief	Initialize ring buffer
+ * @param	RingBuff	: Pointer to ring buffer to initialize
+ * @param	buffer		: Pointer to buffer to associate with RingBuff
+ * @param	itemSize	: Size of each buffer item size
+ * @param	count		: Size of ring buffer
+ * @note	Memory pointed by @a buffer must have correct alignment of
+ * 			@a itemSize, and @a count must be a power of 2 and must at
+ * 			least be 2 or greater.
+ * @return	Nothing
+ */
+int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
+
+/**
+ * @brief	Resets the ring buffer to empty
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Nothing
+ */
+STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff)
+{
+	RingBuff->head = RingBuff->tail = 0;
+}
+
+/**
+ * @brief	Return size the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Size of the ring buffer in bytes
+ */
+STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff)
+{
+	return RingBuff->count;
+}
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Number of items in the ring buffer
+ */
+STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
+{
+	return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff);
+}
+
+/**
+ * @brief	Return number of free items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Number of free items in the ring buffer
+ */
+STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff)
+{
+	return RingBuff->count - RingBuffer_GetCount(RingBuff);
+}
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	1 if the ring buffer is full, otherwise 0
+ */
+STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff)
+{
+	return (RingBuffer_GetCount(RingBuff) >= RingBuff->count);
+}
+
+/**
+ * @brief	Return empty status of ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	1 if the ring buffer is empty, otherwise 0
+ */
+STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
+{
+	return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff);
+}
+
+/**
+ * @brief	Insert a single item into ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: pointer to item
+ * @return	1 when successfully inserted,
+ *			0 on error (Buffer not initialized using
+ *			RingBuffer_Init() or attempted to insert
+ *			when buffer is full)
+ */
+int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data);
+
+/**
+ * @brief	Insert an array of items into ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: Pointer to first element of the item array
+ * @param	num			: Number of items in the array
+ * @return	number of items successfully inserted,
+ *			0 on error (Buffer not initialized using
+ *			RingBuffer_Init() or attempted to insert
+ *			when buffer is full)
+ */
+int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num);
+
+/**
+ * @brief	Pop an item from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: Pointer to memory where popped item be stored
+ * @return	1 when item popped successfuly onto @a data,
+ * 			0 When error (Buffer not initialized using
+ * 			RingBuffer_Init() or attempted to pop item when
+ * 			the buffer is empty)
+ */
+int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data);
+
+/**
+ * @brief	Pop an array of items from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: Pointer to memory where popped items be stored
+ * @param	num			: Max number of items array @a data can hold
+ * @return	Number of items popped onto @a data,
+ * 			0 on error (Buffer not initialized using RingBuffer_Init()
+ * 			or attempted to pop when the buffer is empty)
+ */
+int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num);
+
+
+/**
+ * @}
+ */
+
+#endif /* __RING_BUFFER_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h
new file mode 100644
index 000000000..6f613b9f3
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ritimer_13xx.h
@@ -0,0 +1,197 @@
+/*
+ * @brief LPC13xx RITimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RITIMER_13XX_H_
+#define __RITIMER_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RIT_13XX CHIP: LPC13xx Repetitive Interrupt Timer driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+
+/**
+ * @brief Repetitive Interrupt Timer register block structure
+ */
+typedef struct {				/*!< RITIMER Structure      */
+	__IO uint32_t  COMPVAL;		/*!< Compare register       */
+	__IO uint32_t  MASK;		/*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+	__IO uint32_t  CTRL;		/*!< Control register.      */
+	__IO uint32_t  COUNTER;		/*!< 32-bit counter         */
+	__IO uint32_t  COMPVAL_H;	/*!< Compare upper register */
+	__IO uint32_t  MASK_H;		/*!< Mask upper register    */
+	__I  uint32_t  RESERVED0[1];
+	__IO uint32_t  COUNTER_H;	/*!< Counter upper register */
+} LPC_RITIMER_T;
+
+/*
+ * @brief RITIMER register support bitfields and mask
+ */
+
+/*
+ * RIT control register
+ */
+/**	Set by H/W when the counter value equals the masked compare value */
+#define RIT_CTRL_INT    ((uint32_t) (1))
+/** Set timer enable clear to 0 when the counter value equals the masked compare value  */
+#define RIT_CTRL_ENCLR  ((uint32_t) _BIT(1))
+/** Set timer enable on debug */
+#define RIT_CTRL_ENBR   ((uint32_t) _BIT(2))
+/** Set timer enable */
+#define RIT_CTRL_TEN    ((uint32_t) _BIT(3))
+
+/**
+ * @brief	Initialize the RIT
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+void Chip_RIT_Init(LPC_RITIMER_T *pRITimer);
+
+/**
+ * @brief	Shutdown the RIT
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer);
+
+/**
+ * @brief	Enable Timer
+ * @param	pRITimer		: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL |= RIT_CTRL_TEN;
+}
+
+/**
+ * @brief	Disable Timer
+ * @param	pRITimer		: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL &= ~RIT_CTRL_TEN;
+}
+
+/**
+ * @brief	Enable timer debug
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL |= RIT_CTRL_ENBR;
+}
+
+/**
+ * @brief	Disable timer debug
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL &= ~RIT_CTRL_ENBR;
+}
+
+/**
+ * @brief	Check whether interrupt flag is set or not
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	Current interrupt status, either ET or UNSET
+ */
+IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer);
+
+/**
+ * @brief	Set a tick value for the interrupt to time out
+ * @param	pRITimer	: RITimer peripheral selected
+ * @param	val			: value (in ticks) of the interrupt to be set
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val)
+{
+	pRITimer->COMPVAL = val;
+}
+
+/**
+ * @brief	Enables or clears the RIT or interrupt
+ * @param	pRITimer	: RITimer peripheral selected
+ * @param	val			: RIT to be set, one or more RIT_CTRL_* values
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val)
+{
+	pRITimer->CTRL |= val;
+}
+
+/**
+ * @brief	Clears the RIT interrupt
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL |= RIT_CTRL_INT;
+}
+
+/**
+ * @brief	Returns the current RIT Counter value
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	the current timer counter value
+ */
+STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer)
+{
+	return pRITimer->COUNTER;
+}
+
+/**
+ * @brief	Set timer interval value
+ * @param	pRITimer		: RITimer peripheral selected
+ * @param	time_interval	: timer interval value (ms)
+ * @return	None
+ */
+void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval);
+
+#endif /* defined(CHIP_LPC1347) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RITIMER_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h
new file mode 100644
index 000000000..cae1e8e49
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/romapi_13xx.h
@@ -0,0 +1,79 @@
+/*
+ * @brief LPC13XX ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ROMAPI_13XX_H_
+#define __ROMAPI_13XX_H_
+
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ROMAPI_13XX CHIP: LPC13xx ROM API declarations and functions
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief LPC13XX High level ROM API structure
+ */
+typedef struct {
+	const uint32_t usbdApiBase;				/*!< USBD API function table base address */
+	const uint32_t reserved0;				/*!< Reserved */
+	const uint32_t candApiBase;				/*!< CAN API function table base address */
+	const uint32_t pwrApiBase;				/*!< Power API function table base address */
+	const uint32_t reserved1;				/*!< Reserved */
+	const uint32_t reserved2;				/*!< Reserved */
+	const uint32_t reserved3;				/*!< Reserved */
+	const uint32_t reserved4;				/*!< Reserved */
+} LPC_ROM_API_T;
+
+/**
+ * @brief LPC13XX IAP_ENTRY API function type
+ */
+typedef void (*IAP_ENTRY_T)(unsigned int[], unsigned int[]);
+
+static INLINE void iap_entry(unsigned int cmd_param[], unsigned int status_result[])
+{
+	((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ROMAPI_13XX_H_ */
+
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h
new file mode 100644
index 000000000..493e265db
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/ssp_13xx.h
@@ -0,0 +1,605 @@
+/*
+ * @brief LPC13xx SSP Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SSP_13XX_H_
+#define __SSP_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SSP_13XX CHIP: LPC13xx SSP register block and driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief SSP register block structure
+ */
+typedef struct {			/*!< SSPn Structure         */
+	__IO uint32_t CR0;		/*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
+	__IO uint32_t CR1;		/*!< Control Register 1. Selects master/slave and other modes. */
+	__IO uint32_t DR;		/*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+	__I  uint32_t SR;		/*!< Status Register        */
+	__IO uint32_t CPSR;		/*!< Clock Prescale Register */
+	__IO uint32_t IMSC;		/*!< Interrupt Mask Set and Clear Register */
+	__I  uint32_t RIS;		/*!< Raw Interrupt Status Register */
+	__I  uint32_t MIS;		/*!< Masked Interrupt Status Register */
+	__O  uint32_t ICR;		/*!< SSPICR Interrupt Clear Register */
+#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
+	!defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
+	__IO uint32_t DMACR;	/*!< SSPn DMA control register */
+#endif
+} LPC_SSP_T;
+
+/**
+ * Macro defines for CR0 register
+ */
+
+/** SSP data size select, must be 4 bits to 16 bits */
+#define SSP_CR0_DSS(n)          ((uint32_t) ((n) & 0xF))
+/** SSP control 0 Motorola SPI mode */
+#define SSP_CR0_FRF_SPI         ((uint32_t) (0 << 4))
+/** SSP control 0 TI synchronous serial mode */
+#define SSP_CR0_FRF_TI          ((uint32_t) (1 << 4))
+/** SSP control 0 National Micro-wire mode */
+#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
+/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
+   bus clock high between frames, (0) = low */
+#define SSP_CR0_CPOL_LO     ((uint32_t) (0))
+#define SSP_CR0_CPOL_HI     ((uint32_t) (1 << 6))
+/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
+   on the second clock transition of the frame, (0) = first */
+#define SSP_CR0_CPHA_FIRST  ((uint32_t) (0))
+#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
+/** SSP serial clock rate value load macro, divider rate is
+   PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
+/** SSP serial clock rate value load macro, divider rate is
+   PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
+
+/**
+ * Macro defines for CR1 register
+ */
+
+/** SSP control 1 loopback mode enable bit */
+#define SSP_CR1_LBM_EN      ((uint32_t) (1 << 0))
+/** SSP control 1 enable bit */
+#define SSP_CR1_SSP_EN      ((uint32_t) (1 << 1))
+/** SSP control 1 slave enable */
+#define SSP_CR1_SLAVE_EN    ((uint32_t) (1 << 2))
+#define SSP_CR1_MASTER_EN   ((uint32_t) (0))
+/** SSP control 1 slave out disable bit, disables transmit line in slave
+   mode */
+#define SSP_CR1_SO_DISABLE  ((uint32_t) (1 << 3))
+/** SSP CR1 bit mask */
+#define SSP_CR1_BITMASK     ((uint32_t) (0x0F))
+
+/** SSP CPSR bit mask */
+#define SSP_CPSR_BITMASK    ((uint32_t) (0xFF))
+/**
+ * Macro defines for DR register
+ */
+
+/** SSP data bit mask */
+#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
+
+/**
+ * Macro defines for SR register
+ */
+
+/** SSP SR bit mask */
+#define SSP_SR_BITMASK  ((uint32_t) (0x1F))
+
+/** ICR bit mask */
+#define SSP_ICR_BITMASK ((uint32_t) (0x03))
+
+/**
+ * @brief SSP Type of Status
+ */
+typedef enum _SSP_STATUS {
+	SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
+	SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
+	SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
+	SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
+	SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
+} SSP_STATUS_T;
+
+/**
+ * @brief SSP Type of Interrupt Mask
+ */
+typedef enum _SSP_INTMASK {
+	SSP_RORIM = ((uint32_t)(1 << 0)),	/**< Overun */
+	SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
+	SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
+	SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
+	SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
+} SSP_INTMASK_T;
+
+/**
+ * @brief SSP Type of Mask Interrupt Status
+ */
+typedef enum _SSP_MASKINTSTATUS {
+	SSP_RORMIS = ((uint32_t)(1 << 0)),	/**< Overun */
+	SSP_RTMIS = ((uint32_t)(1 << 1)),	/**< TimeOut */
+	SSP_RXMIS = ((uint32_t)(1 << 2)),	/**< Rx FIFO is at least half full */
+	SSP_TXMIS = ((uint32_t)(1 << 3)),	/**< Tx FIFO is at least half empty */
+	SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
+} SSP_MASKINTSTATUS_T;
+
+/**
+ * @brief SSP Type of Raw Interrupt Status
+ */
+typedef enum _SSP_RAWINTSTATUS {
+	SSP_RORRIS = ((uint32_t)(1 << 0)),	/**< Overun */
+	SSP_RTRIS = ((uint32_t)(1 << 1)),	/**< TimeOut */
+	SSP_RXRIS = ((uint32_t)(1 << 2)),	/**< Rx FIFO is at least half full */
+	SSP_TXRIS = ((uint32_t)(1 << 3)),	/**< Tx FIFO is at least half empty */
+	SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
+} SSP_RAWINTSTATUS_T;
+
+typedef enum _SSP_INTCLEAR {
+	SSP_RORIC = 0x0,
+	SSP_RTIC = 0x1,
+	SSP_INT_CLEAR_BITMASK = 0x3,
+} SSP_INTCLEAR_T;
+
+typedef enum _SSP_DMA {
+	SSP_DMA_RX = (1u),	/**< DMA RX Enable */
+	SSP_DMA_TX = (1u << 1),	/**< DMA TX Enable */
+	SSP_DMA_BITMASK = ((uint32_t)(0x3)),
+} SSP_DMA_T;
+
+/*
+ * @brief SSP clock format
+ */
+typedef enum CHIP_SSP_CLOCK_FORMAT {
+	SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),		/**< CPHA = 0, CPOL = 0 */
+	SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),		/**< CPHA = 0, CPOL = 1 */
+	SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),		/**< CPHA = 1, CPOL = 0 */
+	SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),		/**< CPHA = 1, CPOL = 1 */
+	SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
+	SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
+	SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
+	SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
+} CHIP_SSP_CLOCK_MODE_T;
+
+/*
+ * @brief SSP frame format
+ */
+typedef enum CHIP_SSP_FRAME_FORMAT {
+	SSP_FRAMEFORMAT_SPI = (0 << 4),			/**< Frame format: SPI */
+	CHIP_SSP_FRAME_FORMAT_TI = (1u << 4),			/**< Frame format: TI SSI */
+	SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),	/**< Frame format: Microwire */
+} CHIP_SSP_FRAME_FORMAT_T;
+
+/*
+ * @brief Number of bits per frame
+ */
+typedef enum CHIP_SSP_BITS {
+	SSP_BITS_4 = (3u << 0),		/*!< 4 bits/frame */
+	SSP_BITS_5 = (4u << 0),		/*!< 5 bits/frame */
+	SSP_BITS_6 = (5u << 0),		/*!< 6 bits/frame */
+	SSP_BITS_7 = (6u << 0),		/*!< 7 bits/frame */
+	SSP_BITS_8 = (7u << 0),		/*!< 8 bits/frame */
+	SSP_BITS_9 = (8u << 0),		/*!< 9 bits/frame */
+	SSP_BITS_10 = (9u << 0),	/*!< 10 bits/frame */
+	SSP_BITS_11 = (10u << 0),	/*!< 11 bits/frame */
+	SSP_BITS_12 = (11u << 0),	/*!< 12 bits/frame */
+	SSP_BITS_13 = (12u << 0),	/*!< 13 bits/frame */
+	SSP_BITS_14 = (13u << 0),	/*!< 14 bits/frame */
+	SSP_BITS_15 = (14u << 0),	/*!< 15 bits/frame */
+	SSP_BITS_16 = (15u << 0),	/*!< 16 bits/frame */
+} CHIP_SSP_BITS_T;
+
+/*
+ * @brief SSP config format
+ */
+typedef struct SSP_ConfigFormat {
+	CHIP_SSP_BITS_T bits;					/*!< Format config: bits/frame */
+	CHIP_SSP_CLOCK_MODE_T clockMode;	/*!< Format config: clock phase/polarity */
+	CHIP_SSP_FRAME_FORMAT_T frameFormat;	/*!< Format config: SPI/TI/Microwire */
+} SSP_ConfigFormat;
+
+/**
+ * @brief	Enable SSP operation
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 |= SSP_CR1_SSP_EN;
+}
+
+/**
+ * @brief	Disable SSP operation
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
+}
+
+/**
+ * @brief	Enable loopback mode
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ * @note	Serial input is taken from the serial output (MOSI or MISO) rather
+ * than the serial input pin
+ */
+STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 |= SSP_CR1_LBM_EN;
+}
+
+/**
+ * @brief	Disable loopback mode
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ * @note	Serial input is taken from the serial output (MOSI or MISO) rather
+ * than the serial input pin
+ */
+STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
+}
+
+/**
+ * @brief	Get the current status of SSP controller
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	Stat	: Type of status, should be :
+ *						- SSP_STAT_TFE
+ *						- SSP_STAT_TNF
+ *						- SSP_STAT_RNE
+ *						- SSP_STAT_RFF
+ *						- SSP_STAT_BSY
+ * @return	 SSP controller status, SET or RESET
+ */
+STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
+{
+	return (pSSP->SR & Stat) ? SET : RESET;
+}
+
+/**
+ * @brief	Get the masked interrupt status
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 SSP Masked Interrupt Status Register value
+ * @note	The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
+ */
+STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
+{
+	return pSSP->MIS;
+}
+
+/**
+ * @brief	Get the raw interrupt status
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	RawInt	: Interrupt condition to be get status, shoud be :
+ *						- SSP_RORRIS
+ *						- SSP_RTRIS
+ *						- SSP_RXRIS
+ *						- SSP_TXRIS
+ * @return	 Raw interrupt status corresponding to interrupt condition , SET or RESET
+ * @note	Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
+ */
+STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
+{
+	return (pSSP->RIS & RawInt) ? SET : RESET;
+}
+
+/**
+ * @brief	Get the number of bits transferred in each frame
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 the number of bits transferred in each frame minus one
+ * @note	The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
+ */
+STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
+{
+	return SSP_CR0_DSS(pSSP->CR0);
+}
+
+/**
+ * @brief	Clear the corresponding interrupt condition(s) in the SSP controller
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	IntClear: Type of cleared interrupt, should be :
+ *						- SSP_RORIC
+ *						- SSP_RTIC
+ * @return	 Nothing
+ * @note	Software can clear one or more interrupt condition(s) in the SSP controller
+ */
+STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
+{
+	pSSP->ICR = IntClear;
+}
+
+/**
+ * @brief	Enable interrupt for the SSP
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
+{
+	pSSP->IMSC |= SSP_TXIM;
+}
+
+/**
+ * @brief	Disable interrupt for the SSP
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
+{
+	pSSP->IMSC &= (~SSP_TXIM);
+}
+
+/**
+ * @brief	Get received SSP data
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 SSP 16-bit data received
+ */
+STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
+{
+	return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
+}
+
+/**
+ * @brief	Send SSP 16-bit data
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	tx_data	: SSP 16-bit data to be transmited
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
+{
+	pSSP->DR = SSP_DR_BITMASK(tx_data);
+}
+
+/**
+ * @brief	Set up output clocks per bit for SSP bus
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @param	clk_rate	fs: The number of prescaler-output clocks per bit on the bus, minus one
+ * @param	prescale	: The factor by which the Prescaler divides the SSP peripheral clock PCLK
+ * @return	 Nothing
+ * @note	The bit frequency is PCLK / (prescale x[clk_rate+1])
+ */
+void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
+
+/**
+ * @brief	Set up the SSP frame format
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @param	bits		: The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
+ * @param	frameFormat	: Frame format, should be :
+ *							- SSP_FRAMEFORMAT_SPI
+ *							- SSP_FRAME_FORMAT_TI
+ *							- SSP_FRAMEFORMAT_MICROWIRE
+ * @param	clockMode	: Select Clock polarity and Clock phase, should be :
+ *							- SSP_CLOCK_CPHA0_CPOL0
+ *							- SSP_CLOCK_CPHA0_CPOL1
+ *							- SSP_CLOCK_CPHA1_CPOL0
+ *							- SSP_CLOCK_CPHA1_CPOL1
+ * @return	 Nothing
+ * @note	Note: The clockFormat is only used in SPI mode
+ */
+STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
+{
+	pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
+}
+
+/**
+ * @brief	Set the SSP working as master or slave mode
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	mode	: Operating mode, should be
+ *						- SSP_MODE_MASTER
+ *						- SSP_MODE_SLAVE
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
+{
+	pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
+}
+
+#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
+	!defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX)
+/**
+ * @brief	Enable DMA for SSP
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)
+{
+	pSSP->DMACR |= SSP_DMA_BITMASK;
+}
+
+/**
+ * @brief	Disable DMA for SSP
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)
+{
+	pSSP->DMACR &= ~SSP_DMA_BITMASK;
+}
+
+#endif
+
+/*
+ * @brief SSP mode
+ */
+typedef enum CHIP_SSP_MODE {
+	SSP_MODE_MASTER = (0 << 2),	/**< Master mode */
+	SSP_MODE_SLAVE = (1u << 2),	/**< Slave mode */
+} CHIP_SSP_MODE_T;
+
+/*
+ * @brief SPI address
+ */
+typedef struct {
+	uint8_t port;	/*!< Port Number */
+	uint8_t pin;	/*!< Pin number */
+} SPI_Address_t;
+
+/*
+ * @brief SSP data setup structure
+ */
+typedef struct {
+	void      *tx_data;	/*!< Pointer to transmit data */
+	uint32_t  tx_cnt;	/*!< Transmit counter */
+	void      *rx_data;	/*!< Pointer to transmit data */
+	uint32_t  rx_cnt;	/*!< Receive counter */
+	uint32_t  length;	/*!< Length of transfer data */
+} Chip_SSP_DATA_SETUP_T;
+
+/** SSP configuration parameter defines */
+/** Clock phase control bit */
+#define SSP_CPHA_FIRST          SSP_CR0_CPHA_FIRST
+#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
+
+/** Clock polarity control bit */
+/* There's no bug here!!!
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
+ * That means the active clock is in HI state.
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
+ * high between frames. That means the active clock is in LO state.
+ */
+#define SSP_CPOL_HI             SSP_CR0_CPOL_LO
+#define SSP_CPOL_LO             SSP_CR0_CPOL_HI
+
+/** SSP master mode enable */
+#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
+#define SSP_MASTER_MODE         SSP_CR1_MASTER_EN
+
+/**
+ * @brief   Clean all data in RX FIFO of SSP
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
+
+/**
+ * @brief   SSP Interrupt Read/Write with 8-bit frame width
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SSP Interrupt Read/Write with 16-bit frame width
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SSP Polling Read/Write in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. It starts with writing phase and after that,
+ * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
+ * through xf_setup param.
+ */
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SSP Polling Write in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: Buffer length
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. First, a writing operation will send
+ * the needed data. After that, a dummy reading operation is generated to clear data buffer
+ */
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   SSP Polling Read in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: The length of buffer
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. First, a dummy writing operation is generated
+ * to clear data buffer. After that, a reading operation will receive the needed data
+ */
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   Initialize the SSP
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SSP_Init(LPC_SSP_T *pSSP);
+
+/**
+ * @brief	Deinitialise the SSP
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	Nothing
+ * @note	The SSP controller is disabled
+ */
+void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
+
+/**
+ * @brief   Set the SSP operating modes, master or slave
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	master			: 1 to set master, 0 to set slave
+ * @return	Nothing
+ */
+void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
+
+/**
+ * @brief   Set the clock frequency for SSP interface
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	bitRate		: The SSP bit rate
+ * @return	Nothing
+ */
+void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SSP_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h
new file mode 100644
index 000000000..c298735fa
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/stopwatch.h
@@ -0,0 +1,137 @@
+/*
+ * @brief Common stopwatch support
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __STOPWATCH_H_
+#define __STOPWATCH_H_
+
+#include "cmsis.h"
+
+/** @defgroup Stop_Watch CHIP: Stopwatch primitives.
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief	Initialize stopwatch
+ * @return	Nothing
+ */
+void StopWatch_Init(void);
+
+/**
+ * @brief	Start a stopwatch
+ * @return	Current cycle count
+ */
+uint32_t StopWatch_Start(void);
+
+/**
+ * @brief      Returns number of ticks elapsed since stopwatch was started
+ * @param      startTime	: Time returned by StopWatch_Start().
+ * @return     Number of ticks elapsed since stopwatch was started
+ */
+STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime)
+{
+	return StopWatch_Start() - startTime;
+}
+
+/**
+ * @brief	Returns number of ticks per second of the stopwatch timer
+ * @return	Number of ticks per second of the stopwatch timer
+ */
+uint32_t StopWatch_TicksPerSecond(void);
+
+/**
+ * @brief	Converts from stopwatch ticks to mS.
+ * @param	ticks	: Duration in ticks to convert to mS.
+ * @return	Number of mS in given number of ticks
+ */
+uint32_t StopWatch_TicksToMs(uint32_t ticks);
+
+/**
+ * @brief	Converts from stopwatch ticks to uS.
+ * @param	ticks	: Duration in ticks to convert to uS.
+ * @return	Number of uS in given number of ticks
+ */
+uint32_t StopWatch_TicksToUs(uint32_t ticks);
+
+/**
+ * @brief	Converts from mS to stopwatch ticks.
+ * @param	mS	: Duration in mS to convert to ticks.
+ * @return	Number of ticks in given number of mS
+ */
+uint32_t StopWatch_MsToTicks(uint32_t mS);
+
+/**
+ * @brief	Converts from uS to stopwatch ticks.
+ * @param	uS	: Duration in uS to convert to ticks.
+ * @return	Number of ticks in given number of uS
+ */
+uint32_t StopWatch_UsToTicks(uint32_t uS);
+
+/**
+ * @brief	Delays the given number of ticks using stopwatch primitives
+ * @param	ticks	: Number of ticks to delay
+ * @return	Nothing
+ */
+STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks)
+{
+	uint32_t startTime = StopWatch_Start();
+	while (StopWatch_Elapsed(startTime) < ticks) {}
+}
+
+/**
+ * @brief	Delays the given number of mS using stopwatch primitives
+ * @param	mS	: Number of mS to delay
+ * @return	Nothing
+ */
+STATIC INLINE void StopWatch_DelayMs(uint32_t mS)
+{
+	uint32_t ticks = StopWatch_MsToTicks(mS);
+	uint32_t startTime = StopWatch_Start();
+	while (StopWatch_Elapsed(startTime) < ticks) {}
+}
+
+/**
+ * @brief	Delays the given number of uS using stopwatch primitives
+ * @param	uS	: Number of uS to delay
+ * @return	Nothing
+ */
+STATIC INLINE void StopWatch_DelayUs(uint32_t uS)
+{
+	uint32_t ticks = StopWatch_UsToTicks(uS);
+	uint32_t startTime = StopWatch_Start();
+	while (StopWatch_Elapsed(startTime) < ticks) {}
+}
+
+/**
+ * @}
+ */
+
+#endif /* __STOPWATCH_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h
new file mode 100644
index 000000000..777773dce
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sys_config.h
@@ -0,0 +1,41 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+/* Pick only one. Build for LPC1347 chip family */
+#define CHIP_LPC1347
+
+/* The LPC1347 platform code hasn't been tested on a board and it's possble
+   it may have problems although it builds fine. Enable the ENABLE_UNTESTED_CODE
+   definition to allow the LPC110x platform to build. */
+// #define ENABLE_UNTESTED_CODE
+
+#endif /* __SYS_CONFIG_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h
new file mode 100644
index 000000000..4ce61ca78
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/sysctl_13xx.h
@@ -0,0 +1,702 @@
+/*
+ * @brief LPC13xx System Control registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYSCTL_13XX_H_
+#define __SYSCTL_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SYSCTL_13XX CHIP: LPC13xx System Control block driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1343)
+/**
+ * @brief Start state control structure
+ */
+typedef struct {
+	__IO uint32_t  STARTAPR;		/*!< Start logic edge control register */
+	__IO uint32_t  STARTER;			/*!< Start logic signal enable register */
+	__IO uint32_t  STARTRSRCLR;		/*!< Start logic reset register */
+	__IO uint32_t  STARTSR;			/*!< Start logic status register */
+} LPC_SYSCTL_STARTST_T;
+#endif
+
+/**
+ * @brief LPC13XX System Control block structure
+ */
+typedef struct {			/*!< SYSCTL Structure */
+	__IO uint32_t  SYSMEMREMAP;		/*!< System Memory remap register */
+	__IO uint32_t  PRESETCTRL;		/*!< Peripheral reset Control register */
+	__IO uint32_t  SYSPLLCTRL;		/*!< System PLL control register */
+	__I  uint32_t  SYSPLLSTAT;		/*!< System PLL status register */
+	__IO uint32_t  USBPLLCTRL;		/*!< USB PLL control register, LPC134x only */
+	__I  uint32_t  USBPLLSTAT;		/*!< USB PLL status register, LPC134x only */
+	__I  uint32_t  RESERVED1[2];
+	__IO uint32_t  SYSOSCCTRL;		/*!< System Oscillator control register */
+	__IO uint32_t  WDTOSCCTRL;		/*!< Watchdog Oscillator control register */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED2[2];
+#else
+	__IO uint32_t  IRCCTRL;			/*!< IRC control register */
+	__I  uint32_t  RESERVED2[1];
+#endif
+
+	__IO uint32_t  SYSRSTSTAT;		/*!< System Reset Status register           */
+	__I  uint32_t  RESERVED3[3];
+	__IO uint32_t  SYSPLLCLKSEL;	/*!< System PLL clock source select register */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED4;
+#else
+	__IO uint32_t  SYSPLLCLKUEN;	/*!< System PLL clock source update enable register*/
+#endif
+	__IO uint32_t  USBPLLCLKSEL;	/*!< USB PLL clock source select register, LPC134x only */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED4A[1];
+#else
+	__IO uint32_t  USBPLLCLKUEN;	/*!< USB PLL clock source update enable register, LPC1342/43 only */
+#endif
+	__I  uint32_t  RESERVED5[8];
+	__IO uint32_t  MAINCLKSEL;		/*!< Main clock source select register		*/
+#if defined(CHIP_LPC1347)
+	__IO uint32_t  RESERVED6;
+#else
+	__IO uint32_t  MAINCLKUEN;		/*!< Main clock source update enable register	*/
+#endif
+	__IO uint32_t  SYSAHBCLKDIV;	/*!< System Clock divider register */
+	__I  uint32_t  RESERVED6A;
+	__IO uint32_t  SYSAHBCLKCTRL;	/*!< System Clock control register */
+	__I  uint32_t  RESERVED7[4];
+	__IO uint32_t  SSP0CLKDIV;		/*!< SSP0 clock divider register   */
+	__IO uint32_t  USARTCLKDIV;		/*!< UART clock divider register   */
+	__IO uint32_t  SSP1CLKDIV;		/*!< SSP1 clock divider register */
+	__I  uint32_t  RESERVED8[3];
+	__IO uint32_t  TRACECLKDIV;		/*!< ARM trace clock divider register */
+	__IO uint32_t  SYSTICKCLKDIV;	/*!< SYSTICK clock divider register */
+	__I  uint32_t  RESERVED9[3];
+	__IO uint32_t  USBCLKSEL;		/*!< USB clock source select register, LPC134x only */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED10;
+#else
+	__IO uint32_t  USBCLKUEN;		/*!< USB clock source update enable register, LPC1342/43 only */
+#endif
+	__IO uint32_t  USBCLKDIV;		/*!< USB clock source divider register, LPC134x only */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED11[4];
+#else
+	__I  uint32_t  RESERVED11;
+	__IO uint32_t  WDTCLKSEL;		/*!< WDT clock source select register, some parts only */
+	__IO uint32_t  WDTCLKUEN;		/*!< WDT clock source update enable register, some parts only */
+	__IO uint32_t  WDTCLKDIV;		/*!< WDT clock divider register, some parts only */
+#endif
+	__I  uint32_t  RESERVED13;
+	__IO uint32_t  CLKOUTSEL;		/*!< Clock out source select register */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED12;
+#else
+	__IO uint32_t  CLKOUTUEN;		/*!< Clock out source update enable register, not on LPC1311/13/42/43 only */
+#endif
+	__IO uint32_t  CLKOUTDIV;		/*!< Clock out divider register */
+	__I  uint32_t  RESERVED14[5];
+	__I  uint32_t  PIOPORCAP[2];	/*!< POR captured PIO status registers */
+	__I  uint32_t  RESERVED15[18];
+	__IO uint32_t  BODCTRL;			/*!< Brown Out Detect register */
+	__IO uint32_t  SYSTCKCAL;		/*!< System tick counter calibration register */
+#if defined(CHIP_LPC1347)
+	__I  uint32_t  RESERVED16[6];
+	__IO uint32_t  IRQLATENCY;		/*!< IRQ delay register */
+	__IO uint32_t  NMISRC;			/*!< NMI source control register,some parts only */
+	__IO uint32_t  PINTSEL[8];		/*!< GPIO pin interrupt select register 0-7 */
+	__IO uint32_t  USBCLKCTRL;		/*!< USB clock control register, LPC134x only */
+	__I  uint32_t  USBCLKST;		/*!< USB clock status register, LPC134x only */
+	__I  uint32_t  RESERVED17[25];
+	__IO uint32_t  STARTERP0;		/*!< Start logic 0 interrupt wake-up enable register */
+	__I  uint32_t  RESERVED18[3];
+	__IO uint32_t  STARTERP1;		/*!< Start logic 1 interrupt wake-up enable register */
+	__I  uint32_t  RESERVED19[6];
+#else
+	__I  uint32_t  RESERVED16[42];
+	LPC_SYSCTL_STARTST_T STARTLOGIC[2];
+	__I  uint32_t  RESERVED17[4];
+#endif
+	__IO uint32_t  PDSLEEPCFG;		/*!< Power down states in deep sleep mode register */
+	__IO uint32_t  PDWAKECFG;		/*!< Power down states in wake up from deep sleep register */
+	__IO uint32_t  PDRUNCFG;		/*!< Power configuration register*/
+	__I  uint32_t  RESERVED20[110];
+	__I  uint32_t  DEVICEID;		/*!< Device ID register */
+} LPC_SYSCTL_T;
+
+/**
+ * System memory remap modes used to remap interrupt vectors
+ */
+typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
+	REMAP_BOOT_LOADER_MODE,	/*!< Interrupt vectors are re-mapped to Boot ROM */
+	REMAP_USER_RAM_MODE,	/*!< Interrupt vectors are re-mapped to Static RAM */
+	REMAP_USER_FLASH_MODE	/*!< Interrupt vectors are not re-mapped and reside in Flash */
+} CHIP_SYSCTL_BOOT_MODE_REMAP_T;
+
+/**
+ * @brief	Re-map interrupt vectors
+ * @param	remap	: system memory map value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
+{
+	LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
+}
+
+/**
+ * Peripheral reset identifiers, not available on all devices
+ */
+typedef enum CHIP_SYSCTL_PERIPH_RESET {
+	RESET_SSP0,			/*!< SSP0 reset control */
+	RESET_I2C0,			/*!< I2C0 reset control */
+	RESET_SSP1			/*!< SSP1 reset control */
+} CHIP_SYSCTL_PERIPH_RESET_T;
+
+/**
+ * @brief	Assert reset for a peripheral
+ * @param	periph	: Peripheral to assert reset for
+ * @return	Nothing
+ * @note	The peripheral will stay in reset until reset is de-asserted. Call
+ * Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset.
+ */
+STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
+{
+	LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
+}
+
+/**
+ * @brief	De-assert reset for a peripheral
+ * @param	periph	: Peripheral to de-assert reset for
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
+{
+	LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
+}
+
+/**
+ * @brief	Resets a peripheral
+ * @param	periph	:	Peripheral to reset
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
+{
+	Chip_SYSCTL_AssertPeriphReset(periph);
+	Chip_SYSCTL_DeassertPeriphReset(periph);
+}
+
+/**
+ * System reset status
+ */
+#define SYSCTL_RST_POR    (1 << 0)	/*!< POR reset status */
+#define SYSCTL_RST_EXTRST (1 << 1)	/*!< External reset status */
+#define SYSCTL_RST_WDT    (1 << 2)	/*!< Watchdog reset status */
+#define SYSCTL_RST_BOD    (1 << 3)	/*!< Brown-out detect reset status */
+#define SYSCTL_RST_SYSRST (1 << 4)	/*!< software system reset status */
+
+/**
+ * @brief	Get system reset status
+ * @return	An Or'ed value of SYSCTL_RST_*
+ * @note	This function returns the detected reset source(s).
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
+{
+	return LPC_SYSCTL->SYSRSTSTAT;
+}
+
+/**
+ * @brief	Clear system reset status
+ * @param	reset	: An Or'ed value of SYSCTL_RST_* status to clear
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
+{
+	LPC_SYSCTL->SYSRSTSTAT = reset;
+}
+
+/**
+ * @brief	Read POR captured PIO status
+ * @param	index	: POR register index, 0 or 1
+ * @return	captured POR PIO status
+ * @note	See the user manual for decoing of these bits.
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
+{
+	return LPC_SYSCTL->PIOPORCAP[index];
+}
+
+/**
+ * Brown-out detector reset level
+ */
+typedef enum CHIP_SYSCTL_BODRSTLVL {
+	SYSCTL_BODRSTLVL_1_46V,	/*!< Brown-out reset at 1.46v */
+	SYSCTL_BODRSTLVL_2_06V,	/*!< Brown-out reset at 2.06v */
+	SYSCTL_BODRSTLVL_2_35V,	/*!< Brown-out reset at 2.35v */
+	SYSCTL_BODRSTLVL_2_63V,	/*!< Brown-out reset at 2.63v */
+} CHIP_SYSCTL_BODRSTLVL_T;
+
+/**
+ * Brown-out detector interrupt level
+ */
+typedef enum CHIP_SYSCTL_BODRINTVAL {
+#if defined(CHIP_LPC1343)
+	SYSCTL_BODINTVAL_1_69V,	/*!< Brown-out interrupt at 1.65v */
+#else
+	SYSCTL_BODINTVAL_RESERVED1,
+#endif
+	SYSCTL_BODINTVAL_2_22V,	/*!< Brown-out interrupt at 2.22v */
+	SYSCTL_BODINTVAL_2_52V,	/*!< Brown-out interrupt at 2.52v */
+	SYSCTL_BODINTVAL_2_80V,	/*!< Brown-out interrupt at 2.8v */
+} CHIP_SYSCTL_BODRINTVAL_T;
+
+/**
+ * @brief	Set brown-out detection interrupt and reset levels
+ * @param	rstlvl	: Brown-out detector reset level
+ * @param	intlvl	: Brown-out interrupt level
+ * @return	Nothing
+ * @note	Brown-out detection reset will be disabled upon exiting this function.
+ * Use Chip_SYSCTL_EnableBODReset() to re-enable.
+ */
+STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
+											CHIP_SYSCTL_BODRINTVAL_T intlvl)
+{
+	LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
+}
+
+/**
+ * @brief	Enable brown-out detection reset
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
+{
+	LPC_SYSCTL->BODCTRL |= (1 << 4);
+}
+
+/**
+ * @brief	Disable brown-out detection reset
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
+{
+	LPC_SYSCTL->BODCTRL &= ~(1 << 4);
+}
+
+/**
+ * @brief	Set System tick timer calibration value
+ * @param	sysCalVal	: System tick timer calibration value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
+{
+	LPC_SYSCTL->SYSTCKCAL = sysCalVal;
+}
+
+#if defined(CHIP_LPC1347)
+/**
+ * @brief	Set System IRQ latency
+ * @param	latency	: Latency in clock ticks
+ * @return	Nothing
+ * @note	Sets the IRQ latency, a value between 0 and 255 clocks. Lower
+ * values allow better latency.
+ */
+STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
+{
+	LPC_SYSCTL->IRQLATENCY = latency;
+}
+
+/**
+ * @brief	Get System IRQ latency
+ * @return	Latency in clock ticks
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
+{
+	return LPC_SYSCTL->IRQLATENCY;
+}
+
+/**
+ * Non-Maskable Interrupt Enable/Disable value
+ */
+#define SYSCTL_NMISRC_ENABLE   ((uint32_t) 1 << 31)	/*!< Enable the Non-Maskable Interrupt (NMI) source */
+
+/**
+ * @brief	Set source for non-maskable interrupt (NMI)
+ * @param	intsrc	: IRQ number to assign to the NMI
+ * @return	Nothing
+ * @note	The NMI source will be disabled upon exiting this function. use the
+ * Chip_SYSCTL_EnableNMISource() function to enable the NMI source.
+ */
+STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
+{
+	LPC_SYSCTL->NMISRC = intsrc;
+}
+
+/**
+ * @brief	Enable interrupt used for NMI source
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
+{
+	LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
+}
+
+/**
+ * @brief	Disable interrupt used for NMI source
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
+{
+	LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
+}
+
+/**
+ * @brief	Setup a pin source for the pin interrupts (0-7)
+ * @param	intno	: IRQ number
+ * @param	port		: port number 0/1)
+ * @param	pin		: pin number (0->23 for GPIO Port 0 and 0->31 for GPIO Port 1)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
+
+{
+	LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port * 24 + pin);
+}
+
+/**
+ * @brief	Setup USB clock control
+ * @param	ap_clk	: USB need_clock signal control (0 or 1)
+ * @param	pol_clk	: USB need_clock polarity for triggering the USB wake-up interrupt (0 or 1)
+ * @return	Nothing
+ * @note	See the USBCLKCTRL register in the user manual for these settings.
+ */
+STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
+{
+	LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
+}
+
+/**
+ * @brief	Returns the status of the USB need_clock signal
+ * @return	true if USB need_clock statis is high, otherwise false
+ */
+STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
+{
+	return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
+}
+
+#endif
+
+#if defined(CHIP_LPC1347)
+/**
+ * @brief	Enable PIO start logic for a pin (ERP0)
+ * @param	pin	: PIO pin number (0 - 7)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
+{
+	LPC_SYSCTL->STARTERP0 |= (1 << pin);
+}
+
+/**
+ * @brief	Disable PIO start logic for a pin
+ * @param	pin	: PIO pin number (0 - 7)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
+{
+	LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
+}
+
+/**
+ * Peripheral interrupt wakeup events
+ */
+#define SYSCTL_WAKEUP_WWDTINT    (1 << 12)	/*!< WWDT interrupt wake-up */
+#define SYSCTL_WAKEUP_BODINT     (1 << 13)	/*!< Brown Out Detect (BOD) interrupt wake-up */
+#define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19)	/*!< USB need_clock signal wake-up, LPC1134x only */
+#define SYSCTL_WAKEUP_GPIOINT0   (1 << 20)	/*!< GPIO GROUP0 interrupt wake-up */
+#define SYSCTL_WAKEUP_GPIOINT1   (1 << 21)	/*!< GPIO GROUP1 interrupt wake-up */
+
+/**
+ * @brief	Enables a peripheral's wakeup logic
+ * @param	periphmask	: OR'ed values of SYSCTL_WAKEUP_* for wakeup
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
+{
+	LPC_SYSCTL->STARTERP1 |= periphmask;
+}
+
+/**
+ * @brief	Disables a peripheral's wakeup logic
+ * @param	periphmask	: OR'ed values of SYSCTL_WAKEUP_* for wakeup
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
+{
+	LPC_SYSCTL->STARTERP1 &= ~periphmask;
+}
+
+#else /* defined(CHIP_LPC1343) */
+
+/* Macro for Chip_SYSCTL_SetStartPinRising and Chip_SYSCTL_SetStartPinFalling
+   functions */
+#define SYSCTL_STARTST_PIN_BIT(port, pin)      (((port) * 12) + pin)
+#define SYSCTL_STARTST_PIN_INDEX(port, pin)     (SYSCTL_STARTST_PIN_BIT(port, pin) / 32)
+#define SYSCTL_STARTST_PIN(port, pin)           (1 << (SYSCTL_STARTST_PIN_BIT(port, pin) % 32))
+
+/**
+ * @brief	Set rising edge for PIO start logic (APRP0)
+ * @param	index	: register index (0/1)
+ * @param	pins	: PIO pin(s) mask for setting rising edge start (see note)
+ * @return	Nothing
+ * @note	Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
+ *			is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
+ *			Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
+ *			Multiple pins can be setup for rising edge start with this function
+ *			by Or'ing together the pin values in the call. For example, the
+ *			following call would enable PIO0_5 and PIO_1_10 as rising edge start
+ *			conditions.<br>
+ *			Chip_SYSCTL_SetStartPinRising(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
+ *
+ */
+STATIC INLINE void Chip_SYSCTL_SetStartPinRising(uint8_t index, uint32_t pins)
+{
+	LPC_SYSCTL->STARTLOGIC[index].STARTAPR |= pins;
+}
+
+/**
+ * @brief	Set falling edge for PIO start logic (APRP0)
+ * @param	index	: register index (0/1)
+ * @param	pins	: PIO pin(s) mask for setting falling edge start (see note)
+ * @return	Nothing
+ * @note	Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
+ *			is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
+ *			Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
+ *			Multiple pins can be setup for falling edge start with this function
+ *			by Or'ing together the pin values in the call. For example, the
+ *			following call would enable PIO0_5 and PIO_1_10 as falling edge start
+ *			conditions.<br>
+ *			Chip_SYSCTL_SetStartPinFalling(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
+ */
+STATIC INLINE void Chip_SYSCTL_SetStartPinFalling(uint8_t index, uint32_t pins)
+{
+	LPC_SYSCTL->STARTLOGIC[index].STARTAPR &= ~pins;
+}
+
+/**
+ * @brief	Enables start signal for PIO start logic
+ * @param	index	: register index (0/1)
+ * @param	pins	: PIO pin(s) mask for enabling start (see note)
+ * @return	Nothing
+ * @note	Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
+ *			is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
+ *			Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
+ *			Multiple pins can be enabled with this function by Or'ing together the pin values
+ *			in the call. For example, the following call would enable PIO0_5 and PIO_1_10 <br>
+ *			Chip_SYSCTL_EnableStartPin(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
+ */
+STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint8_t index, uint32_t pins)
+{
+	LPC_SYSCTL->STARTLOGIC[index].STARTER |= pins;
+}
+
+/**
+ * @brief	Disables start signal for PIO start logic
+ * @param	index	: register index (0/1)
+ * @param	pins	: PIO pin(s) mask for disabling start (see note)
+ * @return	Nothing
+ * @note	Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
+ *			is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
+ *			Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
+ *			Multiple pins can be disabled with this function by Or'ing together the pin values
+ *			in the call. For example, the following call would disable PIO0_5 and PIO_1_10 <br>
+ *			Chip_SYSCTL_DisableStartPin(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
+ */
+STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint8_t index, uint32_t pins)
+{
+	LPC_SYSCTL->STARTLOGIC[index].STARTER &= ~pins;
+}
+
+/**
+ * @brief	Resets start logic state for PIO start logic
+ * @param	index	: register index (0/1)
+ * @param	pins	: PIO pin(s) mask for resetting state (see note)
+ * @return	Nothing
+ * @note	Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
+ *			is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
+ *			Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
+ *			Multiple pins can be reset with this function by Or'ing together the pin values
+ *			in the call. For example, the following call would reset start logic signal for PIO0_5 and PIO_1_10 <br>
+ *			Chip_SYSCTL_ResetStartPin(0, SYSCTL_STARTST_PIN(0, 5) | SYSCTL_STARTST_PIN(1, 10));
+ */
+STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint8_t index, uint32_t pins)
+{
+	LPC_SYSCTL->STARTLOGIC[index].STARTRSRCLR |= pins;
+}
+
+/**
+ * @brief	Returns start logic state for PIO pins
+ * @return	The start status of all PIO pins (STARTSRP0 register)
+ * @note	Use index 0 for pin PIO0_0->PIO0_11,PIO1_0->PIO1_11 and PIO2_0->PIO2_7. Index 1
+ *			is used for PIO2_8->PIO2_11 and PIO3_0->PIO3_3. <br>
+ *			Use SYSCTL_STARTST_PIN_INDEX macro to calculate the index value.<br>
+ *			Use the SYSCTL_STARTST_PIN(port, pin) to mask out status conditions.
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetStartPinStatus(uint8_t index)
+{
+	return LPC_SYSCTL->STARTLOGIC[index].STARTSR;
+}
+
+#endif
+
+/**
+ * Deep sleep setup values
+ */
+#define SYSCTL_DEEPSLP_BOD_PD    (1 << 3)	/*!< BOD power-down control in Deep-sleep mode, powered down */
+#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6)	/*!< Watchdog oscillator power control in Deep-sleep, powered down */
+
+/**
+ * @brief	Setup deep sleep behaviour for power down
+ * @param	sleepmask	: OR'ed values of SYSCTL_DEEPSLP_* values (high to powerdown on deepsleep)
+ * @return	Nothing
+ * @note	This must be setup prior to using deep sleep. See the user manual
+ * *(PDSLEEPCFG register) for more info on setting this up. This function selects
+ * which peripherals are powered down on deep sleep.
+ * This function should only be called once with all options for power-down
+ * in that call.
+ */
+void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
+
+/**
+ * @brief	Returns current deep sleep mask
+ * @return	OR'ed values of SYSCTL_DEEPSLP_* values
+ * @note	A high bit indicates the peripheral will power down on deep sleep.
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
+{
+	return LPC_SYSCTL->PDSLEEPCFG;
+}
+
+/**
+ * Deep sleep to wakeup setup values
+ */
+#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0)	/*!< IRC oscillator output wake-up configuration */
+#define SYSCTL_SLPWAKE_IRC_PD    (1 << 1)	/*!< IRC oscillator power-down wake-up configuration */
+#define SYSCTL_SLPWAKE_FLASH_PD  (1 << 2)	/*!< Flash wake-up configuration */
+#define SYSCTL_SLPWAKE_BOD_PD    (1 << 3)	/*!< BOD wake-up configuration */
+#define SYSCTL_SLPWAKE_ADC_PD    (1 << 4)	/*!< ADC wake-up configuration */
+#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5)	/*!< System oscillator wake-up configuration */
+#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6)	/*!< Watchdog oscillator wake-up configuration */
+#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7)	/*!< System PLL wake-up configuration */
+#define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8)	/*!< USB PLL wake-up configuration */
+#define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10)	/*!< USB transceiver wake-up configuration */
+
+/**
+ * @brief	Setup wakeup behaviour from deep sleep
+ * @param	wakeupmask	: OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down)
+ * @return	Nothing
+ * @note	This must be setup prior to using deep sleep. See the user manual
+ * *(PDWAKECFG register) for more info on setting this up. This function selects
+ * which peripherals are powered up on exit from deep sleep.
+ * This function should only be called once with all options for wakeup
+ * in that call.
+ */
+void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
+
+/**
+ * @brief	Return current wakeup mask
+ * @return	OR'ed values of SYSCTL_SLPWAKE_* values
+ * @note	A high state indicates the peripehral will powerup on wakeup.
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
+{
+	return LPC_SYSCTL->PDWAKECFG;
+}
+
+/**
+ * Power down configuration values
+ */
+#define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0)	/*!< IRC oscillator output power down */
+#define SYSCTL_POWERDOWN_IRC_PD    (1 << 1)	/*!< IRC oscillator power-down */
+#define SYSCTL_POWERDOWN_FLASH_PD  (1 << 2)	/*!< Flash power down */
+#define SYSCTL_POWERDOWN_BOD_PD    (1 << 3)	/*!< BOD power down */
+#define SYSCTL_POWERDOWN_ADC_PD    (1 << 4)	/*!< ADC power down */
+#define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5)	/*!< System oscillator power down */
+#define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6)	/*!< Watchdog oscillator power down */
+#define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7)	/*!< System PLL power down */
+#define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8)	/*!< USB PLL power-down */
+#define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)/*!< USB transceiver power-down */
+
+/**
+ * @brief	Power down one or more blocks or peripherals
+ * @param	powerdownmask	: OR'ed values of SYSCTL_POWERDOWN_* values
+ * @return	Nothing
+ */
+void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
+
+/**
+ * @brief	Power up one or more blocks or peripherals
+ * @param	powerupmask	: OR'ed values of SYSCTL_POWERDOWN_* values
+ * @return	Nothing
+ */
+void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
+
+/**
+ * @brief	Get power status
+ * @return	OR'ed values of SYSCTL_POWERDOWN_* values
+ * @note	A high state indicates the peripheral is powered down.
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
+{
+	return LPC_SYSCTL->PDRUNCFG;
+}
+
+/**
+ * @brief	Return the device ID
+ * @return	the device ID
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
+{
+	return LPC_SYSCTL->DEVICEID;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSCTL_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h
new file mode 100644
index 000000000..e0ce52f0b
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/timer_13xx.h
@@ -0,0 +1,445 @@
+/*
+ * @brief LPC13xx 16/32-bit Timer/PWM control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __TIMER_13XX_H_
+#define __TIMER_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup TIMER_13XX CHIP: LPC13xx 16/32-bit Timer driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief 32-bit Standard timer register block structure
+ */
+typedef struct {					/*!< TIMERn Structure       */
+	__IO uint32_t IR;				/*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+	__IO uint32_t TCR;				/*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+	__IO uint32_t TC;				/*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+	__IO uint32_t PR;				/*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+	__IO uint32_t PC;				/*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+	__IO uint32_t MCR;				/*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+	__IO uint32_t MR[4];			/*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+	__IO uint32_t CCR;				/*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+	__IO uint32_t CR[4];			/*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+	__IO uint32_t EMR;				/*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+	__I  uint32_t RESERVED0[12];
+	__IO uint32_t CTCR;				/*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMER_T;
+
+/** Macro to clear interrupt pending */
+#define TIMER_IR_CLR(n)         _BIT(n)
+
+/** Macro for getting a timer match interrupt bit */
+#define TIMER_MATCH_INT(n)      (_BIT((n) & 0x0F))
+/** Macro for getting a capture event interrupt bit */
+#define TIMER_CAP_INT(n)        (_BIT((((n) & 0x0F) + 4)))
+
+/** Timer/counter enable bit */
+#define TIMER_ENABLE            ((uint32_t) (1 << 0))
+/** Timer/counter reset bit */
+#define TIMER_RESET             ((uint32_t) (1 << 1))
+
+/** Bit location for interrupt on MRx match, n = 0 to 3 */
+#define TIMER_INT_ON_MATCH(n)   (_BIT(((n) * 3)))
+/** Bit location for reset on MRx match, n = 0 to 3 */
+#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
+/** Bit location for stop on MRx match, n = 0 to 3 */
+#define TIMER_STOP_ON_MATCH(n)  (_BIT((((n) * 3) + 2)))
+
+/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
+#define TIMER_CAP_RISING(n)     (_BIT(((n) * 3)))
+/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
+#define TIMER_CAP_FALLING(n)    (_BIT((((n) * 3) + 1)))
+/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
+#define TIMER_INT_ON_CAP(n)     (_BIT((((n) * 3) + 2)))
+
+/**
+ * @brief	Initialize a timer
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
+
+/**
+ * @brief	Shutdown a timer
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
+
+/**
+ * @brief	Determine if a match interrupt is pending
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match interrupt number to check
+ * @return	false if the interrupt is not pending, otherwise true
+ * @note	Determine if the match interrupt for the passed timer and match
+ * counter is pending.
+ */
+STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
+}
+
+/**
+ * @brief	Determine if a capture interrupt is pending
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture interrupt number to check
+ * @return	false if the interrupt is not pending, otherwise true
+ * @note	Determine if the capture interrupt for the passed capture pin is
+ * pending.
+ */
+STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
+}
+
+/**
+ * @brief	Clears a (pending) match interrupt
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match interrupt number to clear
+ * @return	Nothing
+ * @note	Clears a pending timer match interrupt.
+ */
+STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->IR = TIMER_IR_CLR(matchnum);
+}
+
+/**
+ * @brief	Clears a (pending) capture interrupt
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture interrupt number to clear
+ * @return	Nothing
+ * @note	Clears a pending timer capture interrupt.
+ */
+STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->IR = (0x10 << capnum);
+}
+
+/**
+ * @brief	Enables the timer (starts count)
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ * @note	Enables the timer to start counting.
+ */
+STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
+{
+	pTMR->TCR |= TIMER_ENABLE;
+}
+
+/**
+ * @brief	Disables the timer (stops count)
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ * @note	Disables the timer to stop counting.
+ */
+STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
+{
+	pTMR->TCR &= ~TIMER_ENABLE;
+}
+
+/**
+ * @brief	Returns the current timer count
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Current timer terminal count value
+ * @note	Returns the current timer terminal count.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
+{
+	return pTMR->TC;
+}
+
+/**
+ * @brief	Returns the current prescale count
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Current timer prescale count value
+ * @note	Returns the current prescale count.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
+{
+	return pTMR->PC;
+}
+
+/**
+ * @brief	Sets the prescaler value
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	prescale	: Prescale value to set the prescale register to
+ * @return	Nothing
+ * @note	Sets the prescale count value.
+ */
+STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
+{
+	pTMR->PR = prescale;
+}
+
+/**
+ * @brief	Sets a timer match value
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer to set match count for
+ * @param	matchval	: Match value for the selected match count
+ * @return	Nothing
+ * @note	Sets one of the timer match values.
+ */
+STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
+{
+	pTMR->MR[matchnum] = matchval;
+}
+
+/**
+ * @brief	Reads a capture register
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture register to read
+ * @return	The selected capture register value
+ * @note	Returns the selected capture register value.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	return pTMR->CR[capnum];
+}
+
+/**
+ * @brief	Resets the timer terminal and prescale counts to 0
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
+
+/**
+ * @brief	Enables a match interrupt that fires when the terminal count
+ *			matches the match counter value.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Disables a match interrupt for a match counter.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	For the specific match counter, enables reset of the terminal count register when a match occurs
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	For the specific match counter, disables reset of the terminal count register when a match occurs
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Enable a match timer to stop the terminal count when a
+ *			match count equals the terminal count.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Disable stop on match for a match timer. Disables a match timer
+ *			to stop the terminal count when a match count equals the terminal count.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Enables capture on on rising edge of selected CAP signal for the
+ *			selected capture register, enables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a rising edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR |= TIMER_CAP_RISING(capnum);
+}
+
+/**
+ * @brief	Disables capture on on rising edge of selected CAP signal. For the
+ *			selected capture register, disables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a rising edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
+}
+
+/**
+ * @brief	Enables capture on on falling edge of selected CAP signal. For the
+ *			selected capture register, enables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a falling edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR |= TIMER_CAP_FALLING(capnum);
+}
+
+/**
+ * @brief	Disables capture on on falling edge of selected CAP signal. For the
+ *			selected capture register, disables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a falling edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
+}
+
+/**
+ * @brief	Enables interrupt on capture of selected CAP signal. For the
+ *			selected capture register, an interrupt will be generated when the enabled
+ *			rising or falling edge on CAPn.capnum is detected.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
+}
+
+/**
+ * @brief	Disables interrupt on capture of selected CAP signal
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
+}
+
+/**
+ * @brief Standard timer initial match pin state and change state
+ */
+typedef enum IP_TIMER_PIN_MATCH_STATE {
+	TIMER_EXTMATCH_DO_NOTHING = 0,	/*!< Timer match state does nothing on match pin */
+	TIMER_EXTMATCH_CLEAR      = 1,	/*!< Timer match state sets match pin low */
+	TIMER_EXTMATCH_SET        = 2,	/*!< Timer match state sets match pin high */
+	TIMER_EXTMATCH_TOGGLE     = 3	/*!< Timer match state toggles match pin */
+} TIMER_PIN_MATCH_STATE_T;
+
+/**
+ * @brief	Sets external match control (MATn.matchnum) pin control. For the pin
+ *          selected with matchnum, sets the function of the pin that occurs on
+ *          a terminal count match for the match count.
+ * @param	pTMR			: Pointer to timer IP register address
+ * @param	initial_state	: Initial state of the pin, high(1) or low(0)
+ * @param	matchState		: Selects the match state for the pin
+ * @param	matchnum		: MATn.matchnum signal to use
+ * @return	Nothing
+ * @note	For the pin selected with matchnum, sets the function of the pin that occurs on
+ * a terminal count match for the match count.
+ */
+void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
+												 TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
+
+/**
+ * @brief Standard timer clock and edge for count source
+ */
+typedef enum IP_TIMER_CAP_SRC_STATE {
+	TIMER_CAPSRC_RISING_PCLK  = 0,	/*!< Timer ticks on PCLK rising edge */
+	TIMER_CAPSRC_RISING_CAPN  = 1,	/*!< Timer ticks on CAPn.x rising edge */
+	TIMER_CAPSRC_FALLING_CAPN = 2,	/*!< Timer ticks on CAPn.x falling edge */
+	TIMER_CAPSRC_BOTH_CAPN    = 3	/*!< Timer ticks on CAPn.x both edges */
+} TIMER_CAP_SRC_STATE_T;
+
+/**
+ * @brief	Sets timer count source and edge with the selected passed from CapSrc.
+ *          If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capSrc	: timer clock source and edge
+ * @param	capnum	: CAPn.capnum pin to use (if used)
+ * @return	Nothing
+ * @note	If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
+ */
+STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
+													 TIMER_CAP_SRC_STATE_T capSrc,
+													 int8_t capnum)
+{
+	pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h
new file mode 100644
index 000000000..f57ee16c5
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/uart_13xx.h
@@ -0,0 +1,788 @@
+/*
+ * @brief LPC13xx UART chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __UART_13XX_H_
+#define __UART_13XX_H_
+
+#include "ring_buffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup UART_13XX CHIP: LPC13xx UART driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief USART register block structure
+ */
+typedef struct {					/*!< USARTn Structure       */
+
+	union {
+		__IO uint32_t  DLL;			/*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+		__O  uint32_t  THR;			/*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+		__I  uint32_t  RBR;			/*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+	};
+
+	union {
+		__IO uint32_t IER;			/*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+		__IO uint32_t DLM;			/*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+	};
+
+	union {
+		__O  uint32_t FCR;			/*!< FIFO Control Register. Controls UART FIFO usage and modes. */
+		__I  uint32_t IIR;			/*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
+	};
+
+	__IO uint32_t LCR;				/*!< Line Control Register. Contains controls for frame formatting and break generation. */
+	__IO uint32_t MCR;				/*!< Modem Control Register. Only present on USART ports with full modem support. */
+	__I  uint32_t LSR;				/*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
+	__I  uint32_t MSR;				/*!< Modem Status Register. Only present on USART ports with full modem support. */
+	__IO uint32_t SCR;				/*!< Scratch Pad Register. Eight-bit temporary storage for software. */
+	__IO uint32_t ACR;				/*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
+	__IO uint32_t ICR;				/*!< IrDA control register (not all UARTS) */
+	__IO uint32_t FDR;				/*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
+	__IO uint32_t OSR;				/*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
+	__IO uint32_t TER1;				/*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+	uint32_t  RESERVED0[3];
+    __IO uint32_t HDEN;				/*!< Half-duplex enable Register- only on some UARTs */
+	__I  uint32_t RESERVED1[1];
+	__IO uint32_t SCICTRL;			/*!< Smart card interface control register- only on some UARTs */
+
+	__IO uint32_t RS485CTRL;		/*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+	__IO uint32_t RS485ADRMATCH;	/*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+	__IO uint32_t RS485DLY;			/*!< RS-485/EIA-485 direction control delay. */
+
+	union {
+		__IO uint32_t SYNCCTRL;		/*!< Synchronous mode control register. Only on USARTs. */
+		__I  uint32_t FIFOLVL;		/*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+	};
+
+	__IO uint32_t TER2;				/*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
+} LPC_USART_T;
+
+
+/**
+ * @brief Macro defines for UART Receive Buffer register
+ */
+#define UART_RBR_MASKBIT    (0xFF)		        /*!< UART Received Buffer mask bit (8 bits) */
+
+/**
+ * @brief Macro defines for UART Divisor Latch LSB register
+ */
+#define UART_LOAD_DLL(div)  ((div) & 0xFF)		/*!< Macro for loading LSB of divisor */
+#define UART_DLL_MASKBIT    (0xFF)	            /*!< Divisor latch LSB bit mask */
+
+/**
+ * @brief Macro defines for UART Divisor Latch MSB register
+ */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)	/*!< Macro for loading MSB of divisors */
+#define UART_DLM_MASKBIT    (0xFF)		            /*!< Divisor latch MSB bit mask */
+
+/**
+ * @brief Macro defines for UART Interrupt Enable Register
+ */
+#define UART_IER_RBRINT      (1 << 0)	/*!< RBR Interrupt enable */
+#define UART_IER_THREINT     (1 << 1)	/*!< THR Interrupt enable */
+#define UART_IER_RLSINT      (1 << 2)	/*!< RX line status interrupt enable */
+#define UART_IER_MSINT       (1 << 3)	/*!< Modem status interrupt enable - valid for 11xx, 17xx/40xx UART1, 18xx/43xx UART1  only */
+#define UART_IER_CTSINT      (1 << 7)	/*!< CTS signal transition interrupt enable - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
+#define UART_IER_ABEOINT     (1 << 8)	/*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT     (1 << 9)	/*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK     (0x307)	/*!< UART interrupt enable register bit mask  - valid for 13xx, 17xx/40xx UART0/2/3, 18xx/43xx UART0/2/3 only*/
+#define UART1_IER_BITMASK    (0x30F)	/*!< UART1 interrupt enable register bit mask - valid for 11xx only */
+#define UART2_IER_BITMASK    (0x38F)	/*!< UART2 interrupt enable register bit mask - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
+
+/**
+ * @brief Macro defines for UART Interrupt Identification Register
+ */
+#define UART_IIR_INTSTAT_PEND   (1 << 0)	/*!< Interrupt pending status - Active low */
+#define UART_IIR_FIFO_EN        (3 << 6)	/*!< These bits are equivalent to FCR[0] */
+#define UART_IIR_ABEO_INT       (1 << 8)	/*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT       (1 << 9)	/*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK        (0x3CF)		/*!< UART interrupt identification register bit mask */
+
+/* Interrupt ID bit definitions */
+#define UART_IIR_INTID_MASK     (7 << 1)	/*!< Interrupt identification: Interrupt ID mask */
+#define UART_IIR_INTID_RLS      (3 << 1)	/*!< Interrupt identification: Receive line interrupt */
+#define UART_IIR_INTID_RDA      (2 << 1)	/*!< Interrupt identification: Receive data available interrupt */
+#define UART_IIR_INTID_CTI      (6 << 1)	/*!< Interrupt identification: Character time-out indicator interrupt */
+#define UART_IIR_INTID_THRE     (1 << 1)	/*!< Interrupt identification: THRE interrupt */
+#define UART_IIR_INTID_MODEM    (0 << 1)	/*!< Interrupt identification: Modem interrupt */
+
+/**
+ * @brief Macro defines for UART FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN        (1 << 0)	/*!< UART FIFO enable */
+#define UART_FCR_RX_RS          (1 << 1)	/*!< UART RX FIFO reset */
+#define UART_FCR_TX_RS          (1 << 2)	/*!< UART TX FIFO reset */
+#define UART_FCR_DMAMODE_SEL    (1 << 3)	/*!< UART DMA mode selection - valid for 17xx/40xx, 18xx/43xx only */
+#define UART_FCR_BITMASK        (0xCF)		/*!< UART FIFO control bit mask */
+
+#define UART_TX_FIFO_SIZE       (16)
+
+/* FIFO trigger level bit definitions */
+#define UART_FCR_TRG_LEV0       (0)			/*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1       (1 << 6)	/*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2       (2 << 6)	/*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3       (3 << 6)	/*!< UART FIFO trigger level 3: 14 character */
+
+/**
+ * @brief Macro defines for UART Line Control Register
+ */
+/* UART word length select bit definitions */
+#define UART_LCR_WLEN_MASK      (3 << 0)		/*!< UART word length select bit mask */
+#define UART_LCR_WLEN5          (0 << 0)		/*!< UART word length select: 5 bit data mode */
+#define UART_LCR_WLEN6          (1 << 0)		/*!< UART word length select: 6 bit data mode */
+#define UART_LCR_WLEN7          (2 << 0)		/*!< UART word length select: 7 bit data mode */
+#define UART_LCR_WLEN8          (3 << 0)		/*!< UART word length select: 8 bit data mode */
+
+/* UART Stop bit select bit definitions */
+#define UART_LCR_SBS_MASK       (1 << 2)		/*!< UART stop bit select: bit mask */
+#define UART_LCR_SBS_1BIT       (0 << 2)		/*!< UART stop bit select: 1 stop bit */
+#define UART_LCR_SBS_2BIT       (1 << 2)		/*!< UART stop bit select: 2 stop bits (in 5 bit data mode, 1.5 stop bits) */
+
+/* UART Parity enable bit definitions */
+#define UART_LCR_PARITY_EN      (1 << 3)		/*!< UART Parity Enable */
+#define UART_LCR_PARITY_DIS     (0 << 3)		/*!< UART Parity Disable */
+#define UART_LCR_PARITY_ODD     (0 << 4)		/*!< UART Parity select: Odd parity */
+#define UART_LCR_PARITY_EVEN    (1 << 4)		/*!< UART Parity select: Even parity */
+#define UART_LCR_PARITY_F_1     (2 << 4)		/*!< UART Parity select: Forced 1 stick parity */
+#define UART_LCR_PARITY_F_0     (3 << 4)		/*!< UART Parity select: Forced 0 stick parity */
+#define UART_LCR_BREAK_EN       (1 << 6)		/*!< UART Break transmission enable */
+#define UART_LCR_DLAB_EN        (1 << 7)		/*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK        (0xFF)			/*!< UART line control bit mask */
+
+/**
+ * @brief Macro defines for UART Modem Control Register
+ */
+#define UART_MCR_DTR_CTRL       (1 << 0)		/*!< Source for modem output pin DTR */
+#define UART_MCR_RTS_CTRL       (1 << 1)		/*!< Source for modem output pin RTS */
+#define UART_MCR_LOOPB_EN       (1 << 4)		/*!< Loop back mode select */
+#define UART_MCR_AUTO_RTS_EN    (1 << 6)		/*!< Enable Auto RTS flow-control */
+#define UART_MCR_AUTO_CTS_EN    (1 << 7)		/*!< Enable Auto CTS flow-control */
+#define UART_MCR_BITMASK        (0xD3)			/*!< UART bit mask value */
+
+/**
+ * @brief Macro defines for UART Line Status Register
+ */
+#define UART_LSR_RDR        (1 << 0)	/*!< Line status: Receive data ready */
+#define UART_LSR_OE         (1 << 1)	/*!< Line status: Overrun error */
+#define UART_LSR_PE         (1 << 2)	/*!< Line status: Parity error */
+#define UART_LSR_FE         (1 << 3)	/*!< Line status: Framing error */
+#define UART_LSR_BI         (1 << 4)	/*!< Line status: Break interrupt */
+#define UART_LSR_THRE       (1 << 5)	/*!< Line status: Transmit holding register empty */
+#define UART_LSR_TEMT       (1 << 6)	/*!< Line status: Transmitter empty */
+#define UART_LSR_RXFE       (1 << 7)	/*!< Line status: Error in RX FIFO */
+#define UART_LSR_TXFE       (1 << 8)	/*!< Line status: Error in RX FIFO */
+#define UART_LSR_BITMASK    (0xFF)		/*!< UART Line status bit mask */
+#define UART1_LSR_BITMASK   (0x1FF)		/*!< UART1 Line status bit mask - valid for 11xx, 18xx/43xx UART0/2/3 only */
+
+/**
+ * @brief Macro defines for UART Modem Status Register
+ */
+#define UART_MSR_DELTA_CTS      (1 << 0)	/*!< Modem status: State change of input CTS */
+#define UART_MSR_DELTA_DSR      (1 << 1)	/*!< Modem status: State change of input DSR */
+#define UART_MSR_LO2HI_RI       (1 << 2)	/*!< Modem status: Low to high transition of input RI */
+#define UART_MSR_DELTA_DCD      (1 << 3)	/*!< Modem status: State change of input DCD */
+#define UART_MSR_CTS            (1 << 4)	/*!< Modem status: Clear To Send State */
+#define UART_MSR_DSR            (1 << 5)	/*!< Modem status: Data Set Ready State */
+#define UART_MSR_RI             (1 << 6)	/*!< Modem status: Ring Indicator State */
+#define UART_MSR_DCD            (1 << 7)	/*!< Modem status: Data Carrier Detect State */
+#define UART_MSR_BITMASK        (0xFF)		/*!< Modem status: MSR register bit-mask value */
+
+/**
+ * @brief Macro defines for UART Auto baudrate control register
+ */
+#define UART_ACR_START              (1 << 0)	/*!< UART Auto-baud start */
+#define UART_ACR_MODE               (1 << 1)	/*!< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART       (1 << 2)	/*!< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR        (1 << 8)	/*!< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR        (1 << 9)	/*!< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK            (0x307)		/*!< UART Auto Baudrate register bit mask */
+
+/**
+ * @brief Macro defines for UART RS485 Control register
+ */
+#define UART_RS485CTRL_NMM_EN       (1 << 0)	/*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
+#define UART_RS485CTRL_RX_DIS       (1 << 1)	/*!< The receiver is disabled */
+#define UART_RS485CTRL_AADEN        (1 << 2)	/*!< Auto Address Detect (AAD) is enabled */
+#define UART_RS485CTRL_SEL_DTR      (1 << 3)	/*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
+												        used for direction control */
+#define UART_RS485CTRL_DCTRL_EN     (1 << 4)	/*!< Enable Auto Direction Control */
+#define UART_RS485CTRL_OINV_1       (1 << 5)	/*!< This bit reverses the polarity of the direction
+												       control signal on the RTS (or DTR) pin. The direction control pin
+												       will be driven to logic "1" when the transmitter has data to be sent */
+#define UART_RS485CTRL_BITMASK      (0x3F)		/*!< RS485 control bit-mask value */
+
+/**
+ * @brief Macro defines for UART IrDA Control Register - valid for 11xx, 17xx/40xx UART0/2/3, 18xx/43xx UART3 only
+ */
+#define UART_ICR_IRDAEN         (1 << 0)			/*!< IrDA mode enable */
+#define UART_ICR_IRDAINV        (1 << 1)			/*!< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN    (1 << 2)			/*!< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n)    ((n & 0x07) << 3)	/*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK        (0x3F)				/*!< UART IRDA bit mask */
+
+/**
+ * @brief Macro defines for UART half duplex register - ????
+ */
+#define UART_HDEN_HDEN          ((1 << 0))			/*!< enable half-duplex mode*/
+
+/**
+ * @brief Macro defines for UART Smart card interface Control Register - valid for 11xx, 18xx/43xx UART0/2/3 only
+ */
+#define UART_SCICTRL_SCIEN        (1 << 0)			/*!< enable asynchronous half-duplex smart card interface*/
+#define UART_SCICTRL_NACKDIS      (1 << 1)			/*!< NACK response is inhibited*/
+#define UART_SCICTRL_PROTSEL_T1   (1 << 2)			/*!< ISO7816-3 protocol T1 is selected*/
+#define UART_SCICTRL_TXRETRY(n)   ((n & 0x07) << 5)	/*!< number of retransmission*/
+#define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8)	/*!< Extra guard time*/
+
+/**
+ * @brief Macro defines for UART Fractional Divider Register
+ */
+#define UART_FDR_DIVADDVAL(n)   (n & 0x0F)			/*!< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n)      ((n << 4) & 0xF0)	/*!< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK        (0xFF)				/*!< UART Fractional Divider register bit mask */
+
+/**
+ * @brief Macro defines for UART Tx Enable Register
+ */
+#define UART_TER1_TXEN      (1 << 7)		/*!< Transmit enable bit  - valid for 11xx, 13xx, 17xx/40xx only */
+#define UART_TER2_TXEN      (1 << 0)		/*!< Transmit enable bit  - valid for 18xx/43xx only */
+
+/**
+ * @brief Macro defines for UART Synchronous Control Register - 11xx, 18xx/43xx UART0/2/3 only 
+ */
+#define UART_SYNCCTRL_SYNC             (1 << 0)			/*!< enable synchronous mode*/
+#define UART_SYNCCTRL_CSRC_MASTER      (1 << 1)  		/*!< synchronous master mode*/
+#define UART_SYNCCTRL_FES              (1 << 2)			/*!< sample on falling edge*/
+#define UART_SYNCCTRL_TSBYPASS         (1 << 3)			/*!< to be defined*/
+#define UART_SYNCCTRL_CSCEN            (1 << 4)			/*!< Continuous running clock enable (master mode only)*/
+#define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5)	        /*!< Do not send start/stop bit*/
+#define UART_SYNCCTRL_CCCLR            (1 << 6)			/*!< stop continuous clock*/
+
+/**
+ * @brief	Enable transmission on UART TxD pin
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @return Nothing
+ */
+STATIC INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART)
+{
+	pUART->TER1 = UART_TER1_TXEN;
+}
+
+/**
+ * @brief	Disable transmission on UART TxD pin
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @return Nothing
+ */
+STATIC INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART)
+{
+	pUART->TER1 = 0;
+}
+
+/**
+ * @brief	Transmit a single data byte through the UART peripheral
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	data	: Byte to transmit
+ * @return	Nothing
+ * @note	This function attempts to place a byte into the UART transmit
+ *			FIFO or transmit hold register regard regardless of UART state
+ */
+STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
+{
+	pUART->THR = (uint32_t) data;
+}
+
+/**
+ * @brief	Read a single byte data from the UART peripheral
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	A single byte of data read
+ * @note	This function reads a byte from the UART receive FIFO or
+ *			receive hold register regard regardless of UART state. The
+ *			FIFO status should be read first prior to using this function
+ */
+STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
+}
+
+/**
+ * @brief	Enable UART interrupts
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	intMask	: OR'ed Interrupts to enable in the Interrupt Enable Register (IER)
+ * @return	Nothing
+ * @note	Use an OR'ed value of UART_IER_* definitions with this function
+ *			to enable specific UART interrupts. The Divisor Latch Access Bit
+ *			(DLAB) in LCR must be cleared in order to access the IER register.
+ *			This function doesn't alter the DLAB state
+ */
+STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask)
+{
+	pUART->IER |= intMask;
+}
+
+/**
+ * @brief	Disable UART interrupts
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	intMask	: OR'ed Interrupts to disable in the Interrupt Enable Register (IER)
+ * @return	Nothing
+ * @note	Use an OR'ed value of UART_IER_* definitions with this function
+ *			to disable specific UART interrupts. The Divisor Latch Access Bit
+ *			(DLAB) in LCR must be cleared in order to access the IER register.
+ *			This function doesn't alter the DLAB state
+ */
+STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask)
+{
+	pUART->IER &= ~intMask;
+}
+
+/**
+ * @brief	Returns UART interrupts that are enabled
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Returns the enabled UART interrupts
+ * @note	Use an OR'ed value of UART_IER_* definitions with this function
+ *			to determine which interrupts are enabled. You can check
+ *			for multiple enabled bits if needed.
+ */
+STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART)
+{
+	return pUART->IER;
+}
+
+/**
+ * @brief	Read the Interrupt Identification Register (IIR)
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Current pending interrupt status per the IIR register
+ */
+STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART)
+{
+	return pUART->IIR;
+}
+
+/**
+ * @brief	Setup the UART FIFOs
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	fcr		: FIFO control register setup OR'ed flags
+ * @return	Nothing
+ * @note	Use OR'ed value of UART_FCR_* definitions with this function
+ *			to select specific options. For example, to enable the FIFOs
+ *			with a RX trip level of 8 characters, use something like
+ *			(UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2)
+ */
+STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr)
+{
+	pUART->FCR = fcr;
+}
+
+/**
+ * @brief	Configure data width, parity and stop bits
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @param	config	: UART configuration, OR'ed values of UART_LCR_* defines
+ * @return	Nothing
+ * @note	Select OR'ed config options for the UART from the UART_LCR_*
+ *			definitions. For example, a configuration of 8 data bits, 1
+ *			stop bit, and even (enabled) parity would be
+ *			(UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_EN | UART_LCR_PARITY_EVEN)
+ */
+STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config)
+{
+	pUART->LCR = config;
+}
+
+/**
+ * @brief	Enable access to Divisor Latches
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART)
+{
+	pUART->LCR |= UART_LCR_DLAB_EN;
+}
+
+/**
+ * @brief	Disable access to Divisor Latches
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART)
+{
+	pUART->LCR &= ~UART_LCR_DLAB_EN;
+}
+
+/**
+ * @brief	Set LSB and MSB divisor latch registers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	dll		: Divisor Latch LSB value
+ * @param	dlm		: Divisor Latch MSB value
+ * @return	Nothing
+ * @note	The Divisor Latch Access Bit (DLAB) in LCR must be set in
+ *			order to access the USART Divisor Latches. This function
+ *			doesn't alter the DLAB state.
+ */
+STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm)
+{
+	pUART->DLL = (uint32_t) dll;
+	pUART->DLM = (uint32_t) dlm;
+}
+
+
+/**
+ * @brief	Return modem control register/status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Modem control register (status)
+ * @note	Mask bits of the returned status value with UART_MCR_*
+ *			definitions for specific statuses.
+ */
+STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART)
+{
+	return pUART->MCR;
+}
+
+/**
+ * @brief	Set modem control register/status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	mcr		: Modem control register flags to set
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_MCR_* definitions with this
+ *			call to set specific options.
+ */
+STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr)
+{
+	pUART->MCR |= mcr;
+}
+
+/**
+ * @brief	Clear modem control register/status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	mcr		: Modem control register flags to clear
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_MCR_* definitions with this
+ *			call to clear specific options.
+ */
+STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr)
+{
+	pUART->MCR &= ~mcr;
+}
+
+/**
+ * @brief	Return Line Status register/status (LSR)
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Line Status register (status)
+ * @note	Mask bits of the returned status value with UART_LSR_*
+ *			definitions for specific statuses.
+ */
+STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART)
+{
+	return pUART->LSR;
+}
+
+/**
+ * @brief	Return Modem Status register/status (MSR)
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Modem Status register (status)
+ * @note	Mask bits of the returned status value with UART_MSR_*
+ *			definitions for specific statuses.
+ */
+STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART)
+{
+	return pUART->MSR;
+}
+
+/**
+ * @brief	Write a byte to the scratchpad register
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	data	: Byte value to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data)
+{
+	pUART->SCR = (uint32_t) data;
+}
+
+/**
+ * @brief	Returns current byte value in the scratchpad register
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Byte value read from scratchpad register
+ */
+STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->SCR & 0xFF);
+}
+
+/**
+ * @brief	Set autobaud register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	acr		: Or'ed values to set for ACR register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_ACR_* definitions with this
+ *			call to set specific options.
+ */
+STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
+{
+	pUART->ACR |= acr;
+}
+
+/**
+ * @brief	Clear autobaud register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	acr		: Or'ed values to clear for ACR register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_ACR_* definitions with this
+ *			call to clear specific options.
+ */
+STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
+{
+	pUART->ACR &= ~acr;
+}
+
+/**
+ * @brief	Set RS485 control register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	ctrl	: Or'ed values to set for RS485 control register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_RS485CTRL_* definitions with this
+ *			call to set specific options.
+ */
+STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
+{
+	pUART->RS485CTRL |= ctrl;
+}
+
+/**
+ * @brief	Clear RS485 control register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	ctrl	: Or'ed values to clear for RS485 control register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_RS485CTRL_* definitions with this
+ *			call to clear specific options.
+ */
+STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
+{
+	pUART->RS485CTRL &= ~ctrl;
+}
+
+/**
+ * @brief	Set RS485 address match value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	addr	: Address match value for RS-485/EIA-485 mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr)
+{
+	pUART->RS485ADRMATCH = (uint32_t) addr;
+}
+
+/**
+ * @brief	Read RS485 address match value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Address match value for RS-485/EIA-485 mode
+ */
+STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
+}
+
+/**
+ * @brief	Set RS485 direction control (RTS or DTR) delay value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	dly		: direction control (RTS or DTR) delay value
+ * @return	Nothing
+ * @note	This delay time is in periods of the baud clock. Any delay
+ *			time from 0 to 255 bit times may be programmed.
+ */
+STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly)
+{
+	pUART->RS485DLY = (uint32_t) dly;
+}
+
+/**
+ * @brief	Read RS485 direction control (RTS or DTR) delay value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	direction control (RTS or DTR) delay value
+ * @note	This delay time is in periods of the baud clock. Any delay
+ *			time from 0 to 255 bit times may be programmed.
+ */
+STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->RS485DLY & 0xFF);
+}
+
+/**
+ * @brief	Initializes the pUART peripheral
+ * @param	pUART		: Pointer to selected pUART peripheral
+ * @return	Nothing
+ */
+void Chip_UART_Init(LPC_USART_T *pUART);
+
+/**
+ * @brief	De-initializes the pUART peripheral.
+ * @param	pUART		: Pointer to selected pUART peripheral
+ * @return	Nothing
+ */
+void Chip_UART_DeInit(LPC_USART_T *pUART);
+
+/**
+ * @brief	Transmit a byte array through the UART peripheral (non-blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to bytes to transmit
+ * @param	numBytes	: Number of bytes to transmit
+ * @return	The actual number of bytes placed into the FIFO
+ * @note	This function places data into the transmit FIFO until either
+ *			all the data is in the FIFO or the FIFO is full. This function
+ *			will not block in the FIFO is full. The actual number of bytes
+ *			placed into the FIFO is returned. This function ignores errors.
+ */
+int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes);
+
+/**
+ * @brief	Read data through the UART peripheral (non-blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to bytes array to fill
+ * @param	numBytes	: Size of the passed data array
+ * @return	The actual number of bytes read
+ * @note	This function reads data from the receive FIFO until either
+ *			all the data has been read or the passed buffer is completely full.
+ *			This function will not block. This function ignores errors.
+ */
+int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes);
+
+/**
+ * @brief	Sets best dividers to get a target bit rate (without fractional divider)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	baudrate	: Target baud rate (baud rate = bit rate)
+ * @return	The actual baud rate, or 0 if no rate can be found
+ */
+uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
+
+/**
+ * @brief	Sets best dividers to get a target bit rate (with fractional divider)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	baudrate	: Target baud rate (baud rate = bit rate)
+ * @return	The actual baud rate, or 0 if no rate can be found
+ */
+uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate);
+
+/**
+ * @brief	Transmit a byte array through the UART peripheral (blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to data to transmit
+ * @param	numBytes	: Number of bytes to transmit
+ * @return	The number of bytes transmitted
+ * @note	This function will send or place all bytes into the transmit
+ *			FIFO. This function will block until the last bytes are in the FIFO.
+ */
+int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes);
+
+/**
+ * @brief	Read data through the UART peripheral (blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to data array to fill
+ * @param	numBytes	: Size of the passed data array
+ * @return	The size of the dat array
+ * @note	This function reads data from the receive FIFO until the passed
+ *			buffer is completely full. The function will block until full.
+ *			This function ignores errors.
+ */
+int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes);
+
+/**
+ * @brief	UART receive-only interrupt handler for ring buffers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @return	Nothing
+ * @note	If ring buffer support is desired for the receive side
+ *			of data transfer, the UART interrupt should call this
+ *			function for a receive based interrupt status.
+ */
+void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
+
+/**
+ * @brief	UART transmit-only interrupt handler for ring buffers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @return	Nothing
+ * @note	If ring buffer support is desired for the transmit side
+ *			of data transfer, the UART interrupt should call this
+ *			function for a transmit based interrupt status.
+ */
+void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
+
+/**
+ * @brief	Populate a transmit ring buffer and start UART transmit
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @param	data	: Pointer to buffer to move to ring buffer
+ * @param	bytes	: Number of bytes to move
+ * @return	The number of bytes placed into the ring buffer
+ * @note	Will move the data into the TX ring buffer and start the
+ *			transfer. If the number of bytes returned is less than the
+ *			number of bytes to send, the ring buffer is considered full.
+ */
+uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes);
+
+/**
+ * @brief	Copy data from a receive ring buffer
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @param	data	: Pointer to buffer to fill from ring buffer
+ * @param	bytes	: Size of the passed buffer in bytes
+ * @return	The number of bytes placed into the ring buffer
+ * @note	Will move the data from the RX ring buffer up to the
+ *			the maximum passed buffer size. Returns 0 if there is
+ *			no data in the ring buffer.
+ */
+int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes);
+
+/**
+ * @brief	UART receive/transmit interrupt handler for ring buffers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRXRB	: Pointer to transmit ring buffer
+ * @param	pTXRB	: Pointer to receive ring buffer
+ * @return	Nothing
+ * @note	This provides a basic implementation of the UART IRQ
+ *			handler for support of a ring buffer implementation for
+ *			transmit and receive.
+ */
+void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h
new file mode 100644
index 000000000..64db6995c
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/usbd_13xx.h
@@ -0,0 +1,77 @@
+/*
+ * @brief LPC13xx USB device register block
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __USBD_13XX_H_
+#define __USBD_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup USBD_13XX CHIP: LPC13xx USB Device driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC1347)
+
+/**
+ * @brief USB device register block structure
+ */
+
+typedef struct {				/*!< (@ 0x40080000) USB Structure */
+	__IO uint32_t DEVCMDSTAT;	/*!< (@ 0x40080000) USB Device Command/Status register */
+	__IO uint32_t INFO;			/*!< (@ 0x40080004) USB Info register */
+	__IO uint32_t EPLISTSTART;	/*!< (@ 0x40080008) USB EP Command/Status List start address */
+	__IO uint32_t DATABUFSTART;	/*!< (@ 0x4008000C) USB Data buffer start address */
+	__IO uint32_t LPM;			/*!< (@ 0x40080010) Link Power Management register */
+	__IO uint32_t EPSKIP;		/*!< (@ 0x40080014) USB Endpoint skip */
+	__IO uint32_t EPINUSE;		/*!< (@ 0x40080018) USB Endpoint Buffer in use */
+	__IO uint32_t EPBUFCFG;		/*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
+	__IO uint32_t INTSTAT;		/*!< (@ 0x40080020) USB interrupt status register */
+	__IO uint32_t INTEN;		/*!< (@ 0x40080024) USB interrupt enable register */
+	__IO uint32_t INTSETSTAT;	/*!< (@ 0x40080028) USB set interrupt status register */
+	__IO uint32_t INTROUTING;	/*!< (@ 0x4008002C) USB interrupt routing register */
+	__I  uint32_t RESERVED0[1];
+	__I  uint32_t EPTOGGLE;		/*!< (@ 0x40080034) USB Endpoint toggle register */
+} LPC_USB_T;
+
+#endif /* defined(CHIP_LPC1347) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USBD_13XX_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h
new file mode 100644
index 000000000..fdb0536de
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/inc/wwdt_13xx.h
@@ -0,0 +1,271 @@
+/*
+ * @brief LPC13xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __WWDT_13XX_H_
+#define __WWDT_13XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup WWDT_13XX CHIP: LPC13xx Windowed Watchdog driver
+ * @ingroup CHIP_13XX_Drivers
+ * @{
+ */
+
+#if !defined(CHIP_LPC1343)
+#define WATCHDOG_WINDOW_SUPPORT
+#endif
+
+#if defined(CHIP_LPC1347)
+#define WATCHDOG_CLKSEL_SUPPORT
+#endif
+
+/** WDT oscillator frequency value */
+#define WDT_OSC     (SYSCTL_IRC_FREQ)
+
+/**
+ * @brief Windowed Watchdog register block structure
+ */
+typedef struct {				/*!< WWDT Structure         */
+	__IO uint32_t  MOD;			/*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+	__IO uint32_t  TC;			/*!< Watchdog timer constant register. This register determines the time-out value. */
+	__O  uint32_t  FEED;		/*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+	__I  uint32_t  TV;			/*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+#ifdef WATCHDOG_CLKSEL_SUPPORT
+	__IO uint32_t CLKSEL;		/*!< Watchdog clock select register. */
+#else
+	__I  uint32_t  RESERVED0;
+#endif
+#ifdef WATCHDOG_WINDOW_SUPPORT
+	__IO uint32_t  WARNINT;		/*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+	__IO uint32_t  WINDOW;		/*!< Watchdog timer window register. This register contains the Watchdog window value. */
+#endif
+} LPC_WWDT_T;
+
+/**
+ * @brief Watchdog Mode register definitions
+ */
+/** Watchdog Mode Bitmask */
+#define WWDT_WDMOD_BITMASK          ((uint32_t) 0x1F)
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDEN             ((uint32_t) (1 << 0))
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDRESET          ((uint32_t) (1 << 1))
+/** WWDT time out flag bit */
+#define WWDT_WDMOD_WDTOF            ((uint32_t) (1 << 2))
+/** WDT Time Out flag bit */
+#define WWDT_WDMOD_WDINT            ((uint32_t) (1 << 3))
+/** WWDT Protect flag bit */
+#define WWDT_WDMOD_WDPROTECT        ((uint32_t) (1 << 4))
+/** WWDT lock bit, locks the current WDT clock */
+#define WWDT_WDMOD_LOCK             ((uint32_t) (1 << 5))
+
+/**
+ * @brief	Initialize the Watchdog timer
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ */
+void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
+
+/**
+ * @brief	Shutdown the Watchdog timer
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ */
+void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT);
+
+/**
+ * @brief	Set WDT timeout constant value used for feed
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	none
+ */
+STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)
+{
+	pWWDT->TC = timeout;
+}
+
+/**
+ * @brief	Feed watchdog timer
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ * @note	If this function isn't called, a watchdog timer warning will occur.
+ * After the warning, a timeout will occur if a feed has happened.
+ */
+STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)
+{
+	pWWDT->FEED = 0xAA;
+	pWWDT->FEED = 0x55;
+}
+
+#if defined(WATCHDOG_WINDOW_SUPPORT)
+/**
+ * @brief	Set WWDT warning interrupt
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	timeout	: WDT warning in ticks, between 0 and 1023
+ * @return	None
+ * @note	This is the number of ticks after the watchdog interrupt that the
+ * warning interrupt will be generated.
+ */
+STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)
+{
+	pWWDT->WARNINT = timeout;
+}
+
+/**
+ * @brief	Set WWDT window time
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	None
+ * @note	The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
+ * function and this function, with this function defining the last tick before the
+ * watchdog window interrupt occurs.
+ */
+STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)
+{
+	pWWDT->WINDOW = timeout;
+}
+
+#endif
+
+/**
+ * @brief	Enable watchdog timer options
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	options	: An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * @note	You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
+ * are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot
+ * be unset.
+ */
+STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)
+{
+	pWWDT->MOD |= options;
+}
+
+/**
+ * @brief	Disable/clear watchdog timer options
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	options	: An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * @note	You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDTOF).
+ */
+STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)
+{
+	pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;
+}
+
+/**
+ * @brief	Enable WWDT activity
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)
+{
+	Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);
+	Chip_WWDT_Feed(pWWDT);
+}
+
+/**
+ * @brief	Read WWDT status flag
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	Watchdog status, an Or'ed value of WWDT_WDMOD_*
+ */
+STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)
+{
+	return pWWDT->MOD;
+}
+
+/**
+ * @brief	Clear WWDT interrupt status flags
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	status	: Or'ed value of status flag(s) that you want to clear, should be:
+ *              - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
+ *              - WWDT_WDMOD_WDINT: Clear watchdog warning flag
+ * @return	None
+ */
+void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status);
+
+/**
+ * @brief	Get the current value of WDT
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	current value of WDT
+ */
+STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)
+{
+	return pWWDT->TV;
+}
+
+#if defined(WATCHDOG_CLKSEL_SUPPORT)
+/**
+ * @brief Watchdog Timer Clock Source Selection register definitions
+ */
+/** Clock source select bitmask */
+#define WWDT_CLKSEL_BITMASK         ((uint32_t) 0x10000003)
+/** Clock source select */
+#define WWDT_CLKSEL_SOURCE(n)       ((uint32_t) (n & 0x03))
+/** Lock the clock source selection */
+#define WWDT_CLKSEL_LOCK            ((uint32_t) (1 << 31))
+
+/**
+ * @brief Watchdog Clock Source definitions
+ */
+typedef enum {
+	WWDT_CLKSRC_IRC = WWDT_CLKSEL_SOURCE(0),				/*!< Internal RC oscillator */
+	WWDT_CLKSRC_WATCHDOG_WDOSC = WWDT_CLKSEL_SOURCE(1),		/*!< Watchdog oscillator (WDOSC) */
+} CHIP_WWDT_CLK_SRC_T;
+
+/**
+ * @brief	Get the current value of WDT
+ * @param	pWWDT		: The base of WatchDog Timer peripheral on the chip
+ * @param	wdtClkSrc	: Selected watchdog clock source
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_WWDT_SelClockSource(LPC_WWDT_T *pWWDT, CHIP_WWDT_CLK_SRC_T wdtClkSrc)
+{
+	pWWDT->CLKSEL = wdtClkSrc & WWDT_CLKSEL_BITMASK;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WWDT_H_ */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/adc_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/adc_13xx.c
new file mode 100644
index 000000000..cd98ec405
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/adc_13xx.c
@@ -0,0 +1,287 @@
+/*
+ * @brief LPC13xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+/* Get the number of clock for a full conversion */
+STATIC INLINE uint8_t getFullConvClk(void)
+{
+#if defined(CHIP_LPC1347)
+    return 31;
+#else
+	return 11;
+#endif
+}
+
+/* Get divider value */
+STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
+{
+	uint32_t adcBlockFreq;
+	uint32_t fullAdcRate;
+	uint8_t div;
+
+	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
+	   A/D converter, which should be less than or equal to 4.5MHz.
+	   A fully conversion requires (bits_accuracy+1) of these clocks.
+	   ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
+	   ADC rate = ADC clock / (the number of clocks required for each conversion);
+	 */
+	adcBlockFreq = Chip_Clock_GetSystemClockRate();
+#if defined(ADC_ACC_12BITS)
+	fullAdcRate = adcRate * getFullConvClk();
+	if (clks == ADC_10BITS) {
+		fullAdcRate /= 2;
+	}
+#else
+	if (burstMode) {
+		fullAdcRate = adcRate * clks;
+	}
+	else {
+		fullAdcRate = adcRate * getFullConvClk();
+	}
+#endif
+	/* Get the round value by fomular: (2*A + B)/(2*B) */
+	div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
+	return div;
+}
+
+/* Set start mode for ADC */
+void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode)
+{
+	uint32_t temp;
+	temp = pADC->CR & (~ADC_CR_START_MASK);
+	pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode));
+}
+
+/* Get the ADC value */
+Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
+{
+	uint32_t temp;
+	temp = pADC->DR[channel];
+	if (!ADC_DR_DONE(temp)) {
+		return ERROR;
+	}
+	/*	if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */
+	/*	return ERROR; */
+	*data = (uint16_t) ADC_DR_RESULT(temp);
+	return SUCCESS;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC peripheral and the ADC setup structure to default value */
+void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup)
+{
+	uint8_t div;
+	uint32_t cr = 0;
+	uint32_t clk;
+
+    /* Power up ADC */
+    Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC_PD);
+
+    /* Enable ADC clock */    
+    Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
+
+#if defined(ADC_TRIM_SUPPORT)
+	pADC->ADTRM = 0xF00;
+#endif
+	pADC->INTEN = 0;		/* Disable all interrupts */
+
+#if defined(CHIP_LPC1347)
+	cr |= ADC_CR_LPWRMODE;
+#else
+	cr |= ADC_CR_PDN;
+#endif
+
+	ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE;
+    
+#if defined(CHIP_LPC1347)
+	ADCSetup->bitsAccuracy = ADC_12BITS;
+	clk = ADC_12BITS;
+#else
+	ADCSetup->bitsAccuracy = ADC_10BITS;
+	clk = 11;
+#endif
+    
+	ADCSetup->burstMode = false;
+	div = getClkDiv(pADC, false, ADCSetup->adcRate, clk);
+	cr |= ADC_CR_CLKDIV(div);
+#if !defined(ADC_ACC_12BITS)
+	cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
+#endif /*defined(ADC_ACC_12BITS)*/
+	pADC->CR = cr;
+}
+
+/* Shutdown ADC */
+void Chip_ADC_DeInit(LPC_ADC_T *pADC)
+{
+	pADC->INTEN = 0x00000100;
+	pADC->CR = 0;
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
+    Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC_PD);
+}
+
+/* Get the ADC value */
+Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
+{
+	return readAdcVal(pADC, channel, data);
+}
+
+/* Get ADC Channel status from ADC data register */
+FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
+{
+	switch (StatusType) {
+	case ADC_DR_DONE_STAT:
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_OVERRUN_STAT:
+		channel += 8;
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_ADINT_STAT:
+		return pADC->STAT >> 16 ? SET : RESET;
+
+	default:
+		break;
+	}
+	return RESET;
+}
+
+/* Enable/Disable interrupt for ADC channel */
+void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->INTEN |= (1UL << channel);
+	}
+	else {
+		pADC->INTEN &= (~(1UL << channel));
+	}
+}
+
+/* Select the mode starting the AD conversion */
+void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption)
+{
+	if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
+		if (EdgeOption) {
+			pADC->CR |= ADC_CR_EDGE;
+		}
+		else {
+			pADC->CR &= ~ADC_CR_EDGE;
+		}
+	}
+	setStartMode(pADC, (uint8_t) mode);
+}
+
+/* Set the ADC Sample rate */
+void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate)
+{
+	uint8_t div;
+	uint32_t cr;
+
+	cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK);
+	ADCSetup->adcRate = rate;
+    
+#if defined(CHIP_LPC1347)
+	div = getClkDiv(pADC, ADCSetup->burstMode, rate, ADCSetup->bitsAccuracy);
+	if (ADCSetup->bitsAccuracy == ADC_10BITS) {
+		cr |= ADC_CR_MODE10BIT;
+	}
+#else
+	div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy));
+#endif
+    
+	cr |= ADC_CR_CLKDIV(div);
+#if !defined(ADC_ACC_12BITS)
+	cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
+#endif /*defined(ADC_ACC_12BITS)*/
+	pADC->CR = cr;
+}
+
+/* Set the ADC accuracy bits */
+void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution)
+{
+	ADCSetup->bitsAccuracy = resolution;
+	Chip_ADC_SetSampleRate(pADC, ADCSetup, ADCSetup->adcRate);
+}
+
+/* Enable or disable the ADC channel on ADC peripheral */
+void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->CR |= ADC_CR_CH_SEL(channel);
+	}
+	else {
+		pADC->CR &= ~ADC_CR_START_MASK;
+		pADC->CR &= ~ADC_CR_CH_SEL(channel);
+	}
+}
+
+/* Enable burst mode */
+void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState)
+{
+	setStartMode(pADC, ADC_NO_START);
+
+#if defined(CHIP_LPC1347)
+	pADC->INTEN &= ~(1 << 8);
+#endif
+	if (NewState == DISABLE) {
+		pADC->CR &= ~ADC_CR_BURST;
+	}
+	else {
+		pADC->CR |= ADC_CR_BURST;
+	}
+}
+
+/* Read the ADC value and convert it to 8bits value */
+Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data)
+{
+	uint16_t temp=0;
+	Status rt;
+
+	rt = readAdcVal(pADC, channel, &temp);
+	*data = (uint8_t) temp;
+
+	return rt;
+}
+
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c
new file mode 100644
index 000000000..b9c3453da
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/chip_13xx.c
@@ -0,0 +1,71 @@
+/*
+ * @brief LPC13xx Miscellaneous chip specific functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/* System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetSystemClockRate();
+}
+
+void Chip_USB_Init(void)
+{
+	/* power UP USB Phy and USB PLL */
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
+	Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_SYSOSC);
+	Chip_Clock_SetupUSBPLL(3,1);
+	while (!Chip_Clock_IsUSBPLLLocked()) {}
+	Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
+}
+
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c
new file mode 100644
index 000000000..24b22be6a
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/clock_13xx.c
@@ -0,0 +1,261 @@
+/*
+ * @brief LPC13XX System clock control functions
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Inprecise clock rates for the watchdog oscillator */
+STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
+	0,					/* WDT_OSC_ILLEGAL */
+	600000,				/* WDT_OSC_0_60 */
+	1050000,			/* WDT_OSC_1_05 */
+	1400000,			/* WDT_OSC_1_40 */
+	1750000,			/* WDT_OSC_1_75 */
+	2100000,			/* WDT_OSC_2_10 */
+	2400000,			/* WDT_OSC_2_40 */
+	2700000,			/* WDT_OSC_2_70 */
+	3000000,			/* WDT_OSC_3_00 */
+	3250000,			/* WDT_OSC_3_25 */
+	3500000,			/* WDT_OSC_3_50 */
+	3750000,			/* WDT_OSC_3_75 */
+	4000000,			/* WDT_OSC_4_00 */
+	4200000,			/* WDT_OSC_4_20 */
+	4400000,			/* WDT_OSC_4_40 */
+	4600000				/* WDT_OSC_4_60 */
+};
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Compute a WDT or LFO rate */
+STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
+{
+	uint32_t div;
+	CHIP_WDTLFO_OSC_T clk;
+
+	/* Get WDT oscillator settings */
+	clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
+	div = reg & 0x1F;
+
+	/* Compute clock rate and divided by divde value */
+	return wdtOSCRate[clk] / ((div + 1) << 1);
+}
+
+/* Compute a PLL frequency */
+STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
+{
+	uint32_t msel = ((PLLReg & 0x1F) + 1);
+
+	return inputRate * msel;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set System PLL clock source */
+void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
+{
+	LPC_SYSCTL->SYSPLLCLKSEL  = (uint32_t) src;
+#if defined(CHIP_LPC1343)
+	LPC_SYSCTL->SYSPLLCLKUEN  = 0;
+	LPC_SYSCTL->SYSPLLCLKUEN  = 1;
+#endif
+}
+
+/* Bypass System Oscillator and set oscillator frequency range */
+void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
+{
+	uint32_t ctrl = 0;
+
+	if (bypass) {
+		ctrl |= (1 << 0);
+	}
+	if (highfr) {
+		ctrl |= (1 << 1);
+	}
+
+	LPC_SYSCTL->SYSOSCCTRL = ctrl;
+}
+
+/* Set USB PLL clock source */
+void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
+{
+	LPC_SYSCTL->USBPLLCLKSEL  = (uint32_t) src;
+#if defined(CHIP_LPC1343)
+	LPC_SYSCTL->USBPLLCLKUEN  = 0;
+	LPC_SYSCTL->USBPLLCLKUEN  = 1;
+#endif
+}
+
+/* Set main system clock source */
+void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
+{
+	LPC_SYSCTL->MAINCLKSEL  = (uint32_t) src;
+#if defined(CHIP_LPC1343)
+	LPC_SYSCTL->MAINCLKUEN  = 0;
+	LPC_SYSCTL->MAINCLKUEN  = 1;
+#endif
+}
+
+/* Set USB clock source and divider */
+void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
+{
+	LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
+#if defined(CHIP_LPC1343)
+	LPC_SYSCTL->USBCLKUEN = 0;
+	LPC_SYSCTL->USBCLKUEN = 1;
+#endif
+	LPC_SYSCTL->USBCLKDIV = div;
+}
+
+#if defined(CHIP_LPC1343)
+/* Set WDT clock source and divider */
+void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div)
+{
+	LPC_SYSCTL->WDTCLKSEL = (uint32_t) src;
+	LPC_SYSCTL->WDTCLKUEN = 0;
+	LPC_SYSCTL->WDTCLKUEN = 1;
+	LPC_SYSCTL->WDTCLKDIV = div;
+}
+
+#endif
+
+/* Set CLKOUT clock source and divider */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
+{
+	LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
+#if defined(CHIP_LPC1343)
+	LPC_SYSCTL->CLKOUTUEN = 0;
+	LPC_SYSCTL->CLKOUTUEN = 1;
+#endif
+	LPC_SYSCTL->CLKOUTDIV = div;
+}
+
+/* Return estimated watchdog oscillator rate */
+uint32_t Chip_Clock_GetWDTOSCRate(void)
+{
+	return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
+}
+
+/* Return System PLL input clock rate */
+uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
+{
+	uint32_t clkRate;
+
+	switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
+	case SYSCTL_PLLCLKSRC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCTL_PLLCLKSRC_SYSOSC:
+		clkRate = Chip_Clock_GetMainOscRate();
+		break;
+
+	default:
+		clkRate = 0;
+	}
+
+	return clkRate;
+}
+
+/* Return System PLL output clock rate */
+uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
+{
+	return Chip_Clock_GetPLLFreq(LPC_SYSCTL->SYSPLLCTRL,
+								 Chip_Clock_GetSystemPLLInClockRate());
+}
+
+/* Return USB PLL input clock rate */
+uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
+{
+	uint32_t clkRate;
+
+	switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
+	case SYSCTL_PLLCLKSRC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCTL_PLLCLKSRC_SYSOSC:
+		clkRate = Chip_Clock_GetMainOscRate();
+		break;
+
+	default:
+		clkRate = 0;
+	}
+
+	return clkRate;
+}
+
+/* Return USB PLL output clock rate */
+uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
+{
+	return Chip_Clock_GetPLLFreq(LPC_SYSCTL->USBPLLCTRL,
+								 Chip_Clock_GetUSBPLLInClockRate());
+}
+
+/* Return main clock rate */
+uint32_t Chip_Clock_GetMainClockRate(void)
+{
+	uint32_t clkRate = 0;
+
+	switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
+	case SYSCTL_MAINCLKSRC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCTL_MAINCLKSRC_PLLIN:
+		clkRate = Chip_Clock_GetSystemPLLInClockRate();
+		break;
+
+	case SYSCTL_MAINCLKSRC_WDTOSC:
+		clkRate = Chip_Clock_GetWDTOSCRate();
+		break;
+
+	case SYSCTL_MAINCLKSRC_PLLOUT:
+		clkRate = Chip_Clock_GetSystemPLLOutClockRate();
+		break;
+	}
+
+	return clkRate;
+}
+
+/* Return system clock rate */
+uint32_t Chip_Clock_GetSystemClockRate(void)
+{
+	/* No point in checking for divide by 0 */
+	return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/flash_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/flash_13xx.c
new file mode 100644
index 000000000..7449a4554
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/flash_13xx.c
@@ -0,0 +1,82 @@
+/*
+ * @brief LPC13xx Flash/EEPROM programming driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/*Read Part Identification number*/
+void Chip_FLASH_ReadPartID(FLASH_READ_PART_ID_OUTPUT_T *pOutput)
+{
+	FLASH_READ_PART_ID_COMMAND_T command;
+	command.cmd = FLASH_READ_PART_ID;
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/*Read Boot code version number */
+void Chip_FLASH_ReadBootCodeVersion(FLASH_READ_BOOTCODE_VER_OUTPUT_T *pOutput)
+{
+	FLASH_READ_BOOTCODE_VER_COMMAND_T command;
+	command.cmd = FLASH_READ_BOOT_VER;
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) pOutput);
+}
+
+/* Reinvoke ISP */
+void Chip_FLASH_ReInvokeISP(void)
+{
+	FLASH_REINVOKE_ISP_COMMAND_T command;
+	FLASH_REINVOKE_ISP_OUTPUT_T output;
+
+	command.cmd = FLASH_REINVOKE_ISP;
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) &output);
+}
+
+/* Read UID */
+void Chip_FLASH_ReadUID(FLASH_READ_UID_OUTPUT_T *pOutput)
+{
+	FLASH_READ_UID_COMMAND_T command;
+	command.cmd = FLASH_READ_UID;
+	Chip_FLASH_Execute((FLASH_COMMAND_T *) &command, (FLASH_OUTPUT_T *) pOutput);
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c
new file mode 100644
index 000000000..367d1d366
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_1.c
@@ -0,0 +1,108 @@
+/*
+ * @brief LPC13xx GPIO chip driver for LPC13(15/16/17/45/46/47) families
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC1347)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize GPIO block */
+void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/* De-Initialize GPIO block */
+void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/* Set a GPIO direction */
+void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
+{
+	if (setting) {
+		pGPIO->DIR[port] |= 1UL << bit;
+	}
+	else {
+		pGPIO->DIR[port] &= ~(1UL << bit);
+	}
+}
+
+/* Set Direction for a GPIO port */
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
+{
+	if (out) {
+		pGPIO->DIR[portNum] |= bitValue;
+	}
+	else {
+		pGPIO->DIR[portNum] &= ~bitValue;
+	}
+}
+
+/* Set GPIO direction for a single GPIO pin */
+void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
+{
+	if (output) {
+		Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
+	}
+	else {
+		Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
+	}
+}
+
+/* Set GPIO direction for a all selected GPIO pins to an input or output */
+void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet)
+{
+	if (outSet) {
+		Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
+	}
+	else {
+		Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
+	}
+}
+
+#endif /* if defined(CHIP_LPC1347) */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_2.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_2.c
new file mode 100644
index 000000000..957a413ee
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpio_13xx_2.c
@@ -0,0 +1,140 @@
+/*
+ * @brief LPC13xx GPIO chip driver for LPC13(11/13/42/43) families
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC1343)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize GPIO block */
+void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/* De-Initialize GPIO block */
+void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/* Set GPIO direction */
+void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
+{
+	if (setting) {
+		pGPIO[port].DIR |= 1UL << bit;
+	}
+	else {
+		pGPIO[port].DIR &= ~(1UL << bit);
+	}
+}
+
+/* Set Direction for a GPIO port */
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit, uint8_t out)
+{
+	if (out) {
+		pGPIO[port].DIR |= bit;
+	}
+	else {
+		pGPIO[port].DIR &= ~bit;
+	}
+}
+
+/* Set GPIO direction for a single GPIO pin */
+void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
+{
+	if (output) {
+		Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
+	}
+	else {
+		Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
+	}
+}
+
+/* Set GPIO direction for a all selected GPIO pins to an input or output */
+void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
+{
+	if (outSet) {
+		Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
+	}
+	else {
+		Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
+	}
+}
+
+/* Composite function for setting up a full interrupt configuration for a single pin */
+void Chip_GPIO_SetupPinInt(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, GPIO_INT_MODE_T mode)
+{
+	uint32_t pinMask = (1 << pin);
+
+	/* Edge mode selected? */
+	if ((uint32_t) mode & 0x2) {
+		Chip_GPIO_SetPinModeEdge(pGPIO, port, pinMask);
+
+		/* Interrupt on both edges selected? */
+		if ((uint32_t) mode & 0x4) {
+			Chip_GPIO_SetEdgeModeBoth(pGPIO, port, pinMask);
+		}
+		else {
+			Chip_GPIO_SetEdgeModeSingle(pGPIO, port, pinMask);
+		}
+	}
+	else {
+		/* Level mode */
+		Chip_GPIO_SetPinModeLevel(pGPIO, port, pinMask);
+	}
+
+	/* Level selections will not alter 'dual edge' mode */
+	if ((uint32_t) mode & 0x1) {
+		/* High edge or level mode selected */
+		Chip_GPIO_SetModeHigh(pGPIO, port, pinMask);
+	}
+	else {
+		Chip_GPIO_SetModeLow(pGPIO, port, pinMask);
+	}
+}
+
+#endif /* if defined(CHIP_LPC1343) */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpiogroup_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpiogroup_13xx.c
new file mode 100644
index 000000000..bab202b6f
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/gpiogroup_13xx.c
@@ -0,0 +1,52 @@
+/*
+ * @brief LPC13xx GPIO group driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC1347)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+#endif /* defined(CHIP_LPC1347) */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2c_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2c_13xx.c
new file mode 100644
index 000000000..0c11daf6c
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2c_13xx.c
@@ -0,0 +1,548 @@
+/*
+ * @brief LPC13xx I2C driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Control flags */
+#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
+#define LPC_I2Cx(id)      ((i2c[id].ip))
+#define SLAVE_ACTIVE(iic) (((iic)->flags & 0xFF00) != 0)
+
+/* I2C common interface structure */
+struct i2c_interface {
+	LPC_I2C_T *ip;		/* IP base address of the I2C device */
+	CHIP_SYSCTL_CLOCK_T clk;	/* Clock used by I2C */
+	I2C_EVENTHANDLER_T mEvent;	/* Current active Master event handler */
+	I2C_EVENTHANDLER_T sEvent;	/* Slave transfer events */
+	I2C_XFER_T *mXfer;	/* Current active xfer pointer */
+	I2C_XFER_T *sXfer;	/* Pointer to store xfer when bus is busy */
+	uint32_t flags;		/* Flags used by I2C master and slave */
+};
+
+/* Slave interface structure */
+struct i2c_slave_interface {
+	I2C_XFER_T *xfer;
+	I2C_EVENTHANDLER_T event;
+};
+
+/* I2C interfaces */
+static struct i2c_interface i2c[I2C_NUM_INTERFACE] = {
+	{LPC_I2C, SYSCTL_CLOCK_I2C, Chip_I2C_EventHandler, NULL, NULL, NULL, 0}
+};
+
+static struct i2c_slave_interface i2c_slave[I2C_NUM_INTERFACE][I2C_SLAVE_NUM_INTERFACE];
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+STATIC INLINE void enableClk(I2C_ID_T id)
+{
+    Chip_Clock_EnablePeriphClock(i2c[id].clk);
+}
+
+STATIC INLINE void disableClk(I2C_ID_T id)
+{
+    Chip_Clock_DisablePeriphClock(i2c[id].clk);
+}
+
+/* Get the ADC Clock Rate */
+STATIC INLINE uint32_t getClkRate(I2C_ID_T id)
+{
+	return Chip_Clock_GetSystemClockRate();
+}
+
+/* Enable I2C and start master transfer */
+STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C)
+{
+	/* Reset STA, STO, SI */
+	pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
+
+	/* Enter to Master Transmitter mode */
+	pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
+}
+
+/* Enable I2C and enable slave transfers */
+STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C)
+{
+	/* Reset STA, STO, SI */
+	pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
+
+	/* Enter to Master Transmitter mode */
+	pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
+}
+
+/* Check if I2C bus is free */
+STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C)
+{
+	return !(pI2C->CONSET & I2C_CON_STO);
+}
+
+/* Get current state of the I2C peripheral */
+STATIC INLINE int getCurState(LPC_I2C_T *pI2C)
+{
+	return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
+}
+
+/* Check if the active state belongs to master mode*/
+STATIC INLINE int isMasterState(LPC_I2C_T *pI2C)
+{
+	return getCurState(pI2C) < 0x60;
+}
+
+/* Set OWN slave address for specific slave ID */
+STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
+{
+	uint32_t index = (uint32_t) sid - 1;
+	pI2C->MASK[index] = mask;
+	if (sid == I2C_SLAVE_0) {
+		pI2C->ADR0 = addr;
+	}
+	else {
+		volatile uint32_t *abase = &pI2C->ADR1;
+		abase[index - 1] = addr;
+	}
+}
+
+/* Match the slave address */
+STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask)
+{
+	mask |= 1;
+	return (addr1 & ~mask) == (addr2 & ~mask);
+}
+
+/* Get the index of the active slave */
+STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr)
+{
+	if (!(slaveAddr >> 1)) {
+		return I2C_SLAVE_GENERAL;					/* General call address */
+	}
+	if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) {
+		return I2C_SLAVE_0;
+	}
+	if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) {
+		return I2C_SLAVE_1;
+	}
+	if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) {
+		return I2C_SLAVE_2;
+	}
+	if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) {
+		return I2C_SLAVE_3;
+	}
+
+	/* If everything is fine the code should never come here */
+	return I2C_SLAVE_GENERAL;
+}
+
+/* Master transfer state change handler handler */
+int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T  *xfer)
+{
+	uint32_t cclr = I2C_CON_FLAGS;
+
+	switch (getCurState(pI2C)) {
+	case 0x08:		/* Start condition on bus */
+	case 0x10:		/* Repeated start condition */
+		pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
+		break;
+
+	/* Tx handling */
+	case 0x18:		/* SLA+W sent and ACK received */
+	case 0x28:		/* DATA sent and ACK received */
+		if (!xfer->txSz) {
+			cclr &= ~(xfer->rxSz ? I2C_CON_STA : I2C_CON_STO);
+		}
+		else {
+			pI2C->DAT = *xfer->txBuff++;
+			xfer->txSz--;
+		}
+		break;
+
+	/* Rx handling */
+	case 0x58:		/* Data Received and NACK sent */
+		cclr &= ~I2C_CON_STO;
+
+	case 0x50:		/* Data Received and ACK sent */
+		*xfer->rxBuff++ = pI2C->DAT;
+		xfer->rxSz--;
+
+	case 0x40:		/* SLA+R sent and ACK received */
+		if (xfer->rxSz > 1) {
+			cclr &= ~I2C_CON_AA;
+		}
+		break;
+
+	/* NAK Handling */
+	case 0x20:		/* SLA+W sent NAK received */
+	case 0x30:		/* DATA sent NAK received */
+	case 0x48:		/* SLA+R sent NAK received */
+		xfer->status = I2C_STATUS_NAK;
+		cclr &= ~I2C_CON_STO;
+		break;
+
+	case 0x38:		/* Arbitration lost */
+		xfer->status = I2C_STATUS_ARBLOST;
+		break;
+
+	/* Bus Error */
+	case 0x00:
+		xfer->status = I2C_STATUS_BUSERR;
+		cclr &= ~I2C_CON_STO;
+	}
+
+	/* Set clear control flags */
+	pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
+	pI2C->CONCLR = cclr;
+
+	/* If stopped return 0 */
+	if (!(cclr & I2C_CON_STO) || (xfer->status == I2C_STATUS_ARBLOST)) {
+		if (xfer->status == I2C_STATUS_BUSY) {
+			xfer->status = I2C_STATUS_DONE;
+		}
+		return 0;
+	}
+	return 1;
+}
+
+/* Find the slave address of SLA+W or SLA+R */
+I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C)
+{
+	switch (getCurState(pI2C)) {
+	case 0x60:
+	case 0x68:
+	case 0x70:
+	case 0x78:
+	case 0xA8:
+	case 0xB0:
+		return lookupSlaveIndex(pI2C, pI2C->DAT);
+	}
+
+	/* If everything is fine code should never come here */
+	return I2C_SLAVE_GENERAL;
+}
+
+/* Slave state machine handler */
+int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
+{
+	uint32_t cclr = I2C_CON_FLAGS;
+	int ret = RET_SLAVE_BUSY;
+
+	xfer->status = I2C_STATUS_BUSY;
+	switch (getCurState(pI2C)) {
+	case 0x80:		/* SLA: Data received + ACK sent */
+	case 0x90:		/* GC: Data received + ACK sent */
+		*xfer->rxBuff++ = pI2C->DAT;
+		xfer->rxSz--;
+		ret = RET_SLAVE_RX;
+		if (xfer->rxSz > 1) {
+			cclr &= ~I2C_CON_AA;
+		}
+		break;
+
+	case 0x60:		/* Own SLA+W received */
+	case 0x68:		/* Own SLA+W received after losing arbitration */
+	case 0x70:		/* GC+W received */
+	case 0x78:		/* GC+W received after losing arbitration */
+		xfer->slaveAddr = pI2C->DAT & ~1;
+		if (xfer->rxSz > 1) {
+			cclr &= ~I2C_CON_AA;
+		}
+		break;
+
+	case 0xA8:		/* SLA+R received */
+	case 0xB0:		/* SLA+R received after losing arbitration */
+		xfer->slaveAddr = pI2C->DAT & ~1;
+
+	case 0xB8:		/* DATA sent and ACK received */
+		pI2C->DAT = *xfer->txBuff++;
+		xfer->txSz--;
+		if (xfer->txSz > 0) {
+			cclr &= ~I2C_CON_AA;
+		}
+		ret = RET_SLAVE_TX;
+		break;
+
+	case 0xC0:		/* Data transmitted and NAK received */
+	case 0xC8:		/* Last data transmitted and ACK received */
+	case 0x88:		/* SLA: Data received + NAK sent */
+	case 0x98:		/* GC: Data received + NAK sent */
+	case 0xA0:		/* STOP/Repeated START condition received */
+		ret = RET_SLAVE_IDLE;
+		cclr &= ~I2C_CON_AA;
+		xfer->status = I2C_STATUS_DONE;
+		if (xfer->slaveAddr & 1) {
+			cclr &= ~I2C_CON_STA;
+		}
+		break;
+	}
+
+	/* Set clear control flags */
+	pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
+	pI2C->CONCLR = cclr;
+
+	return ret;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+/* Chip event handler interrupt based */
+void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event)
+{
+	struct i2c_interface *iic = &i2c[id];
+	volatile I2C_STATUS_T *stat;
+
+	/* Only WAIT event needs to be handled */
+	if (event != I2C_EVENT_WAIT) {
+		return;
+	}
+
+	stat = &iic->mXfer->status;
+	/* Wait for the status to change */
+	while (*stat == I2C_STATUS_BUSY) {}
+}
+
+/* Chip polling event handler */
+void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event)
+{
+	struct i2c_interface *iic = &i2c[id];
+	volatile I2C_STATUS_T *stat;
+
+	/* Only WAIT event needs to be handled */
+	if (event != I2C_EVENT_WAIT) {
+		return;
+	}
+
+	stat = &iic->mXfer->status;
+	/* Call the state change handler till xfer is done */
+	while (*stat == I2C_STATUS_BUSY) {
+		if (Chip_I2C_IsStateChanged(id)) {
+			Chip_I2C_MasterStateHandler(id);
+		}
+	}
+}
+
+/* Initializes the LPC_I2C peripheral with specified parameter */
+void Chip_I2C_Init(I2C_ID_T id)
+{
+	enableClk(id);
+
+	/* Set I2C operation to default */
+	LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
+}
+
+/* De-initializes the I2C peripheral registers to their default reset values */
+void Chip_I2C_DeInit(I2C_ID_T id)
+{
+	/* Disable I2C control */
+	LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
+
+	disableClk(id);
+}
+
+/* Set up clock rate for LPC_I2C peripheral */
+void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate)
+{
+	uint32_t SCLValue;
+
+	SCLValue = (getClkRate(id) / clockrate);
+	LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1);
+	LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH);
+}
+
+/* Get current clock rate for LPC_I2C peripheral */
+uint32_t Chip_I2C_GetClockRate(I2C_ID_T id)
+{
+	return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL);
+}
+
+/* Set the master event handler */
+int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event)
+{
+	struct i2c_interface *iic = &i2c[id];
+	if (!iic->mXfer) {
+		iic->mEvent = event;
+	}
+	return iic->mEvent == event;
+}
+
+/* Get the master event handler */
+I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id)
+{
+	return i2c[id].mEvent;
+}
+
+/* Transmit and Receive data in master mode */
+int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer)
+{
+	struct i2c_interface *iic = &i2c[id];
+
+	iic->mEvent(id, I2C_EVENT_LOCK);
+	xfer->status = I2C_STATUS_BUSY;
+	iic->mXfer = xfer;
+
+	/* If slave xfer not in progress */
+	if (!iic->sXfer) {
+		startMasterXfer(iic->ip);
+	}
+	iic->mEvent(id, I2C_EVENT_WAIT);
+	iic->mXfer = 0;
+
+	/* Wait for stop condition to appear on bus */
+	while (!isI2CBusFree(iic->ip)) {}
+
+	/* Start slave if one is active */
+	if (SLAVE_ACTIVE(iic)) {
+		startSlaverXfer(iic->ip);
+	}
+
+	iic->mEvent(id, I2C_EVENT_UNLOCK);
+	return (int) xfer->status;
+}
+
+/* Master tx only */
+int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len)
+{
+	I2C_XFER_T xfer = {0};
+	xfer.slaveAddr = slaveAddr;
+	xfer.txBuff = buff;
+	xfer.txSz = len;
+	while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
+	return len - xfer.txSz;
+}
+
+/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
+ * This function is useful for communicating with the I2C slave registers
+ */
+int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len)
+{
+	I2C_XFER_T xfer = {0};
+	xfer.slaveAddr = slaveAddr;
+	xfer.txBuff = &cmd;
+	xfer.txSz = 1;
+	xfer.rxBuff = buff;
+	xfer.rxSz = len;
+	while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
+	return len - xfer.rxSz;
+}
+
+/* Sequential master read */
+int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len)
+{
+	I2C_XFER_T xfer = {0};
+	xfer.slaveAddr = slaveAddr;
+	xfer.rxBuff = buff;
+	xfer.rxSz = len;
+	while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
+	return len - xfer.rxSz;
+}
+
+/* Check if master state is active */
+int Chip_I2C_IsMasterActive(I2C_ID_T id)
+{
+	return isMasterState(i2c[id].ip);
+}
+
+/* State change handler for master transfer */
+void Chip_I2C_MasterStateHandler(I2C_ID_T id)
+{
+	if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) {
+		i2c[id].mEvent(id, I2C_EVENT_DONE);
+	}
+}
+
+/* Setup slave function */
+void Chip_I2C_SlaveSetup(I2C_ID_T id,
+						 I2C_SLAVE_ID sid,
+						 I2C_XFER_T *xfer,
+						 I2C_EVENTHANDLER_T event,
+						 uint8_t addrMask)
+{
+	struct i2c_interface *iic = &i2c[id];
+	struct i2c_slave_interface *si2c = &i2c_slave[id][sid];
+	si2c->xfer = xfer;
+	si2c->event = event;
+
+	/* Set up the slave address */
+	if (sid != I2C_SLAVE_GENERAL) {
+		setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask);
+	}
+
+	if (!SLAVE_ACTIVE(iic) && !iic->mXfer) {
+		startSlaverXfer(iic->ip);
+	}
+	iic->flags |= 1 << (sid + 8);
+}
+
+/* I2C Slave event handler */
+void Chip_I2C_SlaveStateHandler(I2C_ID_T id)
+{
+	int ret;
+	struct i2c_interface *iic = &i2c[id];
+
+	/* Get the currently addressed slave */
+	if (!iic->sXfer) {
+		struct i2c_slave_interface *si2c;
+
+		I2C_SLAVE_ID sid = getSlaveIndex(iic->ip);
+		si2c = &i2c_slave[id][sid];
+		iic->sXfer = si2c->xfer;
+		iic->sEvent = si2c->event;
+	}
+
+	iic->sXfer->slaveAddr |= iic->mXfer != 0;
+	ret = handleSlaveXferState(iic->ip, iic->sXfer);
+	if (ret) {
+		if (iic->sXfer->status == I2C_STATUS_DONE) {
+			iic->sXfer = 0;
+		}
+		iic->sEvent(id, (I2C_EVENT_T) ret);
+	}
+}
+
+/* Disable I2C device */
+void Chip_I2C_Disable(I2C_ID_T id)
+{
+	LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC;
+}
+
+/* State change checking */
+int Chip_I2C_IsStateChanged(I2C_ID_T id)
+{
+	return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0;
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2cm_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2cm_13xx.c
new file mode 100644
index 000000000..2c0cd8d49
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/i2cm_13xx.c
@@ -0,0 +1,259 @@
+/*
+ * @brief LPC13xx I2C master driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Control flags */
+#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the LPC_I2C peripheral with specified parameter */
+void Chip_I2CM_Init(LPC_I2C_T *pI2C)
+{
+	/* Enable I2C clock */
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2C);
+
+	/* Peripheral reset control to I2C */
+	Chip_SYSCTL_PeriphReset(RESET_I2C0);
+}
+
+/* De-initializes the I2C peripheral registers to their default reset values */
+void Chip_I2CM_DeInit(LPC_I2C_T *pI2C)
+{
+	/* Disable I2C clock */
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_I2C);
+}
+
+/* Set up bus speed for LPC_I2C interface */
+void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed)
+{
+	uint32_t clockDiv = (Chip_Clock_GetMainClockRate() / busSpeed);
+
+	Chip_I2CM_SetDutyCycle(pI2C, (clockDiv >> 1), (clockDiv - (clockDiv >> 1)));
+}
+
+/* Master transfer state change handler handler */
+uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
+{
+	uint32_t cclr = I2C_CON_FLAGS;
+
+	switch (Chip_I2CM_GetCurState(pI2C)) {
+	case 0x08:		/* Start condition on bus */
+	case 0x10:		/* Repeated start condition */
+		pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
+		break;
+
+	/* Tx handling */
+	case 0x20:		/* SLA+W sent NAK received */
+	case 0x30:		/* DATA sent NAK received */
+		if ((xfer->options & I2CM_XFER_OPTION_IGNORE_NACK) == 0) {
+			xfer->status = I2CM_STATUS_NAK;
+			cclr &= ~I2C_CON_STO;
+			break;
+		}
+
+	case 0x18:		/* SLA+W sent and ACK received */
+	case 0x28:		/* DATA sent and ACK received */
+		if (!xfer->txSz) {
+			if (xfer->rxSz) {
+				cclr &= ~I2C_CON_STA;
+			}
+			else {
+				xfer->status = I2CM_STATUS_OK;
+				cclr &= ~I2C_CON_STO;
+			}
+
+		}
+		else {
+			pI2C->DAT = *xfer->txBuff++;
+			xfer->txSz--;
+		}
+		break;
+
+	/* Rx handling */
+	case 0x58:		/* Data Received and NACK sent */
+	case 0x50:		/* Data Received and ACK sent */
+		*xfer->rxBuff++ = pI2C->DAT;
+		xfer->rxSz--;
+
+	case 0x40:		/* SLA+R sent and ACK received */
+		if ((xfer->rxSz > 1) || (xfer->options & I2CM_XFER_OPTION_LAST_RX_ACK)) {
+			cclr &= ~I2C_CON_AA;
+		}
+		if (xfer->rxSz == 0) {
+			xfer->status = I2CM_STATUS_OK;
+			cclr &= ~I2C_CON_STO;
+		}
+		break;
+
+	/* NAK Handling */
+	case 0x48:		/* SLA+R sent NAK received */
+		xfer->status = I2CM_STATUS_SLAVE_NAK;
+		cclr &= ~I2C_CON_STO;
+		break;
+
+	case 0x38:		/* Arbitration lost */
+		xfer->status = I2CM_STATUS_ARBLOST;
+		break;
+
+	case 0x00:		/* Bus Error */
+		xfer->status = I2CM_STATUS_BUS_ERROR;
+		cclr &= ~I2C_CON_STO;
+		break;
+
+	default:
+		xfer->status = I2CM_STATUS_ERROR;
+		cclr &= ~I2C_CON_STO;
+		break;
+	}
+
+	/* Set clear control flags */
+	pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
+	pI2C->CONCLR = cclr;
+
+	return xfer->status != I2CM_STATUS_BUSY;
+}
+
+/* Transmit and Receive data in master mode */
+void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
+{
+	/* set the transfer status as busy */
+	xfer->status = I2CM_STATUS_BUSY;
+	/* Clear controller state. */
+	Chip_I2CM_ResetControl(pI2C);
+	/* Enter to Master Transmitter mode */
+	Chip_I2CM_SendStart(pI2C);
+}
+
+/* Transmit and Receive data in master mode */
+uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
+{
+	uint32_t ret = 0;
+	/* start transfer */
+	Chip_I2CM_Xfer(pI2C, xfer);
+
+	while (ret == 0) {
+		/* wait for status change interrupt */
+		while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
+		/* call state change handler */
+		ret = Chip_I2CM_XferHandler(pI2C, xfer);
+	}
+	return ret;
+}
+
+/* Master tx only */
+uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len)
+{
+	uint32_t txLen = 0, err = 0;
+
+	/* clear state change interrupt status */
+	Chip_I2CM_ClearSI(pI2C);
+	/* generate START condition */
+	Chip_I2CM_SendStart(pI2C);
+
+	while ((txLen < len) && (err == 0)) {
+		/* wait for status change interrupt */
+		while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
+
+		/* check status and send data */
+		switch (Chip_I2CM_GetCurState(pI2C)) {
+		case 0x08:		/* Start condition on bus */
+		case 0x10:		/* Repeated start condition */
+		case 0x18:		/* SLA+W sent and ACK received */
+		case 0x28:		/* DATA sent and ACK received */
+			Chip_I2CM_WriteByte(pI2C, buff[txLen++]);
+			break;
+
+		case 0x38:		/* Arbitration lost */
+			break;
+
+		default:		/* we shouldn't be in any other state */
+			err = 1;
+			break;
+		}
+		/* clear state change interrupt status */
+		Chip_I2CM_ClearSI(pI2C);
+	}
+
+	return txLen;
+}
+
+/* Sequential master read */
+uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len)
+{
+	uint32_t rxLen = 0, err = 0;
+
+	/* clear state change interrupt status */
+	Chip_I2CM_ClearSI(pI2C);
+	/* generate START condition and auto-ack data received */
+	pI2C->CONSET = I2C_CON_AA | I2C_CON_STA;
+
+	while ((rxLen < len) && (err == 0)) {
+		/* wait for status change interrupt */
+		while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
+
+		/* check status and send data */
+		switch (Chip_I2CM_GetCurState(pI2C)) {
+		case 0x08:		/* Start condition on bus */
+		case 0x10:		/* Repeated start condition */
+		case 0x40:		/* SLA+R sent and ACK received */
+		case 0x50:		/* Data Received and ACK sent */
+			buff[rxLen++] = Chip_I2CM_ReadByte(pI2C);
+			break;
+
+		case 0x38:		/* Arbitration lost */
+			break;
+
+		default:		/* we shouldn't be in any other state */
+			err = 1;
+			break;
+		}
+		/* clear state change interrupt status */
+		Chip_I2CM_ClearSI(pI2C);
+	}
+
+	return rxLen;
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/iocon_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/iocon_13xx.c
new file mode 100644
index 000000000..83d0eeae4
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/iocon_13xx.c
@@ -0,0 +1,59 @@
+/*
+ * @brief LPC13xx IOCON driver
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+ #if defined(CHIP_LPC1347)
+/* I/O Control pin mux */
+void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+	if (port == 0) {
+		pIOCON->PIO0[pin] = modefunc;
+	}
+	else {
+		pIOCON->PIO1[pin] = modefunc;
+	}
+}
+
+#endif
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pinint_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pinint_13xx.c
new file mode 100644
index 000000000..bc0ec6d09
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pinint_13xx.c
@@ -0,0 +1,53 @@
+/*
+ * @brief LPC11xx Pin Interrupt and Pattern Match driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC1347)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+#endif /* defined(CHIP_LPC1347) */
+
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pmu_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pmu_13xx.c
new file mode 100644
index 000000000..18205d7f6
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/pmu_13xx.c
@@ -0,0 +1,114 @@
+/*
+ * @brief LPC13xx PMU chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Enter MCU Sleep mode */
+void Chip_PMU_SleepState(LPC_PMU_T *pPMU)
+{
+	pPMU->PCON = PMU_PCON_PM_SLEEP;
+	SCB->SCR &= ~(1UL << SCB_SCR_SLEEPDEEP_Pos);
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Enter MCU Deep Sleep mode */
+void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU)
+{
+#if defined(CHIP_LPC1347)
+	pPMU->PCON = PMU_PCON_PM_DEEPSLEEP;
+#elif defined(CHIP_LPC1343)
+	pPMU->PCON = PMU_PCON_PM_SLEEP;
+#endif
+	SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Enter MCU Power down mode */
+#if defined(CHIP_LPC1347)
+void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU)
+{
+	SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
+	pPMU->PCON = PMU_PCON_PM_POWERDOWN;
+
+	/* Enter sleep mode */
+	__WFI();
+}
+#endif
+
+/* Enter MCU Deep Power down mode */
+void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU)
+{
+	SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
+	pPMU->PCON = PMU_PCON_PM_DEEPPOWERDOWN;
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Put some of the peripheral in sleep mode */
+void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode)
+{
+	if (SleepMode == PMU_MCU_DEEP_SLEEP) {
+		Chip_PMU_DeepSleepState(pPMU);
+	}
+#if defined(CHIP_LPC1347)
+	else if (SleepMode == PMU_MCU_POWER_DOWN) {
+		Chip_PMU_PowerDownState(pPMU);
+	}
+#endif
+	else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
+		Chip_PMU_DeepPowerDownState(pPMU);
+	}
+	else {
+		/* PMU_MCU_SLEEP */
+		Chip_PMU_SleepState(pPMU);
+	}
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ring_buffer.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ring_buffer.c
new file mode 100644
index 000000000..47a0c34f9
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ring_buffer.c
@@ -0,0 +1,167 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include <string.h>
+#include "ring_buffer.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define RB_INDH(rb)                ((rb)->head & ((rb)->count - 1))
+#define RB_INDT(rb)                ((rb)->tail & ((rb)->count - 1))
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize ring buffer */
+int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
+{
+	RingBuff->data = buffer;
+	RingBuff->count = count;
+	RingBuff->itemSz = itemSize;
+	RingBuff->head = RingBuff->tail = 0;
+
+	return 1;
+}
+
+/* Insert a single item into Ring Buffer */
+int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
+{
+	uint8_t *ptr = RingBuff->data;
+
+	/* We cannot insert when queue is full */
+	if (RingBuffer_IsFull(RingBuff))
+		return 0;
+
+	ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
+	memcpy(ptr, data, RingBuff->itemSz);
+	RingBuff->head++;
+
+	return 1;
+}
+
+/* Insert multiple items into Ring Buffer */
+int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num)
+{
+	uint8_t *ptr = RingBuff->data;
+	int cnt1, cnt2;
+
+	/* We cannot insert when queue is full */
+	if (RingBuffer_IsFull(RingBuff))
+		return 0;
+
+	/* Calculate the segment lengths */
+	cnt1 = cnt2 = RingBuffer_GetFree(RingBuff);
+	if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count)
+		cnt1 = RingBuff->count - RB_INDH(RingBuff);
+	cnt2 -= cnt1;
+
+	cnt1 = MIN(cnt1, num);
+	num -= cnt1;
+
+	cnt2 = MIN(cnt2, num);
+	num -= cnt2;
+
+	/* Write segment 1 */
+	ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
+	memcpy(ptr, data, cnt1 * RingBuff->itemSz);
+	RingBuff->head += cnt1;
+
+	/* Write segment 2 */
+	ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz;
+	data = (const uint8_t *) data + cnt1 * RingBuff->itemSz;
+	memcpy(ptr, data, cnt2 * RingBuff->itemSz);
+	RingBuff->head += cnt2;
+
+	return cnt1 + cnt2;
+}
+
+/* Pop single item from Ring Buffer */
+int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
+{
+	uint8_t *ptr = RingBuff->data;
+
+	/* We cannot pop when queue is empty */
+	if (RingBuffer_IsEmpty(RingBuff))
+		return 0;
+
+	ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
+	memcpy(data, ptr, RingBuff->itemSz);
+	RingBuff->tail++;
+
+	return 1;
+}
+
+/* Pop multiple items from Ring buffer */
+int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num)
+{
+	uint8_t *ptr = RingBuff->data;
+	int cnt1, cnt2;
+
+	/* We cannot insert when queue is empty */
+	if (RingBuffer_IsEmpty(RingBuff))
+		return 0;
+
+	/* Calculate the segment lengths */
+	cnt1 = cnt2 = RingBuffer_GetCount(RingBuff);
+	if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count)
+		cnt1 = RingBuff->count - RB_INDT(RingBuff);
+	cnt2 -= cnt1;
+
+	cnt1 = MIN(cnt1, num);
+	num -= cnt1;
+
+	cnt2 = MIN(cnt2, num);
+	num -= cnt2;
+
+	/* Write segment 1 */
+	ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
+	memcpy(data, ptr, cnt1 * RingBuff->itemSz);
+	RingBuff->tail += cnt1;
+
+	/* Write segment 2 */
+	ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz;
+	data = (uint8_t *) data + cnt1 * RingBuff->itemSz;
+	memcpy(data, ptr, cnt2 * RingBuff->itemSz);
+	RingBuff->tail += cnt2;
+
+	return cnt1 + cnt2;
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ritimer_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ritimer_13xx.c
new file mode 100644
index 000000000..8b6f1e6ad
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ritimer_13xx.c
@@ -0,0 +1,99 @@
+/*
+ * @brief LPC13xx RITimer chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC1347)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the RIT */
+void Chip_RIT_Init(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->COMPVAL = 0xFFFFFFFF;
+	pRITimer->MASK  = 0x00000000;
+	pRITimer->CTRL  = 0x0C;
+	pRITimer->COUNTER   = 0x00000000;
+	pRITimer->COMPVAL_H = 0x0;
+}
+
+/* DeInitialize the RIT */
+void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer)
+{
+	Chip_RIT_Init(pRITimer);
+}
+
+/* Set timer interval value */
+void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval)
+{
+	uint32_t cmp_value;
+
+	/* Determine aapproximate compare value based on clock rate and passed interval */
+	cmp_value = (Chip_Clock_GetSystemClockRate() / 1000) * time_interval;
+
+	/* Set timer compare value */
+	Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
+
+	/* Set timer enable clear bit to clear timer to 0 whenever
+	   counter value equals the contents of RICOMPVAL */
+	Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR);
+}
+
+/* Check whether interrupt is pending */
+IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)
+{
+	uint8_t result;
+
+	if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) {
+		result = SET;
+	}
+	else {
+		return RESET;
+	}
+
+	return (IntStatus) result;
+}
+
+#endif /* defined(CHIP_LPC1347) */
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ssp_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ssp_13xx.c
new file mode 100644
index 000000000..266f5a9bd
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/ssp_13xx.c
@@ -0,0 +1,496 @@
+/*
+ * @brief LPC13xx SSP Registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	if (xf_setup->tx_data) {
+		Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data +
+												 xf_setup->tx_cnt)));
+	}
+	else {
+		Chip_SSP_SendFrame(pSSP, 0xFFFF);
+	}
+
+	xf_setup->tx_cnt += 2;
+}
+
+/** SSP macro: write 1 bytes to FIFO buffer */
+STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	if (xf_setup->tx_data) {
+		Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
+	}
+	else {
+		Chip_SSP_SendFrame(pSSP, 0xFF);
+	}
+
+	xf_setup->tx_cnt++;
+}
+
+/** SSP macro: read 1 bytes from FIFO buffer */
+STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	uint16_t rDat;
+
+	while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
+		   (xf_setup->rx_cnt < xf_setup->length)) {
+		rDat = Chip_SSP_ReceiveFrame(pSSP);
+		if (xf_setup->rx_data) {
+			*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
+		}
+
+		xf_setup->rx_cnt += 2;
+	}
+}
+
+/** SSP macro: read 2 bytes from FIFO buffer */
+STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	uint16_t rDat;
+
+	while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
+		   (xf_setup->rx_cnt < xf_setup->length)) {
+		rDat = Chip_SSP_ReceiveFrame(pSSP);
+		if (xf_setup->rx_data) {
+			*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
+		}
+
+		xf_setup->rx_cnt++;
+	}
+}
+
+/* Returns clock for the peripheral block */
+STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
+{
+	CHIP_SYSCTL_CLOCK_T clkSSP;
+
+	if (pSSP == LPC_SSP0) {
+		clkSSP = SYSCTL_CLOCK_SSP0;
+	}
+	else {
+		clkSSP = SYSCTL_CLOCK_SSP1;
+	}
+		
+	return clkSSP;
+}
+
+/* Returns reset ID for the peripheral block */
+STATIC CHIP_SYSCTL_PERIPH_RESET_T Chip_SSP_GetResetIndex(LPC_SSP_T *pSSP)
+{
+	CHIP_SYSCTL_PERIPH_RESET_T resetSSP;
+
+	if (pSSP == LPC_SSP0) {
+		resetSSP = RESET_SSP0;
+	}
+	else {
+		resetSSP = RESET_SSP1;
+	}
+
+	return resetSSP;
+}
+
+/* Returns reset ID for the peripheral block */
+STATIC void Chip_SSP_SetSSPClkDivider(LPC_SSP_T *pSSP, uint32_t div)
+{
+	if (pSSP == LPC_SSP0) {
+		Chip_Clock_SetSSP0ClockDiv(div);
+	}
+	else {
+		Chip_Clock_SetSSP1ClockDiv(div);
+	}
+}
+
+/* Returns SSP peripheral clock for the peripheral block */
+STATIC uint32_t Chip_SSP_GetPCLKkRate(LPC_SSP_T *pSSP)
+{
+	uint32_t sspCLK = Chip_Clock_GetMainClockRate();
+
+	if (pSSP == LPC_SSP0) {
+		sspCLK /= Chip_Clock_GetSSP0ClockDiv();
+	}
+	else {
+		sspCLK /= Chip_Clock_GetSSP1ClockDiv();
+	}
+
+    return sspCLK;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/*Set up output clocks per bit for SSP bus*/
+void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
+{
+	uint32_t temp;
+	temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
+	pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
+	pSSP->CPSR = prescale;
+}
+
+/* SSP Polling Read/Write in blocking mode */
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
+			/* write data to buffer */
+			if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
+				SSP_Write2BFifo(pSSP, xf_setup);
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			SSP_Read2BFifo(pSSP, xf_setup);
+		}
+	}
+	else {
+		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
+			/* write data to buffer */
+			if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
+				SSP_Write1BFifo(pSSP, xf_setup);
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			SSP_Read1BFifo(pSSP, xf_setup);
+		}
+	}
+	if (xf_setup->tx_data) {
+		return xf_setup->tx_cnt;
+	}
+	else if (xf_setup->rx_data) {
+		return xf_setup->rx_cnt;
+	}
+
+	return 0;
+}
+
+/* SSP Polling Write in blocking mode */
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
+{
+	uint32_t tx_cnt = 0, rx_cnt = 0;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		uint16_t *wdata16;
+
+		wdata16 = (uint16_t *) buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, *wdata16);
+				wdata16++;
+				tx_cnt += 2;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
+				Chip_SSP_ReceiveFrame(pSSP);	/* read dummy data */
+				rx_cnt += 2;
+			}
+		}
+	}
+	else {
+		uint8_t *wdata8;
+
+		wdata8 = buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, *wdata8);
+				wdata8++;
+				tx_cnt++;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				Chip_SSP_ReceiveFrame(pSSP);	/* read dummy data */
+				rx_cnt++;
+			}
+		}
+	}
+
+	return tx_cnt;
+
+}
+
+/* SSP Polling Read in blocking mode */
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
+{
+	uint32_t rx_cnt = 0, tx_cnt = 0;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		uint16_t *rdata16;
+
+		rdata16 = (uint16_t *) buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, 0xFFFF);	/* just send dummy data */
+				tx_cnt += 2;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
+				rdata16++;
+				rx_cnt += 2;
+			}
+		}
+	}
+	else {
+		uint8_t *rdata8;
+
+		rdata8 = buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, 0xFF);	/* just send dummy data		 */
+				tx_cnt++;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
+				rdata8++;
+				rx_cnt++;
+			}
+		}
+	}
+
+	return rx_cnt;
+
+}
+
+/* Clean all data in RX FIFO of SSP */
+void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
+{
+	if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
+		while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
+	}
+
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+}
+
+/* SSP Interrupt Read/Write with 8-bit frame width */
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	/* Check overrun error in RIS register */
+	if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+		return ERROR;
+	}
+
+	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
+		/* check if RX FIFO contains data */
+		SSP_Read1BFifo(pSSP, xf_setup);
+
+		while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
+			/* Write data to buffer */
+			SSP_Write1BFifo(pSSP, xf_setup);
+
+			/* Check overrun error in RIS register */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/*  Check for any data available in RX FIFO */
+			SSP_Read1BFifo(pSSP, xf_setup);
+		}
+
+		return SUCCESS;
+	}
+
+	return ERROR;
+}
+
+/* SSP Interrupt Read/Write with 16-bit frame width */
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	/* Check overrun error in RIS register */
+	if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+		return ERROR;
+	}
+
+	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
+		/* check if RX FIFO contains data */
+		SSP_Read2BFifo(pSSP, xf_setup);
+
+		while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
+			/* Write data to buffer */
+			SSP_Write2BFifo(pSSP, xf_setup);
+
+			/* Check overrun error in RIS register */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/*  Check for any data available in RX FIFO			 */
+			SSP_Read2BFifo(pSSP, xf_setup);
+		}
+
+		return SUCCESS;
+	}
+
+	return ERROR;
+}
+
+/* Set the SSP operating modes, master or slave */
+void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
+{
+	if (master) {
+		Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
+	}
+	else {
+		Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
+	}
+}
+
+/* Set the clock frequency for SSP interface */
+void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
+{
+	uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
+
+	ssp_clk = Chip_SSP_GetPCLKkRate(pSSP);
+
+	cr0_div = 0;
+	cmp_clk = 0xFFFFFFFF;
+	prescale = 2;
+
+	while (cmp_clk > bitRate) {
+		cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
+		if (cmp_clk > bitRate) {
+			cr0_div++;
+			if (cr0_div > 0xFF) {
+				cr0_div = 0;
+				prescale += 2;
+			}
+		}
+	}
+
+	Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
+}
+
+/* Initialize the SSP */
+void Chip_SSP_Init(LPC_SSP_T *pSSP)
+{
+    Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
+    Chip_SSP_SetSSPClkDivider(pSSP, 1);
+    Chip_SYSCTL_PeriphReset(Chip_SSP_GetResetIndex(pSSP));
+
+	Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
+	Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
+	Chip_SSP_SetBitRate(pSSP, 100000);
+}
+
+/* De-initializes the SSP peripheral */
+void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
+{
+	Chip_SSP_Disable(pSSP);
+
+    Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
+    Chip_SSP_SetSSPClkDivider(pSSP, 0);
+}
+
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/stopwatch_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/stopwatch_13xx.c
new file mode 100644
index 000000000..1b76f6288
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/stopwatch_13xx.c
@@ -0,0 +1,108 @@
+/*
+ * @brief LPC13xx specific stopwatch implementation
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+#include "stopwatch.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Precompute these to optimize runtime */
+static uint32_t ticksPerSecond;
+static uint32_t ticksPerMs;
+static uint32_t ticksPerUs;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize stopwatch */
+void StopWatch_Init(void)
+{
+	/* Use timer 1. Set prescaler to divide by 8, should give ticks at 9 MHz.
+	   That gives a useable stopwatch measurement range of about 8 minutes
+	   (if system clock is running at 72 MHz). */
+	const uint32_t prescaleDivisor = 8;
+	Chip_TIMER_Init(LPC_TIMER32_1);
+	Chip_TIMER_PrescaleSet(LPC_TIMER32_1, prescaleDivisor - 1);
+	Chip_TIMER_Enable(LPC_TIMER32_1);
+
+	/* Pre-compute tick rate. */
+	ticksPerSecond = Chip_Clock_GetSystemClockRate() / prescaleDivisor;
+	ticksPerMs = ticksPerSecond / 1000;
+	ticksPerUs = ticksPerSecond / 1000000;
+}
+
+/* Start a stopwatch */
+uint32_t StopWatch_Start(void)
+{
+	/* Return the current timer count. */
+	return Chip_TIMER_ReadCount(LPC_TIMER32_1);
+}
+
+/* Returns number of ticks per second of the stopwatch timer */
+uint32_t StopWatch_TicksPerSecond(void)
+{
+	return ticksPerSecond;
+}
+
+/* Converts from stopwatch ticks to mS. */
+uint32_t StopWatch_TicksToMs(uint32_t ticks)
+{
+	return ticks / ticksPerMs;
+}
+
+/* Converts from stopwatch ticks to uS. */
+uint32_t StopWatch_TicksToUs(uint32_t ticks)
+{
+	return ticks / ticksPerUs;
+}
+
+/* Converts from mS to stopwatch ticks. */
+uint32_t StopWatch_MsToTicks(uint32_t mS)
+{
+	return mS * ticksPerMs;
+}
+
+/* Converts from uS to stopwatch ticks. */
+uint32_t StopWatch_UsToTicks(uint32_t uS)
+{
+	return uS * ticksPerUs;
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c
new file mode 100644
index 000000000..7d657502d
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysctl_13xx.c
@@ -0,0 +1,110 @@
+/*
+ * @brief LPC13xx System Control functions
+ *
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* PDSLEEPCFG register mask */
+#if defined(CHIP_LPC1343)
+#if defined(CHIP_LPC1300L)
+#define PDSLEEPUSEMASK 0x000018B7	/* For CHIP_LPC1300L only */
+#else
+#define PDSLEEPUSEMASK 0x00000FB7
+#endif /* defined (CHIP_LPC1300L) */
+#else
+#define PDSLEEPUSEMASK 0x00000007
+#endif /* defined(CHIP_LPC1343) */
+#define PDSLEEPMASKTMP (SYSCTL_DEEPSLP_BOD_PD | SYSCTL_DEEPSLP_WDTOSC_PD)
+#define PDSLEEPMASK ((PDSLEEPUSEMASK) &~(PDSLEEPMASKTMP))
+
+/* PDWAKECFG register mask */
+#if defined(CHIP_LPC1347)
+#define PDWAKEUPUSEMASK 0x00000800
+#else
+#define PDWAKEUPUSEMASK 0x0000F800
+#endif
+#define PDWAKEUPMASKTMP 0x000005FF
+
+/* PDRUNCFG register mask */
+#if defined(CHIP_LPC1347)
+#define PDRUNCFGUSEMASK 0x0000E800
+#else
+#define PDRUNCFGUSEMASK 0x0000F800
+#endif
+#define PDRUNCFGMASKTMP 0x000005FF
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Setup deep sleep behaviour for power down */
+void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask)
+{
+	/* Update new value */
+	LPC_SYSCTL->PDSLEEPCFG = PDSLEEPMASK | (sleepmask & PDSLEEPMASKTMP);
+}
+
+/* Setup wakeup behaviour from deep sleep */
+void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask)
+{
+	/* Update new value */
+	LPC_SYSCTL->PDWAKECFG = PDWAKEUPUSEMASK | (wakeupmask & PDWAKEUPMASKTMP);
+}
+
+/* Power down one or more blocks or peripherals */
+void Chip_SYSCTL_PowerDown(uint32_t powerdownmask)
+{
+	uint32_t pdrun;
+
+	pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
+	pdrun |= (powerdownmask & PDRUNCFGMASKTMP);
+
+	LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
+}
+
+/* Power up one or more blocks or peripherals */
+void Chip_SYSCTL_PowerUp(uint32_t powerupmask)
+{
+	uint32_t pdrun;
+
+	pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
+	pdrun &= ~(powerupmask & PDRUNCFGMASKTMP);
+
+	LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c
new file mode 100644
index 000000000..b3247bf46
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/sysinit_13xx.c
@@ -0,0 +1,132 @@
+/*
+ * @brief LPC13xx Chip specific SystemInit
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Setup system clocking */
+void Chip_SetupXtalClocking(void)
+{
+	volatile int i;
+
+	/* Powerup main oscillator */
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
+
+	/* Wait an estimated 200us for OSC to be stablized, no status
+	indication, dummy wait */
+	for (i = 0; i < 0x200; i++) {}
+
+	/* Set system PLL input to main oscillator */
+	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_SYSOSC);
+
+	/* Power down PLL to change the PLL divider ratio */
+	Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+	/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
+	MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
+	FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
+	FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
+	Chip_Clock_SetupSystemPLL(5, 1);
+
+	/* Powerup system PLL */
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+	/* Wait for PLL to lock */
+	while (!Chip_Clock_IsSystemPLLLocked()) {}
+
+	/* Set system clock divider to 1 */
+	Chip_Clock_SetSysClockDiv(1);
+
+	/* Setup FLASH access to 3 clocks (72MHz clock) */
+	Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
+
+	/* Set main clock source to the system PLL. This will drive 72MHz
+	for the main clock and 72MHz for the system clock */
+	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
+}
+
+/* Set up and initialize hardware prior to call to main */
+void Chip_SetupIrcClocking(void)
+{
+	/* IRC should be powered up */
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
+
+	/* Set system PLL input to main oscillator */
+	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
+
+	/* Power down PLL to change the PLL divider ratio */
+	Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+	/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
+	MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
+	FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
+	FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
+	Chip_Clock_SetupSystemPLL(5, 1);
+
+	/* Powerup system PLL */
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+	/* Wait for PLL to lock */
+	while (!Chip_Clock_IsSystemPLLLocked()) {}
+
+	/* Set system clock divider to 1 */
+	Chip_Clock_SetSysClockDiv(1);
+
+	/* Setup FLASH access to 3 clocks */
+	Chip_FMC_SetFLASHAccess(FLASHTIM_72MHZ_CPU);
+
+	/* Set main clock source to the system PLL. This will drive 48MHz
+	   for the main clock and 48MHz for the system clock */
+	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
+}
+
+/* Set up and initialize hardware prior to call to main */
+void Chip_SystemInit(void)
+{
+	/* Initial internal clocking */
+	Chip_SetupIrcClocking();
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/timer_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/timer_13xx.c
new file mode 100644
index 000000000..f03d7e227
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/timer_13xx.c
@@ -0,0 +1,115 @@
+/*
+ * @brief LPC13xx 16/32-bit Timer/PWM control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Returns clock index for a specific timer referenced by IP block address */
+STATIC CHIP_SYSCTL_CLOCK_T Chip_TIMER_GetClock(LPC_TIMER_T *pTMR)
+{
+  CHIP_SYSCTL_CLOCK_T tmrClk;
+  if (pTMR == LPC_TIMER32_1) {
+	  tmrClk = SYSCTL_CLOCK_CT32B1;
+  }
+  else if (pTMR == LPC_TIMER16_0) {
+	  tmrClk = SYSCTL_CLOCK_CT16B0;
+  }
+  else if (pTMR == LPC_TIMER16_1) {
+	  tmrClk = SYSCTL_CLOCK_CT16B1;
+  }
+  else {
+	  tmrClk = SYSCTL_CLOCK_CT32B0;
+  }
+
+  return tmrClk;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize a timer */
+void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
+{
+	Chip_Clock_EnablePeriphClock(Chip_TIMER_GetClock(pTMR));
+}
+
+/*	Shutdown a timer */
+void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
+{
+    Chip_Clock_DisablePeriphClock(Chip_TIMER_GetClock(pTMR));
+}
+
+/* Resets the timer terminal and prescale counts to 0 */
+void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
+{
+	uint32_t reg;
+
+	/* Disable timer, set terminal count to non-0 */
+	reg = pTMR->TCR;
+	pTMR->TCR = 0;
+	pTMR->TC = 1;
+
+	/* Reset timer counter */
+	pTMR->TCR = TIMER_RESET;
+
+	/* Wait for terminal count to clear */
+	while (pTMR->TC != 0) {}
+
+	/* Restore timer state */
+	pTMR->TCR = reg;
+}
+
+/* Sets external match control (MATn.matchnum) pin control */
+void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
+								   TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
+{
+	uint32_t mask, reg;
+
+	/* Clear bits corresponding to selected match register */
+	mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2)));
+	reg = pTMR->EMR &= ~mask;
+
+	/* Set new configuration for selected match register */
+	pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) |
+				(((uint32_t) matchState) << (4 + (matchnum * 2)));
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c
new file mode 100644
index 000000000..4a776ab3b
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/uart_13xx.c
@@ -0,0 +1,280 @@
+/*
+ * @brief LPC13xx UART chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the pUART peripheral */
+void Chip_UART_Init(LPC_USART_T *pUART)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_UART0);
+	Chip_Clock_SetUARTClockDiv(1);
+
+	/* Enable FIFOs by default, reset them */
+	Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS));
+
+	/* Default 8N1, with DLAB disabled */
+	Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS));
+
+	/* Disable fractional divider */
+	pUART->FDR = 0x10;
+}
+
+/* De-initializes the pUART peripheral */
+void Chip_UART_DeInit(LPC_USART_T *pUART)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0);
+}
+
+/* Transmit a byte array through the UART peripheral (non-blocking) */
+int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
+{
+	int sent = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	/* Send until the transmit FIFO is full or out of bytes */
+	while ((sent < numBytes) &&
+		   ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) {
+		Chip_UART_SendByte(pUART, *p8);
+		p8++;
+		sent++;
+	}
+
+	return sent;
+}
+
+/* Transmit a byte array through the UART peripheral (blocking) */
+int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes)
+{
+	int pass, sent = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	while (numBytes > 0) {
+		pass = Chip_UART_Send(pUART, p8, numBytes);
+		numBytes -= pass;
+		sent += pass;
+		p8 += pass;
+	}
+
+	return sent;
+}
+
+/* Read data through the UART peripheral (non-blocking) */
+int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
+{
+	int readBytes = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	/* Send until the transmit FIFO is full or out of bytes */
+	while ((readBytes < numBytes) &&
+		   ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) {
+		*p8 = Chip_UART_ReadByte(pUART);
+		p8++;
+		readBytes++;
+	}
+
+	return readBytes;
+}
+
+/* Read data through the UART peripheral (blocking) */
+int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes)
+{
+	int pass, readBytes = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	while (readBytes < numBytes) {
+		pass = Chip_UART_Read(pUART, p8, numBytes);
+		numBytes -= pass;
+		readBytes += pass;
+		p8 += pass;
+	}
+
+	return readBytes;
+}
+
+/* Determines and sets best dividers to get a target bit rate */
+uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
+{
+	uint32_t div, divh, divl, clkin;
+
+	/* Determine UART clock in rate without FDR */
+	clkin = Chip_Clock_GetMainClockRate();
+	div = clkin / (baudrate * 16);
+
+	/* High and low halves of the divider */
+	divh = div / 256;
+	divl = div - (divh * 256);
+
+	Chip_UART_EnableDivisorAccess(pUART);
+	Chip_UART_SetDivisorLatches(pUART, divl, divh);
+	Chip_UART_DisableDivisorAccess(pUART);
+
+	/* Fractional FDR alreadt setup for 1 in UART init */
+
+	return clkin / div;
+}
+
+/* UART receive-only interrupt handler for ring buffers */
+void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
+{
+	/* New data will be ignored if data not popped in time */
+	while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) {
+		uint8_t ch = Chip_UART_ReadByte(pUART);
+		RingBuffer_Insert(pRB, &ch);
+	}
+}
+
+/* UART transmit-only interrupt handler for ring buffers */
+void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
+{
+	uint8_t ch;
+
+	/* Fill FIFO until full or until TX ring buffer is empty */
+	while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 &&
+		   RingBuffer_Pop(pRB, &ch)) {
+		Chip_UART_SendByte(pUART, ch);
+	}
+}
+
+/* Populate a transmit ring buffer and start UART transmit */
+uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
+{
+	uint32_t ret;
+	uint8_t *p8 = (uint8_t *) data;
+
+	/* Don't let UART transmit ring buffer change in the UART IRQ handler */
+	Chip_UART_IntDisable(pUART, UART_IER_THREINT);
+
+	/* Move as much data as possible into transmit ring buffer */
+	ret = RingBuffer_InsertMult(pRB, p8, bytes);
+	Chip_UART_TXIntHandlerRB(pUART, pRB);
+
+	/* Add additional data to transmit ring buffer if possible */
+	ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
+
+	/* Enable UART transmit interrupt */
+	Chip_UART_IntEnable(pUART, UART_IER_THREINT);
+
+	return ret;
+}
+
+/* Copy data from a receive ring buffer */
+int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes)
+{
+	(void) pUART;
+
+	return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes);
+}
+
+/* UART receive/transmit interrupt handler for ring buffers */
+void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
+{
+	/* Handle transmit interrupt if enabled */
+	if (pUART->IER & UART_IER_THREINT) {
+		Chip_UART_TXIntHandlerRB(pUART, pTXRB);
+
+		/* Disable transmit interrupt if the ring buffer is empty */
+		if (RingBuffer_IsEmpty(pTXRB)) {
+			Chip_UART_IntDisable(pUART, UART_IER_THREINT);
+		}
+	}
+
+	/* Handle receive interrupt */
+	Chip_UART_RXIntHandlerRB(pUART, pRXRB);
+}
+
+/* Determines and sets best dividers to get a target baud rate */
+uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate)
+{
+	uint32_t uClk;
+    uint32_t dval, mval;
+    uint32_t dl;
+    uint32_t rate16 = 16 * baudrate;
+	uint32_t actualRate = 0;
+
+	/* Get Clock rate */
+	uClk = Chip_Clock_GetMainClockRate();
+
+    /* The fractional is calculated as (PCLK  % (16 * Baudrate)) / (16 * Baudrate)
+     * Let's make it to be the ratio DivVal / MulVal
+     */
+	dval = uClk % rate16;
+
+   /* The PCLK / (16 * Baudrate) is fractional
+    * => dval = pclk % rate16
+    * mval = rate16;
+    * now mormalize the ratio
+    * dval / mval = 1 / new_mval
+    * new_mval = mval / dval
+    * new_dval = 1
+    */
+    if (dval > 0) {
+        mval = rate16 / dval;
+        dval = 1;
+
+        /* In case mval still bigger then 4 bits
+        * no adjustment require
+        */
+        if (mval > 12) {
+         dval = 0;
+      }
+    }
+    dval &= 0xf;
+    mval &= 0xf;
+    dl = uClk / (rate16 + rate16 *dval / mval);
+
+    /* Update UART registers */
+    Chip_UART_EnableDivisorAccess(pUART);
+	Chip_UART_SetDivisorLatches(pUART, UART_LOAD_DLL(dl), UART_LOAD_DLM(dl));
+	Chip_UART_DisableDivisorAccess(pUART);
+
+	/* Set best fractional divider */
+	pUART->FDR = (UART_FDR_MULVAL(mval) | UART_FDR_DIVADDVAL(dval));
+
+	/* Return actual baud rate */
+	actualRate = uClk / (16 * dl + 16 * dl * dval / mval);
+	return actualRate;
+}
diff --git a/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/wwdt_13xx.c b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/wwdt_13xx.c
new file mode 100644
index 000000000..a57e33482
--- /dev/null
+++ b/hw/mcu/nxp/lpc13xx/lpc_chip_13xx/src/wwdt_13xx.c
@@ -0,0 +1,80 @@
+/*
+ * @brief LPC13xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the Watchdog timer */
+void Chip_WWDT_Init(LPC_WWDT_T *pWWDT)
+{
+    Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_WDT);
+
+	/* Disable watchdog */
+	pWWDT->MOD       = 0;
+	pWWDT->TC        = 0xFF;
+#if defined(WATCHDOG_WINDOW_SUPPORT)
+	pWWDT->WARNINT   = 0xFFFF;
+	pWWDT->WINDOW    = 0xFFFFFF;
+#endif
+}
+
+/* Shutdown the Watchdog timer */
+void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT)
+{
+    Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_WDT);
+}
+
+/* Clear WWDT interrupt status flags */
+void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
+{
+	if (status & WWDT_WDMOD_WDTOF) {
+		pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK;
+	}
+
+	if (status & WWDT_WDMOD_WDINT) {
+		pWWDT->MOD |= WWDT_WDMOD_WDINT;
+	}
+}
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index 83f584f05..32c336fa7 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -40,21 +40,12 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
 
-#define _TINY_USB_SOURCE_FILE_
-
 // NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
 // endpoint's max packet size and need some soft DMA helper
 
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "hal/hal.h"
-#include "osal/osal.h"
-
+#include "chip.h"
 #include "device/dcd.h"
-#include "usbd_dcd.h"
-#include "dcd_lpc_11uxx_13uxx.h"
+#include "dcd_lpc11_13_15.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -134,8 +125,6 @@ typedef struct {
     uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
   }current_td[DCD_11U_13U_QHD_COUNT];
 
-  uint8_t  class_code[DCD_11U_13U_QHD_COUNT]; ///< class where the endpoints belongs to TODO no need for control endpoints
-
 }dcd_11u_13u_data_t;
 
 //--------------------------------------------------------------------+
@@ -194,7 +183,7 @@ bool dcd_init(uint8_t rhport)
   LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
                           CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
 
-  NVIC_EnableIRQ(USB_IRQn);
+  NVIC_EnableIRQ(USB0_IRQn);
 
   return true;
 }
@@ -247,17 +236,12 @@ static void endpoint_non_control_isr(uint32_t int_status)
 
         if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
         {
-          edpt_hdl_t edpt_hdl =
-          {
-              .rhport     = 0,
-              .index      = ep_id,
-              .class_code = dcd_data.class_code[ep_id]
-          };
+          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
 
-          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+          uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
 
           // TODO no way determine if the transfer is failed or not
-          dcd_xfer_complete(edpt_hdl, dcd_data.current_td[ep_id].xferred_total, true);
+          dcd_event_xfer_complete(0, ep_addr, dcd_data.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
         }
 
         //------------- Next TD is available -------------//
@@ -287,97 +271,11 @@ static void endpoint_control_isr(uint32_t int_status)
 
     if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
     {
-      edpt_hdl_t edpt_hdl = { .rhport = 0 };
-
       dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
 
-      // FIXME xferred_byte for control xfer is not needed now !!!
-      dcd_xfer_complete(edpt_hdl, 0, true);
-    }
-  }
-}
-
-void hal_dcd_isr(uint8_t rhport)
-{
-  (void) rhport;
-
-  uint32_t const int_enable = LPC_USB->INTEN;
-  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
-  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;
-
-  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
-
-  dcd_event_t event = { .rhport = rhport };
-
-  //------------- Device Status -------------//
-  if ( int_status & INT_MASK_DEVICE_STATUS )
-  {
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
-    {
-      bus_reset();
-
-      event.event_id = DCD_EVENT_BUS_RESET;
-      dcd_event_handler(&event, true);
-    }
-
-    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
-    { // device disconnect
-      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-      { // debouncing as this can be set when device is powering
-        event.event_id = DCD_EVENT_UNPLUGGED;
-        dcd_event_handler(&event, true);
-      }
-    }
-
-    // TODO support suspend & resume
-    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
-    {
-      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
-      { // suspend signal, bus idle for more than 3ms
-        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-        {
-          event.event_id = DCD_EVENT_SUSPENDED;
-          dcd_event_handler(&event, true);
-        }
-      }
+      // FIXME control xferred bytes
+      dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, 0, XFER_RESULT_SUCCESS, true);
     }
-//        else
-//      { // resume signal
-//        event.event_id = DCD_EVENT_RESUME;
-//        dcd_event_handler(&event, true);
-//      }
-//    }
-  }
-
-  //------------- Setup Received -------------//
-  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
-  { // received control request from host
-    // copy setup request & acknowledge so that the next setup can be received by hw
-    event.event_id = DCD_EVENT_SETUP_RECEIVED;
-    event.setup_received = dcd_data.setup_request;
-
-    dcd_event_handler(&event, true);
-
-    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
-    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
-
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
-    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
-  }
-  //------------- Control Endpoint -------------//
-  else if ( int_status & 0x03 )
-  {
-    endpoint_control_isr(int_status);
-  }
-
-  //------------- Non-Control Endpoints -------------//
-  if( int_status & ~(0x03UL) )
-  {
-    endpoint_non_control_isr(int_status);
   }
 }
 
@@ -439,19 +337,21 @@ static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
 //--------------------------------------------------------------------+
 // BULK/INTERRUPT/ISOCHRONOUS PIPE API
 //--------------------------------------------------------------------+
-void dcd_edpt_stall(edpt_hdl_t edpt_hdl)
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  dcd_data.qhd[edpt_hdl.index][0].stall = dcd_data.qhd[edpt_hdl.index][1].stall = 1;
+  uint8_t const ep_id = edpt_addr2phy(edpt_addr);
+  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 1;
 }
 
-bool dcd_pipe_is_stalled(edpt_hdl_t edpt_hdl)
+bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
 {
-  return dcd_data.qhd[edpt_hdl.index][0].stall || dcd_data.qhd[edpt_hdl.index][1].stall;
+  uint8_t const ep_id = edpt_addr2phy(edpt_addr);
+  return dcd_data.qhd[ep_id][0].stall || dcd_data.qhd[ep_id][1].stall;
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
 {
-  uint8_t ep_id = edpt_addr2phy(edpt_addr);
+  uint8_t const ep_id = edpt_addr2phy(edpt_addr);
 //  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
 
   dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
@@ -467,42 +367,33 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
   }
 }
 
-edpt_hdl_t dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc, uint8_t class_code)
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void) rhport;
-  edpt_hdl_t const null_handle = { 0 };
 
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return null_handle; // TODO not support ISO yet
-
-  TU_ASSERT (p_endpoint_desc->wMaxPacketSize.size <= 64, null_handle); // TODO ISO can be 1023, but ISO not supported now
-
-  // TODO prevent to open if endpoint size is not 64
+  // TODO not support ISO yet
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
 
   //------------- Prepare Queue Head -------------//
   uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
 
-  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable, null_handle ); // endpoint must not previously opened, normally this means running out of endpoints
+  // endpoint must not previously opened, normally this means running out of endpoints
+  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable );
 
   tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
   dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
-  dcd_data.class_code[ep_id] = class_code;
-
   dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
 
   LPC_USB->EPBUFCFG |= BIT_(ep_id);
   LPC_USB->INTEN    |= BIT_(ep_id);
 
-  return (edpt_hdl_t)
-      {
-          .rhport     = 0,
-          .index      = ep_id,
-          .class_code = class_code
-      };
+  return true;
 }
 
-bool dcd_edpt_busy(edpt_hdl_t edpt_hdl)
+bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 {
-  return dcd_data.qhd[edpt_hdl.index][0].active || dcd_data.qhd[edpt_hdl.index][1].active;
+  uint8_t const ep_id = edpt_addr2phy(ep_addr);
+  return dcd_data.qhd[ep_id][0].active || dcd_data.qhd[ep_id][1].active;
 }
 
 static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
@@ -546,33 +437,138 @@ static void queue_xfer_in_next_td(uint8_t ep_id)
   dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
 }
 
-tusb_error_t dcd_edpt_queue_xfer(edpt_hdl_t edpt_hdl, uint8_t * buffer, uint16_t total_bytes)
+tusb_error_t dcd_edpt_queue_xfer(uint8_t ep_id , uint8_t * buffer, uint16_t total_bytes)
 {
-  TU_ASSERT( !dcd_edpt_busy(edpt_hdl), TUSB_ERROR_INTERFACE_IS_BUSY); // endpoint must not in transferring
+  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+  pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
+  return TUSB_ERROR_NONE;
+}
 
-  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  uint8_t const ep_id = edpt_addr2phy(ep_addr);
+
+//  if( dcd_edpt_busy(ep_addr) || dcd_edpt_stalled(ep_addr) )
+//  { // save this transfer data to next td if pipe is busy or already been stalled
+//    dcd_data.next_td[ep_id].buff_addr_offset = addr_offset(buffer);
+//    dcd_data.next_td[ep_id].total_bytes      = total_bytes;
+//
+//    dcd_data.next_ioc = BIT_SET_(dcd_data.next_ioc, ep_id);
+//  }else
+  {
+    dcd_data.current_ioc = BIT_SET_(dcd_data.current_ioc, ep_id);
 
-  pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
+    pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
+  }
 
-  return TUSB_ERROR_NONE;
+	return true;
 }
 
-tusb_error_t  dcd_edpt_xfer(edpt_hdl_t edpt_hdl, uint8_t* buffer, uint16_t total_bytes, bool int_on_complete)
+void tusb_hal_int_enable(uint8_t rhport)
 {
-  if( dcd_edpt_busy(edpt_hdl) || dcd_pipe_is_stalled(edpt_hdl) )
-  { // save this transfer data to next td if pipe is busy or already been stalled
-    dcd_data.next_td[edpt_hdl.index].buff_addr_offset = addr_offset(buffer);
-    dcd_data.next_td[edpt_hdl.index].total_bytes      = total_bytes;
+  (void) rhport; // discard compiler's warning
+  NVIC_EnableIRQ(USB0_IRQn);
+}
 
-    dcd_data.next_ioc = int_on_complete ? BIT_SET_(dcd_data.next_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.next_ioc, edpt_hdl.index);
-  }else
+void tusb_hal_int_disable(uint8_t rhport)
+{
+  (void) rhport; // discard compiler's warning
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+bool tusb_hal_init(void)
+{
+#if 0 // FIXME
+	// TODO remove magic number
+  LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); /* Enable AHB clock to the USB block and USB RAM. */
+  LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
+
+  /* Pull-down is needed, or internally, VBUS will be floating. This is to
+  address the wrong status in VBUSDebouncing bit in CmdStatus register.  */
+  // set PIO0_3 as USB_VBUS
+  LPC_IOCON->PIO0_3   &= ~0x1F;
+  LPC_IOCON->PIO0_3   |= (0x01<<0) | (1 << 3);            /* Secondary function VBUS */
+
+  // set PIO0_6 as usb connect
+  LPC_IOCON->PIO0_6   &= ~0x07;
+  LPC_IOCON->PIO0_6   |= (0x01<<0);            /* Secondary function SoftConn */
+#endif
+  return true;
+}
+
+void USB_IRQHandler(void)
+{
+  uint32_t const int_enable = LPC_USB->INTEN;
+  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
+  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
+
+  if (int_status == 0) return;
+
+  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
+
+  //------------- Device Status -------------//
+  if ( int_status & INT_MASK_DEVICE_STATUS )
   {
-    dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, edpt_hdl.index) : BIT_CLR_(dcd_data.current_ioc, edpt_hdl.index);
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    {
+      bus_reset();
+      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+    }
 
-    pipe_queue_xfer(edpt_hdl.index, addr_offset(buffer), total_bytes);
+    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    {
+      // device disconnect
+      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      {
+        // debouncing as this can be set when device is powering
+        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+      }
+    }
+
+    // TODO support suspend & resume
+    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    {
+      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
+      { // suspend signal, bus idle for more than 3ms
+        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+        {
+          dcd_event_bus_signal(0, DCD_EVENT_SUSPENDED, true);
+        }
+      }
+    }
+//        else
+//      { // resume signal
+//    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+//      }
+//    }
+  }
+
+  //------------- Setup Received -------------//
+  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  {
+    // received control request from host
+    // copy setup request & acknowledge so that the next setup can be received by hw
+    dcd_event_setup_received(0, (uint8_t*) &dcd_data.setup_request, true);
+
+    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
+    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
+
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
+  }
+  //------------- Control Endpoint -------------//
+  else if ( int_status & 0x03 )
+  {
+    endpoint_control_isr(int_status);
   }
 
-	return TUSB_ERROR_NONE;
+  //------------- Non-Control Endpoints -------------//
+  if( int_status & ~(0x03UL) )
+  {
+    endpoint_non_control_isr(int_status);
+  }
 }
 
 #endif
-- 
cgit v1.3.1


From fb842bb8041054c20d53cef2da2d47c4d44d2936 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Dec 2018 22:21:54 +0700
Subject: lp11u able to receive setup packet

---
 hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c  |  13 +-
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c | 186 ++++++++++++------------
 2 files changed, 94 insertions(+), 105 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
index d8a5ec061..51cdfaafc 100644
--- a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
+++ b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
@@ -166,20 +166,17 @@ static const PINMUX_GRP_T pinmuxing[] = {
 	/* PIO2_23					-                           - GPIO */
 };
 
-// required by startup
+// invoked by startup code
 void SystemInit(void)
 {
-
+  /* Enable IOCON clock */
+  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
+  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+  Chip_SetupXtalClocking();
 }
 
 void board_init(void)
 {
-    	/* Enable IOCON clock */
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-
-	Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-Chip_SetupXtalClocking();
 
 #if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
   SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ); // 1 msec tick timer
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index 32c336fa7..864323a8e 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -152,6 +152,24 @@ static void queue_xfer_in_next_td(uint8_t ep_id);
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
+void tusb_hal_int_enable(uint8_t rhport)
+{
+  (void) rhport; // discard compiler's warning
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void tusb_hal_int_disable(uint8_t rhport)
+{
+  (void) rhport; // discard compiler's warning
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+bool tusb_hal_init(void)
+{
+  // TODO remove
+  return true;
+}
+
 void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
@@ -175,6 +193,8 @@ bool dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
+  Chip_USB_Init();
+
   LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
   LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
 
@@ -207,78 +227,6 @@ static void bus_reset(void)
   LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
 }
 
-static void endpoint_non_control_isr(uint32_t int_status)
-{
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
-  {
-    if ( BIT_TEST_(int_status, ep_id) )
-    {
-      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
-
-      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
-      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
-      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
-
-      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
-
-      // there are still data to transfer.
-      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
-      { // NOTE although buff_addr_offset has been increased when xfer is completed
-        // but we still need to increase it one more as we are using double buffering.
-        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
-      }
-      // short packet or (no more byte and both buffers are finished)
-      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
-      { // current TD (request) is completed
-        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
-
-        dcd_data.current_td[ep_id].remaining_bytes = 0;
-
-        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
-        {
-          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
-
-          uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
-
-          // TODO no way determine if the transfer is failed or not
-          dcd_event_xfer_complete(0, ep_addr, dcd_data.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
-        }
-
-        //------------- Next TD is available -------------//
-        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
-        {
-          queue_xfer_in_next_td(ep_id);
-        }
-      }else
-      {
-        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
-      }
-    }
-  }
-}
-
-static void endpoint_control_isr(uint32_t int_status)
-{
-  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
-
-  // there are still data to transfer.
-  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
-  {
-    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
-  }else
-  {
-    dcd_data.current_td[ep_id].remaining_bytes = 0;
-
-    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
-    {
-      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
-
-      // FIXME control xferred bytes
-      dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, 0, XFER_RESULT_SUCCESS, true);
-    }
-  }
-}
-
 //--------------------------------------------------------------------+
 // CONTROL PIPE API
 //--------------------------------------------------------------------+
@@ -464,36 +412,80 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 	return true;
 }
 
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport; // discard compiler's warning
-  NVIC_EnableIRQ(USB0_IRQn);
-}
+//--------------------------------------------------------------------+
+// IRQ
+//--------------------------------------------------------------------+
 
-void tusb_hal_int_disable(uint8_t rhport)
+static void endpoint_non_control_isr(uint32_t int_status)
 {
-  (void) rhport; // discard compiler's warning
-  NVIC_DisableIRQ(USB0_IRQn);
+  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
+  {
+    if ( BIT_TEST_(int_status, ep_id) )
+    {
+      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
+
+      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
+      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
+      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
+
+      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
+
+      // there are still data to transfer.
+      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+      { // NOTE although buff_addr_offset has been increased when xfer is completed
+        // but we still need to increase it one more as we are using double buffering.
+        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
+      }
+      // short packet or (no more byte and both buffers are finished)
+      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
+      { // current TD (request) is completed
+        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
+
+        dcd_data.current_td[ep_id].remaining_bytes = 0;
+
+        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+        {
+          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+
+          uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
+
+          // TODO no way determine if the transfer is failed or not
+          dcd_event_xfer_complete(0, ep_addr, dcd_data.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
+        }
+
+        //------------- Next TD is available -------------//
+        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+        {
+          queue_xfer_in_next_td(ep_id);
+        }
+      }else
+      {
+        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
+      }
+    }
+  }
 }
 
-bool tusb_hal_init(void)
+static void endpoint_control_isr(uint32_t int_status)
 {
-#if 0 // FIXME
-	// TODO remove magic number
-  LPC_SYSCON->SYSAHBCLKCTRL |= ((0x1<<14) | (0x1<<27)); /* Enable AHB clock to the USB block and USB RAM. */
-  LPC_SYSCON->PDRUNCFG &= ~( BIT_(8) | BIT_(10) ); // enable USB PLL & USB transceiver
-
-  /* Pull-down is needed, or internally, VBUS will be floating. This is to
-  address the wrong status in VBUSDebouncing bit in CmdStatus register.  */
-  // set PIO0_3 as USB_VBUS
-  LPC_IOCON->PIO0_3   &= ~0x1F;
-  LPC_IOCON->PIO0_3   |= (0x01<<0) | (1 << 3);            /* Secondary function VBUS */
-
-  // set PIO0_6 as usb connect
-  LPC_IOCON->PIO0_6   &= ~0x07;
-  LPC_IOCON->PIO0_6   |= (0x01<<0);            /* Secondary function SoftConn */
-#endif
-  return true;
+  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
+
+  // there are still data to transfer.
+  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+  {
+    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
+  }else
+  {
+    dcd_data.current_td[ep_id].remaining_bytes = 0;
+
+    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+    {
+      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+
+      // FIXME control xferred bytes
+      dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, 0, XFER_RESULT_SUCCESS, true);
+    }
+  }
 }
 
 void USB_IRQHandler(void)
-- 
cgit v1.3.1


From 5848dd28954a39384d54c4c1662267172925413d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 2 Dec 2018 02:13:48 +0700
Subject: lpc11u use USBSRAM, able to response with 1st request

---
 .../ses/lpc11u6x/LPC11U68_MemoryMap.xml            |   1 +
 .../cdc_msc_hid/ses/lpc11u6x/flash_placement.xml   |   4 +
 .../cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject    |   2 +-
 hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c     |   2 +-
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c    | 274 ++++++++++-----------
 5 files changed, 136 insertions(+), 147 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml
index 81cf6a33d..2913af3a0 100644
--- a/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml
+++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/LPC11U68_MemoryMap.xml
@@ -3,4 +3,5 @@
   <MemorySegment name="FLASH" start="0x00000000" size="0x00040000" access="ReadOnly" />
   <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
   <MemorySegment name="RAM2" start="0x20000000" size="0x00000800" access="Read/Write" />
+  <MemorySegment name="RAM3" start="0x20004000" size="0x00000800" access="Read/Write" />
 </root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml
index 79bedc537..27a63d5be 100644
--- a/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml
+++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/flash_placement.xml
@@ -34,4 +34,8 @@
     <ProgramSection alignment="4" load="No" name=".data2_run" />
     <ProgramSection alignment="4" load="No" name=".bss2" />
   </MemorySegment>
+  <MemorySegment name="$(RAM3_NAME:RAM3)">
+    <ProgramSection alignment="4" load="No" name=".data3_run" />
+    <ProgramSection alignment="4" load="No" name=".bss3" />
+  </MemorySegment>
 </Root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject b/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject
index 876a48114..c7b8c49aa 100644
--- a/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject
+++ b/examples/device/cdc_msc_hid/ses/lpc11u6x/lpc11u6x.emProject
@@ -18,7 +18,7 @@
       arm_target_debug_interface_type="ADIv5"
       arm_target_device_name="LPC11U68"
       arm_target_interface_type="SWD"
-      c_preprocessor_definitions="__LPC11U68__;__LPC1100_FAMILY;__LPC11U00_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;CORE_M0PLUS;BOARD_LPCXPRESSO11U68;CFG_TUSB_MCU=OPT_MCU_LPC11UXX"
+      c_preprocessor_definitions="__LPC11U68__;__LPC1100_FAMILY;__LPC11U00_SUBFAMILY;ARM_MATH_CM0PLUS;FLASH_PLACEMENT=1;CORE_M0PLUS;BOARD_LPCXPRESSO11U68;CFG_TUSB_MCU=OPT_MCU_LPC11UXX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss3&quot;)));CFG_TUSB_MEM_ALIGN=__attribute__ ((aligned(64)))"
       c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc"
       debug_register_definition_file="$(ProjectDir)/LPC11U6x_Registers.xml"
       debug_target_connection="J-Link"
diff --git a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
index 51cdfaafc..f35a06b24 100644
--- a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
+++ b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
@@ -166,7 +166,7 @@ static const PINMUX_GRP_T pinmuxing[] = {
 	/* PIO2_23					-                           - GPIO */
 };
 
-// invoked by startup code
+// Invoked by startup code
 void SystemInit(void)
 {
   /* Enable IOCON clock */
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index 864323a8e..b1002b5eb 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -50,25 +50,22 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-#define DCD_11U_13U_QHD_COUNT 10
+
+// Number of endpoints
+#define EP_COUNT 10
+
+// only SRAM1 & USB RAM can be used for transfer
+#define SRAM_REGION   0x20000000
 
 enum {
   DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
 };
 
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
 enum {
-  INT_MASK_SOF           = BIT_(30),
-  INT_MASK_DEVICE_STATUS = BIT_(31)
+  INT_SOF_MASK           = BIT_(30),
+  INT_DEVICE_STATUS_MASK = BIT_(31)
 };
 
-#ifdef __CC_ARM
-#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
-#endif
-
 enum {
   CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
   CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
@@ -81,21 +78,21 @@ enum {
   CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
 };
 
-// buffer input must be 64 byte alignment
 typedef struct ATTR_PACKED
 {
-  volatile uint16_t buff_addr_offset ; ///< The address offset is updated by hardware after each successful reception/transmission of a packet. Hardware increments the original value with the integer value when the packet size is divided by 64.
+  // Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
+  volatile uint16_t buffer_offset ;
 
-  volatile uint16_t nbytes      : 10 ; ///< For OUT endpoints this is the number of bytes that can be received in this buffer. For IN endpoints this is the number of bytes that must be transmitted. HW decrements this value with the packet size every time when a packet is successfully transferred. Note: If a short packet is received on an OUT endpoint, the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used. Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value.
-  uint16_t is_isochronous       : 1  ;
-  uint16_t feedback_toggle      : 1  ; ///< For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero. For the control endpoint zero this bit is used as the toggle value. When the toggle reset bit is set, the data toggle is updated with the value programmed in this bit. When the endpoint is used as an interrupt endpoint, it can be set to the following values. 0: Interrupt endpoint in ‘toggle mode’ 1: Interrupt endpoint in ‘rate feedback mode’. This means that the data toggle is fixed to zero for all data packets. When the interrupt endpoint is in ‘rate feedback mode’, the TR bit must always be set to zero.
-  uint16_t toggle_reset         : 1  ; ///< When software sets this bit to one, the HW will set the toggle value equal to the value indicated in the “toggle value” (TV) bit. For the control endpoint zero, this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received. For the other endpoints, the toggle can only be reset to zero when the endpoint is reset.
-  uint16_t stall                : 1  ; ///< 0: The selected endpoint is not stalled 1: The selected endpoint is stalled The Active bit has always higher priority than the Stall bit. This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one. Software can only modify this bit when the active bit is zero.
-  uint16_t disable              : 1  ; ///< 0: The selected endpoint is enabled. 1: The selected endpoint is disabled. If a USB token is received for an endpoint that has the disabled bit set, hardware will ignore the token and not return any data or handshake. When a bus reset is received, software must set the disable bit of all endpoints to 1. Software can only modify this bit when the active bit is zero.
-  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
-}dcd_11u_13u_qhd_t;
+  volatile uint16_t nbytes : 10 ;
+  uint16_t is_iso          : 1  ;
+  uint16_t toggle_mode     : 1  ;
+  uint16_t toggle_reset    : 1  ;
+  uint16_t stall           : 1  ;
+  uint16_t disable         : 1  ;
+  volatile uint16_t active : 1  ;
+}ep_cmd_sts_t;
 
-TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
+TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
 
 // NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
 // If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
@@ -104,45 +101,41 @@ TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
 // queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
 
 typedef struct {
-  dcd_11u_13u_qhd_t qhd[DCD_11U_13U_QHD_COUNT][2]; ///< must be 256 byte alignment, 2 for double buffer
+  ep_cmd_sts_t qhd[EP_COUNT][2]; ///< 256 byte aligned, 2 for double buffer
 
   // start at 80, the size should not exceed 48 (for setup_request align at 128)
   struct {
     uint16_t buff_addr_offset;
     uint16_t total_bytes;
-  }next_td[DCD_11U_13U_QHD_COUNT];
+  }next_td[EP_COUNT];
 
   uint32_t current_ioc;          ///< interrupt on complete mask for current TD
   uint32_t next_ioc;             ///< interrupt on complete mask for next TD
 
   // must start from 128
-  ATTR_ALIGNED(64) tusb_control_request_t setup_request;
+  ATTR_ALIGNED(64) uint8_t setup_packet[8];
 
   struct {
     uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
     uint16_t xferred_total;          ///< xferred bytes of the current transfer
 
     uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
-  }current_td[DCD_11U_13U_QHD_COUNT];
+  }current_td[EP_COUNT];
 
-}dcd_11u_13u_data_t;
+}dcd_data_t;
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-// CFG_TUSB_MEM_SECTION must have ATTR_ALIGNED(64) for lpc11u & lpc13u
-#ifdef __ICCARM__
-ATTR_ALIGNED(256) CFG_TUSB_MEM_SECTION // for IAR the first ATTR_ALIGNED takes effect
-#else
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) // GCC & Keil the last ATTR_ALIGNED takes effect
-#endif
-STATIC_VAR dcd_11u_13u_data_t dcd_data;
 
-static inline uint16_t addr_offset(void const * p_buffer) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint16_t addr_offset(void const * p_buffer)
+// EP list must be 256-byte aligned
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) static dcd_data_t _dcd;
+
+static inline uint16_t addr_offset(void const * buffer)
 {
-  TU_ASSERT( (((uint32_t) p_buffer) & 0x3f) == 0, 0 );
-  return (uint16_t) ( (((uint32_t) p_buffer) >> 6 ) & 0xFFFF) ;
+  uint32_t addr = (uint32_t) buffer;
+  TU_ASSERT( (addr & 0x3f) == 0, 0 );
+  return ( (addr >> 6) & 0xFFFFUL ) ;
 }
 
 static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
@@ -193,13 +186,14 @@ bool dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
+  // Setup PLL clock, and power
   Chip_USB_Init();
 
-  LPC_USB->EPLISTSTART  = (uint32_t) dcd_data.qhd;
-  LPC_USB->DATABUFSTART = 0x20000000; // only SRAM1 & USB RAM can be used for transfer
+  LPC_USB->EPLISTSTART  = (uint32_t) _dcd.qhd;
+  LPC_USB->DATABUFSTART = SRAM_REGION;
 
   LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS;
+  LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK;
   LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
                           CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
 
@@ -208,67 +202,9 @@ bool dcd_init(uint8_t rhport)
   return true;
 }
 
-static void bus_reset(void)
-{
-  tu_memclr(&dcd_data, sizeof(dcd_11u_13u_data_t));
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++)
-  { // disable all non-control endpoints on bus reset
-    dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 1;
-  }
-
-  dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
-
-  LPC_USB->EPINUSE      = 0;
-  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
-  LPC_USB->EPSKIP       = 0xFFFFFFFF;
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
-  LPC_USB->INTEN        = INT_MASK_DEVICE_STATUS | BIT_(0) | BIT_(1); // enable device status & control endpoints
-}
-
-//--------------------------------------------------------------------+
-// CONTROL PIPE API
-//--------------------------------------------------------------------+
-void dcd_control_stall(uint8_t rhport)
-{
-  (void) rhport;
-  // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
-  dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 1;
-}
-
-bool dcd_control_xfer(uint8_t rhport, uint8_t dir, uint8_t * p_buffer, uint16_t length, bool int_on_complete)
-{
-  (void) rhport;
-
-  // determine Endpoint where Data & Status phase occurred (IN or OUT)
-  uint8_t const ep_data   = (dir == TUSB_DIR_IN) ? 1 : 0;
-  uint8_t const ep_status = 1 - ep_data;
-
-  dcd_data.current_ioc = int_on_complete ? BIT_SET_(dcd_data.current_ioc, ep_status) : BIT_CLR_(dcd_data.current_ioc, ep_status);
-
-  //------------- Data Phase -------------//
-  if (length)
-  {
-    dcd_data.current_td[ep_data].remaining_bytes = length;
-    dcd_data.current_td[ep_data].xferred_total   = 0;
-
-    queue_xfer_to_buffer(ep_data, 0, addr_offset(p_buffer), length);
-  }
-
-  //------------- Status Phase -------------//
-  dcd_data.current_td[ep_status].remaining_bytes = 0;
-  dcd_data.current_td[ep_status].xferred_total   = 0;
-
-  queue_xfer_to_buffer(ep_status, 0, 0, 0);
-
-  return true;
-}
-
 //--------------------------------------------------------------------+
 // PIPE HELPER
 //--------------------------------------------------------------------+
-static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr) ATTR_CONST ATTR_ALWAYS_INLINE;
 static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
 {
   return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
@@ -287,14 +223,22 @@ static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
 //--------------------------------------------------------------------+
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  uint8_t const ep_id = edpt_addr2phy(edpt_addr);
-  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 1;
+  if ( edpt_number(ep_addr) == 0 )
+  {
+    // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
+    _dcd.qhd[0][0].stall = _dcd.qhd[1][0].stall = 1;
+  }
+  else
+  {
+    uint8_t const ep_id = edpt_addr2phy(edpt_addr);
+    _dcd.qhd[ep_id][0].stall = _dcd.qhd[ep_id][1].stall = 1;
+  }
 }
 
 bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const ep_id = edpt_addr2phy(edpt_addr);
-  return dcd_data.qhd[ep_id][0].stall || dcd_data.qhd[ep_id][1].stall;
+  return _dcd.qhd[ep_id][0].stall || _dcd.qhd[ep_id][1].stall;
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
@@ -302,14 +246,14 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
   uint8_t const ep_id = edpt_addr2phy(edpt_addr);
 //  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
 
-  dcd_data.qhd[ep_id][0].stall = dcd_data.qhd[ep_id][1].stall = 0;
+  _dcd.qhd[ep_id][0].stall = _dcd.qhd[ep_id][1].stall = 0;
 
   // since the next transfer always take place on buffer0 --> clear buffer0 toggle
-  dcd_data.qhd[ep_id][0].toggle_reset    = 1;
-  dcd_data.qhd[ep_id][0].feedback_toggle = 0;
+  _dcd.qhd[ep_id][0].toggle_reset    = 1;
+  _dcd.qhd[ep_id][0].toggle_mode = 0;
 
   //------------- clear stall must carry on any previously queued transfer -------------//
-  if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+  if ( _dcd.next_td[ep_id].total_bytes != 0 )
   {
     queue_xfer_in_next_td(ep_id);
   }
@@ -326,11 +270,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
 
   // endpoint must not previously opened, normally this means running out of endpoints
-  TU_ASSERT( dcd_data.qhd[ep_id][0].disable && dcd_data.qhd[ep_id][1].disable );
+  TU_ASSERT( _dcd.qhd[ep_id][0].disable && _dcd.qhd[ep_id][1].disable );
 
-  tu_memclr(dcd_data.qhd[ep_id], 2*sizeof(dcd_11u_13u_qhd_t));
-  dcd_data.qhd[ep_id][0].is_isochronous = dcd_data.qhd[ep_id][1].is_isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
-  dcd_data.qhd[ep_id][0].disable = dcd_data.qhd[ep_id][1].disable = 0;
+  tu_memclr(_dcd.qhd[ep_id], 2*sizeof(ep_cmd_sts_t));
+  _dcd.qhd[ep_id][0].is_iso = _dcd.qhd[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  _dcd.qhd[ep_id][0].disable = _dcd.qhd[ep_id][1].disable = 0;
 
   LPC_USB->EPBUFCFG |= BIT_(ep_id);
   LPC_USB->INTEN    |= BIT_(ep_id);
@@ -341,28 +285,28 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const ep_id = edpt_addr2phy(ep_addr);
-  return dcd_data.qhd[ep_id][0].active || dcd_data.qhd[ep_id][1].active;
+  return _dcd.qhd[ep_id][0].active || _dcd.qhd[ep_id][1].active;
 }
 
 static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
 {
   uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
 
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
-  dcd_data.current_td[ep_id].remaining_bytes               -= queued_bytes;
+  _dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
+  _dcd.current_td[ep_id].remaining_bytes               -= queued_bytes;
 
-  dcd_data.qhd[ep_id][buff_idx].buff_addr_offset            = buff_addr_offset;
-  dcd_data.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
+  _dcd.qhd[ep_id][buff_idx].buffer_offset            = buff_addr_offset;
+  _dcd.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
 
-  dcd_data.qhd[ep_id][buff_idx].active = 1;
+  _dcd.qhd[ep_id][buff_idx].active = 1;
 }
 
 static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
 {
-  dcd_data.current_td[ep_id].remaining_bytes         = total_bytes;
-  dcd_data.current_td[ep_id].xferred_total           = 0;
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[0] = 0;
-  dcd_data.current_td[ep_id].queued_bytes_in_buff[1] = 0;
+  _dcd.current_td[ep_id].remaining_bytes         = total_bytes;
+  _dcd.current_td[ep_id].xferred_total           = 0;
+  _dcd.current_td[ep_id].queued_bytes_in_buff[0] = 0;
+  _dcd.current_td[ep_id].queued_bytes_in_buff[1] = 0;
 
   LPC_USB->EPINUSE  = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
 
@@ -378,24 +322,44 @@ static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t t
 
 static void queue_xfer_in_next_td(uint8_t ep_id)
 {
-  dcd_data.current_ioc |= ( dcd_data.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
+  _dcd.current_ioc |= ( _dcd.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
 
-  pipe_queue_xfer(ep_id, dcd_data.next_td[ep_id].buff_addr_offset, dcd_data.next_td[ep_id].total_bytes);
+  pipe_queue_xfer(ep_id, _dcd.next_td[ep_id].buff_addr_offset, _dcd.next_td[ep_id].total_bytes);
 
-  dcd_data.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
+  _dcd.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
 }
 
 tusb_error_t dcd_edpt_queue_xfer(uint8_t ep_id , uint8_t * buffer, uint16_t total_bytes)
 {
-  dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+  _dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
   pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
   return TUSB_ERROR_NONE;
 }
 
+
+bool dcd_control_xfer(uint8_t rhport, uint8_t ep_id, uint8_t * p_buffer, uint16_t length)
+{
+  (void) rhport;
+
+  _dcd.current_ioc = BIT_SET_(_dcd.current_ioc, ep_id);
+
+  _dcd.current_td[ep_id].remaining_bytes = length;
+  _dcd.current_td[ep_id].xferred_total   = 0;
+
+  queue_xfer_to_buffer(ep_id, 0, addr_offset(p_buffer), length);
+
+  return true;
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   uint8_t const ep_id = edpt_addr2phy(ep_addr);
 
+  if ( edpt_number(ep_addr) == 0 )
+  {
+    return dcd_control_xfer(rhport, ep_id, buffer, (uint8_t) total_bytes);
+  }
+
 //  if( dcd_edpt_busy(ep_addr) || dcd_edpt_stalled(ep_addr) )
 //  { // save this transfer data to next td if pipe is busy or already been stalled
 //    dcd_data.next_td[ep_id].buff_addr_offset = addr_offset(buffer);
@@ -404,7 +368,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 //    dcd_data.next_ioc = BIT_SET_(dcd_data.next_ioc, ep_id);
 //  }else
   {
-    dcd_data.current_ioc = BIT_SET_(dcd_data.current_ioc, ep_id);
+    _dcd.current_ioc = BIT_SET_(_dcd.current_ioc, ep_id);
 
     pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
   }
@@ -415,46 +379,66 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 //--------------------------------------------------------------------+
 // IRQ
 //--------------------------------------------------------------------+
+static void bus_reset(void)
+{
+  tu_memclr(&_dcd, sizeof(dcd_data_t));
+
+  // disable all non-control endpoints on bus reset
+  for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
+  {
+    _dcd.qhd[ep_id][0].disable = _dcd.qhd[ep_id][1].disable = 1;
+  }
+
+  _dcd.qhd[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
+
+  LPC_USB->EPINUSE      = 0;
+  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
+  LPC_USB->EPSKIP       = 0xFFFFFFFF;
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
+  LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK | BIT_(0) | BIT_(1); // enable device status & control endpoints
+}
 
 static void endpoint_non_control_isr(uint32_t int_status)
 {
-  for(uint8_t ep_id = 2; ep_id < DCD_11U_13U_QHD_COUNT; ep_id++ )
+  for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++ )
   {
     if ( BIT_TEST_(int_status, ep_id) )
     {
-      dcd_11u_13u_qhd_t * const arr_qhd = dcd_data.qhd[ep_id];
+      ep_cmd_sts_t * const arr_qhd = _dcd.qhd[ep_id];
 
       // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
       uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
-      uint16_t const xferred_bytes = dcd_data.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
+      uint16_t const xferred_bytes = _dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
 
-      dcd_data.current_td[ep_id].xferred_total += xferred_bytes;
+      _dcd.current_td[ep_id].xferred_total += xferred_bytes;
 
       // there are still data to transfer.
-      if ( (arr_qhd[buff_idx].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+      if ( (arr_qhd[buff_idx].nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
       { // NOTE although buff_addr_offset has been increased when xfer is completed
         // but we still need to increase it one more as we are using double buffering.
-        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buff_addr_offset+1, dcd_data.current_td[ep_id].remaining_bytes);
+        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buffer_offset+1, _dcd.current_td[ep_id].remaining_bytes);
       }
       // short packet or (no more byte and both buffers are finished)
       else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
       { // current TD (request) is completed
         LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
 
-        dcd_data.current_td[ep_id].remaining_bytes = 0;
+        _dcd.current_td[ep_id].remaining_bytes = 0;
 
-        if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+        if ( BIT_TEST_(_dcd.current_ioc, ep_id) )
         {
-          dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+          _dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
 
           uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
 
           // TODO no way determine if the transfer is failed or not
-          dcd_event_xfer_complete(0, ep_addr, dcd_data.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
+          dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
         }
 
         //------------- Next TD is available -------------//
-        if ( dcd_data.next_td[ep_id].total_bytes != 0 )
+        if ( _dcd.next_td[ep_id].total_bytes != 0 )
         {
           queue_xfer_in_next_td(ep_id);
         }
@@ -471,16 +455,16 @@ static void endpoint_control_isr(uint32_t int_status)
   uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
 
   // there are still data to transfer.
-  if ( (dcd_data.qhd[ep_id][0].nbytes == 0) && (dcd_data.current_td[ep_id].remaining_bytes > 0) )
+  if ( (_dcd.qhd[ep_id][0].nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
   {
-    queue_xfer_to_buffer(ep_id, 0, dcd_data.qhd[ep_id][0].buff_addr_offset, dcd_data.current_td[ep_id].remaining_bytes);
+    queue_xfer_to_buffer(ep_id, 0, _dcd.qhd[ep_id][0].buffer_offset, _dcd.current_td[ep_id].remaining_bytes);
   }else
   {
-    dcd_data.current_td[ep_id].remaining_bytes = 0;
+    _dcd.current_td[ep_id].remaining_bytes = 0;
 
-    if ( BIT_TEST_(dcd_data.current_ioc, ep_id) )
+    if ( BIT_TEST_(_dcd.current_ioc, ep_id) )
     {
-      dcd_data.current_ioc = BIT_CLR_(dcd_data.current_ioc, ep_id);
+      _dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
 
       // FIXME control xferred bytes
       dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, 0, XFER_RESULT_SUCCESS, true);
@@ -499,7 +483,7 @@ void USB_IRQHandler(void)
   uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
 
   //------------- Device Status -------------//
-  if ( int_status & INT_MASK_DEVICE_STATUS )
+  if ( int_status & INT_DEVICE_STATUS_MASK )
   {
     LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
     if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
@@ -542,13 +526,13 @@ void USB_IRQHandler(void)
   {
     // received control request from host
     // copy setup request & acknowledge so that the next setup can be received by hw
-    dcd_event_setup_received(0, (uint8_t*) &dcd_data.setup_request, true);
+    dcd_event_setup_received(0, _dcd.setup_packet, true);
 
     // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
-    dcd_data.qhd[0][0].stall = dcd_data.qhd[1][0].stall = 0;
+    _dcd.qhd[0][0].stall = _dcd.qhd[1][0].stall = 0;
 
     LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
-    dcd_data.qhd[0][1].buff_addr_offset = addr_offset(&dcd_data.setup_request);
+    _dcd.qhd[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
   }
   //------------- Control Endpoint -------------//
   else if ( int_status & 0x03 )
-- 
cgit v1.3.1


From 57f7c18d774fb03582f0cb0b108afb032d2b8a24 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 00:04:55 +0700
Subject: dcd lpc11u6x work with cdc + msc

---
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c | 35 +++++++++----------------
 1 file changed, 13 insertions(+), 22 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index b1002b5eb..6bf37f869 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -103,6 +103,8 @@ TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
 typedef struct {
   ep_cmd_sts_t qhd[EP_COUNT][2]; ///< 256 byte aligned, 2 for double buffer
 
+  uint16_t expected_len[EP_COUNT];
+
   // start at 80, the size should not exceed 48 (for setup_request align at 128)
   struct {
     uint16_t buff_addr_offset;
@@ -295,10 +297,12 @@ static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_
   _dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
   _dcd.current_td[ep_id].remaining_bytes               -= queued_bytes;
 
-  _dcd.qhd[ep_id][buff_idx].buffer_offset            = buff_addr_offset;
-  _dcd.qhd[ep_id][buff_idx].nbytes                      = queued_bytes;
+  _dcd.expected_len[ep_id] = total_bytes;
+
+  _dcd.qhd[ep_id][buff_idx].buffer_offset = buff_addr_offset;
+  _dcd.qhd[ep_id][buff_idx].nbytes        = queued_bytes;
 
-  _dcd.qhd[ep_id][buff_idx].active = 1;
+  _dcd.qhd[ep_id][buff_idx].active        = 1;
 }
 
 static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
@@ -416,13 +420,15 @@ static void endpoint_non_control_isr(uint32_t int_status)
 
       // there are still data to transfer.
       if ( (arr_qhd[buff_idx].nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
-      { // NOTE although buff_addr_offset has been increased when xfer is completed
+      {
+        // NOTE although buff_addr_offset has been increased when xfer is completed
         // but we still need to increase it one more as we are using double buffering.
         queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buffer_offset+1, _dcd.current_td[ep_id].remaining_bytes);
       }
-      // short packet or (no more byte and both buffers are finished)
       else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
-      { // current TD (request) is completed
+      {
+        // short packet or (no more byte and both buffers are finished)
+        // current TD (request) is completed
         LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
 
         _dcd.current_td[ep_id].remaining_bytes = 0;
@@ -454,22 +460,7 @@ static void endpoint_control_isr(uint32_t int_status)
 {
   uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
 
-  // there are still data to transfer.
-  if ( (_dcd.qhd[ep_id][0].nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
-  {
-    queue_xfer_to_buffer(ep_id, 0, _dcd.qhd[ep_id][0].buffer_offset, _dcd.current_td[ep_id].remaining_bytes);
-  }else
-  {
-    _dcd.current_td[ep_id].remaining_bytes = 0;
-
-    if ( BIT_TEST_(_dcd.current_ioc, ep_id) )
-    {
-      _dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
-
-      // FIXME control xferred bytes
-      dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, 0, XFER_RESULT_SUCCESS, true);
-    }
-  }
+  dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, _dcd.expected_len[ep_id] - _dcd.qhd[ep_id][0].nbytes, XFER_RESULT_SUCCESS, true);
 }
 
 void USB_IRQHandler(void)
-- 
cgit v1.3.1


From f28a15a8861aba0c9b3dfd33f7c429e2e001325d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 12:31:03 +0700
Subject: clean up dcd lpc11u

---
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c | 290 +++++++-----------------
 1 file changed, 78 insertions(+), 212 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index 6bf37f869..0f2590284 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -40,9 +40,6 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
 
-// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
-// endpoint's max packet size and need some soft DMA helper
-
 #include "chip.h"
 #include "device/dcd.h"
 #include "dcd_lpc11_13_15.h"
@@ -57,6 +54,8 @@
 // only SRAM1 & USB RAM can be used for transfer
 #define SRAM_REGION   0x20000000
 
+// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
+// endpoint's max packet size and need some soft DMA helper
 enum {
   DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
 };
@@ -95,35 +94,22 @@ typedef struct ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
 
 // NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
-// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
-// next_td stored the 2nd request information
 // current_td is used to keep track of number of remaining & xferred bytes of the current request.
-// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
-
-typedef struct {
-  ep_cmd_sts_t qhd[EP_COUNT][2]; ///< 256 byte aligned, 2 for double buffer
-
-  uint16_t expected_len[EP_COUNT];
-
-  // start at 80, the size should not exceed 48 (for setup_request align at 128)
-  struct {
-    uint16_t buff_addr_offset;
-    uint16_t total_bytes;
-  }next_td[EP_COUNT];
-
-  uint32_t current_ioc;          ///< interrupt on complete mask for current TD
-  uint32_t next_ioc;             ///< interrupt on complete mask for next TD
-
-  // must start from 128
-  ATTR_ALIGNED(64) uint8_t setup_packet[8];
+typedef struct
+{
+  // 256 byte aligned, 2 for double buffer (not used)
+  // Each cmd_sts can only transfer up to 1023 bytes each pass
+  //
+  ep_cmd_sts_t ep[EP_COUNT][2];
 
   struct {
     uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
-    uint16_t xferred_total;          ///< xferred bytes of the current transfer
+    uint16_t xferred_bytes;          ///< xferred bytes of the current transfer
 
-    uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
+    uint16_t nbytes; // Set nbytes, to determine transferred bytes each pass
   }current_td[EP_COUNT];
 
+  ATTR_ALIGNED(64) uint8_t setup_packet[8];
 }dcd_data_t;
 
 //--------------------------------------------------------------------+
@@ -140,9 +126,10 @@ static inline uint16_t addr_offset(void const * buffer)
   return ( (addr >> 6) & 0xFFFFUL ) ;
 }
 
-static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
-static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
-static void queue_xfer_in_next_td(uint8_t ep_id);
+static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
+{
+  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
+}
 
 //--------------------------------------------------------------------+
 // CONTROLLER API
@@ -191,7 +178,7 @@ bool dcd_init(uint8_t rhport)
   // Setup PLL clock, and power
   Chip_USB_Init();
 
-  LPC_USB->EPLISTSTART  = (uint32_t) _dcd.qhd;
+  LPC_USB->EPLISTSTART  = (uint32_t) _dcd.ep;
   LPC_USB->DATABUFSTART = SRAM_REGION;
 
   LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
@@ -205,60 +192,38 @@ bool dcd_init(uint8_t rhport)
 }
 
 //--------------------------------------------------------------------+
-// PIPE HELPER
-//--------------------------------------------------------------------+
-static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
-{
-  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
-}
-
-#if 0
-static inline uint8_t edpt_phy2log(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
-static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
-{
-  return physical_endpoint/2;
-}
-#endif
-
-//--------------------------------------------------------------------+
-// BULK/INTERRUPT/ISOCHRONOUS PIPE API
+// DCD Endpoint Port
 //--------------------------------------------------------------------+
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   if ( edpt_number(ep_addr) == 0 )
   {
     // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
-    _dcd.qhd[0][0].stall = _dcd.qhd[1][0].stall = 1;
+    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 1;
   }
   else
   {
-    uint8_t const ep_id = edpt_addr2phy(edpt_addr);
-    _dcd.qhd[ep_id][0].stall = _dcd.qhd[ep_id][1].stall = 1;
+    uint8_t const ep_id = ep_addr2id(ep_addr);
+    _dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 1;
   }
 }
 
 bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
 {
-  uint8_t const ep_id = edpt_addr2phy(edpt_addr);
-  return _dcd.qhd[ep_id][0].stall || _dcd.qhd[ep_id][1].stall;
+  uint8_t const ep_id = ep_addr2id(ep_addr);
+  return _dcd.ep[ep_id][0].stall || _dcd.ep[ep_id][1].stall;
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
 {
-  uint8_t const ep_id = edpt_addr2phy(edpt_addr);
+  uint8_t const ep_id = ep_addr2id(edpt_addr);
 //  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
 
-  _dcd.qhd[ep_id][0].stall = _dcd.qhd[ep_id][1].stall = 0;
+  _dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 0;
 
   // since the next transfer always take place on buffer0 --> clear buffer0 toggle
-  _dcd.qhd[ep_id][0].toggle_reset    = 1;
-  _dcd.qhd[ep_id][0].toggle_mode = 0;
-
-  //------------- clear stall must carry on any previously queued transfer -------------//
-  if ( _dcd.next_td[ep_id].total_bytes != 0 )
-  {
-    queue_xfer_in_next_td(ep_id);
-  }
+  _dcd.ep[ep_id][0].toggle_reset    = 1;
+  _dcd.ep[ep_id][0].toggle_mode = 0;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -269,113 +234,49 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
 
   //------------- Prepare Queue Head -------------//
-  uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
+  uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
 
-  // endpoint must not previously opened, normally this means running out of endpoints
-  TU_ASSERT( _dcd.qhd[ep_id][0].disable && _dcd.qhd[ep_id][1].disable );
+  // Check if endpoint is available
+  TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
 
-  tu_memclr(_dcd.qhd[ep_id], 2*sizeof(ep_cmd_sts_t));
-  _dcd.qhd[ep_id][0].is_iso = _dcd.qhd[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
-  _dcd.qhd[ep_id][0].disable = _dcd.qhd[ep_id][1].disable = 0;
+  tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
+  _dcd.ep[ep_id][0].is_iso = _dcd.ep[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
 
-  LPC_USB->EPBUFCFG |= BIT_(ep_id);
-  LPC_USB->INTEN    |= BIT_(ep_id);
+  // Enable EP interrupt
+  LPC_USB->INTEN |= BIT_(ep_id);
 
   return true;
 }
 
 bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 {
-  uint8_t const ep_id = edpt_addr2phy(ep_addr);
-  return _dcd.qhd[ep_id][0].active || _dcd.qhd[ep_id][1].active;
+  uint8_t const ep_id = ep_addr2id(ep_addr);
+  return _dcd.ep[ep_id][0].active || _dcd.ep[ep_id][1].active;
 }
 
-static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
+static void prepare_ep_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
 {
   uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
 
-  _dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
-  _dcd.current_td[ep_id].remaining_bytes               -= queued_bytes;
-
-  _dcd.expected_len[ep_id] = total_bytes;
-
-  _dcd.qhd[ep_id][buff_idx].buffer_offset = buff_addr_offset;
-  _dcd.qhd[ep_id][buff_idx].nbytes        = queued_bytes;
-
-  _dcd.qhd[ep_id][buff_idx].active        = 1;
-}
-
-static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
-{
-  _dcd.current_td[ep_id].remaining_bytes         = total_bytes;
-  _dcd.current_td[ep_id].xferred_total           = 0;
-  _dcd.current_td[ep_id].queued_bytes_in_buff[0] = 0;
-  _dcd.current_td[ep_id].queued_bytes_in_buff[1] = 0;
-
-  LPC_USB->EPINUSE  = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
-
-  // need to queue buffer1 first, as activate buffer0 can causes controller does transferring immediately
-  // while buffer1 is not ready yet
-  if ( total_bytes > DCD_11U_13U_MAX_BYTE_PER_TD)
-  {
-    queue_xfer_to_buffer(ep_id, 1, buff_addr_offset+1, total_bytes - DCD_11U_13U_MAX_BYTE_PER_TD);
-  }
-
-  queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
-}
-
-static void queue_xfer_in_next_td(uint8_t ep_id)
-{
-  _dcd.current_ioc |= ( _dcd.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
-
-  pipe_queue_xfer(ep_id, _dcd.next_td[ep_id].buff_addr_offset, _dcd.next_td[ep_id].total_bytes);
-
-  _dcd.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
-}
-
-tusb_error_t dcd_edpt_queue_xfer(uint8_t ep_id , uint8_t * buffer, uint16_t total_bytes)
-{
-  _dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
-  pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
-  return TUSB_ERROR_NONE;
-}
-
-
-bool dcd_control_xfer(uint8_t rhport, uint8_t ep_id, uint8_t * p_buffer, uint16_t length)
-{
-  (void) rhport;
-
-  _dcd.current_ioc = BIT_SET_(_dcd.current_ioc, ep_id);
+  _dcd.current_td[ep_id].nbytes = queued_bytes;
+  _dcd.current_td[ep_id].remaining_bytes     -= queued_bytes;
 
-  _dcd.current_td[ep_id].remaining_bytes = length;
-  _dcd.current_td[ep_id].xferred_total   = 0;
+  _dcd.ep[ep_id][0].buffer_offset = buff_addr_offset;
+  _dcd.ep[ep_id][0].nbytes        = queued_bytes;
 
-  queue_xfer_to_buffer(ep_id, 0, addr_offset(p_buffer), length);
-
-  return true;
+  _dcd.ep[ep_id][0].active        = 1;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
-  uint8_t const ep_id = edpt_addr2phy(ep_addr);
+  uint8_t const ep_id = ep_addr2id(ep_addr);
+  uint16_t buf_offset = addr_offset(buffer);
 
-  if ( edpt_number(ep_addr) == 0 )
-  {
-    return dcd_control_xfer(rhport, ep_id, buffer, (uint8_t) total_bytes);
-  }
+  _dcd.current_td[ep_id].remaining_bytes = total_bytes;
+  _dcd.current_td[ep_id].xferred_bytes   = 0;
+  _dcd.current_td[ep_id].nbytes          = 0;
 
-//  if( dcd_edpt_busy(ep_addr) || dcd_edpt_stalled(ep_addr) )
-//  { // save this transfer data to next td if pipe is busy or already been stalled
-//    dcd_data.next_td[ep_id].buff_addr_offset = addr_offset(buffer);
-//    dcd_data.next_td[ep_id].total_bytes      = total_bytes;
-//
-//    dcd_data.next_ioc = BIT_SET_(dcd_data.next_ioc, ep_id);
-//  }else
-  {
-    _dcd.current_ioc = BIT_SET_(_dcd.current_ioc, ep_id);
-
-    pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
-  }
+  prepare_ep_xfer(ep_id, buf_offset, total_bytes);
 
 	return true;
 }
@@ -390,13 +291,13 @@ static void bus_reset(void)
   // disable all non-control endpoints on bus reset
   for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
   {
-    _dcd.qhd[ep_id][0].disable = _dcd.qhd[ep_id][1].disable = 1;
+    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
   }
 
-  _dcd.qhd[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
+  _dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
 
   LPC_USB->EPINUSE      = 0;
-  LPC_USB->EPBUFCFG     = 0; // all start with single buffer
+  LPC_USB->EPBUFCFG     = 0;
   LPC_USB->EPSKIP       = 0xFFFFFFFF;
 
   LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
@@ -404,75 +305,44 @@ static void bus_reset(void)
   LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK | BIT_(0) | BIT_(1); // enable device status & control endpoints
 }
 
-static void endpoint_non_control_isr(uint32_t int_status)
+static void process_xfer_isr(uint32_t int_status)
 {
-  for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++ )
+  for(uint8_t ep_id = 0; ep_id < EP_COUNT; ep_id++ )
   {
     if ( BIT_TEST_(int_status, ep_id) )
     {
-      ep_cmd_sts_t * const arr_qhd = _dcd.qhd[ep_id];
-
-      // when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
-      uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
-      uint16_t const xferred_bytes = _dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
+      ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
 
-      _dcd.current_td[ep_id].xferred_total += xferred_bytes;
+      _dcd.current_td[ep_id].xferred_bytes += _dcd.current_td[ep_id].nbytes - ep_cs->nbytes;
 
-      // there are still data to transfer.
-      if ( (arr_qhd[buff_idx].nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
+      if ( (ep_cs->nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
       {
-        // NOTE although buff_addr_offset has been increased when xfer is completed
-        // but we still need to increase it one more as we are using double buffering.
-        queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buffer_offset+1, _dcd.current_td[ep_id].remaining_bytes);
+        // There is more data to transfer
+        // buff_offset has been already increased by hw to correct value for next transfer
+        prepare_ep_xfer(ep_id, ep_cs->buffer_offset, _dcd.current_td[ep_id].remaining_bytes);
       }
-      else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active  )
+      else
       {
-        // short packet or (no more byte and both buffers are finished)
-        // current TD (request) is completed
-        LPC_USB->EPSKIP   = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
-
         _dcd.current_td[ep_id].remaining_bytes = 0;
 
-        if ( BIT_TEST_(_dcd.current_ioc, ep_id) )
-        {
-          _dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
-
-          uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
-
-          // TODO no way determine if the transfer is failed or not
-          dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
-        }
+        uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
 
-        //------------- Next TD is available -------------//
-        if ( _dcd.next_td[ep_id].total_bytes != 0 )
-        {
-          queue_xfer_in_next_td(ep_id);
-        }
-      }else
-      {
-        // transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
+        // TODO no way determine if the transfer is failed or not
+        dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_bytes, XFER_RESULT_SUCCESS, true);
       }
     }
   }
 }
 
-static void endpoint_control_isr(uint32_t int_status)
-{
-  uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
-
-  dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, _dcd.expected_len[ep_id] - _dcd.qhd[ep_id][0].nbytes, XFER_RESULT_SUCCESS, true);
-}
-
 void USB_IRQHandler(void)
 {
-  uint32_t const int_enable = LPC_USB->INTEN;
-  uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
+  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
+
+  uint32_t int_status = LPC_USB->INTSTAT & LPC_USB->INTEN;
   LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
 
   if (int_status == 0) return;
 
-  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
-
   //------------- Device Status -------------//
   if ( int_status & INT_DEVICE_STATUS_MASK )
   {
@@ -512,30 +382,26 @@ void USB_IRQHandler(void)
 //    }
   }
 
-  //------------- Setup Received -------------//
+  // Setup Receive
   if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
   {
-    // received control request from host
-    // copy setup request & acknowledge so that the next setup can be received by hw
+    // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
+    _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
+    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
+
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+
     dcd_event_setup_received(0, _dcd.setup_packet, true);
 
-    // NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
-    _dcd.qhd[0][0].stall = _dcd.qhd[1][0].stall = 0;
+    // keep waiting for next setup
+    _dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
 
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
-    _dcd.qhd[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
-  }
-  //------------- Control Endpoint -------------//
-  else if ( int_status & 0x03 )
-  {
-    endpoint_control_isr(int_status);
+    // clear bit0
+    int_status = BIT_CLR_(int_status, 0);
   }
 
-  //------------- Non-Control Endpoints -------------//
-  if( int_status & ~(0x03UL) )
-  {
-    endpoint_non_control_isr(int_status);
-  }
+  // Endpoint transfer complete interrupt
+  process_xfer_isr(int_status);
 }
 
 #endif
-- 
cgit v1.3.1


From 66bd9f0a16676b1b7a8d7db987b3109baf5e76a8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 13:15:28 +0700
Subject: wrap up lpc11u port

---
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c | 83 ++++++++++++-------------
 1 file changed, 41 insertions(+), 42 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
index 0f2590284..568bcc586 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
@@ -54,10 +54,13 @@
 // only SRAM1 & USB RAM can be used for transfer
 #define SRAM_REGION   0x20000000
 
-// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
-// endpoint's max packet size and need some soft DMA helper
+/* Although device controller are the same. DMA of
+ * - LPC11u can only transfer up to nbytes = 64
+ * - LPC13 can transfer nbytes = 1023 (maximum)
+ * - LPC15 can ???
+ */
 enum {
-  DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
+  DMA_NBYTES_MAX = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
 };
 
 enum {
@@ -80,7 +83,7 @@ enum {
 typedef struct ATTR_PACKED
 {
   // Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
-  volatile uint16_t buffer_offset ;
+  volatile uint16_t buffer_offset;
 
   volatile uint16_t nbytes : 10 ;
   uint16_t is_iso          : 1  ;
@@ -93,21 +96,23 @@ typedef struct ATTR_PACKED
 
 TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
 
+typedef struct
+{
+  uint16_t total_bytes;
+  uint16_t xferred_bytes;
+
+  uint16_t nbytes;
+}xfer_dma_t;
+
 // NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
 // current_td is used to keep track of number of remaining & xferred bytes of the current request.
 typedef struct
 {
   // 256 byte aligned, 2 for double buffer (not used)
-  // Each cmd_sts can only transfer up to 1023 bytes each pass
-  //
+  // Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
   ep_cmd_sts_t ep[EP_COUNT][2];
 
-  struct {
-    uint16_t remaining_bytes;        ///< expected bytes of the queued transfer
-    uint16_t xferred_bytes;          ///< xferred bytes of the current transfer
-
-    uint16_t nbytes; // Set nbytes, to determine transferred bytes each pass
-  }current_td[EP_COUNT];
+  xfer_dma_t dma[EP_COUNT];
 
   ATTR_ALIGNED(64) uint8_t setup_packet[8];
 }dcd_data_t;
@@ -119,7 +124,7 @@ typedef struct
 // EP list must be 256-byte aligned
 CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) static dcd_data_t _dcd;
 
-static inline uint16_t addr_offset(void const * buffer)
+static inline uint16_t get_buf_offset(void const * buffer)
 {
   uint32_t addr = (uint32_t) buffer;
   TU_ASSERT( (addr & 0x3f) == 0, 0 );
@@ -204,26 +209,23 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   else
   {
     uint8_t const ep_id = ep_addr2id(ep_addr);
-    _dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 1;
+    _dcd.ep[ep_id][0].stall = 1;
   }
 }
 
 bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const ep_id = ep_addr2id(ep_addr);
-  return _dcd.ep[ep_id][0].stall || _dcd.ep[ep_id][1].stall;
+  return _dcd.ep[ep_id][0].stall;
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
 {
   uint8_t const ep_id = ep_addr2id(edpt_addr);
-//  uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
-
-  _dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 0;
 
-  // since the next transfer always take place on buffer0 --> clear buffer0 toggle
-  _dcd.ep[ep_id][0].toggle_reset    = 1;
-  _dcd.ep[ep_id][0].toggle_mode = 0;
+  _dcd.ep[ep_id][0].stall        = 0;
+  _dcd.ep[ep_id][0].toggle_reset = 1;
+  _dcd.ep[ep_id][0].toggle_mode  = 0;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -240,7 +242,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
 
   tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
-  _dcd.ep[ep_id][0].is_iso = _dcd.ep[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
 
   // Enable EP interrupt
   LPC_USB->INTEN |= BIT_(ep_id);
@@ -251,32 +253,28 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const ep_id = ep_addr2id(ep_addr);
-  return _dcd.ep[ep_id][0].active || _dcd.ep[ep_id][1].active;
+  return _dcd.ep[ep_id][0].active;
 }
 
-static void prepare_ep_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
+static void prepare_ep_xfer(uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
 {
-  uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
-
-  _dcd.current_td[ep_id].nbytes = queued_bytes;
-  _dcd.current_td[ep_id].remaining_bytes     -= queued_bytes;
+  uint16_t const nbytes = tu_min16(total_bytes, DMA_NBYTES_MAX);
 
-  _dcd.ep[ep_id][0].buffer_offset = buff_addr_offset;
-  _dcd.ep[ep_id][0].nbytes        = queued_bytes;
+  _dcd.dma[ep_id].nbytes = nbytes;
 
+  _dcd.ep[ep_id][0].buffer_offset = buf_offset;
+  _dcd.ep[ep_id][0].nbytes        = nbytes;
   _dcd.ep[ep_id][0].active        = 1;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   uint8_t const ep_id = ep_addr2id(ep_addr);
-  uint16_t buf_offset = addr_offset(buffer);
 
-  _dcd.current_td[ep_id].remaining_bytes = total_bytes;
-  _dcd.current_td[ep_id].xferred_bytes   = 0;
-  _dcd.current_td[ep_id].nbytes          = 0;
+  tu_varclr(&_dcd.dma[ep_id]);
+  _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  prepare_ep_xfer(ep_id, buf_offset, total_bytes);
+  prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes);
 
 	return true;
 }
@@ -294,7 +292,7 @@ static void bus_reset(void)
     _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
   }
 
-  _dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
+  _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
 
   LPC_USB->EPINUSE      = 0;
   LPC_USB->EPBUFCFG     = 0;
@@ -312,23 +310,24 @@ static void process_xfer_isr(uint32_t int_status)
     if ( BIT_TEST_(int_status, ep_id) )
     {
       ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
+      xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
 
-      _dcd.current_td[ep_id].xferred_bytes += _dcd.current_td[ep_id].nbytes - ep_cs->nbytes;
+      xfer_dma->xferred_bytes += xfer_dma->nbytes - ep_cs->nbytes;
 
-      if ( (ep_cs->nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
+      if ( (ep_cs->nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
       {
         // There is more data to transfer
         // buff_offset has been already increased by hw to correct value for next transfer
-        prepare_ep_xfer(ep_id, ep_cs->buffer_offset, _dcd.current_td[ep_id].remaining_bytes);
+        prepare_ep_xfer(ep_id, ep_cs->buffer_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
       }
       else
       {
-        _dcd.current_td[ep_id].remaining_bytes = 0;
+        xfer_dma->total_bytes = xfer_dma->xferred_bytes;
 
         uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
 
         // TODO no way determine if the transfer is failed or not
-        dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_bytes, XFER_RESULT_SUCCESS, true);
+        dcd_event_xfer_complete(0, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
       }
     }
   }
@@ -394,7 +393,7 @@ void USB_IRQHandler(void)
     dcd_event_setup_received(0, _dcd.setup_packet, true);
 
     // keep waiting for next setup
-    _dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
+    _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
 
     // clear bit0
     int_status = BIT_CLR_(int_status, 0);
-- 
cgit v1.3.1


From 63faea392939cd7d2fa03d95b55542e783728b0b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 17:43:16 +0700
Subject: migrate lpc17 to lpcopen, usb device work ok

---
 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c | 96 +++++++++++++++----------------
 src/portable/nxp/lpc17xx/hal_lpc175x_6x.c | 23 +++-----
 2 files changed, 57 insertions(+), 62 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
index af7ceae0c..3889e8104 100644
--- a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
+++ b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
@@ -42,7 +42,7 @@
 
 #include "device/dcd.h"
 #include "dcd_lpc175x_6x.h"
-#include "LPC17xx.h"
+#include "chip.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -111,13 +111,13 @@ ATTR_ALIGNED(128) static dcd_data_t _dcd;
 //--------------------------------------------------------------------+
 static void sie_cmd_code (sie_cmdphase_t phase, uint8_t code_data)
 {
-  LPC_USB->USBDevIntClr = (DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK);
-  LPC_USB->USBCmdCode   = (phase << 8) | (code_data << 16);
+  LPC_USB->DevIntClr = (DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK);
+  LPC_USB->CmdCode   = (phase << 8) | (code_data << 16);
 
   uint32_t const wait_flag = (phase == SIE_CMDPHASE_READ) ? DEV_INT_COMMAND_DATA_FULL_MASK : DEV_INT_COMMAND_CODE_EMPTY_MASK;
-  while ((LPC_USB->USBDevIntSt & wait_flag) == 0) {}
+  while ((LPC_USB->DevIntSt & wait_flag) == 0) {}
 
-  LPC_USB->USBDevIntClr = wait_flag;
+  LPC_USB->DevIntClr = wait_flag;
 }
 
 static void sie_write (uint8_t cmd_code, uint8_t data_len, uint8_t data)
@@ -135,7 +135,7 @@ static uint32_t sie_read (uint8_t cmd_code, uint8_t data_len)
   // TODO multiple read
   sie_cmd_code(SIE_CMDPHASE_COMMAND , cmd_code);
   sie_cmd_code(SIE_CMDPHASE_READ    , cmd_code);
-  return LPC_USB->USBCmdData;
+  return LPC_USB->CmdData;
 }
 
 //--------------------------------------------------------------------+
@@ -149,12 +149,12 @@ static inline uint8_t ep_addr2idx(uint8_t ep_addr)
 static void set_ep_size(uint8_t ep_id, uint16_t max_packet_size)
 {
   // follows example in 11.10.4.2
-  LPC_USB->USBReEp    |= BIT_(ep_id);
-  LPC_USB->USBEpInd    = ep_id; // select index before setting packet size
-  LPC_USB->USBMaxPSize = max_packet_size;
+  LPC_USB->ReEp    |= BIT_(ep_id);
+  LPC_USB->EpInd    = ep_id; // select index before setting packet size
+  LPC_USB->MaxPSize = max_packet_size;
 
-  while ((LPC_USB->USBDevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {}
-  LPC_USB->USBDevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
+  while ((LPC_USB->DevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {}
+  LPC_USB->DevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
 }
 
 
@@ -164,17 +164,17 @@ static void set_ep_size(uint8_t ep_id, uint16_t max_packet_size)
 static void bus_reset(void)
 {
   // step 7 : slave mode set up
-  LPC_USB->USBEpIntClr     = 0xFFFFFFFF; // clear all pending interrupt
-  LPC_USB->USBDevIntClr    = 0xFFFFFFFF; // clear all pending interrupt
-  LPC_USB->USBEpIntEn      = 0x03UL;     // control endpoint cannot use DMA, non-control all use DMA
-  LPC_USB->USBEpIntPri     = 0x03UL;     // fast for control endpoint
+  LPC_USB->EpIntClr     = 0xFFFFFFFF; // clear all pending interrupt
+  LPC_USB->DevIntClr    = 0xFFFFFFFF; // clear all pending interrupt
+  LPC_USB->EpIntEn      = 0x03UL;     // control endpoint cannot use DMA, non-control all use DMA
+  LPC_USB->EpIntPri     = 0x03UL;     // fast for control endpoint
 
   // step 8 : DMA set up
-  LPC_USB->USBEpDMADis     = 0xFFFFFFFF; // firstly disable all dma
-  LPC_USB->USBDMARClr      = 0xFFFFFFFF; // clear all pending interrupt
-  LPC_USB->USBEoTIntClr    = 0xFFFFFFFF;
-  LPC_USB->USBNDDRIntClr   = 0xFFFFFFFF;
-  LPC_USB->USBSysErrIntClr = 0xFFFFFFFF;
+  LPC_USB->EpDMADis     = 0xFFFFFFFF; // firstly disable all dma
+  LPC_USB->DMARClr      = 0xFFFFFFFF; // clear all pending interrupt
+  LPC_USB->EoTIntClr    = 0xFFFFFFFF;
+  LPC_USB->NDDRIntClr   = 0xFFFFFFFF;
+  LPC_USB->SysErrIntClr = 0xFFFFFFFF;
 
   tu_memclr(&_dcd, sizeof(dcd_data_t));
 }
@@ -183,16 +183,16 @@ bool dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
-  //------------- user manual 11.13 usb device controller initialization -------------//  LPC_USB->USBEpInd = 0;
+  //------------- user manual 11.13 usb device controller initialization -------------//
   // step 6 : set up control endpoint
   set_ep_size(0, CFG_TUD_ENDOINT0_SIZE);
   set_ep_size(1, CFG_TUD_ENDOINT0_SIZE);
 
   bus_reset();
 
-  LPC_USB->USBDevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_FAST_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
-  LPC_USB->USBUDCAH = (uint32_t) _dcd.udca;
-  LPC_USB->USBDMAIntEn = (DMA_INT_END_OF_XFER_MASK /*| DMA_INT_NEW_DD_REQUEST_MASK*/ | DMA_INT_ERROR_MASK);
+  LPC_USB->DevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_FAST_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
+  LPC_USB->UDCAH = (uint32_t) _dcd.udca;
+  LPC_USB->DMAIntEn = (DMA_INT_END_OF_XFER_MASK /*| DMA_INT_NEW_DD_REQUEST_MASK*/ | DMA_INT_ERROR_MASK);
 
   sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);    // connect
 
@@ -234,16 +234,16 @@ static void control_ep_write(void const * buffer, uint8_t len)
 {
   uint32_t const * buf32 = (uint32_t const *) buffer;
 
-  LPC_USB->USBCtrl   = USBCTRL_WRITE_ENABLE_MASK; // logical endpoint = 0
-  LPC_USB->USBTxPLen = (uint32_t) len;
+  LPC_USB->Ctrl   = USBCTRL_WRITE_ENABLE_MASK; // logical endpoint = 0
+  LPC_USB->TxPLen = (uint32_t) len;
 
   for (uint8_t count = 0; count < byte2dword(len); count++)
   {
-    LPC_USB->USBTxData = *buf32; // NOTE: cortex M3 have no problem with alignment
+    LPC_USB->TxData = *buf32; // NOTE: cortex M3 have no problem with alignment
     buf32++;
   }
 
-  LPC_USB->USBCtrl = 0;
+  LPC_USB->Ctrl = 0;
 
   // select control IN & validate the endpoint
   sie_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0);
@@ -252,19 +252,19 @@ static void control_ep_write(void const * buffer, uint8_t len)
 
 static uint8_t control_ep_read(void * buffer, uint8_t len)
 {
-  LPC_USB->USBCtrl = USBCTRL_READ_ENABLE_MASK; // logical endpoint = 0
-  while ((LPC_USB->USBRxPLen & USBRXPLEN_PACKET_READY_MASK) == 0) {} // TODO blocking, should have timeout
+  LPC_USB->Ctrl = USBCTRL_READ_ENABLE_MASK; // logical endpoint = 0
+  while ((LPC_USB->RxPLen & USBRXPLEN_PACKET_READY_MASK) == 0) {} // TODO blocking, should have timeout
 
-  len = tu_min8(len, (uint8_t) (LPC_USB->USBRxPLen & USBRXPLEN_PACKET_LENGTH_MASK) );
+  len = tu_min8(len, (uint8_t) (LPC_USB->RxPLen & USBRXPLEN_PACKET_LENGTH_MASK) );
   uint32_t *buf32 = (uint32_t*) buffer;
 
   for (uint8_t count=0; count < byte2dword(len); count++)
   {
-    *buf32 = LPC_USB->USBRxData;
+    *buf32 = LPC_USB->RxData;
     buf32++;
   }
 
-  LPC_USB->USBCtrl = 0;
+  LPC_USB->Ctrl = 0;
 
   // select control OUT & clear the endpoint
   sie_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
@@ -415,15 +415,15 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t t
     if ( ep_id % 2 )
     {
       // Clear EP interrupt before Enable DMA
-      LPC_USB->USBEpIntEn &= ~BIT_(ep_id);
-      LPC_USB->USBEpDMAEn = BIT_(ep_id);
+      LPC_USB->EpIntEn &= ~BIT_(ep_id);
+      LPC_USB->EpDMAEn = BIT_(ep_id);
 
       // endpoint IN need to actively raise DMA request
-      LPC_USB->USBDMARSet = BIT_(ep_id);
+      LPC_USB->DMARSet = BIT_(ep_id);
     }else
     {
       // Enable DMA
-      LPC_USB->USBEpDMAEn = BIT_(ep_id);
+      LPC_USB->EpDMAEn = BIT_(ep_id);
     }
 
     return true;
@@ -442,7 +442,7 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
   {
     bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
 
-    LPC_USB->USBEpIntClr = BIT_(0);
+    LPC_USB->EpIntClr = BIT_(0);
 
     if (is_setup)
     {
@@ -470,7 +470,7 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
   // Control In complete
   if ( ep_int_status & BIT_(1) )
   {
-    LPC_USB->USBEpIntClr = BIT_(1);
+    LPC_USB->EpIntClr = BIT_(1);
     dcd_event_xfer_complete(rhport, TUSB_DIR_IN_MASK, _dcd.control.in_bytes, XFER_RESULT_SUCCESS, true);
   }
 }
@@ -517,8 +517,8 @@ static void dd_complete_isr(uint8_t rhport, uint8_t ep_id)
 // main USB IRQ handler
 void hal_dcd_isr(uint8_t rhport)
 {
-  uint32_t const dev_int_status = LPC_USB->USBDevIntSt & LPC_USB->USBDevIntEn;
-  LPC_USB->USBDevIntClr = dev_int_status;// Acknowledge handled interrupt
+  uint32_t const dev_int_status = LPC_USB->DevIntSt & LPC_USB->DevIntEn;
+  LPC_USB->DevIntClr = dev_int_status;// Acknowledge handled interrupt
 
   // Bus event
   if (dev_int_status & DEV_INT_DEVICE_STATUS_MASK)
@@ -527,7 +527,7 @@ void hal_dcd_isr(uint8_t rhport)
   }
 
   // Endpoint interrupt
-  uint32_t const ep_int_status = LPC_USB->USBEpIntSt & LPC_USB->USBEpIntEn;
+  uint32_t const ep_int_status = LPC_USB->EpIntSt & LPC_USB->EpIntEn;
 
   // Control Endpoint are fast
   if (dev_int_status & DEV_INT_ENDPOINT_FAST_MASK)
@@ -544,10 +544,10 @@ void hal_dcd_isr(uint8_t rhport)
     {
       if ( BIT_TEST_(ep_int_status, ep_id) )
       {
-        LPC_USB->USBEpIntClr = BIT_(ep_id);
+        LPC_USB->EpIntClr = BIT_(ep_id);
 
         // Clear Ep interrupt for next DMA
-        LPC_USB->USBEpIntEn &= ~BIT_(ep_id);
+        LPC_USB->EpIntEn &= ~BIT_(ep_id);
 
         dd_complete_isr(rhport, ep_id);
       }
@@ -557,11 +557,11 @@ void hal_dcd_isr(uint8_t rhport)
   // DMA transfer complete (RAM <-> EP) for Non-Control
   // OUT: USB transfer is fully complete
   // IN : UBS transfer is still on-going -> enable EpIntEn to know when it is complete
-  uint32_t const dma_int_status = LPC_USB->USBDMAIntSt & LPC_USB->USBDMAIntEn;
+  uint32_t const dma_int_status = LPC_USB->DMAIntSt & LPC_USB->DMAIntEn;
   if (dma_int_status & DMA_INT_END_OF_XFER_MASK)
   {
-    uint32_t const eot = LPC_USB->USBEoTIntSt;
-    LPC_USB->USBEoTIntClr = eot; // acknowledge interrupt source
+    uint32_t const eot = LPC_USB->EoTIntSt;
+    LPC_USB->EoTIntClr = eot; // acknowledge interrupt source
 
     for ( uint8_t ep_id = 2; ep_id < DCD_ENDPOINT_MAX; ep_id++ )
     {
@@ -570,7 +570,7 @@ void hal_dcd_isr(uint8_t rhport)
         if ( ep_id & 0x01 )
         {
           // IN enable EpInt for end of usb transfer
-          LPC_USB->USBEpIntEn |= BIT_(ep_id);
+          LPC_USB->EpIntEn |= BIT_(ep_id);
         }else
         {
           // OUT
diff --git a/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c b/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
index 13cb178f2..d01c9e29d 100644
--- a/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
+++ b/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
@@ -40,8 +40,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X
 
-#include "LPC17xx.h"
-#include "lpc17xx_pinsel.h"
+#include "chip.h"
 
 void tusb_hal_int_enable(uint8_t rhport)
 {
@@ -63,15 +62,14 @@ bool tusb_hal_init(void)
   enum {
     USBCLK_DEVCIE = 0x12,     // AHB + Device
     USBCLK_HOST   = 0x19,     // AHB + Host + OTG (!)
-
-    PCONP_PCUSB   = BIT_(31)
   };
 
-  LPC_SC->PCONP |= PCONP_PCUSB; // enable USB Peripherals
+  Chip_USB_Init();
 
   //------------- user manual 11.13 usb device controller initialization -------------//
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 0, .Pinnum = 29, .Funcnum = 1} ); // P0.29 as D+
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 0, .Pinnum = 30, .Funcnum = 1} ); // P0.30 as D-
+  /* Configure P0.29 as D+, P0.30 as D- */
+  Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1);
+  Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
 
 #if MODE_HOST_SUPPORTED
   PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 22, .Funcnum = 2} ); // P1.22 as USB_PWRD
@@ -83,8 +81,10 @@ bool tusb_hal_init(void)
 #endif
 
 #if TUSB_OPT_DEVICE_ENABLED
-  LPC_PINCON->PINSEL4 = bit_set_range(LPC_PINCON->PINSEL4, 18, 19, BIN8(01)); // P2_9 as USB Connect
+//  LPC_PINCON->PINSEL4 = bit_set_range(LPC_PINCON->PINSEL4, 18, 19, BIN8(01)); // P2_9 as USB Connect
+  Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1);
 
+#if 0
   // P1_30 as VBUS, ignore if it is already in VBUS mode
   if ( !(!BIT_TEST_(LPC_PINCON->PINSEL3, 28) && BIT_TEST_(LPC_PINCON->PINSEL3, 29)) )
   {
@@ -94,6 +94,7 @@ bool tusb_hal_init(void)
       .Portnum = 1, .Pinnum = 30,
       .Funcnum = 2, .Pinmode = PINSEL_PINMODE_PULLDOWN} );
   }
+#endif
 
   LPC_USB->USBClkCtrl = USBCLK_DEVCIE;
   while ((LPC_USB->USBClkSt & USBCLK_DEVCIE) != USBCLK_DEVCIE);
@@ -115,10 +116,4 @@ void USB_IRQHandler(void)
   #endif
 }
 
-void check_failed(uint8_t *file, uint32_t line)
-{
-  (void) file;
-  (void) line;
-}
-
 #endif
-- 
cgit v1.3.1


From 9e33f19378da1e19568714797698b6b62296924f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 17:47:37 +0700
Subject: clean up

---
 src/portable/nxp/lpc17xx/hal_lpc175x_6x.c | 21 +++++----------------
 1 file changed, 5 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c b/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
index d01c9e29d..bc61178d8 100644
--- a/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
+++ b/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
@@ -44,13 +44,13 @@
 
 void tusb_hal_int_enable(uint8_t rhport)
 {
-  (void) rhport; // discard compiler's warning
+  (void) rhport;
   NVIC_EnableIRQ(USB_IRQn);
 }
 
 void tusb_hal_int_disable(uint8_t rhport)
 {
-  (void) rhport; // discard compiler's warning
+  (void) rhport;
   NVIC_DisableIRQ(USB_IRQn);
 }
 
@@ -66,7 +66,6 @@ bool tusb_hal_init(void)
 
   Chip_USB_Init();
 
-  //------------- user manual 11.13 usb device controller initialization -------------//
   /* Configure P0.29 as D+, P0.30 as D- */
   Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1);
   Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
@@ -75,27 +74,17 @@ bool tusb_hal_init(void)
   PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 22, .Funcnum = 2} ); // P1.22 as USB_PWRD
   PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 19, .Funcnum = 2} ); // P1.19 as USB_PPWR
 
+  // Enable host
   LPC_USB->USBClkCtrl = USBCLK_HOST;
   while ((LPC_USB->USBClkSt & USBCLK_HOST) != USBCLK_HOST);
   LPC_USB->OTGStCtrl = 0x3;
 #endif
 
 #if TUSB_OPT_DEVICE_ENABLED
-//  LPC_PINCON->PINSEL4 = bit_set_range(LPC_PINCON->PINSEL4, 18, 19, BIN8(01)); // P2_9 as USB Connect
+  // P2_9 as USB Connect
   Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1);
 
-#if 0
-  // P1_30 as VBUS, ignore if it is already in VBUS mode
-  if ( !(!BIT_TEST_(LPC_PINCON->PINSEL3, 28) && BIT_TEST_(LPC_PINCON->PINSEL3, 29)) )
-  {
-    // some board like lpcxpresso1769 does not connect VBUS signal to pin P1_30, this allow those board to overwrite
-    // by always pulling P1_30 to high
-    PINSEL_ConfigPin( &(PINSEL_CFG_Type) {
-      .Portnum = 1, .Pinnum = 30,
-      .Funcnum = 2, .Pinmode = PINSEL_PINMODE_PULLDOWN} );
-  }
-#endif
-
+  // Enable Device
   LPC_USB->USBClkCtrl = USBCLK_DEVCIE;
   while ((LPC_USB->USBClkSt & USBCLK_DEVCIE) != USBCLK_DEVCIE);
 #endif
-- 
cgit v1.3.1


From 7f55bbaf0522ba4dad55294c1a88fb6d60e5d7d4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 18:32:06 +0700
Subject: clean up

---
 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
index 3889e8104..e94670a92 100644
--- a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
+++ b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
@@ -130,12 +130,11 @@ static void sie_write (uint8_t cmd_code, uint8_t data_len, uint8_t data)
   }
 }
 
-static uint32_t sie_read (uint8_t cmd_code, uint8_t data_len)
+static uint8_t sie_read (uint8_t cmd_code)
 {
-  // TODO multiple read
   sie_cmd_code(SIE_CMDPHASE_COMMAND , cmd_code);
   sie_cmd_code(SIE_CMDPHASE_READ    , cmd_code);
-  return LPC_USB->CmdData;
+  return (uint8_t) LPC_USB->CmdData;
 }
 
 //--------------------------------------------------------------------+
@@ -353,8 +352,7 @@ bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
-  uint32_t const ep_state = sie_read(SIE_CMDCODE_ENDPOINT_SELECT +  ep_addr2idx(ep_addr), 1);
-
+  uint8_t const ep_state = sie_read(SIE_CMDCODE_ENDPOINT_SELECT +  ep_addr2idx(ep_addr));
   return (ep_state & SIE_SELECT_ENDPOINT_STALL_MASK) ? true : false;
 }
 
@@ -407,7 +405,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t t
     tu_memclr(dd, sizeof(dma_desc_t));
     dd->isochronous = is_iso;
     dd->max_packet_size = ep_size;
-    dd->buffer = buffer;
+    dd->buffer = (uint32_t) buffer;
     dd->buflen = total_bytes;
 
     _dcd.udca[ep_id] = dd;
@@ -440,7 +438,7 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
   // Control out complete
   if ( ep_int_status & BIT_(0) )
   {
-    bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0, 1) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
+    bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
 
     LPC_USB->EpIntClr = BIT_(0);
 
@@ -478,7 +476,7 @@ static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
 // handle bus event signal
 static void bus_event_isr(uint8_t rhport)
 {
-  uint8_t const dev_status = sie_read(SIE_CMDCODE_DEVICE_STATUS, 1);
+  uint8_t const dev_status = sie_read(SIE_CMDCODE_DEVICE_STATUS);
   if (dev_status & SIE_DEV_STATUS_RESET_MASK)
   {
     bus_reset();
@@ -583,7 +581,7 @@ void hal_dcd_isr(uint8_t rhport)
   // Errors
   if ( (dev_int_status & DEV_INT_ERROR_MASK) || (dma_int_status & DMA_INT_ERROR_MASK) )
   {
-    uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS, 1);
+    uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS);
     (void) error_status;
     TU_BREAKPOINT();
   }
-- 
cgit v1.3.1


From bb7123eed1c89cebefeaddd98fe96397ce4abf43 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 21:22:11 +0700
Subject: use lpcopen for ea4357, blinky ok

---
 .../cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject      | 131 +++++++-
 hw/bsp/ea4357/board_ea4357.c                       | 104 ++++--
 hw/bsp/ea4357/board_ea4357.h                       |  10 +-
 hw/bsp/ea4357/oem_base_board/pca9532.c             | 349 ---------------------
 hw/bsp/ea4357/oem_base_board/pca9532.h             |  94 ------
 src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c     |   3 +-
 6 files changed, 200 insertions(+), 491 deletions(-)
 delete mode 100644 hw/bsp/ea4357/oem_base_board/pca9532.c
 delete mode 100644 hw/bsp/ea4357/oem_base_board/pca9532.h

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject b/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject
index 363fae3e2..3cf3a6b52 100644
--- a/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject
+++ b/examples/device/cdc_msc_hid/ses/lpc43xx/lpc43xx.emProject
@@ -20,7 +20,7 @@
       arm_target_interface_type="SWD"
       build_treat_warnings_as_errors="Yes"
       c_preprocessor_definitions="CORE_M4;__LPC4300_FAMILY;__LPC435x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4357;CFG_TUSB_MCU=OPT_MCU_LPC43XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
-      c_user_include_directories="../../src;$(rootDir)/hw/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/CMSIS_LPC43xx_DriverLib/inc"
+      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)//inc;$(lpcDir)//inc/config_43xx"
       debug_register_definition_file="LPC43xx_Registers.xml"
       debug_target_connection="J-Link"
       gcc_entry_point="Reset_Handler"
@@ -28,7 +28,7 @@
       linker_memory_map_file="LPC4357 Cortex-M4_MemoryMap.xml"
       linker_section_placement_file="flash_placement.xml"
       linker_section_placements_segments="FLASH RX 0x1a000000 0x00080000;RAM RWX 0x10000000 0x00008000"
-      macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc43xx"
+      macros="DeviceFamily=LPC4300;DeviceSubFamily=LPC435x;Target=LPC4357 Cortex-M4;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_43xx"
       project_directory=""
       project_type="Executable"
       target_reset_script="Reset();"
@@ -47,24 +47,127 @@
         <folder Name="ea4357">
           <file file_name="../../../../../hw/bsp/ea4357/board_ea4357.c" />
           <file file_name="../../../../../hw/bsp/ea4357/board_ea4357.h" />
-          <folder Name="oem_base_board">
-            <file file_name="../../../../../hw/bsp/ea4357/oem_base_board/pca9532.c" />
-            <file file_name="../../../../../hw/bsp/ea4357/oem_base_board/pca9532.h" />
-          </folder>
+          <file file_name="../../../../../hw/bsp/ea4357/pca9532.c" />
+          <file file_name="../../../../../hw/bsp/ea4357/pca9532.h" />
         </folder>
       </folder>
       <folder Name="mcu">
         <folder Name="nxp">
-          <folder Name="lpc43xx">
-            <folder Name="CMSIS_LPC43xx_DriverLib">
-              <folder Name="src">
-                <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/system_LPC43xx.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpio.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_cgu.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_scu.c" />
-                <file file_name="../../../../../hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2c.c" />
+          <folder Name="lpc_chip_43xx">
+            <folder Name="inc">
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/adc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/aes_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/arm_common_tables.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/arm_math.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/atimer_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/ccan_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cguccu_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_clocks.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_lpc18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/chip_lpc43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/clock_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx_m0app.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/cmsis_43xx_m0sub.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm0.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm0plus.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm3.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm4.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cm4_simd.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_sc000.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/core_sc300.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/creg_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/dac_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/eeprom.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/eeprom_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/emc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/enet_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/error.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/evrt_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/fmc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/fpu_init.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/gima_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/gpdma_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/gpio_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/gpiogroup_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/hsadc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2c_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2c_common_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2cm_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/i2s_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/iap.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/iap_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/lcd_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/lpc_types.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/mcpwm_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/otp_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/packing.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/pinint_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/pmc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/qei_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/rgu_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/ring_buffer.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/ritimer_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/romapi_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/rtc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/rtc_ut.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sct_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sct_pwm_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/scu_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sdif_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sdio_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sdmmc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sdmmc_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/sgpio_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/spi_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/spifi_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/ssp_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/stopwatch.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/timer_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/uart_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/usbhs_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/wwdt_18xx_43xx.h" />
+              <folder Name="config_43xx">
+                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/config_43xx/cmsis_43xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/inc/config_43xx/sys_config.h" />
               </folder>
             </folder>
+            <folder Name="src">
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/chip_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/clock_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/fpu_init.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/gpdma_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/gpio_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/gpiogroup_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2c_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2cm_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/i2s_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/iap_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/lcd_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/otp_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/pinint_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/pmc_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/ring_buffer.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/ritimer_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/rtc_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sct_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sct_pwm_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sdif_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sdio_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sdmmc_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/spi_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/ssp_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/stopwatch_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/sysinit_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/timer_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/uart_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_43xx/src/wwdt_18xx_43xx.c" />
+            </folder>
           </folder>
         </folder>
       </folder>
diff --git a/hw/bsp/ea4357/board_ea4357.c b/hw/bsp/ea4357/board_ea4357.c
index a7b4caa2a..da06a63c1 100644
--- a/hw/bsp/ea4357/board_ea4357.c
+++ b/hw/bsp/ea4357/board_ea4357.c
@@ -36,10 +36,12 @@
 */
 /**************************************************************************/
 
+#ifdef BOARD_EA4357
+
 #include "bsp/board.h"
-#include "tusb.h"
+#include "pca9532.h"
 
-#ifdef BOARD_EA4357
+#include "tusb.h"
 
 #define BOARD_UART_PORT           LPC_USART0
 #define BOARD_UART_PIN_PORT       0x0f
@@ -88,31 +90,77 @@ uint32_t tusb_hal_millis(void)
 /*------------------------------------------------------------------*/
 /* BOARD API
  *------------------------------------------------------------------*/
-void board_init(void)
+
+/* System configuration variables used by chip driver */
+const uint32_t ExtRateIn = 0;
+const uint32_t OscRateIn = 12000000;
+
+static const PINMUX_GRP_T pinmuxing[] =
 {
-  CGU_Init();
+  /* RMII pin group */
+  {0x1, 19, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)}, //ENET_REF_CLK
+  {0x0,  1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, //ENET_TXEN
+  {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_TXD0
+  {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_TXD1
+  {0x1, 17, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_MDIO
+  {0xC,  1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_MDC
+  {0x1, 16, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)}, //ENET_RX_DV
+  {0x1, 15, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_RXD0
+  {0x0,  0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, //ENET_RXD1
+
+  /*  I2S  */
+  {0x3,  0,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)}, //I2S0_TX_CLK
+  {0xC, 12,  (SCU_PINIO_FAST | SCU_MODE_FUNC6)}, //I2S0_TX_SDA
+  {0xC, 13,  (SCU_PINIO_FAST | SCU_MODE_FUNC6)}, //I2S0_TX_WS
+  {0x6,  0,  (SCU_PINIO_FAST | SCU_MODE_FUNC4)}, //I2S0_RX_SCK
+  {0x6,  1,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //I2S0_RX_WS
+  {0x6,  2,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, //I2S0_RX_SDA
+};
 
-#if CFG_TUSB_OS == OPT_OS_NONE // TODO may move to main.c
-  SysTick_Config(CGU_GetPCLKFrequency(CGU_PERIPHERAL_M4CORE) / BOARD_TICKS_HZ); // 1 msec tick timer
-#endif
+/* Pin clock mux values, re-used structure, value in first index is meaningless */
+static const PINMUX_GRP_T pinclockmuxing[] =
+{
+  {0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+  {0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+  {0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+  {0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+};
 
-  //------------- USB -------------//
-  // USB0 Power: EA4357 channel B U20 GPIO26 active low (base board), P2_3 on LPC4357
-  scu_pinmux(0x02, 3, MD_PUP | MD_EZI, FUNC7);		// USB0 VBus Power
+// Invoked by startup code
+void SystemInit(void)
+{
+	/* Setup system level pin muxing */
+	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-  scu_pinmux(0x09, 5, GPIO_PDN, FUNC4); // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
-  GPIO_SetDir(5, BIT_(18), 1);
-  #endif
+	/* Clock pins only, group field not used */
+	for (int i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
+	{
+		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+	}
 
-  // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
-  // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
+  Chip_SetupXtalClocking();
+}
+
+void board_init(void)
+{
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config( SystemCoreClock / BOARD_TICKS_HZ );
+#endif
+
+  Chip_GPIO_Init(LPC_GPIO_PORT);
 
   //------------- LED -------------//
-  I2C_Init(LPC_I2C0, 100000);
-  I2C_Cmd(LPC_I2C0, ENABLE);
+  /* Init I2C */
+  Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
+  Chip_I2C_Init(I2C0);
+  Chip_I2C_SetClockRate(I2C0, 100000);
+  Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
+
   pca9532_init();
 
+#if 0
   //------------- BUTTON -------------//
   for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++)
   {
@@ -120,7 +168,6 @@ void board_init(void)
     GPIO_SetDir(buttons[i].gpio_port, BIT_(buttons[i].gpio_pin), 0);
   }
 
-#if 0
   //------------- UART -------------//
   scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
   scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
@@ -134,8 +181,19 @@ void board_init(void)
   UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
 #endif
 
-  //------------- NAND Flash (K9FXX) Size = 128M, Page Size = 2K, Block Size = 128K, Number of Block = 1024 -------------//
-//  nand_init();
+#if 0
+  //------------- USB -------------//
+  // USB0 Power: EA4357 channel B U20 GPIO26 active low (base board), P2_3 on LPC4357
+  scu_pinmux(0x02, 3, MD_PUP | MD_EZI, FUNC7);		// USB0 VBus Power
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  scu_pinmux(0x09, 5, GPIO_PDN, FUNC4); // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
+  GPIO_SetDir(5, BIT_(18), 1);
+  #endif
+#endif
+
+  // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
+  // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
 }
 
 //--------------------------------------------------------------------+
@@ -157,14 +215,14 @@ void board_led_control(bool state)
 //--------------------------------------------------------------------+
 static bool button_read(uint8_t id)
 {
-  return !BIT_TEST_( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
+//  return !BIT_TEST_( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
 }
 
 uint32_t board_buttons(void)
 {
   uint32_t result = 0;
 
-  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
+//  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
 
   return result;
 }
diff --git a/hw/bsp/ea4357/board_ea4357.h b/hw/bsp/ea4357/board_ea4357.h
index 87282718d..80ff678b5 100644
--- a/hw/bsp/ea4357/board_ea4357.h
+++ b/hw/bsp/ea4357/board_ea4357.h
@@ -43,15 +43,7 @@
  extern "C" {
 #endif
 
-#include "LPC43xx.h"
-#include "lpc43xx_scu.h"
-#include "lpc43xx_cgu.h"
-#include "lpc43xx_gpio.h"
-#include "lpc43xx_uart.h"
-#include "lpc43xx_i2c.h"
-
-// For LEDs
-#include "oem_base_board/pca9532.h"
+#include "chip.h"
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/ea4357/oem_base_board/pca9532.c b/hw/bsp/ea4357/oem_base_board/pca9532.c
deleted file mode 100644
index 7b526f670..000000000
--- a/hw/bsp/ea4357/oem_base_board/pca9532.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/*****************************************************************************
- *
- *   Copyright(C) 2011, Embedded Artists AB
- *   All rights reserved.
- *
- ******************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * Embedded Artists AB assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. Embedded Artists AB
- * reserves the right to make changes in the software without
- * notification. Embedded Artists AB also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- *****************************************************************************/
-
-/*
- * NOTE: I2C must have been initialized before calling any functions in this
- * file.
- */
-
-/******************************************************************************
- * Includes
- *****************************************************************************/
-#include "bsp/board.h"
-
-#ifdef BOARD_EA4357
-
-#include "lpc43xx_i2c.h"
-#include "lpc43xx_cgu.h"
-#include "lpc_types.h"
-#include "pca9532.h"
-
-/******************************************************************************
- * Defines and typedefs
- *****************************************************************************/
-
-#define I2C_PORT (LPC_I2C0)
-
-#define LS_MODE_ON     0x01
-#define LS_MODE_BLINK0 0x02
-#define LS_MODE_BLINK1 0x03
-
-/******************************************************************************
- * External global variables
- *****************************************************************************/
-
-
-/******************************************************************************
- * Local variables
- *****************************************************************************/
-
-static uint16_t blink0Shadow = 0;
-static uint16_t blink1Shadow = 0;
-static uint16_t ledStateShadow = 0;
-
-/******************************************************************************
- * Local Functions
- *****************************************************************************/
-
-static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
-{
-  I2C_M_SETUP_Type i2cData;
-
-	i2cData.sl_addr7bit = addr;
-	i2cData.tx_data = buf;
-	i2cData.tx_length = len;
-	i2cData.rx_data = NULL;
-	i2cData.rx_length = 0;
-	i2cData.retransmissions_max = 3;
-
-  return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
-}
-
-static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
-{
-  I2C_M_SETUP_Type i2cData;
-
-	i2cData.sl_addr7bit = addr;
-	i2cData.tx_data = NULL;
-	i2cData.tx_length = 0;
-	i2cData.rx_data = buf;
-	i2cData.rx_length = len;
-	i2cData.retransmissions_max = 3;
-
-  return I2C_MasterTransferData(I2C_PORT, &i2cData, I2C_TRANSFER_POLLING);
-}
-
-static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode)
-{
-#define IS_LED_SET(bit, x) ( ( ((x) & (bit)) != 0 ) ? 1 : 0 )
-
-    int i = 0;
-
-    for (i = 0; i < 4; i++) {
-
-        ls[i] |= ( (IS_LED_SET(0x0001, states)*mode << 0)
-                | (IS_LED_SET(0x0002, states)*mode << 2)
-                | (IS_LED_SET(0x0004, states)*mode << 4)
-                | (IS_LED_SET(0x0008, states)*mode << 6) );
-
-        states >>= 4;
-    }
-}
-
-static void setLeds(void)
-{
-    uint8_t buf[5];
-    uint8_t ls[4] = {0,0,0,0};
-    uint16_t states = ledStateShadow;
-
-    /* LEDs in On/Off state */
-    setLsStates(states, ls, LS_MODE_ON);
-
-    /* set the LEDs that should blink */
-    setLsStates(blink0Shadow, ls, LS_MODE_BLINK0);
-    setLsStates(blink1Shadow, ls, LS_MODE_BLINK1);
-
-
-    buf[0] = PCA9532_LS0 | PCA9532_AUTO_INC;
-    buf[1] = ls[0];
-    buf[2] = ls[1];
-    buf[3] = ls[2];
-    buf[4] = ls[3];
-    I2CWrite(PCA9532_I2C_ADDR, buf, 5);
-}
-
-/******************************************************************************
- * Public Functions
- *****************************************************************************/
-
-/******************************************************************************
- *
- * Description:
- *    Initialize the PCA9532 Device
- *
- *****************************************************************************/
-void pca9532_init (void)
-{
-    /* nothing to initialize */
-}
-
-/******************************************************************************
- *
- * Description:
- *    Get the LED states
- *
- * Params:
- *    [in]  shadow  - TRUE if the states should be retrieved from the shadow
- *                    variables. The shadow variable are updated when any
- *                    of setLeds, setBlink0Leds and/or setBlink1Leds are
- *                    called.
- *
- *                    FALSE if the state should be retrieved from the PCA9532
- *                    device. A blinkin LED may be reported as on or off
- *                    depending on the state when calling the function.
- *
- * Returns:
- *      A mask where a 1 indicates that a LED is on (or blinking).
- *
- *****************************************************************************/
-uint16_t pca9532_getLedState (uint32_t shadow)
-{
-    uint8_t buf[2];
-    uint16_t ret = 0;
-
-    if (shadow) {
-        /* a blink LED is reported as on*/
-        ret = (ledStateShadow | blink0Shadow | blink1Shadow);
-    }
-    else {
-
-        /*
-         * A blinking LED may be reported as on or off depending on
-         * its state when reading the Input register.
-         */
-
-        buf[0] = PCA9532_INPUT0;
-        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
-
-        I2CRead(PCA9532_I2C_ADDR, buf, 1);
-        ret = buf[0];
-
-
-        buf[0] = PCA9532_INPUT1;
-        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
-
-        I2CRead(PCA9532_I2C_ADDR, buf, 1);
-        ret |= (buf[0] << 8);
-
-
-        /* invert since LEDs are active low */
-        ret = ((~ret) & 0xFFFF);
-    }
-
-    return (ret & ~PCA9532_NOT_USED);
-}
-
-
-/******************************************************************************
- *
- * Description:
- *    Set LED states (on or off).
- *
- * Params:
- *    [in]  ledOnMask  - The LEDs that should be turned on. This mask has
- *                       priority over ledOffMask
- *    [in]  ledOffMask - The LEDs that should be turned off.
- *
- *****************************************************************************/
-void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask)
-{
-    /* turn off leds */
-    ledStateShadow &= (~(ledOffMask) & 0xffff);
-
-    /* ledOnMask has priority over ledOffMask */
-    ledStateShadow |= ledOnMask;
-
-    /* turn off blinking */
-    blink0Shadow &= (~(ledOffMask) & 0xffff);
-    blink1Shadow &= (~(ledOffMask) & 0xffff);
-
-    setLeds();
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the blink period for PWM0. Valid values are 0 - 255 where 0
- *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
- *
- * Params:
- *    [in]  period  - the period for pwm0
- *
- *****************************************************************************/
-void pca9532_setBlink0Period(uint8_t period)
-{
-    uint8_t buf[2];
-
-    buf[0] = PCA9532_PSC0;
-    buf[1] = period;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the duty cycle for PWM0. Valid values are 0 - 100. 25 means the LED
- *    is on 25% of the period.
- *
- * Params:
- *    [in]  duty  - duty cycle
- *
- *****************************************************************************/
-void pca9532_setBlink0Duty(uint8_t duty)
-{
-    uint8_t buf[2];
-    uint32_t tmp = duty;
-    if (tmp > 100) {
-        tmp = 100;
-    }
-
-    tmp = (256 * tmp)/100;
-
-    buf[0] = PCA9532_PWM0;
-    buf[1] = tmp;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the LEDs that should blink with rate and duty cycle from PWM0.
- *    Blinking is turned off with pca9532_setLeds.
- *
- * Params:
- *    [in]  ledMask  - LEDs that should blink.
- *
- *****************************************************************************/
-void pca9532_setBlink0Leds(uint16_t ledMask)
-{
-    blink0Shadow |= ledMask;
-    setLeds();
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the blink period for PWM1. Valid values are 0 - 255 where 0
- *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
- *
- * Params:
- *    [in]  period  - The period for PWM1
- *
- *****************************************************************************/
-void pca9532_setBlink1Period(uint8_t period)
-{
-    uint8_t buf[2];
-
-    buf[0] = PCA9532_PSC1;
-    buf[1] = period;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the duty cycle for PWM1. Valid values are 0 - 100. 25 means the LED
- *    is on 25% of the period.
- *
- * Params:
- *    [in]  duty  - duty cycle.
- *
- *****************************************************************************/
-void pca9532_setBlink1Duty(uint8_t duty)
-{
-    uint8_t buf[2];
-
-    uint32_t tmp = duty;
-    if (tmp > 100) {
-        tmp = 100;
-    }
-
-    tmp = (256 * tmp)/100;
-
-    buf[0] = PCA9532_PWM1;
-    buf[1] = tmp;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the LEDs that should blink with rate and duty cycle from PWM1.
- *    Blinking is turned off with pca9532_setLeds.
- *
- * Params:
- *    [in]  ledMask  - LEDs that should blink.
- *
- *****************************************************************************/
-void pca9532_setBlink1Leds(uint16_t ledMask)
-{
-    blink1Shadow |= ledMask;
-    setLeds();
-}
-
-#endif
diff --git a/hw/bsp/ea4357/oem_base_board/pca9532.h b/hw/bsp/ea4357/oem_base_board/pca9532.h
deleted file mode 100644
index 885075326..000000000
--- a/hw/bsp/ea4357/oem_base_board/pca9532.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*****************************************************************************
- *
- *   Copyright(C) 2011, Embedded Artists AB
- *   All rights reserved.
- *
- ******************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * Embedded Artists AB assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. Embedded Artists AB
- * reserves the right to make changes in the software without
- * notification. Embedded Artists AB also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- *****************************************************************************/
-#ifndef __PCA9532C_H
-#define __PCA9532C_H
-
-
-#define PCA9532_I2C_ADDR    (0x60)
-
-#define PCA9532_INPUT0 0x00
-#define PCA9532_INPUT1 0x01
-#define PCA9532_PSC0   0x02
-#define PCA9532_PWM0   0x03
-#define PCA9532_PSC1   0x04
-#define PCA9532_PWM1   0x05
-#define PCA9532_LS0    0x06
-#define PCA9532_LS1    0x07
-#define PCA9532_LS2    0x08
-#define PCA9532_LS3    0x09
-
-#define PCA9532_AUTO_INC 0x10
-
-
-/*
- * The Keys on the base board are mapped to LED0 -> LED3 on
- * the PCA9532.
- */
-
-#define KEY1 0x0001
-#define KEY2 0x0002
-#define KEY3 0x0004
-#define KEY4 0x0008
-
-#define KEY_MASK 0x000F
-
-/*
- * MMC Card Detect and MMC Write Protect are mapped to LED4
- * and LED5 on the PCA9532. Please note that WP is active low.
- */
-
-#define MMC_CD 0x0010
-#define MMC_WP 0x0020
-
-#define MMC_MASK  0x30
-
-/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */
-#define PCA9532_NOT_USED 0xC0
-
-/*
- * Below are the LED constants to use when enabling/disabling a LED.
- * The LED names are the names printed on the base board and not
- * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532,
- * base_LED2 -> LED9, and so on.
- */
-
-#define LED1 0x0100
-#define LED2 0x0200
-#define LED3 0x0400
-#define LED4 0x0800
-#define LED5 0x1000
-#define LED6 0x2000
-#define LED7 0x4000
-#define LED8 0x8000
-
-#define LED_MASK 0xFF00
-
-void pca9532_init (void);
-uint16_t pca9532_getLedState (uint32_t shadow);
-void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask);
-void pca9532_setBlink0Period(uint8_t period);
-void pca9532_setBlink0Duty(uint8_t duty);
-void pca9532_setBlink0Leds(uint16_t ledMask);
-void pca9532_setBlink1Period(uint8_t period);
-void pca9532_setBlink1Duty(uint8_t duty);
-void pca9532_setBlink1Leds(uint16_t ledMask);
-
-#endif /* end __PCA9532C_H */
-/****************************************************************************
-**                            End Of File
-*****************************************************************************/
diff --git a/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
index 213b8dd99..07c7a0ca8 100644
--- a/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
+++ b/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
@@ -40,8 +40,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC43XX
 
-#include "LPC43xx.h"
-#include "lpc43xx_cgu.h"
+#include "chip.h"
 
 enum {
   LPC43XX_USBMODE_DEVICE = 2,
-- 
cgit v1.3.1


From 9fec39d893083e6a2dd15eb9b08bc5978c7726e2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 22:58:21 +0700
Subject: use lpcopen for lpc43x, work well

---
 hw/bsp/ea4357/board_ea4357.c                   | 24 ++++++------------------
 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c | 21 +++++++++------------
 src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c | 18 ++++--------------
 3 files changed, 19 insertions(+), 44 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/ea4357/board_ea4357.c b/hw/bsp/ea4357/board_ea4357.c
index da06a63c1..754b68aa1 100644
--- a/hw/bsp/ea4357/board_ea4357.c
+++ b/hw/bsp/ea4357/board_ea4357.c
@@ -41,8 +41,6 @@
 #include "bsp/board.h"
 #include "pca9532.h"
 
-#include "tusb.h"
-
 #define BOARD_UART_PORT           LPC_USART0
 #define BOARD_UART_PIN_PORT       0x0f
 #define BOARD_UART_PIN_TX         10 // PF.10 : UART0_TXD
@@ -97,16 +95,7 @@ const uint32_t OscRateIn = 12000000;
 
 static const PINMUX_GRP_T pinmuxing[] =
 {
-  /* RMII pin group */
-  {0x1, 19, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)}, //ENET_REF_CLK
-  {0x0,  1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)}, //ENET_TXEN
-  {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_TXD0
-  {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_TXD1
-  {0x1, 17, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_MDIO
-  {0xC,  1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_MDC
-  {0x1, 16, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)}, //ENET_RX_DV
-  {0x1, 15, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)}, //ENET_RXD0
-  {0x0,  0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)}, //ENET_RXD1
+  // USB
 
   /*  I2S  */
   {0x3,  0,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)}, //I2S0_TX_CLK
@@ -181,16 +170,15 @@ void board_init(void)
   UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
 #endif
 
-#if 0
   //------------- USB -------------//
-  // USB0 Power: EA4357 channel B U20 GPIO26 active low (base board), P2_3 on LPC4357
-  scu_pinmux(0x02, 3, MD_PUP | MD_EZI, FUNC7);		// USB0 VBus Power
+  // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
+  Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
 
   #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-  scu_pinmux(0x09, 5, GPIO_PDN, FUNC4); // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
-  GPIO_SetDir(5, BIT_(18), 1);
+  // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
+  Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
   #endif
-#endif
 
   // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
   // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
diff --git a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
index 66ca04b71..90e13a6c1 100644
--- a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
+++ b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
@@ -50,9 +50,7 @@
 #include "device/dcd.h"
 #include "dcd_lpc43xx.h"
 
-#include "LPC43xx.h"
-#include "lpc43xx_cgu.h"
-
+#include "chip.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -74,7 +72,7 @@ CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
 CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
 #endif
 
-static LPC_USB0_Type * const LPC_USB[2] = { LPC_USB0, ((LPC_USB0_Type*) LPC_USB1_BASE) };
+static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
 
 static dcd_data_t* const dcd_data_ptr[2] =
 {
@@ -112,19 +110,18 @@ void dcd_set_config(uint8_t rhport, uint8_t config_num)
 /// follows LPC43xx User Manual 23.10.3
 static void bus_reset(uint8_t rhport)
 {
-  LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
+  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
 
   // The reset value for all endpoint types is the control endpoint. If one endpoint
   // direction is enabled and the paired endpoint of opposite direction is disabled, then the
   // endpoint type of the unused direction must bechanged from the control type to any other
   // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
   // for the data PID tracking on the active endpoint.
-  lpc_usb->ENDPTCTRL1 = lpc_usb->ENDPTCTRL2 = lpc_usb->ENDPTCTRL3 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
 
-  // USB1 only has 3 non-control endpoints
-  if ( rhport == 0)
+  // USB0 has 5 but USB1 only has 3 non-control endpoints
+  for( int i=1; i < (rhport ? 6 : 4); i++)
   {
-    lpc_usb->ENDPTCTRL4 = lpc_usb->ENDPTCTRL5 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
+    lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
   }
 
   //------------- Clear All Registers -------------//
@@ -156,7 +153,7 @@ static void bus_reset(uint8_t rhport)
 
 bool dcd_init(uint8_t rhport)
 {
-  LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
+  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
   dcd_data_t* p_dcd = dcd_data_ptr[rhport];
 
   tu_memclr(p_dcd, sizeof(dcd_data_t));
@@ -203,7 +200,7 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
 
 static inline volatile uint32_t * get_endpt_ctrl_reg(uint8_t rhport, uint8_t ep_idx)
 {
- return &(LPC_USB[rhport]->ENDPTCTRL0) + ep_idx/2;
+ return &(LPC_USB[rhport]->ENDPTCTRL[0]) + ep_idx/2;
 }
 
 //--------------------------------------------------------------------+
@@ -321,7 +318,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 //--------------------------------------------------------------------+
 void hal_dcd_isr(uint8_t rhport)
 {
-  LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
+  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
 
   uint32_t const int_enable = lpc_usb->USBINTR_D;
   uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
diff --git a/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
index 07c7a0ca8..4c13e568d 100644
--- a/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
+++ b/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
@@ -80,14 +80,9 @@ static void hal_controller_reset(uint8_t rhport)
 
 bool tusb_hal_init(void)
 {
-  LPC_CREG->CREG0 &= ~(1<<5); /* Turn on the phy */
-
-  //------------- USB0 -------------//
+  // USB0
 #if CFG_TUSB_RHPORT0_MODE
-  CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
-  TU_VERIFY( CGU_ERROR_SUCCESS == CGU_SetPLL0()); /* the usb core require output clock = 480MHz */
-  CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
-  CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);   /* Enable PLL after all setting is done */
+  Chip_USB0_Init();
 
   // reset controller & set role
   hal_controller_reset(0);
@@ -103,14 +98,9 @@ bool tusb_hal_init(void)
   #endif
 #endif
 
-  //------------- USB1 -------------//
+  // USB1
 #if CFG_TUSB_RHPORT1_MODE
-  // Host require to config P2_5, TODO confirm whether device mode require P2_5 or not
-  scu_pinmux(0x2, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);	// USB1_VBUS monitor presence, must be high for bus reset occur
-
-  /* connect CLK_USB1 to 60 MHz clock */
-  CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_USB1); /* FIXME Run base BASE_USB1_CLK clock from PLL1 (assume PLL1 is 60 MHz, no division required) */
-  LPC_SCU->SFSUSB = (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST) ? 0x16 : 0x12; // enable USB1 with on-chip FS PHY
+  Chip_USB1_Init();
 
   hal_controller_reset(1);
 
-- 
cgit v1.3.1


From 29f721ba2c1f22427501a6cc0437c2ed4a35c630 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 23:06:28 +0700
Subject: dcd lpc43 clean up

---
 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c | 27 ++++++--------------------
 1 file changed, 6 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
index 90e13a6c1..2ed7c55b7 100644
--- a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
+++ b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
@@ -45,7 +45,6 @@
 //--------------------------------------------------------------------+
 #include "common/tusb_common.h"
 #include "tusb_hal.h"
-#include "osal/osal.h"
 
 #include "device/dcd.h"
 #include "dcd_lpc43xx.h"
@@ -198,11 +197,6 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
   }
 }
 
-static inline volatile uint32_t * get_endpt_ctrl_reg(uint8_t rhport, uint8_t ep_idx)
-{
- return &(LPC_USB[rhport]->ENDPTCTRL[0]) + ep_idx/2;
-}
-
 //--------------------------------------------------------------------+
 // DCD Endpoint Port
 //--------------------------------------------------------------------+
@@ -212,15 +206,13 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir    = edpt_dir(ep_addr);
   uint8_t const ep_idx = 2*epnum + dir;
 
-  volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
-
   if ( epnum == 0)
   {
     // Stall both Control IN and OUT
-    (*endpt_ctrl) |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
+    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
   }else
   {
-    (*endpt_ctrl) |= ENDPTCTRL_MASK_STALL << (ep_idx & 0x01 ? 16 : 0);
+    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (ep_idx & 0x01 ? 16 : 0);
   }
 }
 
@@ -236,11 +228,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir    = edpt_dir(ep_addr);
   uint8_t const ep_idx = 2*epnum + dir;
 
-  volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
-
   // data toggle also need to be reset
-  (*endpt_ctrl) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0);
-  (*endpt_ctrl) &= ~(ENDPTCTRL_MASK_STALL << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0));
+  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0);
+  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0));
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -261,13 +251,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
   p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
 
-  //------------- Endpoint Control Register -------------//
-  volatile uint32_t * endpt_ctrl = get_endpt_ctrl_reg(rhport, ep_idx);
-
-  // endpoint must not be already enabled
-  TU_VERIFY( !( (*endpt_ctrl) &  (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
-
-  (*endpt_ctrl) |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
+  // Enable EP Control
+  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
 
   return true;
 }
-- 
cgit v1.3.1


From 1d6bbd9990c666b7a7e5c9e14f484f86fe49a9c8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Dec 2018 23:14:05 +0700
Subject: clean up dcd 43

---
 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c | 40 +++++++++-----------------
 1 file changed, 14 insertions(+), 26 deletions(-)

(limited to 'src')

diff --git a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
index 2ed7c55b7..49a69e297 100644
--- a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
+++ b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
@@ -54,10 +54,6 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
 typedef struct {
   dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
   dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
@@ -103,7 +99,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 
 void dcd_set_config(uint8_t rhport, uint8_t config_num)
 {
-
+  // nothing to do
 }
 
 /// follows LPC43xx User Manual 23.10.3
@@ -147,7 +143,6 @@ static void bus_reset(uint8_t rhport)
 	p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
 
 	p_dcd->qhd[0].int_on_setup = 1; // OUT only
-
 }
 
 bool dcd_init(uint8_t rhport)
@@ -204,7 +199,6 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const epnum  = edpt_number(ep_addr);
   uint8_t const dir    = edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
 
   if ( epnum == 0)
   {
@@ -212,25 +206,26 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
     LPC_USB[rhport]->ENDPTCTRL[epnum] |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
   }else
   {
-    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (ep_idx & 0x01 ? 16 : 0);
+    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
   }
 }
 
-// TOOD implement later
 bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
 {
-  return false;
+  uint8_t const epnum  = edpt_number(ep_addr);
+  uint8_t const dir    = edpt_dir(ep_addr);
+
+  return LPC_USB[rhport]->ENDPTCTRL[epnum] & (ENDPTCTRL_MASK_STALL << (dir ? 16 : 0));
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const epnum  = edpt_number(ep_addr);
   uint8_t const dir    = edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
 
   // data toggle also need to be reset
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0);
-  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0));
+  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
+  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir  ? 16 : 0));
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -297,7 +292,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   return true;
 }
 
-
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
@@ -315,19 +309,17 @@ void hal_dcd_isr(uint8_t rhport)
   if (int_status & INT_MASK_RESET)
   {
     bus_reset(rhport);
-
-    dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
-    dcd_event_handler(&event, true);
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
   }
 
   if (int_status & INT_MASK_SUSPEND)
   {
     if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
-    { // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+    {
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
       if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
       {
-        dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPENDED };
-        dcd_event_handler(&event, true);
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
       }
     }
   }
@@ -355,10 +347,7 @@ void hal_dcd_isr(uint8_t rhport)
       // 23.10.10.2 Operational model for setup transfers
       lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
 
-      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
-      event.setup_received = p_dcd->qhd[0].setup_request;
-
-      dcd_event_handler(&event, true);
+      dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
     }
 
     if ( edpt_complete )
@@ -383,8 +372,7 @@ void hal_dcd_isr(uint8_t rhport)
 
   if (int_status & INT_MASK_SOF)
   {
-    dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
-    dcd_event_handler(&event, true);
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
 
   if (int_status & INT_MASK_NAK) {}
-- 
cgit v1.3.1


From bf5ac608ffda592ef13d8aa7f2873bccc867891c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Dec 2018 12:47:58 +0700
Subject: rename dcd 18 43

---
 src/portable/nxp/lpc18_43/dcd_lpc18_43.c       | 381 ++++++++++++++++++++++++
 src/portable/nxp/lpc18_43/dcd_lpc18_43.h       | 160 +++++++++++
 src/portable/nxp/lpc18_43/hal_lpc18_43.c       | 154 ++++++++++
 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c | 382 -------------------------
 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.h | 160 -----------
 src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c | 154 ----------
 6 files changed, 695 insertions(+), 696 deletions(-)
 create mode 100644 src/portable/nxp/lpc18_43/dcd_lpc18_43.c
 create mode 100644 src/portable/nxp/lpc18_43/dcd_lpc18_43.h
 create mode 100644 src/portable/nxp/lpc18_43/hal_lpc18_43.c
 delete mode 100644 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
 delete mode 100644 src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.h
 delete mode 100644 src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c

(limited to 'src')

diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
new file mode 100644
index 000000000..a611bc081
--- /dev/null
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
@@ -0,0 +1,381 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc43xx.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_LPC43XX
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "common/tusb_common.h"
+#include "tusb_hal.h"
+
+#include "device/dcd.h"
+#include "dcd_lpc43xx.h"
+
+#include "chip.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+typedef struct {
+  dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
+  dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
+}dcd_data_t;
+
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
+#endif
+
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
+#endif
+
+static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
+
+static dcd_data_t* const dcd_data_ptr[2] =
+{
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
+  &dcd_data0,
+#else
+  NULL,
+#endif
+
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  &dcd_data1
+#else
+  NULL
+#endif
+};
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+void dcd_connect(uint8_t rhport)
+{
+  LPC_USB[rhport]->USBCMD_D |= BIT_(0);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  // nothing to do
+}
+
+/// follows LPC43xx User Manual 23.10.3
+static void bus_reset(uint8_t rhport)
+{
+  LPC_USBHS_T* lpc_usb = LPC_USB[rhport];
+
+  // The reset value for all endpoint types is the control endpoint. If one endpoint
+  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
+  // endpoint type of the unused direction must bechanged from the control type to any other
+  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
+  // for the data PID tracking on the active endpoint.
+
+  // USB0 has 5 but USB1 only has 3 non-control endpoints
+  for( int i=1; i < (rhport ? 6 : 4); i++)
+  {
+    lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
+  }
+
+  //------------- Clear All Registers -------------//
+  lpc_usb->ENDPTNAK       = lpc_usb->ENDPTNAK;
+  lpc_usb->ENDPTNAKEN     = 0;
+  lpc_usb->USBSTS_D       = lpc_usb->USBSTS_D;
+  lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
+  lpc_usb->ENDPTCOMPLETE  = lpc_usb->ENDPTCOMPLETE;
+
+  while (lpc_usb->ENDPTPRIME);
+  lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
+  while (lpc_usb->ENDPTFLUSH);
+
+  // read reset bit in portsc
+
+  //------------- Queue Head & Queue TD -------------//
+  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
+  tu_memclr(p_dcd, sizeof(dcd_data_t));
+
+  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
+	p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
+	p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE;
+	p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
+
+	p_dcd->qhd[0].int_on_setup = 1; // OUT only
+}
+
+bool dcd_init(uint8_t rhport)
+{
+  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
+  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
+
+  tu_memclr(p_dcd, sizeof(dcd_data_t));
+
+  lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
+  lpc_usb->USBSTS_D  = lpc_usb->USBSTS_D;
+  lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
+
+  lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
+  lpc_usb->USBCMD_D |= BIT_(0); // connect
+
+  // enable interrupt
+  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// HELPER
+//--------------------------------------------------------------------+
+// index to bit position in register
+static inline uint8_t ep_idx2bit(uint8_t ep_idx)
+{
+  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
+}
+
+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
+{
+  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+
+  p_qtd->next        = QTD_NEXT_INVALID;
+  p_qtd->active      = 1;
+  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+  if (data_ptr != NULL)
+  {
+    p_qtd->buffer[0]   = (uint32_t) data_ptr;
+    for(uint8_t i=1; i<5; i++)
+    {
+      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = edpt_number(ep_addr);
+  uint8_t const dir    = edpt_dir(ep_addr);
+
+  if ( epnum == 0)
+  {
+    // Stall both Control IN and OUT
+    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
+  }else
+  {
+    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
+  }
+}
+
+bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = edpt_number(ep_addr);
+  uint8_t const dir    = edpt_dir(ep_addr);
+
+  return LPC_USB[rhport]->ENDPTCTRL[epnum] & (ENDPTCTRL_MASK_STALL << (dir ? 16 : 0));
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = edpt_number(ep_addr);
+  uint8_t const dir    = edpt_dir(ep_addr);
+
+  // data toggle also need to be reset
+  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
+  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir  ? 16 : 0));
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  // TODO USB1 only has 4 non-control enpoint (USB0 has 5)
+  // TODO not support ISO yet
+  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
+
+  uint8_t const epnum  = edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir    = edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  //------------- Prepare Queue Head -------------//
+  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
+  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
+
+  p_qhd->zero_length_termination = 1;
+  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
+  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
+
+  // Enable EP Control
+  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
+
+  return true;
+}
+
+bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = edpt_number(ep_addr);
+  uint8_t const dir    = edpt_dir(ep_addr);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
+  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
+
+  return p_qtd->active;
+//  return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = edpt_number(ep_addr);
+  uint8_t const dir   = edpt_dir(ep_addr);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  if ( epnum == 0 )
+  {
+    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
+    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
+    while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
+  }
+
+  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
+  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
+
+  //------------- Prepare qtd -------------//
+  qtd_init(p_qtd, buffer, total_bytes);
+  p_qtd->int_on_complete = true;
+  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+
+  // start transfer
+  LPC_USB[rhport]->ENDPTPRIME = BIT_( ep_idx2bit(ep_idx) ) ;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void hal_dcd_isr(uint8_t rhport)
+{
+  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
+
+  uint32_t const int_enable = lpc_usb->USBINTR_D;
+  uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
+  lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
+
+  if (int_status == 0) return;// disabled interrupt sources
+
+
+  if (int_status & INT_MASK_RESET)
+  {
+    bus_reset(rhport);
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  if (int_status & INT_MASK_SUSPEND)
+  {
+    if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
+    {
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
+      {
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
+      }
+    }
+  }
+
+  // TODO disconnection does not generate interrupt !!!!!!
+//	if (int_status & INT_MASK_PORT_CHANGE)
+//	{
+//	  if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
+//	  {
+//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
+//      dcd_event_handler(&event, true);
+//	  }
+//	}
+
+  if (int_status & INT_MASK_USB)
+  {
+    uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
+    lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
+
+    dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
+
+    if (lpc_usb->ENDPTSETUPSTAT)
+    {
+      //------------- Set up Received -------------//
+      // 23.10.10.2 Operational model for setup transfers
+      lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
+
+      dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
+    }
+
+    if ( edpt_complete )
+    {
+      for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
+      {
+        if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
+        {
+          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+          dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
+          dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
+
+          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
+              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
+
+          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
+          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
+        }
+      }
+    }
+  }
+
+  if (int_status & INT_MASK_SOF)
+  {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (int_status & INT_MASK_NAK) {}
+  if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
+}
+
+#endif
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h b/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
new file mode 100644
index 000000000..cd54cae7c
--- /dev/null
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
@@ -0,0 +1,160 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc43xx.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+/** \ingroup group_dcd
+ *  \defgroup group_dcd_lpc143xx LPC43xx
+ *  @{ */
+
+#ifndef _TUSB_DCD_LPC43XX_H_
+#define _TUSB_DCD_LPC43XX_H_
+
+#include "common/tusb_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+#define DCD_QHD_MAX 12
+#define DCD_QTD_MAX 12
+
+#define QTD_NEXT_INVALID 0x01
+
+/*---------- ENDPTCTRL ----------*/
+enum {
+  ENDPTCTRL_MASK_STALL          = BIT_(0),
+  ENDPTCTRL_MASK_TOGGLE_INHIBIT = BIT_(5), ///< used for test only
+  ENDPTCTRL_MASK_TOGGLE_RESET   = BIT_(6),
+  ENDPTCTRL_MASK_ENABLE         = BIT_(7)
+};
+
+/*---------- USBCMD ----------*/
+enum {
+  USBCMD_MASK_RUN_STOP         = BIT_(0),
+  USBCMD_MASK_RESET            = BIT_(1),
+  USBCMD_MASK_SETUP_TRIPWIRE   = BIT_(13),
+  USBCMD_MASK_ADD_QTD_TRIPWIRE = BIT_(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
+};
+// Interrupt Threshold bit 23:16
+
+/*---------- USBSTS, USBINTR ----------*/
+enum {
+  INT_MASK_USB         = BIT_(0),
+  INT_MASK_ERROR       = BIT_(1),
+  INT_MASK_PORT_CHANGE = BIT_(2),
+  INT_MASK_RESET       = BIT_(6),
+  INT_MASK_SOF         = BIT_(7),
+  INT_MASK_SUSPEND     = BIT_(8),
+  INT_MASK_NAK         = BIT_(16)
+};
+
+//------------- PORTSC -------------//
+enum {
+  PORTSC_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
+  PORTSC_FORCE_PORT_RESUME_MASK      = BIT_(6),
+  PORTSC_SUSPEND_MASK                = BIT_(7)
+};
+
+typedef struct
+{
+  // Word 0: Next QTD Pointer
+  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
+
+  // Word 1: qTQ Token
+  uint32_t                      : 3  ;
+  volatile uint32_t xact_err    : 1  ;
+  uint32_t                      : 1  ;
+  volatile uint32_t buffer_err  : 1  ;
+  volatile uint32_t halted      : 1  ;
+  volatile uint32_t active      : 1  ;
+  uint32_t                      : 2  ;
+  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
+  uint32_t                      : 3  ;
+  uint32_t int_on_complete      : 1  ;
+  volatile uint32_t total_bytes : 15 ;
+  uint32_t                      : 0  ;
+
+  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
+  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
+
+  //------------- DCD Area -------------//
+  uint16_t expected_bytes;
+  uint8_t reserved[2];
+} dcd_qtd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
+
+typedef struct
+{
+  // Word 0: Capabilities and Characteristics
+  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
+  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
+  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
+  uint32_t                         : 2  ;
+  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
+  uint32_t iso_mult                : 2  ; ///<
+  uint32_t                         : 0  ;
+
+  // Word 1: Current qTD Pointer
+	volatile uint32_t qtd_addr;
+
+	// Word 2-9: Transfer Overlay
+	volatile dcd_qtd_t qtd_overlay;
+
+	// Word 10-11: Setup request (control OUT only)
+	volatile tusb_control_request_t setup_request;
+
+	//--------------------------------------------------------------------+
+  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
+	/// thus there are 16 bytes padding free that we can make use of.
+  //--------------------------------------------------------------------+
+	uint8_t reserved[16];
+}  dcd_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_DCD_LPC43XX_H_ */
+
+/** @} */
diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
new file mode 100644
index 000000000..76bd56b20
--- /dev/null
+++ b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
@@ -0,0 +1,154 @@
+/**************************************************************************/
+/*!
+    @file     hal_lpc43xx.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "tusb.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX
+
+#include "chip.h"
+
+enum {
+  LPC43XX_USBMODE_DEVICE = 2,
+  LPC43XX_USBMODE_HOST   = 3
+};
+
+enum {
+  LPC43XX_USBMODE_VBUS_LOW  = 0,
+  LPC43XX_USBMODE_VBUS_HIGH = 1
+};
+
+void tusb_hal_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
+}
+
+void tusb_hal_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
+}
+
+
+static void hal_controller_reset(uint8_t rhport)
+{ // TODO timeout expired to prevent trap
+  volatile uint32_t * p_reg_usbcmd;
+
+  p_reg_usbcmd = (rhport ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
+// NXP chip powered with non-host mode --> sts bit is not correctly reflected
+  (*p_reg_usbcmd) |= BIT_(1);
+
+//  tu_timeout_t timeout;
+//  tu_timeout_set(&timeout, 2); // should not take longer the time to stop controller
+  while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !tu_timeout_expired(&timeout)*/) {}
+//
+//  return tu_timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
+}
+
+bool tusb_hal_init(void)
+{
+  // USB0
+#if CFG_TUSB_RHPORT0_MODE
+  Chip_USB0_Init();
+
+  // reset controller & set role
+  hal_controller_reset(0);
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
+  #else // TODO OTG
+    LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
+    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+    #if CFG_TUD_FULLSPEED // TODO for easy testing
+      LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
+    #endif
+  #endif
+#endif
+
+  // USB1
+#if CFG_TUSB_RHPORT1_MODE
+  Chip_USB1_Init();
+
+  hal_controller_reset(1);
+
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
+  #else // TODO OTG
+    LPC_USB1->USBMODE_D = LPC43XX_USBMODE_DEVICE;
+  #endif
+
+  LPC_USB1->PORTSC1_D |= (1<<24); // TODO abstract, force rhport to fullspeed
+#endif
+
+  return true;
+}
+
+void hal_dcd_isr(uint8_t rhport);
+
+#if CFG_TUSB_RHPORT0_MODE
+void USB0_IRQHandler(void)
+{
+  #if MODE_HOST_SUPPORTED
+    hal_hcd_isr(0);
+  #endif
+
+  #if TUSB_OPT_DEVICE_ENABLED
+    hal_dcd_isr(0);
+  #endif
+}
+#endif
+
+#if CFG_TUSB_RHPORT1_MODE
+void USB1_IRQHandler(void)
+{
+  #if MODE_HOST_SUPPORTED
+    hal_hcd_isr(1);
+  #endif
+
+  #if TUSB_OPT_DEVICE_ENABLED
+    hal_dcd_isr(1);
+  #endif
+}
+#endif
+
+
+void check_failed(uint8_t *file, uint32_t line)
+{
+  (void) file;
+  (void) line;
+}
+
+#endif
diff --git a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
deleted file mode 100644
index 49a69e297..000000000
--- a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc43xx.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_LPC43XX
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "tusb_hal.h"
-
-#include "device/dcd.h"
-#include "dcd_lpc43xx.h"
-
-#include "chip.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-typedef struct {
-  dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
-  dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
-}dcd_data_t;
-
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data0;
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(2048) static dcd_data_t dcd_data1;
-#endif
-
-static LPC_USBHS_T * const LPC_USB[2] = { LPC_USB0, LPC_USB1 };
-
-static dcd_data_t* const dcd_data_ptr[2] =
-{
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  &dcd_data0,
-#else
-  NULL,
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  &dcd_data1
-#else
-  NULL
-#endif
-};
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-void dcd_connect(uint8_t rhport)
-{
-  LPC_USB[rhport]->USBCMD_D |= BIT_(0);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-  // nothing to do
-}
-
-/// follows LPC43xx User Manual 23.10.3
-static void bus_reset(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-
-  // The reset value for all endpoint types is the control endpoint. If one endpoint
-  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
-  // endpoint type of the unused direction must bechanged from the control type to any other
-  // type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
-  // for the data PID tracking on the active endpoint.
-
-  // USB0 has 5 but USB1 only has 3 non-control endpoints
-  for( int i=1; i < (rhport ? 6 : 4); i++)
-  {
-    lpc_usb->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
-  }
-
-  //------------- Clear All Registers -------------//
-  lpc_usb->ENDPTNAK       = lpc_usb->ENDPTNAK;
-  lpc_usb->ENDPTNAKEN     = 0;
-  lpc_usb->USBSTS_D       = lpc_usb->USBSTS_D;
-  lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
-  lpc_usb->ENDPTCOMPLETE  = lpc_usb->ENDPTCOMPLETE;
-
-  while (lpc_usb->ENDPTPRIME);
-  lpc_usb->ENDPTFLUSH = 0xFFFFFFFF;
-  while (lpc_usb->ENDPTFLUSH);
-
-  // read reset bit in portsc
-
-  //------------- Queue Head & Queue TD -------------//
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-	p_dcd->qhd[0].zero_length_termination = p_dcd->qhd[1].zero_length_termination = 1;
-	p_dcd->qhd[0].max_package_size = p_dcd->qhd[1].max_package_size = CFG_TUD_ENDOINT0_SIZE;
-	p_dcd->qhd[0].qtd_overlay.next = p_dcd->qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
-
-	p_dcd->qhd[0].int_on_setup = 1; // OUT only
-}
-
-bool dcd_init(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-  dcd_data_t* p_dcd = dcd_data_ptr[rhport];
-
-  tu_memclr(p_dcd, sizeof(dcd_data_t));
-
-  lpc_usb->ENDPOINTLISTADDR = (uint32_t) p_dcd->qhd; // Endpoint List Address has to be 2K alignment
-  lpc_usb->USBSTS_D  = lpc_usb->USBSTS_D;
-  lpc_usb->USBINTR_D = INT_MASK_USB | INT_MASK_ERROR | INT_MASK_PORT_CHANGE | INT_MASK_RESET | INT_MASK_SUSPEND | INT_MASK_SOF;
-
-  lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
-  lpc_usb->USBCMD_D |= BIT_(0); // connect
-
-  // enable interrupt
-  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// HELPER
-//--------------------------------------------------------------------+
-// index to bit position in register
-static inline uint8_t ep_idx2bit(uint8_t ep_idx)
-{
-  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
-}
-
-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
-{
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
-
-  p_qtd->next        = QTD_NEXT_INVALID;
-  p_qtd->active      = 1;
-  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-  if (data_ptr != NULL)
-  {
-    p_qtd->buffer[0]   = (uint32_t) data_ptr;
-    for(uint8_t i=1; i<5; i++)
-    {
-      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = edpt_number(ep_addr);
-  uint8_t const dir    = edpt_dir(ep_addr);
-
-  if ( epnum == 0)
-  {
-    // Stall both Control IN and OUT
-    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ( (ENDPTCTRL_MASK_STALL << 16) || (ENDPTCTRL_MASK_STALL << 0) );
-  }else
-  {
-    LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_STALL << (dir ? 16 : 0);
-  }
-}
-
-bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = edpt_number(ep_addr);
-  uint8_t const dir    = edpt_dir(ep_addr);
-
-  return LPC_USB[rhport]->ENDPTCTRL[epnum] & (ENDPTCTRL_MASK_STALL << (dir ? 16 : 0));
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = edpt_number(ep_addr);
-  uint8_t const dir    = edpt_dir(ep_addr);
-
-  // data toggle also need to be reset
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_MASK_TOGGLE_RESET << ( dir ? 16 : 0 );
-  LPC_USB[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_MASK_STALL << ( dir  ? 16 : 0));
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  // TODO USB1 only has 4 non-control enpoint (USB0 has 5)
-  // TODO not support ISO yet
-  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
-  uint8_t const epnum  = edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir    = edpt_dir(p_endpoint_desc->bEndpointAddress);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
-
-  p_qhd->zero_length_termination = 1;
-  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
-  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
-
-  // Enable EP Control
-  LPC_USB[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
-
-  return true;
-}
-
-bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = edpt_number(ep_addr);
-  uint8_t const dir    = edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-  return p_qtd->active;
-//  return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = edpt_number(ep_addr);
-  uint8_t const dir   = edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
-
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(LPC_USB[rhport]->ENDPTSETUPSTAT & BIT_(0)) {}
-  }
-
-  dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-  dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-  //------------- Prepare qtd -------------//
-  qtd_init(p_qtd, buffer, total_bytes);
-  p_qtd->int_on_complete = true;
-  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
-
-  // start transfer
-  LPC_USB[rhport]->ENDPTPRIME = BIT_( ep_idx2bit(ep_idx) ) ;
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void hal_dcd_isr(uint8_t rhport)
-{
-  LPC_USBHS_T* const lpc_usb = LPC_USB[rhport];
-
-  uint32_t const int_enable = lpc_usb->USBINTR_D;
-  uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
-  lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;// disabled interrupt sources
-
-
-  if (int_status & INT_MASK_RESET)
-  {
-    bus_reset(rhport);
-    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
-  }
-
-  if (int_status & INT_MASK_SUSPEND)
-  {
-    if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
-    {
-      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
-      {
-        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
-      }
-    }
-  }
-
-  // TODO disconnection does not generate interrupt !!!!!!
-//	if (int_status & INT_MASK_PORT_CHANGE)
-//	{
-//	  if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
-//	  {
-//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
-//      dcd_event_handler(&event, true);
-//	  }
-//	}
-
-  if (int_status & INT_MASK_USB)
-  {
-    uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
-    lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
-
-    dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
-
-    if (lpc_usb->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
-
-      dcd_event_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request, true);
-    }
-
-    if ( edpt_complete )
-    {
-      for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
-      {
-        if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
-        {
-          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-          dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
-          dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ep_idx];
-
-          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
-              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
-        }
-      }
-    }
-  }
-
-  if (int_status & INT_MASK_SOF)
-  {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  if (int_status & INT_MASK_NAK) {}
-  if (int_status & INT_MASK_ERROR) TU_ASSERT(false, );
-}
-
-#endif
diff --git a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.h b/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.h
deleted file mode 100644
index 85334a34d..000000000
--- a/src/portable/nxp/lpc43xx_lpc18xx/dcd_lpc43xx.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc43xx.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-/** \ingroup group_dcd
- *  \defgroup group_dcd_lpc143xx LPC43xx
- *  @{ */
-
-#ifndef _TUSB_DCD_LPC43XX_H_
-#define _TUSB_DCD_LPC43XX_H_
-
-#include "common/tusb_common.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-#define DCD_QHD_MAX 12
-#define DCD_QTD_MAX 12
-
-#define QTD_NEXT_INVALID 0x01
-
-/*---------- ENDPTCTRL ----------*/
-enum {
-  ENDPTCTRL_MASK_STALL          = BIT_(0),
-  ENDPTCTRL_MASK_TOGGLE_INHIBIT = BIT_(5), ///< used for test only
-  ENDPTCTRL_MASK_TOGGLE_RESET   = BIT_(6),
-  ENDPTCTRL_MASK_ENABLE         = BIT_(7)
-};
-
-/*---------- USBCMD ----------*/
-enum {
-  USBCMD_MASK_RUN_STOP         = BIT_(0),
-  USBCMD_MASK_RESET            = BIT_(1),
-  USBCMD_MASK_SETUP_TRIPWIRE   = BIT_(13),
-  USBCMD_MASK_ADD_QTD_TRIPWIRE = BIT_(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-};
-// Interrupt Threshold bit 23:16
-
-/*---------- USBSTS, USBINTR ----------*/
-enum {
-  INT_MASK_USB         = BIT_(0),
-  INT_MASK_ERROR       = BIT_(1),
-  INT_MASK_PORT_CHANGE = BIT_(2),
-  INT_MASK_RESET       = BIT_(6),
-  INT_MASK_SOF         = BIT_(7),
-  INT_MASK_SUSPEND     = BIT_(8),
-  INT_MASK_NAK         = BIT_(16)
-};
-
-//------------- PORTSC -------------//
-enum {
-  PORTSC_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
-  PORTSC_FORCE_PORT_RESUME_MASK      = BIT_(6),
-  PORTSC_SUSPEND_MASK                = BIT_(7)
-};
-
-typedef struct
-{
-  // Word 0: Next QTD Pointer
-  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
-
-  // Word 1: qTQ Token
-  uint32_t                      : 3  ;
-  volatile uint32_t xact_err    : 1  ;
-  uint32_t                      : 1  ;
-  volatile uint32_t buffer_err  : 1  ;
-  volatile uint32_t halted      : 1  ;
-  volatile uint32_t active      : 1  ;
-  uint32_t                      : 2  ;
-  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
-  uint32_t                      : 3  ;
-  uint32_t int_on_complete      : 1  ;
-  volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 0  ;
-
-  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
-
-  //------------- DCD Area -------------//
-  uint16_t expected_bytes;
-  uint8_t reserved[2];
-} dcd_qtd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
-
-typedef struct
-{
-  // Word 0: Capabilities and Characteristics
-  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
-  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
-  uint32_t                         : 2  ;
-  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
-  uint32_t iso_mult                : 2  ; ///<
-  uint32_t                         : 0  ;
-
-  // Word 1: Current qTD Pointer
-	volatile uint32_t qtd_addr;
-
-	// Word 2-9: Transfer Overlay
-	volatile dcd_qtd_t qtd_overlay;
-
-	// Word 10-11: Setup request (control OUT only)
-	volatile tusb_control_request_t setup_request;
-
-	//--------------------------------------------------------------------+
-  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
-	/// thus there are 16 bytes padding free that we can make use of.
-  //--------------------------------------------------------------------+
-	uint8_t reserved[16];
-}  dcd_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
-
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC43XX_H_ */
-
-/** @} */
diff --git a/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c b/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
deleted file mode 100644
index 4c13e568d..000000000
--- a/src/portable/nxp/lpc43xx_lpc18xx/hal_lpc43xx.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_lpc43xx.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb.h"
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX
-
-#include "chip.h"
-
-enum {
-  LPC43XX_USBMODE_DEVICE = 2,
-  LPC43XX_USBMODE_HOST   = 3
-};
-
-enum {
-  LPC43XX_USBMODE_VBUS_LOW  = 0,
-  LPC43XX_USBMODE_VBUS_HIGH = 1
-};
-
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-
-static void hal_controller_reset(uint8_t rhport)
-{ // TODO timeout expired to prevent trap
-  volatile uint32_t * p_reg_usbcmd;
-
-  p_reg_usbcmd = (rhport ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
-// NXP chip powered with non-host mode --> sts bit is not correctly reflected
-  (*p_reg_usbcmd) |= BIT_(1);
-
-//  tu_timeout_t timeout;
-//  tu_timeout_set(&timeout, 2); // should not take longer the time to stop controller
-  while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !tu_timeout_expired(&timeout)*/) {}
-//
-//  return tu_timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
-}
-
-bool tusb_hal_init(void)
-{
-  // USB0
-#if CFG_TUSB_RHPORT0_MODE
-  Chip_USB0_Init();
-
-  // reset controller & set role
-  hal_controller_reset(0);
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
-    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-    #if CFG_TUD_FULLSPEED // TODO for easy testing
-      LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
-    #endif
-  #endif
-#endif
-
-  // USB1
-#if CFG_TUSB_RHPORT1_MODE
-  Chip_USB1_Init();
-
-  hal_controller_reset(1);
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB1->USBMODE_D = LPC43XX_USBMODE_DEVICE;
-  #endif
-
-  LPC_USB1->PORTSC1_D |= (1<<24); // TODO abstract, force rhport to fullspeed
-#endif
-
-  return true;
-}
-
-void hal_dcd_isr(uint8_t rhport);
-
-#if CFG_TUSB_RHPORT0_MODE
-void USB0_IRQHandler(void)
-{
-  #if MODE_HOST_SUPPORTED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-#endif
-
-#if CFG_TUSB_RHPORT1_MODE
-void USB1_IRQHandler(void)
-{
-  #if MODE_HOST_SUPPORTED
-    hal_hcd_isr(1);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(1);
-  #endif
-}
-#endif
-
-
-void check_failed(uint8_t *file, uint32_t line)
-{
-  (void) file;
-  (void) line;
-}
-
-#endif
-- 
cgit v1.3.1


From 7120e12971800606d934ad2d9ff985a01eb0e9ee Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Dec 2018 13:17:12 +0700
Subject: add mcb1800, blink led ok

---
 .../device/cdc_msc_hid/ses/cdc_msc_hid.emProject   |     1 +
 .../cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s      |   110 +
 .../cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js      |    19 +
 .../cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml  |     7 +
 .../cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml  | 30452 +++++++++++++++++++
 .../cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s      |   516 +
 .../cdc_msc_hid/ses/lpc18xx/flash_placement.xml    |    37 +
 .../cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject      |   129 +
 .../device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s    |   415 +
 hw/bsp/board.h                                     |    17 +-
 hw/bsp/ea4357/board_ea4357.c                       |     6 +-
 hw/bsp/mcb1800/board_mcb1800.c                     |   399 +
 hw/bsp/mcb1800/board_mcb1800.h                     |    51 +
 src/portable/nxp/lpc18_43/dcd_lpc18_43.c           |     4 +-
 src/portable/nxp/lpc18_43/hal_lpc18_43.c           |     9 +-
 15 files changed, 32150 insertions(+), 22 deletions(-)
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s
 create mode 100644 hw/bsp/mcb1800/board_mcb1800.c
 create mode 100644 hw/bsp/mcb1800/board_mcb1800.h

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
index 0be56bcfd..4da3d9d67 100644
--- a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
+++ b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
@@ -7,4 +7,5 @@
   <import file_name="lpc175x_6x/lpc175x_6x.emProject" />
   <import file_name="lpc13xx/lpc13xx.emProject" />
   <import file_name="lpc11u6x/lpc11u6x.emProject" />
+  <import file_name="lpc18xx/lpc18xx.emProject" />
 </solution>
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s
new file mode 100644
index 000000000..e17b60508
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Startup.s
@@ -0,0 +1,110 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                         Preprocessor Definitions                          *
+ *                         ------------------------                          *
+ * NO_STACK_INIT                                                             *
+ *                                                                           *
+ *   If defined, the stack pointer will not be initialised.                  *
+ *                                                                           *
+ * NO_SYSTEM_INIT                                                            *
+ *                                                                           *
+ *   If defined, the SystemInit() function will not be called. By default    *
+ *   SystemInit() is called after reset to enable the clocks and memories to *
+ *   be initialised prior to any C startup initialisation.                   *
+ *                                                                           *
+ * NO_VTOR_CONFIG                                                            *
+ *                                                                           *
+ *   If defined, the vector table offset register will not be configured.    *
+ *                                                                           *
+ * MEMORY_INIT                                                               *
+ *                                                                           *
+ *   If defined, the MemoryInit() function will be called. By default        *
+ *   MemoryInit() is called after SystemInit() to enable an external memory  *
+ *   controller.                                                             *
+ *                                                                           *
+ * STACK_INIT_VAL                                                            *
+ *                                                                           *
+ *   If defined, specifies the initial stack pointer value. If undefined,    *
+ *   the stack pointer will be initialised to point to the end of the        *
+ *   RAM segment.                                                            *
+ *                                                                           *
+ * VECTORS_IN_RAM                                                            *
+ *                                                                           *
+ *   If defined, the exception vectors will be copied from Flash to RAM.     *
+ *                                                                           *
+ *****************************************************************************/
+
+  .syntax unified
+
+  .global Reset_Handler
+  .extern _vectors
+
+  .section .init, "ax"
+  .thumb_func
+
+  .equ VTOR_REG, 0xE000ED08
+
+#ifndef STACK_INIT_VAL
+#define STACK_INIT_VAL __RAM_segment_end__
+#endif
+
+Reset_Handler:
+#ifndef NO_STACK_INIT
+  /* Initialise main stack */
+  ldr r0, =STACK_INIT_VAL
+  bic r0, #0x7
+  mov sp, r0
+#endif
+
+#ifndef NO_SYSTEM_INIT
+  /* Initialise system */
+  ldr r0, =SystemInit
+  blx r0
+#endif
+
+#ifdef MEMORY_INIT
+  ldr r0, =MemoryInit
+  blx r0
+#endif
+
+#ifdef VECTORS_IN_RAM
+  /* Copy exception vectors into RAM */
+  ldr r0, =__vectors_start__
+  ldr r1, =__vectors_end__
+  ldr r2, =__vectors_ram_start__
+1:
+  cmp r0, r1
+  beq 2f
+  ldr r3, [r0]
+  str r3, [r2]
+  adds r0, r0, #4
+  adds r2, r2, #4
+  b 1b
+2:
+#endif
+
+#ifndef NO_VTOR_CONFIG
+  /* Configure vector table offset register */
+  ldr r0, =VTOR_REG
+#ifdef VECTORS_IN_RAM
+  ldr r1, =_vectors_ram
+#else
+  ldr r1, =_vectors
+#endif
+  str r1, [r0]
+#endif
+
+  /* Jump to program start */
+  b _start
+
+
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js
new file mode 100644
index 000000000..20560af43
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1800_Target.js
@@ -0,0 +1,19 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+function Reset() {
+  TargetInterface.resetAndStop();
+}
+
+function EnableTrace(traceInterfaceType) {
+  // TODO: Enable trace
+}
+
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml
new file mode 100644
index 000000000..4ded8a9f3
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC1857_MemoryMap.xml
@@ -0,0 +1,7 @@
+<!DOCTYPE Board_Memory_Definition_File>
+<root name="LPC1857">
+  <MemorySegment name="RAM" start="0x10000000" size="0x00008000" access="Read/Write" />
+  <MemorySegment name="FLASH" start="0x1A000000" size="0x00080000" access="ReadOnly" />
+  <MemorySegment name="FLASH2" start="0x1B000000" size="0x00080000" access="ReadOnly" />
+  <MemorySegment name="RAM2" start="0x20000000" size="0x00010000" access="Read/Write" />
+</root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml
new file mode 100644
index 000000000..5e68d4c0f
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Registers.xml
@@ -0,0 +1,30452 @@
+<!DOCTYPE Register_Definition_File>
+<Processor name="LPC18xx" description="Register cmsis file for LPC18xx parts">
+  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
+    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
+        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
+        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
+      </BitField>
+      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
+        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
+        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
+        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
+      </BitField>
+      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
+        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
+      </BitField>
+      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
+      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
+      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
+      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
+      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
+      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
+      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
+      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
+      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
+        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
+        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
+      </BitField>
+      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
+      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
+      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
+      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
+      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
+      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
+        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
+        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
+      </BitField>
+      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
+      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
+    </Register>
+    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
+      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
+    </Register>
+    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="STATE_L" description="State variable." />
+      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="5" name="STATE_H" description="State variable." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
+      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
+      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
+      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
+      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
+      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
+      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
+      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
+      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
+      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
+      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
+      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
+      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
+      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
+      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
+      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
+    </Register>
+    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+    </Register>
+    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
+        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+    </Register>
+    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
+      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
+    </Register>
+    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
+      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
+    </Register>
+    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
+      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
+    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
+        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
+        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
+        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
+      </BitField>
+      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
+        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
+        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
+      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
+      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
+      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
+      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
+        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
+        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
+      </BitField>
+      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
+        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
+        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
+      </BitField>
+      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
+        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
+        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
+      </BitField>
+      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
+        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
+        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
+      </BitField>
+      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
+        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
+        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
+      </BitField>
+      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
+    </Register>
+    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
+      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
+      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
+        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
+        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
+      </BitField>
+      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
+      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
+        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
+        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
+        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
+        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
+      </BitField>
+      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
+        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
+        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
+        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
+        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
+        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
+        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
+        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
+      </BitField>
+      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
+    </Register>
+    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ADDRESS" description="Address." />
+    </Register>
+    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
+    </Register>
+    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
+    </Register>
+    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="Input or output data" />
+    </Register>
+    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
+      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
+      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
+      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
+        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
+        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
+        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
+        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
+      </BitField>
+      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
+        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
+        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
+        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
+        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
+        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
+        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
+      </BitField>
+      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
+    </Register>
+    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
+      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
+      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
+      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
+      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
+        <Enum name="NO_CHANGE" start="0" description="No change." />
+        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
+      </BitField>
+      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
+        <Enum name="NO_CHANGE" start="0" description="No change." />
+        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
+      </BitField>
+      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
+        <Enum name="NO_CHANGE" start="0" description="No change." />
+        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
+        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
+        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
+      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
+        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
+        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
+      </BitField>
+      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
+        <Enum name="NO_CHANGE" start="0" description="No change" />
+        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
+      </BitField>
+      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
+        <Enum name="NO_CHANGE" start="0" description="No change" />
+        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
+      </BitField>
+      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
+        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
+        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
+      </BitField>
+      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
+        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
+        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
+      </BitField>
+      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
+      </BitField>
+      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
+      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
+      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
+      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
+      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
+        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
+        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
+      </BitField>
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
+      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
+      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
+      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
+      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
+      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
+      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
+    </Register>
+    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
+      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
+        <Enum name="NONE" start="0" description="None. No response expected from card" />
+        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
+      </BitField>
+      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
+        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
+        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
+      </BitField>
+      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
+        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
+        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
+      </BitField>
+      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
+        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
+        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
+      </BitField>
+      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
+        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
+        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
+      </BitField>
+      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
+        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
+        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
+      </BitField>
+      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
+        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
+        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
+      </BitField>
+      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
+        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
+        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
+      </BitField>
+      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
+        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
+        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
+      </BitField>
+      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
+        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
+        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
+      </BitField>
+      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
+      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
+        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
+        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
+      </BitField>
+      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
+        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
+        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
+      </BitField>
+      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
+      </BitField>
+      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
+      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
+      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
+      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
+        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
+        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
+      </BitField>
+      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
+        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
+        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
+      </BitField>
+      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
+    </Register>
+    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
+    </Register>
+    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
+    </Register>
+    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
+    </Register>
+    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
+    </Register>
+    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
+      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
+      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
+      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
+      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
+      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
+      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
+      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
+      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
+      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
+      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
+      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
+      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
+    </Register>
+    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
+      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
+        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
+        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
+        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
+        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
+        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
+        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
+        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
+        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
+      </BitField>
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
+    </Register>
+    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
+    </Register>
+    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
+      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
+      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
+      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
+      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
+        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
+        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
+        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
+        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
+        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
+        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
+        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
+        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
+    </Register>
+    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
+    </Register>
+    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
+      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
+      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
+      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
+      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
+      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
+      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
+      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
+      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
+      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
+      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
+    </Register>
+    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
+    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
+      </BitField>
+      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
+        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
+        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
+        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
+        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
+        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
+        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
+        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
+        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
+      </BitField>
+      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
+        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
+        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM" description="Endian mode.">
+        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
+        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
+      </BitField>
+      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
+        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
+        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
+        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
+        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
+        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
+        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
+        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
+        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
+        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
+        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
+      </BitField>
+      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RD" description="Read data strategy.">
+        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
+        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
+        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
+        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
+    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
+      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
+      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
+      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
+      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
+      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
+      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
+      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
+      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
+      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
+      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
+      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
+      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
+      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
+      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
+        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
+      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
+      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
+      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
+        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
+      </BitField>
+      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
+      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
+      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
+        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
+      </BitField>
+      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
+        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
+      </BitField>
+      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
+        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
+        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
+        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
+        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
+      <BitField start="6" size="1" name="URI" description="USB reset received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
+      </BitField>
+      <BitField start="8" size="1" name="SLI" description="DCSuspend">
+        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
+        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
+        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
+      </BitField>
+      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
+      </BitField>
+      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="HCH" description="HCHalted">
+        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
+        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
+      </BitField>
+      <BitField start="13" size="1" name="RCL" description="Reclamation">
+        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
+        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
+      </BitField>
+      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
+        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
+      </BitField>
+      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
+        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
+      </BitField>
+      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
+      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
+      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
+      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
+      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
+      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
+        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
+        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
+      </BitField>
+      <BitField start="25" size="7" name="USBADR" description="USB device address" />
+    </Register>
+    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
+    </Register>
+    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="RESERVED" description="reserved" />
+      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
+    </Register>
+    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
+    </Register>
+    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
+      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
+      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
+      <BitField start="13" size="3" name="RESERVED" description="reserved" />
+      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status">
+        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
+        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
+      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
+      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
+        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
+        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
+        <Enum name="OFF" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="amber" />
+        <Enum name="GREEN" start="0x2" description="green" />
+        <Enum name="UNDEFINED" start="0x3" description="undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
+        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
+        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
+        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
+        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
+        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
+        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
+        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
+      </BitField>
+      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
+        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
+        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
+        <Enum name="NO_CHANGE_" start="0" description="No change." />
+        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
+      </BitField>
+      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
+        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
+        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
+      </BitField>
+      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
+      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status">
+        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
+        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
+        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
+        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
+        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
+        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
+      </BitField>
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
+        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="Amber" />
+        <Enum name="GREEN" start="0x2" description="Green" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
+      </BitField>
+      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
+        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
+      </BitField>
+      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
+        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
+      </BitField>
+      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
+        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
+      </BitField>
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
+        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
+        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
+        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
+        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
+        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
+      </BitField>
+    </Register>
+    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
+      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
+      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
+      </BitField>
+      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
+      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
+      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
+        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
+        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
+      </BitField>
+      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
+      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
+      </BitField>
+      <BitField start="8" size="1" name="ID" description="USB ID">
+        <Enum name="A_DEVICE" start="0" description="A-device" />
+        <Enum name="B_DEVICE" start="1" description="B-device" />
+      </BitField>
+      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
+      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
+      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
+      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
+      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
+      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
+      <BitField start="15" size="1" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
+      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
+      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
+      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
+      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
+      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
+      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
+      <BitField start="23" size="1" name="RESERVED" description="reserved" />
+      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
+      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
+        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
+        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
+      </BitField>
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="26" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
+      </BitField>
+      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
+        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
+        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="6" size="26" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="reserved" />
+      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="20" size="3" name="RESERVED" description="reserved" />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
+    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
+      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
+      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
+      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
+      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
+      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
+      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
+      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
+      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
+      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
+      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
+      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
+      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
+      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
+      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
+      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
+        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
+      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
+      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
+      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
+        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
+      </BitField>
+      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
+      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
+      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
+        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
+      </BitField>
+      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
+        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
+      </BitField>
+      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
+        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
+        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
+        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
+        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="6" size="1" name="URI" description="USB reset received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
+      </BitField>
+      <BitField start="8" size="1" name="SLI" description="DCSuspend">
+        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
+        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
+        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
+      </BitField>
+      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
+      </BitField>
+      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
+      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="HCH" description="HCHalted">
+        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
+        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
+      </BitField>
+      <BitField start="13" size="1" name="RCL" description="Reclamation">
+        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
+        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
+      </BitField>
+      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
+        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
+      </BitField>
+      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
+        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
+      </BitField>
+      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
+      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
+      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
+      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
+      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
+      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
+      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="reserved" />
+      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
+        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
+        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
+      </BitField>
+      <BitField start="25" size="7" name="USBADR" description="USB device address" />
+    </Register>
+    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
+    </Register>
+    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="RESERVED" description="reserved" />
+      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
+    </Register>
+    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
+    </Register>
+    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
+      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
+      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
+      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
+      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
+      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
+      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
+      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
+        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
+        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
+      </BitField>
+      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
+        <Enum name="READ" start="0" description="Read" />
+        <Enum name="WRITE" start="1" description="Write" />
+      </BitField>
+      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
+      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
+    </Register>
+    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BINT" description="bInterval value" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status">
+        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
+        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
+      </BitField>
+      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
+      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
+      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
+        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
+        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
+      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
+        <Enum name="OFF" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="amber" />
+        <Enum name="GREEN" start="0x2" description="green" />
+        <Enum name="UNDEFINED" start="0x3" description="undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
+        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
+        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
+        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
+        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
+        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
+      </BitField>
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
+        <Enum name="ULPI" start="0x2" description="ULPI" />
+        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
+      </BitField>
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
+        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
+        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
+      </BitField>
+      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
+        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
+        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
+        <Enum name="NO_CHANGE_" start="0" description="No change." />
+        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
+      </BitField>
+      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
+        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
+        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
+      </BitField>
+      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
+      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status">
+        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
+        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
+        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
+        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
+        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
+        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
+      </BitField>
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
+        <Enum name="OFF" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="Amber" />
+        <Enum name="GREEN" start="0x2" description="Green" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
+      </BitField>
+      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
+        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
+      </BitField>
+      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
+        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
+      </BitField>
+      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
+        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
+        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
+      </BitField>
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
+        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
+        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
+        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
+        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
+        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
+      </BitField>
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
+        <Enum name="ULPI" start="0x2" description="ULPI" />
+        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
+      </BitField>
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
+        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
+        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
+      </BitField>
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
+      </BitField>
+      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
+        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
+        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
+    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
+      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
+      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
+      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
+    </Register>
+    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
+      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
+      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
+      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
+    </Register>
+    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
+      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
+      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
+      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
+      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
+      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
+      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
+      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
+      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
+      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
+    </Register>
+    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
+      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
+      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
+      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
+      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
+      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
+      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
+      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
+      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
+      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
+      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
+      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
+      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
+      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
+      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
+      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
+      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
+      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
+      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
+      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
+      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
+      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
+      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
+    </Register>
+    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
+      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
+      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RED" description="Red color component" />
+      <BitField start="8" size="8" name="GREEN" description="Green color component" />
+      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RED" description="Red color component" />
+      <BitField start="8" size="8" name="GREEN" description="Green color component" />
+      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
+    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
+      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
+      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
+      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
+      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
+    </Register>
+    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="INTEN" access="WriteOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFEC" size="4" name="INTSTATSET" access="WriteOnly" description="EEPROM interrupt status set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_SET_ST" description="Set program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
+    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
+      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
+      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
+      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
+      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
+      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
+      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
+      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
+      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
+      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
+      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
+      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
+      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
+      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
+      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
+      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
+      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
+      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
+      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
+      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
+      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
+      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
+      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
+    </Register>
+    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
+    </Register>
+    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
+    </Register>
+    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
+      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
+      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M3_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M3_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
+      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
+      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
+      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
+      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
+      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
+      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
+    </Register>
+    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
+      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
+      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
+      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
+      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
+      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
+      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
+      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
+      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
+      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
+    </Register>
+    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
+      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
+      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
+      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
+      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
+      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
+      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
+    </Register>
+    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
+      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
+      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
+      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="MO" description="Always 1" />
+    </Register>
+    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
+    </Register>
+    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
+      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
+      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
+      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
+      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
+      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
+      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
+      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
+      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
+      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
+      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
+      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
+      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
+      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
+      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
+    </Register>
+    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
+    </Register>
+    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
+      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
+    </Register>
+    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
+    </Register>
+    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
+      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
+    </Register>
+    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
+    </Register>
+    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
+    </Register>
+    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
+      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
+      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
+      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
+      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
+      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
+      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
+      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
+      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
+      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
+      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
+      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
+      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
+      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
+    </Register>
+    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
+    </Register>
+    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
+    </Register>
+    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
+    </Register>
+    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
+      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
+      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
+      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
+      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
+      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
+      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
+      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
+      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
+      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
+      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
+      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
+      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
+      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
+      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
+      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
+      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
+      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
+      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
+      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
+      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
+      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
+      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
+      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
+      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
+      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
+      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
+      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
+      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
+      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
+      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
+      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
+      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
+      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
+      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
+      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
+      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
+      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
+      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
+      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
+      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
+      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
+      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
+      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
+    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
+    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
+    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M3 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register" />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
+    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
+        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
+        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
+        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
+        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
+        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
+        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
+      </BitField>
+      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
+        <Enum name="POWERED" start="0" description="Powered." />
+        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
+        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
+        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
+      </BitField>
+      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
+        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
+        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="INACTIVE" start="0x3" description="Inactive." />
+      </BitField>
+      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the  data sheet for the trip values.">
+        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
+        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
+        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
+        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
+      </BitField>
+      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the  data sheet for the trip values.">
+        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
+        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
+        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
+        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
+      </BitField>
+      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
+        <Enum name="RESERVED" start="0x0" description="Reserved" />
+        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
+        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
+        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
+        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
+      </BitField>
+      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
+        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
+        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
+      </BitField>
+      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="M3MEMMAP" access="Read/Write" description="ARM Cortex-M3 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
+      <BitField start="12" size="20" name="M3MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
+    </Register>
+    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="1" name="M3TAPSEL" description="JTAG debug disable for M3 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect." />
+        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
+        <Enum name="SPIFI" start="0x0" description="SPIFI" />
+        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
+      </BitField>
+      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
+        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
+        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
+        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
+        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
+      </BitField>
+      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
+        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
+        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
+        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
+        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
+      </BitField>
+      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
+        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
+        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
+        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
+        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
+      </BitField>
+      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
+        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
+        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
+        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
+      </BitField>
+      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
+        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
+        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
+        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
+      </BitField>
+      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
+        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
+        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
+        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
+      </BitField>
+      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
+        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
+        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
+        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
+      </BitField>
+      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
+        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
+        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
+        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
+      </BitField>
+      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
+        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
+        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
+        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
+      </BitField>
+      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
+        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
+        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
+      </BitField>
+      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
+        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
+        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
+      </BitField>
+      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
+        <Enum name="ADC0" start="0x0" description="ADC0" />
+        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
+        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
+      </BitField>
+      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
+        <Enum name="ADC1" start="0x0" description="ADC1" />
+        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
+        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
+      </BitField>
+      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
+        <Enum name="DAC" start="0x0" description="DAC" />
+        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
+        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
+      </BitField>
+    </Register>
+    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
+      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
+        <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." />
+        <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." />
+        <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." />
+        <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." />
+        <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." />
+        <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." />
+        <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." />
+        <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." />
+        <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." />
+      </BitField>
+      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
+      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
+        <Enum name="POWER_DOWN" start="0" description="Power-down" />
+        <Enum name="ACTIVE" start="1" description="Active (Default)" />
+      </BitField>
+    </Register>
+    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
+      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M3_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
+        <Enum name="1_BASE_M3_CLK_CLOCK" start="0x0" description="1 BASE_M3_CLK clock. Use for BASE_M3_CLK up to 21 MHz." />
+        <Enum name="2_BASE_M3_CLK_CLOCKS" start="0x1" description="2 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 43 MHz." />
+        <Enum name="3_BASE_M3_CLK_CLOCKS" start="0x2" description="3 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 64 MHz." />
+        <Enum name="4_BASE_M3_CLK_CLOCKS" start="0x3" description="4 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 86 MHz." />
+        <Enum name="5_BASE_M3_CLK_CLOCKS" start="0x4" description="5 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 107 MHz." />
+        <Enum name="6_BASE_M3_CLK_CLOCKS" start="0x5" description="6 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 129 MHz." />
+        <Enum name="7_BASE_M3_CLK_CLOCKS" start="0x6" description="7 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 150 MHz." />
+        <Enum name="8_BASE_M3_CLK_CLOCKS" start="0x7" description="8 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 172 MHz." />
+        <Enum name="9_BASE_M3_CLK_CLOCKS" start="0x8" description="9 BASE_M3_CLK clocks. Use for BASE_M3_CLK up to 180 MHz." />
+      </BitField>
+      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
+      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
+        <Enum name="POWER_DOWN" start="0" description="Power-down" />
+        <Enum name="ACTIVE" start="1" description="Active (Default)" />
+      </BitField>
+    </Register>
+    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
+        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
+        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
+        <Enum name="MII" start="0x0" description="MII" />
+        <Enum name="RMII" start="0x4" description="RMII" />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
+        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
+        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
+      </BitField>
+      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
+        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
+        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
+      </BitField>
+      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5284 E02B or 0x6284 E02B = LPC1850/30/20/10&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;(flashless parts)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;0x4284 E02B = LPC1857/53 (parts with on-chip flash)" />
+    </Register>
+    <Register start="+0x500" size="4" name="USB0FLADJ" access="None" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
+    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
+        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
+        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
+        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
+      </BitField>
+      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
+      </BitField>
+      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
+      </BitField>
+      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
+      </BitField>
+      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
+      </BitField>
+      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
+      </BitField>
+      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
+      </BitField>
+      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
+      </BitField>
+      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
+      </BitField>
+      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
+      </BitField>
+      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
+      </BitField>
+      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
+      </BitField>
+      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
+      </BitField>
+      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
+      </BitField>
+      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
+      </BitField>
+      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
+      </BitField>
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
+      </BitField>
+      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
+      </BitField>
+      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
+      </BitField>
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
+      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
+      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
+      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
+      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
+      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
+      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
+      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
+      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
+      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
+      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
+      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
+      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
+      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
+      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
+      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
+      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
+      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
+      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
+      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
+      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
+      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
+      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
+      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
+      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
+      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
+      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
+      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
+      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
+      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
+      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
+      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
+      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
+      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
+      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
+      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
+      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
+      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
+      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
+      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
+      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
+      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
+      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
+      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
+      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
+      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
+      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
+      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
+      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
+      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
+      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
+      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
+      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
+      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
+      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
+      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
+      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
+      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
+      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
+      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
+      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
+      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
+      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
+      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
+      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
+      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
+      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
+      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
+      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
+      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
+      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
+      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
+      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
+      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
+      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
+      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
+      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
+      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
+      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
+      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
+      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
+      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
+      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
+      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
+      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
+      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
+      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
+      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
+      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
+      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
+      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
+    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
+      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
+        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
+        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect." />
+        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
+      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
+        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
+        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
+      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
+      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
+      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
+      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
+      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
+      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
+      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
+      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
+      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
+      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
+      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
+      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
+      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
+      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
+      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
+      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
+        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
+        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
+      </BitField>
+    </Register>
+    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
+        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
+        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
+        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
+        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
+        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
+        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
+      </BitField>
+      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
+        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
+      </BitField>
+      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
+        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
+        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
+        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
+        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
+        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
+        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
+      </BitField>
+      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
+        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
+      </BitField>
+      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
+        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
+        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
+        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
+        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
+        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
+        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
+      </BitField>
+      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
+        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
+      </BitField>
+      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
+        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
+        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
+        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
+        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
+      </BitField>
+    </Register>
+    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
+        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
+      </BitField>
+      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
+        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
+      </BitField>
+      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
+        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
+      </BitField>
+      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
+        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
+      </BitField>
+      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
+        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
+      </BitField>
+    </Register>
+    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
+    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
+      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
+      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
+        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
+        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
+      </BitField>
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
+        <Enum name="IRC" start="0x01" description="IRC" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="RESERVED" start="0x0A" description="Reserved" />
+        <Enum name="RESERVED" start="0x0B" description="Reserved" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
+        <Enum name="ENABLE" start="0" description="Enable" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
+        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
+        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
+      </BitField>
+      <BitField start="2" size="1" name="HF" description="Select frequency range">
+        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
+        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
+      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="PLL0 power down">
+        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
+        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
+        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
+        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
+      </BitField>
+      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
+      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
+      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FRM" description="Free running mode" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
+      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
+      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
+      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
+    </Register>
+    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
+      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
+      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="PLL0 power down">
+        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
+        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
+        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
+        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
+      </BitField>
+      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
+      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
+      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FRM" description="Free running mode" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
+      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
+        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
+        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
+      </BitField>
+      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
+        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
+      </BitField>
+      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
+      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="PLL1 power down">
+        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
+        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
+        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
+        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
+      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
+      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
+        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
+        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
+      </BitField>
+      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
+        <Enum name="1" start="0x0" description="1" />
+        <Enum name="PEQ2" start="0x1" description="2 (default)" />
+        <Enum name="PEQ4" start="0x2" description="4" />
+        <Enum name="8" start="0x3" description="8" />
+      </BitField>
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
+        <Enum name="1" start="0x0" description="1" />
+        <Enum name="NEQ2" start="0x1" description="2" />
+        <Enum name="NEQ3" start="0x2" description="3 (default)" />
+        <Enum name="4" start="0x3" description="4" />
+      </BitField>
+      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="RESERVED" start="0x09" description="Reserved" />
+        <Enum name="RESERVED" start="0x0A" description="Reserved" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
+        <Enum name="DIV1" start="0x0" description="1 (default)" />
+        <Enum name="DIV2" start="0x1" description="2" />
+        <Enum name="DIV3" start="0x2" description="3" />
+        <Enum name="DIV4" start="0x3" description="4" />
+      </BitField>
+      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
+      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
+      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
+      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x06C" size="4" name="BASE_M3_CLK" access="Read/Write" description="Output stage BASE_M3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="RESERVED" start="0x07" description="Reserved" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="RESERVED" start="0x07" description="Reserved" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="RESERVED" start="0x07" description="Reserved" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
+    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400" size="4" name="CLK_M3_BUS_CFG" access="Read/Write" description="CLK_M3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0408" size="4" name="CLK_M3_SPIFI_CFG" access="Read/Write" description="CLK_M3_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0410" size="4" name="CLK_M3_GPIO_CFG" access="Read/Write" description="CLK_M3_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0418" size="4" name="CLK_M3_LCD_CFG" access="Read/Write" description="CLK_M3_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0420" size="4" name="CLK_M3_ETHERNET_CFG" access="Read/Write" description="CLK_M3_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0428" size="4" name="CLK_M3_USB0_CFG" access="Read/Write" description="CLK_M3_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0430" size="4" name="CLK_M3_EMC_CFG" access="Read/Write" description="CLK_M3_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0438" size="4" name="CLK_M3_SDIO_CFG" access="Read/Write" description="CLK_M3_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0440" size="4" name="CLK_M3_DMA_CFG" access="Read/Write" description="CLK_M3_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0448" size="4" name="CLK_M3_M3CORE_CFG" access="Read/Write" description="CLK_M3_M3CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0468" size="4" name="CLK_M3_SCT_CFG" access="Read/Write" description="CLK_M3_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0470" size="4" name="CLK_M3_USB1_CFG" access="Read/Write" description="CLK_M3_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0478" size="4" name="CLK_M3_EMCDIV_CFG" access="Read/Write" description="CLK_M3_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="3" name="DIV" description="Clock divider value">
+        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
+        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0480" size="4" name="CLK_M3_FLASHA_CFG" access="Read/Write" description="CLK_M3_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0488" size="4" name="CLK_M3_FLASHB_CFG" access="Read/Write" description="CLK_M3_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04A0" size="4" name="CLK_M3_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500" size="4" name="CLK_M3_WWDT_CFG" access="Read/Write" description="CLK_M3_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0508" size="4" name="CLK_M3_USART0_CFG" access="Read/Write" description="CLK_M3_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0510" size="4" name="CLK_M3_UART1_CFG" access="Read/Write" description="CLK_M3_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0518" size="4" name="CLK_M3_SSP0_CFG" access="Read/Write" description="CLK_M3_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0520" size="4" name="CLK_M3_TIMER0_CFG" access="Read/Write" description="CLK_M3_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0528" size="4" name="CLK_M3_TIMER1_CFG" access="Read/Write" description="CLK_M3_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0530" size="4" name="CLK_M3_SCU_CFG" access="Read/Write" description="CLK_M3_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0538" size="4" name="CLK_M3_CREG_CFG" access="Read/Write" description="CLK_M3_CREG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600" size="4" name="CLK_M3_RITIMER_CFG" access="Read/Write" description="CLK_M3_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0608" size="4" name="CLK_M3_USART2_CFG" access="Read/Write" description="CLK_M3_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0610" size="4" name="CLK_M3_USART3_CFG" access="Read/Write" description="CLK_M3_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0618" size="4" name="CLK_M3_TIMER2_CFG" access="Read/Write" description="CLK_M3_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0620" size="4" name="CLK_M3_TIMER3_CFG" access="Read/Write" description="CLK_M3_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0628" size="4" name="CLK_M3_SSP1_CFG" access="Read/Write" description="CLK_M3_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0630" size="4" name="CLK_M3_QEI_CFG" access="Read/Write" description="CLK_M3_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
+        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
+        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x404" size="4" name="CLK_M3_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040C" size="4" name="CLK_M3_SPIFI_STAT" access="ReadOnly" description="CLK_M3_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0414" size="4" name="CLK_M3_GPIO_STAT" access="ReadOnly" description="CLK_M3_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x041C" size="4" name="CLK_M3_LCD_STAT" access="ReadOnly" description="CLK_M3_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0424" size="4" name="CLK_M3_ETHERNET_STAT" access="ReadOnly" description="CLK_M3_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x042C" size="4" name="CLK_M3_USB0_STAT" access="ReadOnly" description="CLK_M3_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0434" size="4" name="CLK_M3_EMC_STAT" access="ReadOnly" description="CLK_M3_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x043C" size="4" name="CLK_M3_SDIO_STAT" access="ReadOnly" description="CLK_M3_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0444" size="4" name="CLK_M3_DMA_STAT" access="ReadOnly" description="CLK_M3_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044C" size="4" name="CLK_M3_M3CORE_STAT" access="ReadOnly" description="CLK_M3_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x046C" size="4" name="CLK_M3_SCT_STAT" access="ReadOnly" description="CLK_M3_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0474" size="4" name="CLK_M3_USB1_STAT" access="ReadOnly" description="CLK_M3_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x047C" size="4" name="CLK_M3_EMCDIV_STAT" access="ReadOnly" description="CLK_M3_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="3" name="DIV" description="Clock divider value">
+        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
+        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0484" size="4" name="CLK_M3_FLASHA_STAT" access="ReadOnly" description="CLK_M3_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048C" size="4" name="CLK_M3_FLASHB_STAT" access="ReadOnly" description="CLK_M3_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04A4" size="4" name="CLK_M3_EEPROM_STAT" access="ReadOnly" description="CLK_M3_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504" size="4" name="CLK_M3_WWDT_STAT" access="ReadOnly" description="CLK_M3_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050C" size="4" name="CLK_M3_USART0_STAT" access="ReadOnly" description="CLK_M3_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0514" size="4" name="CLK_M3_UART1_STAT" access="ReadOnly" description="CLK_M3_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x051C" size="4" name="CLK_M3_SSP0_STAT" access="ReadOnly" description="CLK_M3_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0524" size="4" name="CLK_M3_TIMER0_STAT" access="ReadOnly" description="CLK_M3_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x052C" size="4" name="CLK_M3_TIMER1_STAT" access="ReadOnly" description="CLK_M3_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0534" size="4" name="CLK_M3_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x053C" size="4" name="CLK_M3_CREG_STAT" access="ReadOnly" description="CLK_M3_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x604" size="4" name="CLK_M3_RITIMER_STAT" access="ReadOnly" description="CLK_M3_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x060C" size="4" name="CLK_M3_USART2_STAT" access="ReadOnly" description="CLK_M3_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0614" size="4" name="CLK_M3_USART3_STAT" access="ReadOnly" description="CLK_M3_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x061C" size="4" name="CLK_M3_TIMER2_STAT" access="ReadOnly" description="CLK_M3_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0624" size="4" name="CLK_M3_TIMER3_STAT" access="ReadOnly" description="CLK_M3_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x062C" size="4" name="CLK_M3_SSP1_STAT" access="ReadOnly" description="CLK_M3_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0634" size="4" name="CLK_M3_QEI_STAT" access="ReadOnly" description="CLK_M3_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
+    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
+    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
+      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
+      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
+      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
+      <BitField start="13" size="1" name="M3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="25" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
+      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
+      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="M3_RST" description="Status of the M3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+    </Register>
+    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="16" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="18" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
+      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="13" size="1" name="M3_RST" description="Current status of the M3_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="25" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="28" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
+    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
+        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
+        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
+      </BitField>
+      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
+        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
+        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
+      </BitField>
+      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
+      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
+      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
+        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
+        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
+    </Register>
+    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="Count" description="Counter timer value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
+        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
+        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
+        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart." />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
+        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
+        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Edge sampling.">
+        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
+        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
+        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
+        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
+        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
+        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
+        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
+        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart." />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
+        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
+        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Edge sampling.">
+        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
+        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
+        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
+        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
+        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
+        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
+        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
+        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart." />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
+        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
+        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Edge sampling.">
+        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
+        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
+        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
+        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
+        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
+      </BitField>
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
+      </BitField>
+      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
+      </BitField>
+      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
+        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
+        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
+        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
+      </BitField>
+      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
+        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
+      </BitField>
+      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
+        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
+      </BitField>
+      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
+        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
+      </BitField>
+      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
+      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
+      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
+      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart" />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SEL" description="Direction control.">
+        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
+        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
+      </BitField>
+      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
+        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="NORMAL" start="0" description="During normal operation." />
+        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
+        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
+      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
+        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="NORMAL" start="0" description="During normal operation." />
+        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
+        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
+      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
+    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
+        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
+        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
+      </BitField>
+      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
+        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
+        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
+      </BitField>
+      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
+        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
+        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
+        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
+        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
+      </BitField>
+      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
+        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
+        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
+        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
+        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
+      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
+        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
+        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
+      </BitField>
+      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
+        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
+        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
+      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
+        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
+        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
+      </BitField>
+      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
+      </BitField>
+      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
+      </BitField>
+      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
+      </BitField>
+      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
+      </BitField>
+      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
+      </BitField>
+      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
+      </BitField>
+      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
+      </BitField>
+    </Register>
+    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
+      </BitField>
+      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
+      </BitField>
+      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
+      </BitField>
+      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
+      </BitField>
+      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
+      </BitField>
+      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
+      </BitField>
+      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
+      </BitField>
+      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
+      </BitField>
+    </Register>
+    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DAC" description="Select DAC">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
+        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
+      </BitField>
+      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
+        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
+      </BitField>
+    </Register>
+    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
+    </Register>
+    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
+      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
+      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
+    </Register>
+    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
+      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
+      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
+      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
+      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+    </Register>
+    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
+      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
+      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
+      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
+      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
+    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
+        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
+        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
+      </BitField>
+      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
+        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
+        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
+      </BitField>
+      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
+        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
+        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
+        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
+        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
+      </BitField>
+      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
+        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
+        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
+      </BitField>
+      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
+        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
+        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
+    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
+        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
+        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
+      </BitField>
+      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
+        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
+        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
+      </BitField>
+      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
+        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
+        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
+      </BitField>
+    </Register>
+    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
+    </Register>
+    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
+      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
+      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
+      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
+      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
+      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
+      <BitField start="30" size="2" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
+        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
+        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
+      </BitField>
+      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
+        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
+        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
+        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
+        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
+        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
+        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
+        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
+        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
+        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
+        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
+      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
+        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
+        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
+        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
+        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
+      </BitField>
+      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
+        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
+        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
+      </BitField>
+      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
+        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
+        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
+      </BitField>
+    </Register>
+    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+    </Register>
+    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+    </Register>
+    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
+      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
+      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
+    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
+      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
+      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
+      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
+        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
+        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
+    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
+      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
+      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
+      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
+        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
+        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
+    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INIT" description="Initialization">
+        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
+        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
+        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
+      </BitField>
+      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
+        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
+        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
+      </BitField>
+      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
+        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
+        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="reserved" />
+      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
+        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
+        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
+        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
+        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
+      </BitField>
+      <BitField start="7" size="1" name="TEST" description="Test mode enable">
+        <Enum name="TEST_MODE_" start="1" description="Test mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
+        <Enum name="NO_ERROR_" start="0x0" description="No error." />
+        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
+        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
+        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
+        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
+        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
+        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
+        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
+      </BitField>
+      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="5" size="1" name="EPASS" description="Error passive">
+        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
+        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
+      </BitField>
+      <BitField start="6" size="1" name="EWARN" description="Warning status">
+        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
+        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
+      </BitField>
+      <BitField start="7" size="1" name="BOFF" description="Busoff status">
+        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
+        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
+      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
+      <BitField start="15" size="1" name="RP" description="Receive error passive">
+        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
+        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
+      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
+      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
+      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="tbd." />
+      <BitField start="2" size="1" name="BASIC" description="Basic mode">
+        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
+        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SILENT" description="Silent mode">
+        <Enum name="SILENT" start="1" description="The module is in silent mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
+        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
+        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
+      </BitField>
+      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
+        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
+        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
+        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
+        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
+      </BitField>
+      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
+        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
+        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
+    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
+    </Register>
+    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
+    </Register>
+    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
+        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
+        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
+      </BitField>
+      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
+        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
+        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
+      </BitField>
+      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
+        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
+        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
+      </BitField>
+      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
+        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
+        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
+    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
+      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
+      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
+      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
+      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
+      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
+      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
+      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
+      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
+      <BitField start="20" size="12" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
+      <BitField start="1" size="31" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="POS" description="Current position value." />
+    </Register>
+    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
+    </Register>
+    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
+    </Register>
+    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
+    </Register>
+    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
+    </Register>
+    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
+    </Register>
+    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
+    </Register>
+    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
+    </Register>
+    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
+    </Register>
+    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
+    </Register>
+    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
+    </Register>
+    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
+    </Register>
+    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
+    </Register>
+    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
+    </Register>
+    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
+    </Register>
+    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
+    </Register>
+    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
+    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
+        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
+        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
+        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
+        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
+        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
+        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
+        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
+        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
+        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
+        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
+        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
+        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
+        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
+        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
+        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
+        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
+        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
+        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
+        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
+        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
+        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
+        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
+        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
+        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
+        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
+        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
+        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
+        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
+        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
+        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
+        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
+        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
+        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
+        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
+        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
+        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
+        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
+        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
+        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
+        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
+        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
+        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
+        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
+        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
+        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
+        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
+      <BitField start="16" size="1" name="BIAS" description="Settling time">
+        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
+        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
+      </BitField>
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
+        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
+        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
+      </BitField>
+      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
+        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
+        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
+      </BitField>
+      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
+        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
+        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
+        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
+        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
+    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INIT" description="Initialization">
+        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
+        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
+        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
+      </BitField>
+      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
+        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
+        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
+      </BitField>
+      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
+        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
+        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="reserved" />
+      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
+        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
+        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
+        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
+        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
+      </BitField>
+      <BitField start="7" size="1" name="TEST" description="Test mode enable">
+        <Enum name="TEST_MODE_" start="1" description="Test mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
+        <Enum name="NO_ERROR_" start="0x0" description="No error." />
+        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
+        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
+        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
+        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
+        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
+        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
+        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
+      </BitField>
+      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="5" size="1" name="EPASS" description="Error passive">
+        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
+        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
+      </BitField>
+      <BitField start="6" size="1" name="EWARN" description="Warning status">
+        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
+        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
+      </BitField>
+      <BitField start="7" size="1" name="BOFF" description="Busoff status">
+        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
+        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
+      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
+      <BitField start="15" size="1" name="RP" description="Receive error passive">
+        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
+        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
+      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
+      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
+      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="tbd." />
+      <BitField start="2" size="1" name="BASIC" description="Basic mode">
+        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
+        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SILENT" description="Silent mode">
+        <Enum name="SILENT" start="1" description="The module is in silent mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
+        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
+        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
+      </BitField>
+      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
+        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
+        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
+        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
+        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
+      </BitField>
+      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
+        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
+        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
+      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
+      <BitField start="16" size="1" name="BURST" description="Burst mode">
+        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
+        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
+      </BitField>
+      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
+        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
+        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
+        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
+        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
+        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
+        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
+        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
+        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="21" size="1" name="PDN" description="Power mode">
+        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
+        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
+      </BitField>
+      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
+        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
+        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
+        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
+        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
+        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
+        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
+        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
+        <Enum name="RESERVED_" start="0x7" description="Reserved." />
+      </BitField>
+      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
+        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
+        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
+      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
+      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
+      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
+      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
+      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
+      <BitField start="16" size="1" name="BURST" description="Burst mode">
+        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
+        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
+      </BitField>
+      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
+        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
+        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
+        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
+        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
+        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
+        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
+        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
+        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="21" size="1" name="PDN" description="Power mode">
+        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
+        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
+      </BitField>
+      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
+        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
+        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
+        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
+        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
+        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
+        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
+        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
+        <Enum name="RESERVED_" start="0x7" description="Reserved." />
+      </BitField>
+      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
+        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
+        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
+      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
+      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
+      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
+      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
+    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
+    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+    </Register>
+    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
+      <BitField name="DAC" start="4" size="4" />
+      <BitField name="DMA" start="20" size="4" />
+    </Register>
+    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
+      <BitField name="FLASH" start="4" size="4" />
+      <BitField name="ETHERNET" start="12" size="4" />
+      <BitField name="SDIO" start="20" size="4" />
+      <BitField name="LCD" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
+      <BitField name="USB0" start="4" size="4" />
+      <BitField name="USB1" start="12" size="4" />
+      <BitField name="SCT" start="20" size="4" />
+      <BitField name="RITIMER" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
+      <BitField name="TIMER0" start="4" size="4" />
+      <BitField name="TIMER1" start="12" size="4" />
+      <BitField name="TIMER2" start="20" size="4" />
+      <BitField name="TIMER3" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
+      <BitField name="MCPWM" start="4" size="4" />
+      <BitField name="ADC0" start="12" size="4" />
+      <BitField name="I2C0" start="20" size="4" />
+      <BitField name="I2C1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
+      <BitField name="ADC1" start="12" size="4" />
+      <BitField name="SSP0" start="20" size="4" />
+      <BitField name="SSP1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
+      <BitField name="USART0" start="4" size="4" />
+      <BitField name="UART1" start="12" size="4" />
+      <BitField name="USART2" start="20" size="4" />
+      <BitField name="USART3" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
+      <BitField name="I2S0" start="4" size="4" />
+      <BitField name="I2S1" start="12" size="4" />
+      <BitField name="SPIFI" start="20" size="4" />
+    </Register>
+    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
+      <BitField name="PIN_INT0" start="4" size="4" />
+      <BitField name="PIN_INT1" start="12" size="4" />
+      <BitField name="PIN_INT2" start="20" size="4" />
+      <BitField name="PIN_INT3" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
+      <BitField name="PIN_INT4" start="4" size="4" />
+      <BitField name="PIN_INT5" start="12" size="4" />
+      <BitField name="PIN_INT6" start="20" size="4" />
+      <BitField name="PIN_INT7" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
+      <BitField name="GINT0" start="4" size="4" />
+      <BitField name="GINT1" start="12" size="4" />
+      <BitField name="EVENTROUTER" start="20" size="4" />
+      <BitField name="C_CAN1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
+      <BitField name="ATIMER" start="20" size="4" />
+      <BitField name="RTC" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
+      <BitField name="WWDT" start="12" size="4" />
+      <BitField name="C_CAN0" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
+      <BitField name="QEI" start="4" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
+    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
+      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
+      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
+      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
+    </Register>
+    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
+      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
+    </Register>
+    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
+      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
+    </Register>
+    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
+      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
+      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
+      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCB" start="" description="System Control Block">
+    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
+      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
+    </Register>
+    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
+      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
+      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
+      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
+      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
+    </Register>
+    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
+      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
+      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
+      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
+      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
+      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
+      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
+      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
+      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
+      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
+      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
+    </Register>
+    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
+      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
+    </Register>
+    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
+      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
+      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
+      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
+      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
+      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
+      <BitField name="VECTRESET" start="0" size="1" description="" />
+    </Register>
+    <Register name="SCR" start="0xE000ED10" description="System Control Register">
+      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
+      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
+      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
+    </Register>
+    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
+      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
+      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
+      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
+      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
+      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
+      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
+    </Register>
+    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
+      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
+      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
+      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
+    </Register>
+    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
+      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
+    </Register>
+    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
+      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
+      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
+    </Register>
+    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
+      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
+      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
+      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
+      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
+      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
+      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
+      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
+      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
+      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
+      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
+      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
+      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
+      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
+      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
+    </Register>
+    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
+      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
+      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
+      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
+      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
+      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
+    </Register>
+    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
+      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
+      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
+      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
+      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
+      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
+      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
+    </Register>
+    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
+      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
+      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
+      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
+      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
+      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
+      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
+    </Register>
+    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
+      <BitField name="DEBUGEVT" start="31" size="1" description="" />
+      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
+      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
+    </Register>
+    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
+      <BitField name="EXTERNAL" start="4" size="1" description="" />
+      <BitField name="VCATCH" start="3" size="1" description="" />
+      <BitField name="DWTTRAP" start="2" size="1" description="" />
+      <BitField name="BKPT" start="1" size="1" description="" />
+      <BitField name="HALTED" start="0" size="1" description="" />
+    </Register>
+    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
+    </Register>
+    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
+    </Register>
+    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
+      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
+    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
+      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
+      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
+      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
+    </Register>
+    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
+      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
+      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
+    </Register>
+    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
+      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
+    </Register>
+    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
+      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
+      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
+      <BitField name="REGION" start="0" size="4" description="MPU region field" />
+    </Register>
+    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
+      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
+      <BitField name="AP" start="24" size="3" description="Access permission field" />
+      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
+      <BitField name="S" start="18" size="1" description="Shareable bit" />
+      <BitField name="C" start="17" size="1" description="Memory access attribute" />
+      <BitField name="B" start="16" size="1" description="Memory access attribute" />
+      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
+      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
+      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
+    </Register>
+  </RegisterGroup>
+</Processor>
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s
new file mode 100644
index 000000000..8f9a39e42
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/LPC18xx_Vectors.s
@@ -0,0 +1,516 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                         Preprocessor Definitions                          *
+ *                         ------------------------                          *
+ * VECTORS_IN_RAM                                                            *
+ *                                                                           *
+ *   If defined, an area of RAM will large enough to store the vector table  *
+ *   will be reserved.                                                       *
+ *                                                                           *
+ *****************************************************************************/
+
+  .syntax unified
+  .code 16
+
+  .section .init, "ax"
+  .align 0
+
+/*****************************************************************************
+ * Default Exception Handlers                                                *
+ *****************************************************************************/
+
+  .thumb_func
+  .weak NMI_Handler
+NMI_Handler:
+  b .
+
+  .thumb_func
+  .weak HardFault_Handler
+HardFault_Handler:
+  b .
+
+  .thumb_func
+  .weak SVC_Handler
+SVC_Handler:
+  b .
+
+  .thumb_func
+  .weak PendSV_Handler
+PendSV_Handler:
+  b .
+
+  .thumb_func
+  .weak SysTick_Handler
+SysTick_Handler:
+  b .
+
+  .thumb_func
+Dummy_Handler:
+  b .
+
+#if defined(__OPTIMIZATION_SMALL)
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Dummy_Handler
+
+  .weak DMA_IRQHandler
+  .thumb_set DMA_IRQHandler,Dummy_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Dummy_Handler
+
+  .weak ETHERNET_IRQHandler
+  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
+
+  .weak SDIO_IRQHandler
+  .thumb_set SDIO_IRQHandler,Dummy_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Dummy_Handler
+
+  .weak USB0_IRQHandler
+  .thumb_set USB0_IRQHandler,Dummy_Handler
+
+  .weak USB1_IRQHandler
+  .thumb_set USB1_IRQHandler,Dummy_Handler
+
+  .weak SCT_IRQHandler
+  .thumb_set SCT_IRQHandler,Dummy_Handler
+
+  .weak RITIMER_IRQHandler
+  .thumb_set RITIMER_IRQHandler,Dummy_Handler
+
+  .weak TIMER0_IRQHandler
+  .thumb_set TIMER0_IRQHandler,Dummy_Handler
+
+  .weak TIMER1_IRQHandler
+  .thumb_set TIMER1_IRQHandler,Dummy_Handler
+
+  .weak TIMER2_IRQHandler
+  .thumb_set TIMER2_IRQHandler,Dummy_Handler
+
+  .weak TIMER3_IRQHandler
+  .thumb_set TIMER3_IRQHandler,Dummy_Handler
+
+  .weak MCPWM_IRQHandler
+  .thumb_set MCPWM_IRQHandler,Dummy_Handler
+
+  .weak ADC0_IRQHandler
+  .thumb_set ADC0_IRQHandler,Dummy_Handler
+
+  .weak I2C0_IRQHandler
+  .thumb_set I2C0_IRQHandler,Dummy_Handler
+
+  .weak I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Dummy_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Dummy_Handler
+
+  .weak SSP0_IRQHandler
+  .thumb_set SSP0_IRQHandler,Dummy_Handler
+
+  .weak SSP1_IRQHandler
+  .thumb_set SSP1_IRQHandler,Dummy_Handler
+
+  .weak USART0_IRQHandler
+  .thumb_set USART0_IRQHandler,Dummy_Handler
+
+  .weak UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Dummy_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Dummy_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Dummy_Handler
+
+  .weak I2S0_IRQHandler
+  .thumb_set I2S0_IRQHandler,Dummy_Handler
+
+  .weak I2S1_IRQHandler
+  .thumb_set I2S1_IRQHandler,Dummy_Handler
+
+  .weak SPIFI_IRQHandler
+  .thumb_set SPIFI_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT0_IRQHandler
+  .thumb_set PIN_INT0_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT1_IRQHandler
+  .thumb_set PIN_INT1_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT2_IRQHandler
+  .thumb_set PIN_INT2_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT3_IRQHandler
+  .thumb_set PIN_INT3_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT4_IRQHandler
+  .thumb_set PIN_INT4_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT5_IRQHandler
+  .thumb_set PIN_INT5_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT6_IRQHandler
+  .thumb_set PIN_INT6_IRQHandler,Dummy_Handler
+
+  .weak PIN_INT7_IRQHandler
+  .thumb_set PIN_INT7_IRQHandler,Dummy_Handler
+
+  .weak GINT0_IRQHandler
+  .thumb_set GINT0_IRQHandler,Dummy_Handler
+
+  .weak GINT1_IRQHandler
+  .thumb_set GINT1_IRQHandler,Dummy_Handler
+
+  .weak EVENTROUTER_IRQHandler
+  .thumb_set EVENTROUTER_IRQHandler,Dummy_Handler
+
+  .weak C_CAN1_IRQHandler
+  .thumb_set C_CAN1_IRQHandler,Dummy_Handler
+
+  .weak ATIMER_IRQHandler
+  .thumb_set ATIMER_IRQHandler,Dummy_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Dummy_Handler
+
+  .weak WWDT_IRQHandler
+  .thumb_set WWDT_IRQHandler,Dummy_Handler
+
+  .weak C_CAN0_IRQHandler
+  .thumb_set C_CAN0_IRQHandler,Dummy_Handler
+
+  .weak QEI_IRQHandler
+  .thumb_set QEI_IRQHandler,Dummy_Handler
+
+#else
+
+  .thumb_func
+  .weak DAC_IRQHandler
+DAC_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak DMA_IRQHandler
+DMA_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak FLASH_IRQHandler
+FLASH_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ETHERNET_IRQHandler
+ETHERNET_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SDIO_IRQHandler
+SDIO_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak LCD_IRQHandler
+LCD_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USB0_IRQHandler
+USB0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USB1_IRQHandler
+USB1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SCT_IRQHandler
+SCT_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak RITIMER_IRQHandler
+RITIMER_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER0_IRQHandler
+TIMER0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER1_IRQHandler
+TIMER1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER2_IRQHandler
+TIMER2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER3_IRQHandler
+TIMER3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak MCPWM_IRQHandler
+MCPWM_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ADC0_IRQHandler
+ADC0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2C0_IRQHandler
+I2C0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2C1_IRQHandler
+I2C1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ADC1_IRQHandler
+ADC1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP0_IRQHandler
+SSP0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP1_IRQHandler
+SSP1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USART0_IRQHandler
+USART0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak UART1_IRQHandler
+UART1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USART2_IRQHandler
+USART2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USART3_IRQHandler
+USART3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2S0_IRQHandler
+I2S0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2S1_IRQHandler
+I2S1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SPIFI_IRQHandler
+SPIFI_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT0_IRQHandler
+PIN_INT0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT1_IRQHandler
+PIN_INT1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT2_IRQHandler
+PIN_INT2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT3_IRQHandler
+PIN_INT3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT4_IRQHandler
+PIN_INT4_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT5_IRQHandler
+PIN_INT5_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT6_IRQHandler
+PIN_INT6_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PIN_INT7_IRQHandler
+PIN_INT7_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak GINT0_IRQHandler
+GINT0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak GINT1_IRQHandler
+GINT1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak EVENTROUTER_IRQHandler
+EVENTROUTER_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak C_CAN1_IRQHandler
+C_CAN1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ATIMER_IRQHandler
+ATIMER_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak RTC_IRQHandler
+RTC_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak WWDT_IRQHandler
+WWDT_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak C_CAN0_IRQHandler
+C_CAN0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak QEI_IRQHandler
+QEI_IRQHandler:
+  b .
+
+#endif
+
+/*****************************************************************************
+ * Vector Table                                                              *
+ *****************************************************************************/
+
+  .section .vectors, "ax"
+  .align 0
+  .global _vectors
+  .extern __stack_end__
+  .extern Reset_Handler
+
+_vectors:
+  .word __stack_end__
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word SVC_Handler
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word DAC_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word DMA_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word FLASH_IRQHandler
+  .word ETHERNET_IRQHandler
+  .word SDIO_IRQHandler
+  .word LCD_IRQHandler
+  .word USB0_IRQHandler
+  .word USB1_IRQHandler
+  .word SCT_IRQHandler
+  .word RITIMER_IRQHandler
+  .word TIMER0_IRQHandler
+  .word TIMER1_IRQHandler
+  .word TIMER2_IRQHandler
+  .word TIMER3_IRQHandler
+  .word MCPWM_IRQHandler
+  .word ADC0_IRQHandler
+  .word I2C0_IRQHandler
+  .word I2C1_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word ADC1_IRQHandler
+  .word SSP0_IRQHandler
+  .word SSP1_IRQHandler
+  .word USART0_IRQHandler
+  .word UART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word I2S0_IRQHandler
+  .word I2S1_IRQHandler
+  .word SPIFI_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word PIN_INT0_IRQHandler
+  .word PIN_INT1_IRQHandler
+  .word PIN_INT2_IRQHandler
+  .word PIN_INT3_IRQHandler
+  .word PIN_INT4_IRQHandler
+  .word PIN_INT5_IRQHandler
+  .word PIN_INT6_IRQHandler
+  .word PIN_INT7_IRQHandler
+  .word GINT0_IRQHandler
+  .word GINT1_IRQHandler
+  .word EVENTROUTER_IRQHandler
+  .word C_CAN1_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word Dummy_Handler /* Reserved */
+  .word ATIMER_IRQHandler
+  .word RTC_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word WWDT_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word C_CAN0_IRQHandler
+  .word QEI_IRQHandler
+_vectors_end:
+
+#ifdef VECTORS_IN_RAM
+  .section .vectors_ram, "ax"
+  .align 0
+  .global _vectors_ram
+
+_vectors_ram:
+  .space _vectors_end - _vectors, 0
+#endif
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml
new file mode 100644
index 000000000..79bedc537
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/flash_placement.xml
@@ -0,0 +1,37 @@
+<!DOCTYPE Linker_Placement_File>
+<Root name="Flash Section Placement">
+  <MemorySegment name="$(FLASH_NAME:FLASH)">
+    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
+    <ProgramSection alignment="4" load="Yes" name=".init" />
+    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
+    <ProgramSection alignment="4" load="Yes" name=".text" />
+    <ProgramSection alignment="4" load="Yes" name=".dtors" />
+    <ProgramSection alignment="4" load="Yes" name=".ctors" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata" />
+    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
+    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
+    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
+    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
+  </MemorySegment>
+  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
+    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
+    <ProgramSection alignment="4" load="No" name=".fast_run" />
+    <ProgramSection alignment="4" load="No" name=".data_run" />
+    <ProgramSection alignment="4" load="No" name=".bss" />
+    <ProgramSection alignment="4" load="No" name=".tbss" />
+    <ProgramSection alignment="4" load="No" name=".tdata_run" />
+    <ProgramSection alignment="4" load="No" name=".non_init" />
+    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
+    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
+    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
+  </MemorySegment>
+  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
+    <ProgramSection alignment="4" load="Yes" name=".text2" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
+    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
+  </MemorySegment>
+  <MemorySegment name="$(RAM2_NAME:RAM2)">
+    <ProgramSection alignment="4" load="No" name=".data2_run" />
+    <ProgramSection alignment="4" load="No" name=".bss2" />
+  </MemorySegment>
+</Root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject b/examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject
new file mode 100644
index 000000000..8e9123dc7
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/lpc18xx.emProject
@@ -0,0 +1,129 @@
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="lpc18xx" target="8" version="2">
+  <project Name="lpc18xx">
+    <configuration
+      Name="Common"
+      Placement="Flash"
+      Target="LPC1857"
+      arm_architecture="v7M"
+      arm_core_type="Cortex-M3"
+      arm_endian="Little"
+      arm_fpu_type="None"
+      arm_interwork="No"
+      arm_linker_heap_size="256"
+      arm_linker_process_stack_size="0"
+      arm_linker_stack_size="256"
+      arm_simulator_memory_simulation_parameter="RAM;0x10000000;0x00008000;ROM;0x1A000000;0x00080000;ROM;0x1B000000;0x00080000;RAM;0x20000000;0x00010000"
+      arm_target_debug_interface_type="ADIv5"
+      arm_target_device_name="LPC1857"
+      arm_target_interface_type="SWD"
+      c_preprocessor_definitions="LPC18xx;__LPC1800_FAMILY;__LPC185x_SUBFAMILY;ARM_MATH_CM3;FLASH_PLACEMENT=1;CORE_M3;BOARD_MCB1800;CFG_TUSB_MCU=OPT_MCU_LPC18XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
+      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)//inc;$(lpcDir)//inc/config_18xx"
+      debug_register_definition_file="$(ProjectDir)/LPC18xx_Registers.xml"
+      debug_target_connection="J-Link"
+      gcc_entry_point="Reset_Handler"
+      linker_memory_map_file="$(ProjectDir)/LPC1857_MemoryMap.xml"
+      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
+      macros="DeviceFamily=LPC1800;DeviceSubFamily=LPC185x;Target=LPC1857;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_18xx"
+      package_dependencies="LPC1800"
+      project_directory=""
+      project_type="Executable"
+      target_reset_script="Reset();"
+      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
+    <folder Name="System Files">
+      <file file_name="thumb_crt0.s" />
+      <file file_name="LPC1800_Startup.s" />
+      <file file_name="LPC18xx_Vectors.s">
+        <configuration Name="Common" file_type="Assembly" />
+      </file>
+      <file file_name="LPC1857_MemoryMap.xml" />
+      <file file_name="flash_placement.xml" />
+      <file file_name="LPC1800_Target.js">
+        <configuration Name="Common" file_type="Reset Script" />
+      </file>
+    </folder>
+    <configuration
+      Name="Debug"
+      link_use_linker_script_file="No"
+      linker_section_placement_file="flash_placement.xml" />
+    <folder Name="hw">
+      <folder Name="bsp">
+        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
+        <file file_name="../../../../../hw/bsp/board.h" />
+        <folder Name="mcb1800">
+          <file file_name="../../../../../hw/bsp/mcb1800/board_mcb1800.c" />
+          <file file_name="../../../../../hw/bsp/mcb1800/board_mcb1800.h" />
+        </folder>
+      </folder>
+      <folder Name="mcu">
+        <folder Name="nxp">
+          <folder Name="lpc_chip_18xx">
+            <folder Name="inc">
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/arm_common_tables.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/arm_math.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cguccu_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_clocks.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_lpc18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/chip_lpc43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/clock_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_18xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx_m0app.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/cmsis_43xx_m0sub.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm0.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm0plus.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm3.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm4.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cm4_simd.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_sc000.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/core_sc300.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/creg_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/gpio_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/lpc_types.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/uart_18xx_43xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/usbhs_18xx_43xx.h" />
+              <folder Name="config_18xx">
+                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/config_18xx/cmsis_18xx.h" />
+                <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/inc/config_18xx/sys_config.h" />
+              </folder>
+            </folder>
+            <folder Name="src">
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/chip_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/clock_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/gpio_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/sysinit_18xx_43xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_18xx/src/uart_18xx_43xx.c" />
+            </folder>
+          </folder>
+        </folder>
+      </folder>
+    </folder>
+    <folder
+      Name="segger_rtt"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../../../../lib/segger_rtt"
+      recurse="No" />
+    <folder
+      Name="src"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../src"
+      recurse="Yes" />
+    <folder
+      Name="tinyusb"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../../../../src"
+      recurse="Yes" />
+  </project>
+  <configuration
+    Name="MCB1800"
+    c_preprocessor_definitions="DEBUG"
+    gcc_debugging_level="Level 3"
+    gcc_optimization_level="None" />
+</solution>
diff --git a/examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s
new file mode 100644
index 000000000..17f88e0ca
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc18xx/thumb_crt0.s
@@ -0,0 +1,415 @@
+// **********************************************************************
+// *                    SEGGER Microcontroller GmbH                     *
+// *                        The Embedded Experts                        *
+// **********************************************************************
+// *                                                                    *
+// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
+// *            (c) 2001 - 2018 Rowley Associates Limited               *
+// *                                                                    *
+// *           www.segger.com     Support: support@segger.com           *
+// *                                                                    *
+// **********************************************************************
+// *                                                                    *
+// * All rights reserved.                                               *
+// *                                                                    *
+// * Redistribution and use in source and binary forms, with or         *
+// * without modification, are permitted provided that the following    *
+// * conditions are met:                                                *
+// *                                                                    *
+// * - Redistributions of source code must retain the above copyright   *
+// *   notice, this list of conditions and the following disclaimer.    *
+// *                                                                    *
+// * - Neither the name of SEGGER Microcontroller GmbH                  *
+// *   nor the names of its contributors may be used to endorse or      *
+// *   promote products derived from this software without specific     *
+// *   prior written permission.                                        *
+// *                                                                    *
+// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+// * DISCLAIMED.                                                        *
+// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
+// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+// * DAMAGE.                                                            *
+// *                                                                    *
+// **********************************************************************
+//
+//
+//                           Preprocessor Definitions
+//                           ------------------------
+// APP_ENTRY_POINT
+//
+//   Defines the application entry point function, if undefined this setting
+//   defaults to "main".
+//
+// INITIALIZE_STACK
+//
+//   If defined, the contents of the stack will be initialized to a the
+//   value 0xCC.
+//
+// INITIALIZE_SECONDARY_SECTIONS
+//
+//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
+//
+// INITIALIZE_TCM_SECTIONS
+//
+//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
+//   will be initialized.
+//
+// INITIALIZE_USER_SECTIONS
+//
+//   If defined, the function InitializeUserMemorySections will be called prior
+//   to entering main in order to allow the user to initialize any user defined
+//   memory sections.
+//
+// FULL_LIBRARY
+//
+//  If defined then 
+//    - argc, argv are setup by the debug_getargs.
+//    - the exit symbol is defined and executes on return from main.
+//    - the exit symbol calls destructors, atexit functions and then debug_exit.
+//  
+//  If not defined then
+//    - argc and argv are zero.
+//    - the exit symbol is defined, executes on return from main and loops
+//
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+  .syntax unified
+
+  .global _start
+  .extern APP_ENTRY_POINT
+  .global exit
+  .weak exit
+
+#ifdef INITIALIZE_USER_SECTIONS
+  .extern InitializeUserMemorySections
+#endif
+
+  .section .init, "ax"
+  .code 16
+  .balign 2
+  .thumb_func
+
+_start:
+  /* Set up main stack if size > 0 */
+  ldr r1, =__stack_end__
+  ldr r0, =__stack_start__
+  subs r2, r1, r0
+  beq 1f
+#ifdef __ARM_EABI__
+  movs r2, #0x7
+  bics r1, r2
+#endif
+  mov sp, r1
+#ifdef INITIALIZE_STACK
+  movs r2, #0xCC
+  ldr r0, =__stack_start__
+  bl memory_set
+#endif
+1:
+
+  /* Set up process stack if size > 0 */
+  ldr r1, =__stack_process_end__
+  ldr r0, =__stack_process_start__
+  subs r2, r1, r0
+  beq 1f
+#ifdef __ARM_EABI__
+  movs r2, #0x7
+  bics r1, r2
+#endif
+  msr psp, r1
+  movs r2, #2
+  msr control, r2
+#ifdef INITIALIZE_STACK
+  movs r2, #0xCC
+  bl memory_set
+#endif
+1:
+
+  /* Copy initialized memory sections into RAM (if necessary). */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  ldr r2, =__data_end__
+  bl memory_copy
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  ldr r2, =__text_end__
+  bl memory_copy
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  ldr r2, =__fast_end__
+  bl memory_copy
+  ldr r0, =__ctors_load_start__
+  ldr r1, =__ctors_start__
+  ldr r2, =__ctors_end__
+  bl memory_copy
+  ldr r0, =__dtors_load_start__
+  ldr r1, =__dtors_start__
+  ldr r2, =__dtors_end__
+  bl memory_copy
+  ldr r0, =__rodata_load_start__
+  ldr r1, =__rodata_start__
+  ldr r2, =__rodata_end__
+  bl memory_copy
+  ldr r0, =__tdata_load_start__
+  ldr r1, =__tdata_start__
+  ldr r2, =__tdata_end__
+  bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+  ldr r0, =__data2_load_start__
+  ldr r1, =__data2_start__
+  ldr r2, =__data2_end__
+  bl memory_copy
+  ldr r0, =__text2_load_start__
+  ldr r1, =__text2_start__
+  ldr r2, =__text2_end__
+  bl memory_copy
+  ldr r0, =__rodata2_load_start__
+  ldr r1, =__rodata2_start__
+  ldr r2, =__rodata2_end__
+  bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+#ifdef INITIALIZE_TCM_SECTIONS
+  ldr r0, =__data_tcm_load_start__
+  ldr r1, =__data_tcm_start__
+  ldr r2, =__data_tcm_end__
+  bl memory_copy
+  ldr r0, =__text_tcm_load_start__
+  ldr r1, =__text_tcm_start__
+  ldr r2, =__text_tcm_end__
+  bl memory_copy
+  ldr r0, =__rodata_tcm_load_start__
+  ldr r1, =__rodata_tcm_start__
+  ldr r2, =__rodata_tcm_end__
+  bl memory_copy
+#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
+
+  /* Zero the bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  movs r2, #0
+  bl memory_set
+  ldr r0, =__tbss_start__
+  ldr r1, =__tbss_end__
+  movs r2, #0
+  bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+  ldr r0, =__bss2_start__
+  ldr r1, =__bss2_end__
+  mov r2, #0
+  bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+#ifdef INITIALIZE_TCM_SECTIONS
+  ldr r0, =__bss_tcm_start__
+  ldr r1, =__bss_tcm_end__
+  mov r2, #0
+  bl memory_set
+#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
+
+  /* Initialize the heap */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  subs r1, r1, r0
+  cmp r1, #8
+  blt 1f
+  movs r2, #0
+  str r2, [r0]
+  adds r0, r0, #4
+  str r1, [r0]
+1:
+
+#ifdef INITIALIZE_USER_SECTIONS
+  ldr r2, =InitializeUserMemorySections
+  blx r2
+#endif
+
+  /* Call constructors */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+ctor_loop:
+  cmp r0, r1
+  beq ctor_end
+  ldr r2, [r0]
+  adds r0, #4
+  push {r0-r1}  
+  blx r2
+  pop {r0-r1}
+  b ctor_loop
+ctor_end:
+
+  /* Setup initial call frame */
+  movs r0, #0
+  mov lr, r0
+  mov r12, sp
+
+  .type start, function
+start:
+  /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+  movs r0, #ARGSSPACE
+  ldr r1, =args
+  ldr r2, =debug_getargs  
+  blx r2
+  ldr r1, =args
+#else
+  movs r0, #0
+  movs r1, #0
+#endif
+  ldr r2, =APP_ENTRY_POINT
+  blx r2
+
+  .thumb_func
+exit:
+#ifdef FULL_LIBRARY  
+  mov r5, r0 // save the exit parameter/return result
+
+  /* Call destructors */
+  ldr r0, =__dtors_start__
+  ldr r1, =__dtors_end__
+dtor_loop:
+  cmp r0, r1
+  beq dtor_end
+  ldr r2, [r0]
+  add r0, #4
+  push {r0-r1}
+  blx r2
+  pop {r0-r1}
+  b dtor_loop
+dtor_end:
+
+  /* Call atexit functions */
+  ldr r2, =_execute_at_exit_fns  
+  blx r2
+
+  /* Call debug_exit with return result/exit parameter */
+  mov r0, r5
+  ldr r2, =debug_exit  
+  blx r2
+#endif
+
+  /* Returned from application entry point, loop forever. */
+exit_loop:
+  b exit_loop
+
+  .thumb_func
+memory_copy:
+  cmp r0, r1
+  beq 2f
+  subs r2, r2, r1
+  beq 2f
+1:
+  ldrb r3, [r0]
+  adds r0, r0, #1
+  strb r3, [r1]
+  adds r1, r1, #1
+  subs r2, r2, #1
+  bne 1b
+2:
+  bx lr
+
+  .thumb_func
+memory_set:
+  cmp r0, r1
+  beq 1f
+  strb r2, [r0]
+  adds r0, r0, #1
+  b memory_set
+1:
+  bx lr
+
+  // default C/C++ library helpers
+
+.macro HELPER helper_name
+  .section .text.\helper_name, "ax", %progbits
+  .balign 2
+  .global \helper_name
+  .weak \helper_name  
+\helper_name:
+  .thumb_func
+.endm
+
+.macro JUMPTO name
+#if defined(__thumb__) && !defined(__thumb2__)
+  mov r12, r0
+  ldr r0, =\name
+  push {r0}
+  mov r0, r12
+  pop {pc}
+#else
+  b \name
+#endif
+.endm
+
+HELPER __aeabi_read_tp
+  ldr r0, =__tbss_start__-8
+  bx lr
+HELPER abort
+  b .
+HELPER __assert
+  b .
+HELPER __aeabi_assert
+  b .
+HELPER __sync_synchronize
+  bx lr
+HELPER __getchar
+  JUMPTO debug_getchar
+HELPER __putchar
+  JUMPTO debug_putchar
+HELPER __open
+  JUMPTO debug_fopen
+HELPER __close
+  JUMPTO debug_fclose
+HELPER __write   
+  mov r3, r0
+  mov r0, r1
+  movs r1, #1  
+  JUMPTO debug_fwrite
+HELPER __read  
+  mov r3, r0
+  mov r0, r1
+  movs r1, #1 
+  JUMPTO debug_fread
+HELPER __seek
+  push {r4, lr}
+  mov r4, r0
+  bl debug_fseek
+  cmp r0, #0
+  bne 1f
+  mov r0, r4
+  bl debug_ftell
+  pop {r4, pc}
+1:
+  ldr r0, =-1
+  pop {r4, pc}
+  // char __user_locale_name_buffer[];
+  .section .bss.__user_locale_name_buffer, "aw", %nobits
+  .global __user_locale_name_buffer
+  .weak __user_locale_name_buffer
+  __user_locale_name_buffer:
+  .word 0x0
+
+#ifdef FULL_LIBRARY
+  .bss
+args:
+  .space ARGSSPACE
+#endif
+
+  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
+  .section .stack, "wa", %nobits
+  .section .stack_process, "wa", %nobits
+  .section .heap, "wa", %nobits
+
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index a9cfeab38..306778ee3 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -52,24 +52,25 @@
 
 #include "ansi_escape.h"
 
+// NXP LPC
 #if defined BOARD_LPCXPRESSO11U14
   #include "lpcxpresso11u14/board_lpcxpresso11u14.h"
-#elif defined BOARD_LPCXPRESSO11U68
-  #include "lpcxpresso11u68/board_lpcxpresso11u68.h"
 #elif defined BOARD_LPCXPRESSO1347
   #include "lpcxpresso1347/board_lpcxpresso1347.h"
+#elif defined BOARD_LPCXPRESSO11U68
+  #include "lpcxpresso11u68/board_lpcxpresso11u68.h"
 #elif defined BOARD_LPCXPRESSO1769
   #include "lpcxpresso1769/board_lpcxpresso1769.h"
-#elif defined BOARD_NGX4330
-  #include "ngx/board_ngx4330.h"
+#elif defined BOARD_MCB1800
+  #include "mcb1800/board_mcb1800.h"
 #elif defined BOARD_EA4357
   #include "ea4357/board_ea4357.h"
-#elif defined BOARD_MCB4300
-  #include "keil/board_mcb4300.h"
-#elif defined BOARD_LPCLINK2
-  #include "lpcxpresso/board_lpclink2.h"
+
+// Nordic nRF
 #elif defined BOARD_PCA10056
   #include "pca10056/board_pca10056.h"
+
+// Atmel SAM
 #elif defined BOARD_METRO_M4_EXPRESS
   #include "metro_m4_express/board_metro_m4_express.h"
 #elif defined BOARD_METRO_M0_EXPRESS
diff --git a/hw/bsp/ea4357/board_ea4357.c b/hw/bsp/ea4357/board_ea4357.c
index 754b68aa1..d59e4cb3c 100644
--- a/hw/bsp/ea4357/board_ea4357.c
+++ b/hw/bsp/ea4357/board_ea4357.c
@@ -38,7 +38,7 @@
 
 #ifdef BOARD_EA4357
 
-#include "bsp/board.h"
+#include "../board.h"
 #include "pca9532.h"
 
 #define BOARD_UART_PORT           LPC_USART0
@@ -184,9 +184,7 @@ void board_init(void)
   // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
 }
 
-//--------------------------------------------------------------------+
-// LEDS
-//--------------------------------------------------------------------+
+// LED
 void board_led_control(bool state)
 {
   if (state)
diff --git a/hw/bsp/mcb1800/board_mcb1800.c b/hw/bsp/mcb1800/board_mcb1800.c
new file mode 100644
index 000000000..7fe43e638
--- /dev/null
+++ b/hw/bsp/mcb1800/board_mcb1800.c
@@ -0,0 +1,399 @@
+/**************************************************************************/
+/*!
+ @file    board_mcb1800.c
+ @author  hathach (tinyusb.org)
+
+ @section LICENSE
+
+ Software License Agreement (BSD License)
+
+ Copyright (c) 2018, hathach (tinyusb.org)
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holders nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#ifdef BOARD_MCB1800
+
+#include "../board.h"
+#include "tusb.h"
+
+#define LED_PORT  6
+#define LED_PIN   24
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+/* System configuration variables used by chip driver */
+const uint32_t ExtRateIn = 0;
+const uint32_t OscRateIn = 12000000;
+
+STATIC const PINMUX_GRP_T pinmuxing[] = {
+	/* RMII pin group */
+	{0x1, 19,
+	 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
+	{0x0, 1,  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
+	{0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
+	{0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
+	{0x1, 17,
+	 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
+	{0xC, 1,  (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
+	{0x1, 16,
+	 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
+	{0x1, 15,
+	 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
+	{0x0, 0,
+	 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
+	/* External data lines D0 .. D15 */
+	{0x1, 7,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 8,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 9,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 10,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 11,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 12,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 13,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 14,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x5, 4,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 5,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 6,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 7,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 0,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 1,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 2,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x5, 3,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 2,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 3,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 4,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 5,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 6,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 7,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 8,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 9,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xE, 5,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 6,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 7,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 8,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 9,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 10,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 11,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 12,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	/* Address lines A0 .. A23 */
+	{0x2, 9,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x2, 10,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x2, 11,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x2, 12,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x2, 13,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 0,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x1, 1,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x1, 2,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x2, 8,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x2, 7,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x2, 6,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x2, 2,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x2, 1,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x2, 0,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x6, 8,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
+	{0x6, 7,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
+	{0xD, 16,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 15,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xE, 0,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 1,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 2,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 3,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xE, 4,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xA, 4,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	/* EMC control signals */
+	{0x1, 4,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x6, 6,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
+	{0xD, 13,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xD, 10,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0x6, 9,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 6,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x6, 4,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x6, 5,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x6, 11,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x6, 12,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x6, 10,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0xD, 0,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
+	{0xE, 13,
+	 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
+	{0x1, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
+	{0x1, 4,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
+	{0x6, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC1)},
+	{0x1, 5,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
+	{0x1, 6,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
+	/* Board LEDs */
+	{0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
+	{0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
+	{0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
+	{0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
+	{0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
+	{0x9, 0,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
+	{0x9, 1,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
+	{0x9, 2,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
+	/* SSP0 */
+	{0xF, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC0)},
+	{0xF, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
+	{0xF, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
+	{0xF, 3,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
+	/* LCD interface, 16bpp */
+	{0x4, 1, ( SCU_MODE_PULLUP | SCU_MODE_FUNC5)},
+	{0x4, 2, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0x4, 5, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0x4, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0x4, 7, ( SCU_MODE_PULLUP | SCU_MODE_FUNC0)},
+	{0x4, 9, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0x4, 10, (SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0x7, 0, ( SCU_MODE_PULLUP | SCU_MODE_FUNC0)},
+	{0x7, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
+	{0x8, 3, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
+	{0x8, 4, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
+	{0x8, 5, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
+	{0x8, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
+	{0x8, 7, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
+	{0xB, 0, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0xB, 1, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0xB, 2, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0xB, 3, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0xB, 4, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0xB, 5, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	{0xB, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
+	/*  I2S  */
+	{0x3, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
+	{0x6, 0,  (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
+	{0x7, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
+	{0x6, 2,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
+	{0x7, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
+	{0x6, 1,  (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
+	/*  CCAN  */
+	{0x3, 2,    (SCU_MODE_INACT | SCU_MODE_FUNC2)},	/* PE.3 CAN TD1 | SCU_MODE_FUNC1) */
+	{0x3, 1,    (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2)},	/* PE.2	CAN RD1 | SCU_MODE_FUNC1) */
+};
+
+
+/* Pin clock mux values, re-used structure, value in first index is meaningless */
+STATIC const PINMUX_GRP_T pinclockmuxing[] = {
+	{0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+	{0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+	{0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+	{0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+};
+
+
+/*------------------------------------------------------------------*/
+/* BOARD API
+ *------------------------------------------------------------------*/
+// Invoked by startup code
+void SystemInit(void)
+{
+	/* Setup system level pin muxing */
+	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+
+	/* Clock pins only, group field not used */
+	for (int i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
+	{
+		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+	}
+
+  Chip_SetupXtalClocking();
+}
+
+void board_init(void)
+{
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config( SystemCoreClock / BOARD_TICKS_HZ );
+#endif
+
+  Chip_GPIO_Init(LPC_GPIO_PORT);
+
+  //------------- LED -------------//
+  /* Port and bit mapping for LEDs on GPIOs */
+  const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4};
+  const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14};
+
+  for (int i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) 
+  {
+    Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, ledports[i], ledbits[i]);
+    Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, false);
+  }
+
+#if 0
+  //------------- BUTTON -------------//
+  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++)
+  {
+    scu_pinmux(buttons[i].mux_port, buttons[i].mux_pin, GPIO_NOPULL, FUNC0);
+    GPIO_SetDir(buttons[i].gpio_port, BIT_(buttons[i].gpio_pin), 0);
+  }
+
+  //------------- UART -------------//
+  scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_TX, MD_PDN, FUNC1);
+  scu_pinmux(BOARD_UART_PIN_PORT, BOARD_UART_PIN_RX, MD_PLN | MD_EZI | MD_ZI, FUNC1);
+
+  UART_CFG_Type UARTConfigStruct;
+  UART_ConfigStructInit(&UARTConfigStruct);
+  UARTConfigStruct.Baud_rate   = CFG_UART_BAUDRATE;
+  UARTConfigStruct.Clock_Speed = 0;
+
+  UART_Init(BOARD_UART_PORT, &UARTConfigStruct);
+  UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
+#endif
+
+  //------------- USB -------------//
+  // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
+  Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
+
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
+  Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
+  #endif
+
+  // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
+  // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
+}
+
+void board_led_control(bool state)
+{
+  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
+}
+
+//------------- Buttons -------------//
+static bool button_read(uint8_t id)
+{
+//  return !BIT_TEST_( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
+}
+
+uint32_t board_buttons(void)
+{
+  uint32_t result = 0;
+
+//  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
+
+  return result;
+}
+
+
+//------------- UART -------------//
+uint8_t  board_uart_getchar(void)
+{
+  //return UART_ReceiveByte(BOARD_UART_PORT);
+}
+void board_uart_putchar(uint8_t c)
+{
+  //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
+}
+
+/*------------------------------------------------------------------*/
+/* TUSB HAL MILLISECOND
+ *------------------------------------------------------------------*/
+#if CFG_TUSB_OS == OPT_OS_NONE
+
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t tusb_hal_millis(void)
+{
+  return board_tick2ms(system_ticks);
+}
+
+#endif
+
+#endif
+
diff --git a/hw/bsp/mcb1800/board_mcb1800.h b/hw/bsp/mcb1800/board_mcb1800.h
new file mode 100644
index 000000000..ac8bf124d
--- /dev/null
+++ b/hw/bsp/mcb1800/board_mcb1800.h
@@ -0,0 +1,51 @@
+/**************************************************************************/
+/*!
+ @file    board_mcb1800.h
+ @author  hathach (tinyusb.org)
+
+ @section LICENSE
+
+ Software License Agreement (BSD License)
+
+ Copyright (c) 2018, hathach (tinyusb.org)
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holders nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+#ifndef BOARD_MCB1800_H_
+#define BOARD_MCB1800_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "chip.h"
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_MCB1800_H_ */
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
index a611bc081..af1fa619c 100644
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
@@ -38,7 +38,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_LPC43XX
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -47,7 +47,7 @@
 #include "tusb_hal.h"
 
 #include "device/dcd.h"
-#include "dcd_lpc43xx.h"
+#include "dcd_lpc18_43.h"
 
 #include "chip.h"
 
diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
index 76bd56b20..f91cf1309 100644
--- a/src/portable/nxp/lpc18_43/hal_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
@@ -38,7 +38,7 @@
 
 #include "tusb.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX
+#if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX)
 
 #include "chip.h"
 
@@ -144,11 +144,4 @@ void USB1_IRQHandler(void)
 }
 #endif
 
-
-void check_failed(uint8_t *file, uint32_t line)
-{
-  (void) file;
-  (void) line;
-}
-
 #endif
-- 
cgit v1.3.1


From 261e0f9801abc7f6d13afcad51b5feadd19f50ee Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Dec 2018 16:06:50 +0700
Subject: adding lpc40xx support

---
 hw/bsp/ea4088qs/board_ea4088qs.c                   |   53 +
 hw/bsp/ea4088qs/board_ea4088qs.h                   |   51 +
 hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c       |    2 +-
 hw/bsp/readme.md                                   |   11 +-
 hw/mcu/nxp/lpc_chip_40xx/.cproject                 |  219 +++
 hw/mcu/nxp/lpc_chip_40xx/.project                  |   26 +
 hw/mcu/nxp/lpc_chip_40xx/inc/adc_17xx_40xx.h       |  263 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/can_17xx_40xx.h       | 1130 +++++++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/chip.h                |  152 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h     |  190 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h     |  203 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h     |  206 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h     |  896 ++++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/cmp_17xx_40xx.h       |  408 +++++
 hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h               |   66 +
 hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h          |  171 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h            | 1772 ++++++++++++++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h       |  673 ++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h         |  636 +++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h        |  688 ++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/crc_17xx_40xx.h       |  236 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/dac_17xx_40xx.h       |  166 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/eeprom_17xx_40xx.h    |  320 ++++
 hw/mcu/nxp/lpc_chip_40xx/inc/emc_17xx_40xx.h       |  358 ++++
 hw/mcu/nxp/lpc_chip_40xx/inc/enet_17xx_40xx.h      |  914 ++++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/error.h               |  184 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/fmc_17xx_40xx.h       |  133 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/fpu_init.h            |   52 +
 hw/mcu/nxp/lpc_chip_40xx/inc/gpdma_17xx_40xx.h     |  450 +++++
 hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h      |  491 ++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/gpioint_17xx_40xx.h   |  227 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/i2c_17xx_40xx.h       |  541 ++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/i2s_17xx_40xx.h       |  534 ++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/iap.h                 |  184 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h     |  274 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/lcd_17xx_40xx.h       |  387 +++++
 hw/mcu/nxp/lpc_chip_40xx/inc/lpc_types.h           |  216 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/mcpwm_17xx_40xx.h     |   80 +
 hw/mcu/nxp/lpc_chip_40xx/inc/pmu_17xx_40xx.h       |  135 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/qei_17xx_40xx.h       |   86 +
 hw/mcu/nxp/lpc_chip_40xx/inc/ring_buffer.h         |  188 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/ritimer_17xx_40xx.h   |  199 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/romapi_17xx_40xx.h    |   91 +
 hw/mcu/nxp/lpc_chip_40xx/inc/rtc_17xx_40xx.h       |  646 +++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/sdc_17xx_40xx.h       |  583 +++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc.h               |  450 +++++
 hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc_17xx_40xx.h     |  202 +++
 hw/mcu/nxp/lpc_chip_40xx/inc/spi_17xx_40xx.h       |  416 +++++
 hw/mcu/nxp/lpc_chip_40xx/inc/spifi_17xx_40xx.h     |   79 +
 hw/mcu/nxp/lpc_chip_40xx/inc/ssp_17xx_40xx.h       |  598 +++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/stopwatch.h           |  137 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h          |   42 +
 hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h    |  360 ++++
 hw/mcu/nxp/lpc_chip_40xx/inc/timer_17xx_40xx.h     |  445 +++++
 hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h      |  814 +++++++++
 hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h       |  160 ++
 hw/mcu/nxp/lpc_chip_40xx/inc/wwdt_17xx_40xx.h      |  276 +++
 hw/mcu/nxp/lpc_chip_40xx/src/adc_17xx_40xx.c       |  256 +++
 hw/mcu/nxp/lpc_chip_40xx/src/can_17xx_40xx.c       | 1507 +++++++++++++++++
 hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c      |  110 ++
 hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c     |  516 ++++++
 hw/mcu/nxp/lpc_chip_40xx/src/cmp_17xx_40xx.c       |   64 +
 hw/mcu/nxp/lpc_chip_40xx/src/crc_17xx_40xx.c       |  110 ++
 hw/mcu/nxp/lpc_chip_40xx/src/dac_17xx_40xx.c       |   84 +
 hw/mcu/nxp/lpc_chip_40xx/src/eeprom_17xx_40xx.c    |  258 +++
 hw/mcu/nxp/lpc_chip_40xx/src/emc_17xx_40xx.c       |  282 ++++
 hw/mcu/nxp/lpc_chip_40xx/src/enet_17xx_40xx.c      |  289 ++++
 hw/mcu/nxp/lpc_chip_40xx/src/fpu_init.c            |   97 ++
 hw/mcu/nxp/lpc_chip_40xx/src/gpdma_17xx_40xx.c     |  704 ++++++++
 hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c      |   46 +
 hw/mcu/nxp/lpc_chip_40xx/src/gpioint_17xx_40xx.c   |   46 +
 hw/mcu/nxp/lpc_chip_40xx/src/i2c_17xx_40xx.c       |  561 +++++++
 hw/mcu/nxp/lpc_chip_40xx/src/i2s_17xx_40xx.c       |  260 +++
 hw/mcu/nxp/lpc_chip_40xx/src/iap.c                 |  175 ++
 hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c     |   83 +
 hw/mcu/nxp/lpc_chip_40xx/src/lcd_17xx_40xx.c       |  210 +++
 hw/mcu/nxp/lpc_chip_40xx/src/pmu_17xx_40xx.c       |  118 ++
 hw/mcu/nxp/lpc_chip_40xx/src/ring_buffer.c         |  167 ++
 hw/mcu/nxp/lpc_chip_40xx/src/ritimer_17xx_40xx.c   |  100 ++
 hw/mcu/nxp/lpc_chip_40xx/src/rtc_17xx_40xx.c       |  221 +++
 hw/mcu/nxp/lpc_chip_40xx/src/sdc_17xx_40xx.c       |  247 +++
 hw/mcu/nxp/lpc_chip_40xx/src/sdmmc_17xx_40xx.c     | 1196 +++++++++++++
 hw/mcu/nxp/lpc_chip_40xx/src/spi_17xx_40xx.c       |  227 +++
 hw/mcu/nxp/lpc_chip_40xx/src/ssp_17xx_40xx.c       |  478 ++++++
 hw/mcu/nxp/lpc_chip_40xx/src/stopwatch_17xx_40xx.c |  110 ++
 hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c    |   70 +
 hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c   |  178 ++
 hw/mcu/nxp/lpc_chip_40xx/src/timer_17xx_40xx.c     |  116 ++
 hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c      |  533 ++++++
 hw/mcu/nxp/lpc_chip_40xx/src/wwdt_17xx_40xx.c      |   72 +
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c           |  590 +++++++
 src/portable/nxp/lpc17_40/dcd_lpc17_40.h           |  164 ++
 src/portable/nxp/lpc17_40/hal_lpc17_40.c           |  108 ++
 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c          |  590 -------
 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.h          |  164 --
 src/portable/nxp/lpc17xx/hal_lpc175x_6x.c          |  108 --
 src/portable/nxp/lpc18_43/dcd_lpc18_43.c           |   15 +-
 src/portable/nxp/lpc18_43/dcd_lpc18_43.h           |    4 -
 src/tusb_option.h                                  |    5 +-
 99 files changed, 29831 insertions(+), 878 deletions(-)
 create mode 100644 hw/bsp/ea4088qs/board_ea4088qs.c
 create mode 100644 hw/bsp/ea4088qs/board_ea4088qs.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/.cproject
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/.project
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/adc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/can_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/chip.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/cmp_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/crc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/dac_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/eeprom_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/emc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/enet_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/error.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/fmc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/fpu_init.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/gpdma_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/gpioint_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/i2c_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/i2s_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/iap.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/lcd_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/lpc_types.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/mcpwm_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/pmu_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/qei_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/ring_buffer.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/ritimer_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/romapi_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/rtc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/sdc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/spi_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/spifi_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/ssp_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/stopwatch.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/timer_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/inc/wwdt_17xx_40xx.h
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/adc_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/can_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/cmp_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/crc_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/dac_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/eeprom_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/emc_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/enet_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/fpu_init.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/gpdma_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/gpioint_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/i2c_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/i2s_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/iap.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/lcd_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/pmu_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/ring_buffer.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/ritimer_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/rtc_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/sdc_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/sdmmc_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/spi_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/ssp_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/stopwatch_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/timer_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c
 create mode 100644 hw/mcu/nxp/lpc_chip_40xx/src/wwdt_17xx_40xx.c
 create mode 100644 src/portable/nxp/lpc17_40/dcd_lpc17_40.c
 create mode 100644 src/portable/nxp/lpc17_40/dcd_lpc17_40.h
 create mode 100644 src/portable/nxp/lpc17_40/hal_lpc17_40.c
 delete mode 100644 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
 delete mode 100644 src/portable/nxp/lpc17xx/dcd_lpc175x_6x.h
 delete mode 100644 src/portable/nxp/lpc17xx/hal_lpc175x_6x.c

(limited to 'src')

diff --git a/hw/bsp/ea4088qs/board_ea4088qs.c b/hw/bsp/ea4088qs/board_ea4088qs.c
new file mode 100644
index 000000000..9df56c183
--- /dev/null
+++ b/hw/bsp/ea4088qs/board_ea4088qs.c
@@ -0,0 +1,53 @@
+/**************************************************************************/
+/*!
+ @file    board_ea4088qs.c
+ @author  hathach (tinyusb.org)
+
+ @section LICENSE
+
+ Software License Agreement (BSD License)
+
+ Copyright (c) 2018, hathach (tinyusb.org)
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holders nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#ifdef BOARD_EA4088QS
+
+#include "../board.h"
+
+#define LED_PORT      0
+#define LED_PIN       22
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+//------------- IMPLEMENTATION -------------//
+
+#endif
diff --git a/hw/bsp/ea4088qs/board_ea4088qs.h b/hw/bsp/ea4088qs/board_ea4088qs.h
new file mode 100644
index 000000000..dc5854ada
--- /dev/null
+++ b/hw/bsp/ea4088qs/board_ea4088qs.h
@@ -0,0 +1,51 @@
+/**************************************************************************/
+/*!
+ @file    board_ea4088qs.h
+ @author  hathach (tinyusb.org)
+
+ @section LICENSE
+
+ Software License Agreement (BSD License)
+
+ Copyright (c) 2018, hathach (tinyusb.org)
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holders nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+#ifndef BOARD_EA4088QS_H_
+#define BOARD_EA4088QS_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "chip.h"
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_EA4088QS_H_ */
diff --git a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
index 7e5529709..a17454d29 100644
--- a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
@@ -39,7 +39,7 @@
 
 #ifdef BOARD_LPCXPRESSO1769
 
-#include "bsp/board.h"
+#include "../board.h"
 
 #define LED_PORT      0
 #define LED_PIN       22
diff --git a/hw/bsp/readme.md b/hw/bsp/readme.md
index 3f6f7eb8a..4b4e928ae 100644
--- a/hw/bsp/readme.md
+++ b/hw/bsp/readme.md
@@ -6,11 +6,12 @@ This code base already had supported for a handful of boards. However due to my
 
 ### NXP MCU ###
 
-- LPCXpresso 11U68
-- [**LPCXpresso 1347**](http://www.embeddedartists.com/products/lpcxpresso/lpc1347_xpr.php) with base board (for some peripherals to work)
-- [**LPCXpresso 1769**](http://www.embeddedartists.com/products/lpcxpresso/lpc1347_xpr.php) with base board (for some peripherals to work)
-- [Keil MCB1800 Evaluation Board](http://www.keil.com/mcb1800)
-- [**Embedded Artists LPC4357 OEM & Base board**](http://www.embeddedartists.com/products/kits/lpc4357_kit.php)
+- [**LPCXpresso 11U68**](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc11u68:OM13058)
+- [**LPCXpresso 1347**](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1347:OM13045)
+- [**LPCXpresso 1769**](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1769:OM13000)
+- [**Keil MCB1800 Evaluation Board**](http://www.keil.com/mcb1800)
+- [**Embedded Artists LPC4088 Quick Start board**](https://www.embeddedartists.com/products/lpc4088-quickstart-board)
+- [**Embedded Artists LPC4357 Developer Kit**](http://www.embeddedartists.com/products/kits/lpc4357_kit.php)
 
 ### MicroChip SAMD ###
 
diff --git a/hw/mcu/nxp/lpc_chip_40xx/.cproject b/hw/mcu/nxp/lpc_chip_40xx/.cproject
new file mode 100644
index 000000000..debdb475a
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/.cproject
@@ -0,0 +1,219 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.crt.advproject.config.lib.debug.488589898">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.lib.debug.488589898" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings>
+					<externalSetting>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/lpc_chip_40xx"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/lpc_chip_40xx/Debug"/>
+						<entry flags="RESOLVED" kind="libraryFile" name="lpc_chip_40xx" srcPrefixMapping="" srcRootPath=""/>
+					</externalSetting>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.lib.debug.488589898" name="Debug" parent="com.crt.advproject.config.lib.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;lib${BuildArtifactFileName}&quot; ; # arm-none-eabi-objdump -h -S &quot;lib${BuildArtifactFileName}&quot; &gt;&quot;${BuildArtifactFileBaseName}.lss&quot;">
+					<folderInfo id="com.crt.advproject.config.lib.debug.488589898." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.lib.debug.1243271677" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.lib.debug">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.lib.debug.514063794" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.lib.debug"/>
+							<builder buildPath="${workspace_loc:/lpc_chip_40xx}/Debug" id="com.crt.advproject.builder.lib.debug.1364751995" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.lib.debug"/>
+							<tool id="com.crt.advproject.cpp.lib.debug.637996021" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.lib.debug"/>
+							<tool id="com.crt.advproject.gcc.lib.debug.815926782" name="MCU C Compiler" superClass="com.crt.advproject.gcc.lib.debug">
+								<option id="com.crt.advproject.gcc.arch.738206826" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.thumb.782112307" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.2029893922" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="__REDLIB__"/>
+									<listOptionValue builtIn="false" value="DEBUG"/>
+									<listOptionValue builtIn="false" value="__CODE_RED"/>
+									<listOptionValue builtIn="false" value="__USE_LPCOPEN"/>
+									<listOptionValue builtIn="false" value="CORE_M4"/>
+								</option>
+								<option id="gnu.c.compiler.option.misc.other.1796613038" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fsingle-precision-constant" valueType="string"/>
+								<option id="gnu.c.compiler.option.include.paths.1624409724" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc}&quot;"/>
+								</option>
+								<option id="com.crt.advproject.gcc.hdrlib.648300082" superClass="com.crt.advproject.gcc.hdrlib" value="Redlib" valueType="enumerated"/>
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+							</tool>
+							<tool id="com.crt.advproject.gas.lib.debug.838868324" name="MCU Assembler" superClass="com.crt.advproject.gas.lib.debug">
+								<option id="com.crt.advproject.gas.arch.1725544584" name="Architecture" superClass="com.crt.advproject.gas.arch" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.thumb.1870502517" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" value="true" valueType="boolean"/>
+								<option id="gnu.both.asm.option.flags.crt.2068952934" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" value="-c -x assembler-with-cpp -D__REDLIB__ -DDEBUG -D__CODE_RED" valueType="string"/>
+								<option id="com.crt.advproject.gas.hdrlib.115925876" superClass="com.crt.advproject.gas.hdrlib" value="Redlib" valueType="enumerated"/>
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+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1125448621" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+								<inputType id="com.crt.advproject.assembler.input.257461317" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+							</tool>
+							<tool id="com.crt.advproject.ar.lib.debug.801619814" name="MCU Archiver" superClass="com.crt.advproject.ar.lib.debug"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="inc"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="libs"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.crt.advproject.config.lib.release.1914508511">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.lib.release.1914508511" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings>
+					<externalSetting>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/lpc_chip_40xx"/>
+						<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/lpc_chip_40xx/Release"/>
+						<entry flags="RESOLVED" kind="libraryFile" name="lpc_chip_40xx" srcPrefixMapping="" srcRootPath=""/>
+					</externalSetting>
+				</externalSettings>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib" cleanCommand="rm -rf" description="Release build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.lib.release.1914508511" name="Release" parent="com.crt.advproject.config.lib.release" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;lib${BuildArtifactFileName}&quot; ; # arm-none-eabi-objdump -h -S &quot;lib${BuildArtifactFileName}&quot; &gt;&quot;${BuildArtifactFileBaseName}.lss&quot;">
+					<folderInfo id="com.crt.advproject.config.lib.release.1914508511." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.lib.release.1876037804" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.lib.release">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.lib.release.181125685" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.lib.release"/>
+							<builder buildPath="${workspace_loc:/lpc_chip_40xx}/Release" id="com.crt.advproject.builder.lib.release.2021892158" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.lib.release"/>
+							<tool id="com.crt.advproject.cpp.lib.release.1523476515" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.lib.release"/>
+							<tool id="com.crt.advproject.gcc.lib.release.353683273" name="MCU C Compiler" superClass="com.crt.advproject.gcc.lib.release">
+								<option id="com.crt.advproject.gcc.arch.295952267" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.thumb.2093081092" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" value="true" valueType="boolean"/>
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.940702662" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" valueType="definedSymbols">
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+									<listOptionValue builtIn="false" value="__USE_LPCOPEN"/>
+									<listOptionValue builtIn="false" value="CORE_M4"/>
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+								<option id="gnu.c.compiler.option.misc.other.1188528943" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -fsingle-precision-constant" valueType="string"/>
+								<option id="gnu.c.compiler.option.include.paths.1029102987" superClass="gnu.c.compiler.option.include.paths" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc}&quot;"/>
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+								<option id="com.crt.advproject.gcc.lib.release.option.optimization.level.1021563918" superClass="com.crt.advproject.gcc.lib.release.option.optimization.level" value="gnu.c.optimization.level.size" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.hdrlib.1872638133" superClass="com.crt.advproject.gcc.hdrlib" value="Redlib" valueType="enumerated"/>
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+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="lpc_chip_40xx.com.crt.advproject.projecttype.lib.1226452111" name="Static Library" projectType="com.crt.advproject.projecttype.lib"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC177x_8x_407x_8x_512.cfx" property_3="NXP" property_4="LPC4088" property_count="5" version="70002"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC4088" flash_driver="LPC177x_8x_407x_8x_512.cfx" match_id="0x481D3F47" name="LPC4088" stub="crt_emu_cm3_nxp"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC4088&lt;/name&gt;&#13;
+&lt;family&gt;LPC407x_8x&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamLoc64" location="0x10000000" size="0x10000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph32" location="0x20000000" size="0x8000"/&gt;&#13;
+&lt;prog_flash blocksz="0x1000" location="0x0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/&gt;&#13;
+&lt;prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" determined="infoFile" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" determined="infoFile" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x200000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPDMA" determined="infoFile" id="GPDMA" location="0x20080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ETHERNET" determined="infoFile" id="ETHERNET" location="0x20084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="LCD" determined="infoFile" id="LCD" location="0x20088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x2008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x20090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO" determined="infoFile" id="GPIO" location="0x20098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" determined="infoFile" id="EMC" location="0x2009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER0" determined="infoFile" id="TIMER0" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER1" determined="infoFile" id="TIMER1" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART0" determined="infoFile" id="UART0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" determined="infoFile" id="UART1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM0" determined="infoFile" id="PWM0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PWM1" determined="infoFile" id="PWM1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="COMPARATOR" determined="infoFile" id="COMPARATOR" location="0x40020000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" determined="infoFile" id="RTC" location="0x40024000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIOINT" determined="infoFile" id="GPIOINT" location="0x40028080"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x4002c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40030000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x40034000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAFRAM" determined="infoFile" id="CANAFRAM" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CANAF" determined="infoFile" id="CANAF" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCAN" determined="infoFile" id="CCAN" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN1" determined="infoFile" id="CAN1" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CAN2" determined="infoFile" id="CAN2" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" determined="infoFile" id="DAC" location="0x4008c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER2" determined="infoFile" id="TIMER2" location="0x40090000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER3" determined="infoFile" id="TIMER3" location="0x40094000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART2" determined="infoFile" id="UART2" location="0x40098000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART3" determined="infoFile" id="UART3" location="0x4009c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C2" determined="infoFile" id="I2C2" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART4" determined="infoFile" id="UART4" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S" determined="infoFile" id="I2S" location="0x400a8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP2" determined="infoFile" id="SSP2" location="0x400ac000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCPWM" determined="infoFile" id="MCPWM" location="0x400b8000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" determined="infoFile" id="QEI" location="0x400bc000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDMMC" determined="infoFile" id="SDMMC" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x400fc000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc407x_8x_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+	</storageModule>
+</cproject>
diff --git a/hw/mcu/nxp/lpc_chip_40xx/.project b/hw/mcu/nxp/lpc_chip_40xx/.project
new file mode 100644
index 000000000..33c983c4b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/.project
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>lpc_chip_40xx</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/adc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/adc_17xx_40xx.h
new file mode 100644
index 000000000..7c705704c
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/adc_17xx_40xx.h
@@ -0,0 +1,263 @@
+/*
+ * @brief  LPC17xx/40xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ADC_17XX_40XX_H_
+#define __ADC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ADC_17XX_40XX CHIP:  LPC17xx/40xx A/D conversion driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#define ADC_ACC_12BITS
+#define ADC_TRIM_SUPPORT
+
+#if defined(CHIP_LPC175X_6X)
+#define ADC_MAX_SAMPLE_RATE 200000
+#else
+#define ADC_MAX_SAMPLE_RATE 400000
+#endif
+
+/**
+ * @brief 10 or 12-bit ADC register block structure
+ */
+typedef struct {					/*!< ADCn Structure */
+	__IO uint32_t CR;				/*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
+	__I  uint32_t GDR;				/*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+	__I  uint32_t RESERVED0;
+	__IO uint32_t INTEN;			/*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+	__I  uint32_t DR[8];			/*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
+	__I  uint32_t STAT;				/*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+#if defined(ADC_TRIM_SUPPORT)
+	__IO uint32_t ADTRM;
+#endif
+} LPC_ADC_T;
+
+/**
+ * @brief ADC register support bitfields and mask
+ */
+#if defined(ADC_ACC_12BITS)
+ #define ADC_DR_RESULT(n)        ((((n) >> 4) & 0xFFF))	/*!< Mask for getting the 12 bits ADC data read value */
+#else
+ #define ADC_DR_RESULT(n)        ((((n) >> 6) & 0x3FF))	/*!< Mask for getting the 10 bits ADC data read value */
+ #define ADC_CR_BITACC(n)        ((((n) & 0x7) << 17))	/*!< Number of ADC accuracy bits */
+#endif
+
+#define ADC_DR_DONE(n)          (((n) >> 31))			/*!< Mask for reading the ADC done status */
+#define ADC_DR_OVERRUN(n)       ((((n) >> 30) & (1UL)))	/*!< Mask for reading the ADC overrun status */
+#define ADC_CR_CH_SEL(n)        ((1UL << (n)))			/*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CLKDIV(n)        ((((n) & 0xFF) << 8))	/*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
+#define ADC_CR_BURST            ((1UL << 16))			/*!< Repeated conversions A/D enable bit */
+#define ADC_CR_PDN              ((1UL << 21))			/*!< ADC convert is operational */
+#define ADC_CR_START_MASK       ((7UL << 24))			/*!< ADC start mask bits */
+#define ADC_CR_START_MODE_SEL(SEL)  ((SEL << 24))		/*!< Select Start Mode */
+#define ADC_CR_START_NOW        ((1UL << 24))			/*!< Start conversion now */
+#define ADC_CR_START_CTOUT15    ((2UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT8     ((3UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_ADCTRIG0   ((4UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG1   ((5UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_MCOA2      ((6UL << 24))			/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_EDGE             ((1UL << 27))			/*!< Start conversion on a falling edge on the selected CAP/MAT signal */
+#if defined(ADC_ACC_12BITS)
+#define ADC_SAMPLE_RATE_CONFIG_MASK         (ADC_CR_CLKDIV(0xFF))
+#else
+#define ADC_SAMPLE_RATE_CONFIG_MASK         (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
+#endif
+
+/**
+ * @brief	ADC status register used for IP drivers
+ */
+typedef enum IP_ADC_STATUS {
+	ADC_DR_DONE_STAT,	/*!< ADC data register staus */
+	ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
+	ADC_DR_ADINT_STAT	/*!< ADC interrupt status */
+} ADC_STATUS_T;
+
+/** The channels on one ADC peripheral*/
+typedef enum CHIP_ADC_CHANNEL {
+	ADC_CH0 = 0,	/**< ADC channel 0 */
+	ADC_CH1,		/**< ADC channel 1 */
+	ADC_CH2,		/**< ADC channel 2 */
+	ADC_CH3,		/**< ADC channel 3 */
+	ADC_CH4,		/**< ADC channel 4 */
+	ADC_CH5,		/**< ADC channel 5 */
+	ADC_CH6,		/**< ADC channel 6 */
+	ADC_CH7,		/**< ADC channel 7 */
+} ADC_CHANNEL_T;
+
+/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
+typedef enum CHIP_ADC_EDGE_CFG {
+	ADC_TRIGGERMODE_RISING = 0,		/**< Trigger event: rising edge */
+	ADC_TRIGGERMODE_FALLING,		/**< Trigger event: falling edge */
+} ADC_EDGE_CFG_T;
+
+/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
+typedef enum CHIP_ADC_START_MODE {
+	ADC_NO_START = 0,
+	ADC_START_NOW,			/*!< Start conversion now */
+	ADC_START_ON_CTOUT15,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+	ADC_START_ON_CTOUT8,	/*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+	ADC_START_ON_ADCTRIG0,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+	ADC_START_ON_ADCTRIG1,	/*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+	ADC_START_ON_MCOA2		/*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_START_MODE_T;
+
+/** Clock setup structure for ADC controller passed to the initialize function */
+typedef struct {
+	uint32_t adcRate;		/*!< ADC rate */
+	uint8_t  bitsAccuracy;	/*!< ADC bit accuracy */
+	bool     burstMode;		/*!< ADC Burt Mode */
+} ADC_CLOCK_SETUP_T;
+
+/**
+ * @brief	Initialize the ADC peripheral and the ADC setup structure to default value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be set
+ * @return	Nothing
+ * @note	Default setting for ADC is 400kHz - 10bits
+ */
+void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
+
+/**
+ * @brief	Shutdown ADC
+ * @param	pADC	: The base of ADC peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_ADC_DeInit(LPC_ADC_T *pADC);
+
+/**
+ * @brief	Read the ADC value from a channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	data		: Pointer to where to put data
+ * @return	SUCCESS or ERROR if no conversion is ready
+ */
+Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
+
+/**
+ * @brief	Read the ADC value and convert it to 8bits value
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel:	selected channel
+ * @param	data		: Storage for data
+ * @return	Status	: ERROR or SUCCESS
+ */
+Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
+
+/**
+ * @brief	Read the ADC channel status
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	StatusType	: Status type of ADC_DR_*
+ * @return	SET or RESET
+ */
+FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
+
+/**
+ * @brief	Enable/Disable interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: ADC channel to read
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	SET or RESET
+ */
+void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
+
+/**
+ * @brief	Enable/Disable global interrupt for ADC channel
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, ENABLE or DISABLE
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
+{
+	Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
+}
+
+/**
+ * @brief	Select the mode starting the AD conversion
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	mode		: Stating mode, should be :
+ *							- ADC_NO_START				: Must be set for Burst mode
+ *							- ADC_START_NOW				: Start conversion now
+ *							- ADC_START_ON_CTOUT15		: Start conversion when the edge selected by bit 27 occurs on CTOUT_15
+ *							- ADC_START_ON_CTOUT8		: Start conversion when the edge selected by bit 27 occurs on CTOUT_8
+ *							- ADC_START_ON_ADCTRIG0		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
+ *							- ADC_START_ON_ADCTRIG1		: Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
+ *							- ADC_START_ON_MCOA2		: Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
+ * @param	EdgeOption	: Stating Edge Condition, should be :
+ *							- ADC_TRIGGERMODE_RISING	: Trigger event on rising edge
+ *							- ADC_TRIGGERMODE_FALLING	: Trigger event on falling edge
+ * @return	Nothing
+ */
+void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
+
+/**
+ * @brief	Set the ADC Sample rate
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	ADCSetup	: ADC setup structure to be modified
+ * @param	rate		: Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
+ * @return	Nothing
+ */
+void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
+
+/**
+ * @brief	Enable or disable the ADC channel on ADC peripheral
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	channel		: Channel to be enable or disable
+ * @param	NewState	: New state, should be:
+ *								- ENABLE
+ *								- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
+
+/**
+ * @brief	Enable burst mode
+ * @param	pADC		: The base of ADC peripheral on the chip
+ * @param	NewState	: New state, should be:
+ *							- ENABLE
+ *							- DISABLE
+ * @return	Nothing
+ */
+void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/can_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/can_17xx_40xx.h
new file mode 100644
index 000000000..e842dc27b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/can_17xx_40xx.h
@@ -0,0 +1,1130 @@
+/*
+ * @brief LPC17xx/40xx CAN driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CAN_17XX_40XX_H_
+#define __CAN_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CAN_17XX_40XX CHIP: LPC17xx/40xx CAN driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/** The number of entry in AF RAM region */
+#define CANAF_RAM_ENTRY_NUM        512
+
+/**
+ * @brief CAN AF RAM section definitions
+ */
+typedef enum {
+	CANAF_RAM_FULLCAN_SEC,	/*!<FullCAN Section*/
+	CANAF_RAM_SFF_SEC,		/*!<Standard ID Section*/
+	CANAF_RAM_SFF_GRP_SEC,	/*!<Group Standard ID Section*/
+	CANAF_RAM_EFF_SEC,		/*!<Extended ID Section*/
+	CANAF_RAM_EFF_GRP_SEC,	/*!<Group Extended ID Section*/
+	CANAF_RAM_SECTION_NUM,
+} CANAF_RAM_SECTION_T;
+
+/**
+ * @brief CAN acceptance filter RAM register block structure
+ */
+typedef struct							/*!< AF RAM Mask Table        */
+{
+	__IO uint32_t MASK[CANAF_RAM_ENTRY_NUM];	/*!< Acceptance Filter RAM ID mask register */
+} LPC_CANAF_RAM_T;
+
+/**
+ * @brief CAN acceptance filter register block structure
+ */
+typedef struct							/*!< CAN AF structure        */
+{
+	__IO uint32_t AFMR;						/*!< Acceptance Filter Register */
+	__IO uint32_t ENDADDR[CANAF_RAM_SECTION_NUM];				/*!< Start/End Address Registers */
+	__I  uint32_t LUTERRAD;					/*!< LUT Error Address Register */
+	__I  uint32_t LUTERR;					/*!< LUT Error Register */
+	__IO uint32_t FCANIE;					/*!< Global FullCANInterrupt Enable Register */
+	__IO uint32_t FCANIC[2];				/*!< FullCAN Interrupt and Capture Registers */
+} LPC_CANAF_T;
+
+/**
+ * @brief Central CAN register block structure
+ */
+typedef struct							/*!< Central CAN structure                  */
+{
+	__I  uint32_t TXSR;						/*!< CAN Central Transmit Status Register */
+	__I  uint32_t RXSR;						/*!< CAN Central Receive Status Register */
+	__I  uint32_t MSR;						/*!< CAN Central Miscellaneous Register */
+} IP_CAN_001_CR_T;
+
+/**
+ * @brief CAN Transmit register block structure
+ */
+typedef struct							/*!< CAN Transmit structure                  */
+{
+	__IO uint32_t TFI;					/*!< CAN Transmit Frame Information register*/
+	__IO uint32_t TID;					/*!< CAN Transfer Identifier register*/
+	__IO uint32_t TD[2];				/*!<CAN Transmit Data register*/
+} LPC_CAN_TX_T;
+
+/**
+ * @brief CAN Receive register block structure
+ */
+typedef struct				/*!< CAN Receive Frame structure                  */
+{
+	__IO uint32_t RFS;		/*!< Characteristic of the received frame. It includes the following characteristics:
+							   CAN_RFS_BP: indicate that the current message is received in Bypass mode.
+							 *							CAN_RFS_RTR: indicate the value of Remote Transmission Request bit in the current message.
+							 *							CAN_RFS_FF: indicate that the identifier in the current message is 11-bit or 29-bit identifier.
+							   Use CAN_RFS_ID_INDEX(RFS value) to get the ID Index of the matched entry in the Lookup Table RAM.
+							   Use CAN_RFS_DLC(RFS value) to get the Data Length Code field of the current received message.
+							 */
+	__IO uint32_t RID;		/*!<Identifier in the received message. Use RFS field to determine if it is 11-bit or 29-bit identifier.*/
+	__IO uint32_t RD[2];	/*!< Data bytes of the received message. Use DLC value in RFS fied to determine the number of data bytes.*/
+} IP_CAN_001_RX_T;
+
+/**
+ * @brief CAN register block structure
+ */
+typedef struct							/*!< CANn structure               */
+{
+	__IO uint32_t MOD;					/*!< CAN Mode Register */
+	__O  uint32_t CMR;					/*!< CAN Command Register */
+	__IO uint32_t GSR;					/*!< CAN Global Status Register */
+	__I  uint32_t ICR;					/*!< CAN Interrupt and Capture Register */
+	__IO uint32_t IER;					/*!< CAN Interrupt Enable Register*/
+	__IO uint32_t BTR;					/*!< CAN Bus Timing Register*/
+	__IO uint32_t EWL;					/*!< CAN Error Warning Limit Register*/
+	__I  uint32_t SR;					/*!< CAN Status Register*/
+	__IO IP_CAN_001_RX_T RX;			/*!< CAN Receive Registers*/
+	__IO LPC_CAN_TX_T TX[3];		/*!< CAN Transmit Registers*/
+} LPC_CAN_T;
+
+/*
+ * @brief CAN Mode  register definitions
+ */
+/** CAN Mode Register Bitmask */
+#define CAN_MOD_BITMASK     (0xBF)
+
+/** CAN Operationg Mode */
+#define CAN_MOD_OPERATION   ((uint32_t) 0)
+
+/** CAN Reset mode */
+#define CAN_MOD_RM          ((uint32_t) (1 << 0))
+
+/** CAN Listen Only Mode (Don't send ACK/Message)*/
+#define CAN_MOD_LOM         ((uint32_t) (1 << 1))
+
+/** CAN Self Test mode (Don't care ACK after sending message)*/
+#define CAN_MOD_STM         ((uint32_t) (1 << 2))
+
+/** CAN Transmit Priority mode (Determine the transmit priority basing on Tx Priority Register)*/
+#define CAN_MOD_TPM         ((uint32_t) (1 << 3))
+
+/** CAN Sleep mode */
+#define CAN_MOD_SM          ((uint32_t) (1 << 4))
+
+/** CAN Receive Polarity mode (Determine RD is active Low or High).*/
+#define CAN_MOD_RPM         ((uint32_t) (1 << 5))
+
+/** CAN Test mode (TD pin will reflects the bit detected on RD pin)*/
+#define CAN_MOD_TM          ((uint32_t) (1 << 7))
+
+/*
+ * @brief CAN Command  register definitions
+ */
+/** CAN Command Register Bitmask */
+#define CAN_CMR_BITMASK     (0xFF)
+
+/** Request to Send message which is available in selected Transmit Buffer*/
+#define CAN_CMR_TR          ((uint32_t) (1))
+
+/** Cancel the current transmission or the pending transmission request*/
+#define CAN_CMR_AT          ((uint32_t) (1 << 1))
+
+/** Release the information in Receive Buffer */
+#define CAN_CMR_RRB         ((uint32_t) (1 << 2))
+
+/** Clear the Data Overrun bit in Status Register(s)*/
+#define CAN_CMR_CDO         ((uint32_t) (1 << 3))
+
+/** Self Reception Request.The message sent is received simultaneously. */
+#define CAN_CMR_SRR         ((uint32_t) (1 << 4))
+
+/** Select one or multi transmit buffer(s).( n = 0/1/2) */
+#define CAN_CMR_STB(n)       ((uint32_t) (1 << (n + 5)))
+
+/*
+ * @brief CAN Global Status register definitions
+ */
+/** CAN Global Status Register Bitmask */
+#define CAN_GSR_BITMASK     (0xFFFF00FF)
+
+/** CAN Receive Buffer Status (At least one complete message is received) */
+#define CAN_GSR_RBS         ((uint32_t) (1))
+
+/** CAN Data Overrun Status */
+#define CAN_GSR_DOS         ((uint32_t) (1 << 1))
+
+/** CAN Transmit Buffer Status  (All 3 Transmit Buffers are available)*/
+#define CAN_GSR_TBS         ((uint32_t) (1 << 2))
+
+/** CAN Transmit Complete Status (All requested transmission(s) has (have) been successfully completed)*/
+#define CAN_GSR_TCS         ((uint32_t) (1 << 3))
+
+/** CAN Receive Status (The CAN controller is receiving a message)*/
+#define CAN_GSR_RS          ((uint32_t) (1 << 4))
+
+/** CAN Transmit Status (The CAN controller is sending a message)*/
+#define CAN_GSR_TS          ((uint32_t) (1 << 5))
+
+/** CAN Error Status */
+#define CAN_GSR_ES          ((uint32_t) (1 << 6))
+
+/** CAN Bus Status (CAN Controller is involed in bus activity or not*/
+#define CAN_GSR_BS          ((uint32_t) (1 << 7))
+
+/** CAN Current value of the Rx Error Counter */
+#define CAN_GSR_RXERR(n)    ((uint32_t) ((n >> 16) & 0xFF)
+
+/** CAN Current value of the Tx Error Counter */
+#define CAN_GSR_TXERR(n)    ((uint32_t) ((n >> 24) & 0xFF)
+
+/*
+ * @brief CAN Interrupt and Capture  register definitions
+ */
+/** CAN Interrupt and Capture Registe Bitmask */
+#define CAN_ICR_BITMASK     (0xFFFF07FF)
+
+/** CAN Receive Interrupt  (A new message was received)*/
+#define CAN_ICR_RI          ((uint32_t) (1))
+
+/** CAN Transmit Interrupt (Transmit buffer 1 is available) */
+#define CAN_ICR_TI1         ((uint32_t) (1 << 1))
+
+/** CAN Error Warning Interrupt */
+#define CAN_ICR_EI          ((uint32_t) (1 << 2))
+
+/** CAN Data Overrun Interrupt */
+#define CAN_ICR_DOI         ((uint32_t) (1 << 3))
+
+/** CAN Wake-Up Interrupt */
+#define CAN_ICR_WUI         ((uint32_t) (1 << 4))
+
+/** CAN Error Passive Interrupt */
+#define CAN_ICR_EPI         ((uint32_t) (1 << 5))
+
+/** CAN Arbitration Lost Interrupt */
+#define CAN_ICR_ALI         ((uint32_t) (1 << 6))
+
+/** CAN Bus Error Interrupt */
+#define CAN_ICR_BEI         ((uint32_t) (1 << 7))
+
+/** CAN ID Ready Interrupt */
+#define CAN_ICR_IDI         ((uint32_t) (1 << 8))
+
+/** CAN Transmit Interrupt 2 (Transmit buffer 2 is available) */
+#define CAN_ICR_TI2         ((uint32_t) (1 << 9))
+
+/** CAN Transmit Interrupt 3 (Transmit buffer 3 is available)*/
+#define CAN_ICR_TI3         ((uint32_t) (1 << 10))
+
+/** CAN Error Code Capture (Error Location)*/
+#define CAN_ICR_ERRBIT_VAL(n)   ((uint32_t) (((n) >> 16) & 0x1F))
+/** Start of Frame error value */
+#define CAN_ICR_ERR_SOF             (3)
+/** ID28...ID21 Error value */
+#define CAN_ICR_ERR_ID28_ID21       (2)
+/** ID28...ID21 Error value */
+#define CAN_ICR_ERR_ID20_ID18       (6)
+/**SRTR Bit Error value */
+#define CAN_ICR_ERR_SRTR        (4)
+/**IDE Bit Error value */
+#define CAN_ICR_ERR_IDE     (5)
+/** ID17...ID13 Error value */
+#define CAN_ICR_ERR_ID17_ID13       (7)
+/** ID12...ID15 Error value */
+#define CAN_ICR_ERR_ID12_ID5        (0x0F)
+/** ID4...ID0 Error value */
+#define CAN_ICR_ERR_ID4_ID0     (0x0E)
+/**RTR Bit Error value */
+#define CAN_ICR_ERR_RTR     (0x0C)
+/**Reserved Bit 1 Error value */
+#define CAN_ICR_ERR_ReservedBit_1       (0x0D)
+/**Reserved Bit 0 Error value */
+#define CAN_ICR_ERR_ReservedBit_0       (0x09)
+/** DLC Error value */
+#define CAN_ICR_ERR_DLC     (0x0B)
+/** Data Field Error value */
+#define CAN_ICR_ERR_DATA_FIELD      (0x0A)
+/** CRC Sequence Error value */
+#define CAN_ICR_ERR_CRC_SEQ     (0x08)
+/** CRC Delimiter Error value */
+#define CAN_ICR_ERR_CRC_DELIMITER       (0x18)
+/** ACK Error value */
+#define CAN_ICR_ERR_ACK     (0x19)
+/** ACK Delimiter Error value */
+#define CAN_ICR_ERR_ACK_DELIMITER       (0x1B)
+/** EOF Error value */
+#define CAN_ICR_ERR_EOF     (0x1A)
+/** Intermission Error value */
+#define CAN_ICR_ERR_INTERMISSION        (0x12)
+
+/** CAN Error Direction */
+#define CAN_ICR_ERRDIR_RECEIVE      ((uint32_t) (1 << 21))
+
+/** CAN Error Type Capture */
+#define CAN_ICR_ERRC_VAL(n)     ((uint32_t) (((n) >> 22) & 0x3))
+#define CAN_ICR_BIT_ERROR       (0)
+#define CAN_ICR_FORM_ERROR      (1)
+#define CAN_ICR_STUFF_ERROR     (2)
+#define CAN_ICR_OTHER_ERROR     (3)
+
+/** CAN Arbitration Lost Capture */
+#define CAN_ICR_ALCBIT_VAL(n)       ((uint32_t) (((n) >> 24) & 0xFF))
+
+/*
+ * @brief CAN Interrupt Enable  register definitions
+ */
+/** CAN Interrupt Enable  Register Bitmask */
+#define CAN_IER_BITMASK     (0x7FF)
+
+/** CAN Receive Interrupt Enable */
+#define CAN_IER_RIE         ((uint32_t) (1))
+
+/** CAN Transmit Interrupt Enable for buffer 1 */
+#define CAN_IER_TIE1        ((uint32_t) (1 << 1))
+
+/** CAN Error Warning Interrupt Enable */
+#define CAN_IER_EIE         ((uint32_t) (1 << 2))
+
+/** CAN Data Overrun Interrupt Enable */
+#define CAN_IER_DOIE        ((uint32_t) (1 << 3))
+
+/** CAN Wake-Up Interrupt Enable */
+#define CAN_IER_WUIE        ((uint32_t) (1 << 4))
+
+/** CAN Error Passive Interrupt Enable */
+#define CAN_IER_EPIE        ((uint32_t) (1 << 5))
+
+/** CAN Arbitration Lost Interrupt Enable */
+#define CAN_IER_ALIE        ((uint32_t) (1 << 6))
+
+/** CAN Bus Error Interrupt Enable */
+#define CAN_IER_BEIE        ((uint32_t) (1 << 7))
+
+/** CAN ID Ready Interrupt Enable */
+#define CAN_IER_IDIE        ((uint32_t) (1 << 8))
+
+/** CAN Transmit Enable Interrupt for Buffer 2 */
+#define CAN_IER_TIE2        ((uint32_t) (1 << 9))
+
+/** CAN Transmit Enable Interrupt for Buffer 3 */
+#define CAN_IER_TIE3        ((uint32_t) (1 << 10))
+
+/*
+ * @brief CAN Bus Timing  register definitions
+ */
+/** CAN Bus Timing  Register Bitmask */
+#define CAN_BTR_BITMASK     (0xFFC3FF)
+
+/** CAN Baudrate Prescaler */
+#define CAN_BTR_BRP(n)      ((uint32_t) ((n) & 0x3FF))
+
+/** CAN Synchronization Jump Width */
+#define CAN_BTR_SJW(n)      ((uint32_t) (((n) & 0x3) << 14))
+
+/** CAN Time Segment 1 */
+#define CAN_BTR_TESG1(n)    ((uint32_t) (((n) & 0xF) << 16))
+
+/** CAN Time Segment 2 */
+#define CAN_BTR_TESG2(n)    ((uint32_t) (((n) & 0xF) << 20))
+
+/** CAN Sampling */
+#define CAN_BTR_SAM         ((uint32_t) (1 << 23))
+
+/*
+ * @brief CAN Error Warning Limit  register definitions
+ */
+/** CAN Error Warning Limit  Register Bitmask */
+#define CAN_EWL_BITMASK     (0xFF)
+
+/** CAN Error Warning Limit */
+#define CAN_EWL_VAL(n)      ((uint32_t) ((n) & 0xFF))
+
+/*
+ * @brief CAN Status  Registe definitions
+ */
+/** CAN Status  Registe Bitmask */
+#define CAN_SR_BITMASK     (0xFFFFFF)
+
+/** CAN Receive Buffer Status (Bit 0, 8, 16 are the same)*/
+#define CAN_SR_RBS(n)     ((uint32_t) (1 << ((n) * 8)))
+
+/** CAN Data Overrun Status (Bit 1, 9, 17 are the same)*/
+#define CAN_SR_DOS(n)     ((uint32_t) (1 << (1 + (n) * 8)))
+
+/** CAN Transmit Buffer Status (Tx Buffer n=0/1/2  is available)*/
+#define CAN_SR_TBS(n)     ((uint32_t) (1 << (2 + (n) * 8)))
+
+/** CAN Transmission Complete Status (The request on Tx Buffer n=0/1/2 has been completed) */
+#define CAN_SR_TCS(n)     ((uint32_t) (1 << (3 + (n) * 8)))
+
+/** CAN Receive Status (Bit 4, 12, 20 are the same)*/
+#define CAN_SR_RS(n)      ((uint32_t) (1 << (4 + (n) * 8)))
+
+/** CAN Transmit Status (The CAN controller is sending a message in Tx Buffer n=0/1/2) */
+#define CAN_SR_TS(n)      ((uint32_t) (1 << (5 + (n) * 8)))
+
+/** CAN Error Status (Bit 6, 14, 22 are the same)*/
+#define CAN_SR_ES(n)      ((uint32_t) (1 << (6 + (n) * 8)))
+
+/** CAN Bus Status (Bit 7, 15, 23 are the same)*/
+#define CAN_SR_BS(n)      ((uint32_t) (1 << (7 + (n) * 8)))
+
+/*
+ * @brief CAN Receive Frame Status  register definitions
+ */
+/** CAN Receive Frame Status Register  Bitmask */
+#define CAN_RFS_BITMASK     (0xC00F07FF)
+
+/** CAN ID Index */
+#define CAN_RFS_ID_INDEX(n) ((uint32_t) ((n) & 0x3FF))
+
+/** CAN Bypass */
+#define CAN_RFS_BP          ((uint32_t) (1 << 10))
+
+/** CAN Data Length Code */
+#define CAN_RFS_DLC(n)      ((uint32_t) ((n >> 16) & 0x0F))
+
+/** CAN Remote Transmission Request */
+#define CAN_RFS_RTR         ((uint32_t) (1 << 30))
+
+/** CAN control 11 bit or 29 bit Identifier */
+#define CAN_RFS_FF          ((uint32_t) ((uint32_t) 1 << 31))
+
+/*
+ * @brief CAN Receive Identifier Register definitions
+ */
+/** CAN 11 bit Identifier */
+#define CAN_RID_ID_11(n)        ((uint32_t) ((n) & 0x7FF))
+
+/** CAN 29 bit Identifier */
+#define CAN_RID_ID_29(n)        ((uint32_t) ((n) & 0x1FFFFFFF))
+
+/*
+ * @brief CAN Transmit Frame Information register definitions
+ */
+/** CAN Transmit Frame Information  Register  Bitmask */
+#define CAN_TFI_BITMASK     (0xC00F00FF)
+
+/** CAN Priority */
+#define CAN_TFI_PRIO(n)         ((uint32_t) ((n) & 0xFF))
+
+/** CAN Data Length Code */
+#define CAN_TFI_DLC(n)          ((uint32_t) (((n) & 0xF) << 16))
+
+/** CAN Remote Frame Transmission */
+#define CAN_TFI_RTR             ((uint32_t) (1 << 30))
+
+/** CAN control 11-bit or 29-bit Identifier */
+#define CAN_TFI_FF              ((uint32_t) ((uint32_t) 1 << 31))
+
+/*
+ * @brief CAN Transfer Identifier register definitions
+ */
+/** CAN 11-bit Identifier */
+#define CAN_TID_ID11(n)         ((uint32_t) ((n) & 0x7FF))
+
+/** CAN 11-bit Identifier */
+#define CAN_TID_ID29(n)         ((uint32_t) ((n) & 0x1FFFFFFF))
+
+/*
+ * @brief CAN Central transmit Status register definitions
+ */
+/** CAN Central transmit Status Register  Bitmask */
+#define CAN_TSR_BITMASK     (0x30303)
+
+/** Bit indicate CAN n (0/1) is sending a message */
+#define CAN_TSR_TS(n)         ((uint32_t) (1 << (n + 0)))
+
+/** Bit indicate all 3 Tx buffer of CAN n (0/1) are available */
+#define CAN_TSR_TBS(n)        ((uint32_t) (1 << (n + 8)))
+
+/** Bit indicate all requested transmissions have been completed successfully by the CAN n(0/1) */
+#define CAN_TSR_TCS(n)        ((uint32_t) (1 << (n + 16)))
+
+/*
+ * @brief CAN Central Receive Status register definitions
+ */
+/** CAN Central Receive Status Register  Bitmask */
+#define CAN_RSR_BITMASK     (0x30303)
+
+/** Bit indicate CAN n (0/1) is receiving a message */
+#define CAN_RSR_RS(n)         ((uint32_t) (1 << (n + 0)))
+
+/** Bit indicate a received message is available in CAN n (0/1) */
+#define CAN_RSR_RBS(n)        ((uint32_t) (1 << (n + 8)))
+
+/** Bit indicate a message was lost because the preceding message to CAN n(0/1) controller was not
+   read out quickly enough*/
+#define CAN_RSR_DOS(n)        ((uint32_t) (1 << (n + 16)))
+
+/*
+ * @brief CAN Central Miscellaneous Status register definitions
+ */
+/** CAN Central Receive Status Register  Bitmask */
+#define CAN_MSR_BITMASK     (0x303)
+
+/** Bit indicate Tx/Rx Error Counter has reached the limit set in CAN n (0/1) */
+#define CAN_MSR_E(n)      ((uint32_t) (1 << (n + 0)))
+
+/** Bit indicate CAN n (0/1) is currently involved in bus activities*/
+#define CAN_MSR_BS(n)     ((uint32_t) (1 << (n + 8)))
+
+/*
+ * @brief Acceptance Filter Mode register definitions
+ */
+/** CAN Acceptance Filter Operation mode */
+#define CANAF_AFMR_OPERATION     ((uint32_t) (0))
+
+/** CAN Acceptance Filter Off mode */
+#define CANAF_AFMR_ACCOFF     ((uint32_t) (1))
+
+/** CAN Acceptance File Bypass mode */
+#define CANAF_AFMR_ACCBP      ((uint32_t) (1 << 1))
+
+/** FullCAN Mode Enhancements */
+#define CANAF_AFMR_EFCAN      ((uint32_t) (1 << 2))
+
+/*
+ * @brief Extended Frame Group Start Address register definitions
+ */
+/** The start address of the table of grouped Extended Identifier */
+#define CANAF_ENDADDR(n)       ((uint32_t) (((n) & 0x3FF) << 2))
+#define CANAF_ENDADDR_VAL(n)   ((uint32_t) ((n >> 2) & 0x3FF))
+
+/*
+ * @brief LUT Error Address register definitions
+ */
+/** CAN Look-Up Table Error Address */
+#define CANAF_LUTERRAD(n)     ((uint32_t) (((n) & 0x1FF) << 2))
+
+/*
+ * @brief LUT Error register definitions
+ */
+/** CAN Look-Up Table Error */
+#define CANAF_LUTERR      ((uint32_t) (1))
+
+/*
+ * @brief Global FullCANInterrupt Enable register definitions
+ */
+/** Global FullCANInterrupt Enable Register  Bitmask */
+#define CANAF_FCANIE_BITMASK     (0x01)
+
+/** Global FullCANInterrupt Enable */
+#define CANAF_FCANIE      ((uint32_t) (1))
+
+/*
+ * @brief FullCAN Message Layout definitions
+ */
+
+/** FF Bit Position*/
+#define CANAF_FULLCAN_MSG_FF_POS    (31)
+/** RTR Bit Position*/
+#define CANAF_FULLCAN_MSG_RTR_POS   (30)
+/** Message Lost Bit Position*/
+#define CANAF_FULLCAN_MSG_LOST_POS  (26)
+/** SEM Bit Position*/
+#define CANAF_FULLCAN_MSG_SEM_POS   (24)
+/** SEM Bit Mask*/
+#define CANAF_FULLCAN_MSG_SEM_BITMASK   (0x03)
+/** DLC Bit Position*/
+#define CANAF_FULLCAN_MSG_DLC_POS   (16)
+/** DLC Bit Mask*/
+#define CANAF_FULLCAN_MSG_DLC_BITMASK   (0x0F)
+/** SCC Bit Position*/
+#define CANAF_FULLCAN_MSG_SCC_POS   (13)
+/** SCC Bit Mask*/
+#define CANAF_FULLCAN_MSG_SCC_BITMASK   (0x07)
+/** 11bit-ID Bit Position*/
+#define CANAF_FULLCAN_MSG_ID11_POS  (0)
+/** 11bit-ID Bit Mask*/
+#define CANAF_FULLCAN_MSG_ID11_BITMASK  (0x7FF)
+
+/*
+ * @brief FullCAN Message Status
+ */
+/** AF is updating FullCAN Message*/
+#define CANAF_FULCAN_MSG_AF_UPDATING        (0x01)
+/** AF has finished updating FullCAN Message*/
+#define CANAF_FULCAN_MSG_AF_FINISHED        (0x03)
+/** CPU is in process of reading FullCAN Message*/
+#define CANAF_FULCAN_MSG_CPU_READING        (0x0)
+
+/*
+ * @brief FullCAN Interrupt and Capture register definitions
+ */
+/** FullCAN Interrupt and Capture (0-31)*/
+#define CANAF_FCAN_IC_INTPND(n)   ((n >= 32) ? ((uint32_t) (1 << (n - 32))) : ((uint32_t) (1 << n)))
+
+/*
+ * @brief Standard ID Entry definitions
+ */
+/** Start position of Controller Number Bits */
+#define CAN_STD_ENTRY_CTRL_NO_POS       (13 )
+/** Mask of Controller Number Bits */
+#define CAN_STD_ENTRY_CTRL_NO_MASK      (0x07)
+/** Start position of Disable bit */
+#define CAN_STD_ENTRY_DISABLE_POS       (12 )
+/** Mask of Disable Bit */
+#define CAN_STD_ENTRY_DISABLE_MASK      (0x01)
+/** Start position of Interrupt Enable bit (FullCAN entry only)*/
+#define CAN_STD_ENTRY_IE_POS            (11 )
+/** Mask of Interrupt Enable bit (FullCAN entry only)*/
+#define CAN_STD_ENTRY_IE_MASK           (0x01)
+/** Start position of ID bit */
+#define CAN_STD_ENTRY_ID_POS            (0  )
+/** Mask of ID Bit */
+#define CAN_STD_ENTRY_ID_MASK           (0x7FF)
+
+/*
+ * @brief Extended ID Entry definitions
+ */
+/** Start position of Controller Number Bits */
+#define CAN_EXT_ENTRY_CTRL_NO_POS       (29 )
+/** Mask of Controller Number Bits */
+#define CAN_EXT_ENTRY_CTRL_NO_MASK      (0x07)
+/** Start position of ID bit */
+#define CAN_EXT_ENTRY_ID_POS            (0  )
+/** Mask of ID Bit */
+#define CAN_EXT_ENTRY_ID_MASK           (0x1FFFFFFF)
+
+/*
+ * @brief CAN Message Type definitions
+ */
+
+/** Remote Message */
+#define CAN_REMOTE_MSG         ((uint32_t) (1 << 0))
+
+/** Message use Extend ID*/
+#define CAN_EXTEND_ID_USAGE     ((uint32_t) (1 << 30))
+
+/** The maximum data length in CAN Message */
+#define CAN_MSG_MAX_DATA_LEN       (8)
+
+/**
+ * @brief CAN Buffer ID definition
+ */
+typedef enum {
+	CAN_BUFFER_1 = 0,	/*!< Buffer 1 */
+	CAN_BUFFER_2,		/*!< Buffer 2 */
+	CAN_BUFFER_3,		/*!< Buffer 3 */
+	CAN_BUFFER_LAST,	/*!< Last Buffer */
+} CAN_BUFFER_ID_T;
+
+/**
+ * @brief CAN Message Object Structure
+ */
+typedef struct						/*!< Message structure */
+{
+	uint32_t ID;					/*!< Message Identifier. If 30th-bit is set, this is 29-bit ID, othewise 11-bit ID */
+	uint32_t Type;					/*!< Message Type. which can include: - CAN_REMOTE_MSG type*/
+	uint32_t DLC;					/*!< Message Data Length: 0~8 */
+	uint8_t  Data[CAN_MSG_MAX_DATA_LEN];/*!< Message Data */
+} CAN_MSG_T;
+
+/**
+ * @brief CAN Bus Timing Structure
+ */
+typedef struct						/*!< Bus Timing structure */
+{
+	uint16_t BRP;					/*!< Baud Rate Prescaler */
+	uint8_t SJW;					/*!< SJW value*/
+	uint8_t TESG1;					/*!< TESG1 value */
+	uint8_t TESG2;					/*!< TESG2 value */
+	uint8_t SAM;					/*!<0: The bus is sampled once, 1: sampled 3 times */
+} IP_CAN_BUS_TIMING_T;
+
+/**
+ * @brief Standard ID Entry structure
+ */
+typedef struct {
+	uint8_t CtrlNo;				/*!<Controller Number: 0 for CAN1 and 1 for CAN2*/
+	uint8_t Disable;			/*!< 0(ENABLE)/1(DISABLE): Response On/Off dynamically*/
+	uint16_t ID_11;				/*!< Standard ID, should be 11-bit value */
+} CAN_STD_ID_ENTRY_T;
+
+/**
+ * @brief Standard ID Range structure
+ */
+typedef struct {
+	CAN_STD_ID_ENTRY_T LowerID;	/*!< Lower ID Bound, should be in 11-bit value*/
+	CAN_STD_ID_ENTRY_T UpperID;	/*!< Upper ID Bound, should be in 11-bit value*/
+} CAN_STD_ID_RANGE_ENTRY_T;
+
+/**
+ * @brief Extended ID  Entry structure
+ */
+typedef struct {
+	uint8_t CtrlNo;			/*!<Controller Number: 0 for CAN1 and 1 for CAN2*/
+	uint32_t ID_29;			/*!< Extend ID, shoud be 29-bit value */
+} CAN_EXT_ID_ENTRY_T;
+
+/**
+ * @brief Extended ID Range structure
+ */
+typedef struct {
+	CAN_EXT_ID_ENTRY_T LowerID;	/*!< Lower ID Bound, should be in 29-bit value*/
+	CAN_EXT_ID_ENTRY_T UpperID;	/*!< Upper ID Bound, should be in 29-bit value*/
+} CAN_EXT_ID_RANGE_ENTRY_T;
+
+/**
+ * @brief Acceptance Filter Section Table structure
+ */
+typedef struct {
+	CAN_STD_ID_ENTRY_T *FullCANSec;		/*!< The pointer to fullCAN section */
+	uint16_t FullCANEntryNum;					/*!< FullCAN Entry Number */
+	CAN_STD_ID_ENTRY_T *SffSec;			/*!< The pointer to individual Standard ID Section */
+	uint16_t SffEntryNum;						/*!< Standard ID Entry Number */
+	CAN_STD_ID_RANGE_ENTRY_T *SffGrpSec;	/*!< The pointer to  Group Standard ID  Section */
+	uint16_t SffGrpEntryNum;					/*!< Group Standard ID Entry Number */
+	CAN_EXT_ID_ENTRY_T *EffSec;			/*!< The pointer to Extended ID Section */
+	uint16_t EffEntryNum;						/*!< Extended ID Entry Number */
+	CAN_EXT_ID_RANGE_ENTRY_T *EffGrpSec;	/*!< The pointer to Group Extended ID Section */
+	uint16_t EffGrpEntryNum;					/*!< Group Extended ID Entry Number */
+} CANAF_LUT_T;
+
+#define CAN_SEG1_DEFAULT_VAL 5
+#define CAN_SEG2_DEFAULT_VAL 4
+#define CAN_SJW_DEFAULT_VAL 0
+
+/**
+ * @brief CAN Mode definition
+ */
+typedef enum {
+	CAN_RESET_MODE = CAN_MOD_RM,				/*!< CAN Reset Mode */
+	CAN_SELFTEST_MODE = CAN_MOD_STM,			/*!< CAN Selftest Mode */
+	CAN_TEST_MODE = CAN_MOD_TM,					/*!< CAN Test Mode */
+	CAN_LISTEN_ONLY_MODE = CAN_MOD_LOM,			/*!< CAN Listen Only Mode */
+	CAN_SLEEP_MODE = CAN_MOD_SM,				/*!< CAN Sleep Mode */
+	CAN_OPERATION_MODE = CAN_MOD_OPERATION,		/*!< CAN Operation Mode */
+	CAN_TRANSMIT_PRIORITY_MODE = CAN_MOD_TPM,	/*!< CAN Transmit Priority Mode */
+	CAN_RECEIVE_PRIORITY_MODE = CAN_MOD_RPM,	/*!< CAN Receive Priority Mode */
+} CAN_MODE_T;
+
+/**
+ * @brief CAN AF Mode definition
+ */
+typedef enum {
+	CAN_AF_NORMAL_MODE = 0,					/*!< Acceptance Filter Normal Mode */
+	CAN_AF_OFF_MODE = CANAF_AFMR_ACCOFF,	/*!< Acceptance Filter Off Mode */
+	CAN_AF_BYBASS_MODE = CANAF_AFMR_ACCBP,	/*!< Acceptance Fileter Bypass Mode */
+	CAN_AF_FULL_MODE = CANAF_AFMR_EFCAN,	/*!< FullCAN Mode Enhancement */
+} CAN_AF_MODE_T;
+
+/**
+ * @brief	Set the CAN command request
+ * @param	pCAN	: Pointer to CAN peripheral block
+ * @param	command	: Command request (Or'ed bit values of CAN_CMR_*).
+ * @return	None
+ */
+STATIC INLINE void Chip_CAN_SetCmd(LPC_CAN_T *pCAN, uint32_t command)
+{
+	pCAN->CMR = command;
+}
+
+/**
+ * @brief	Set Error Warning Limit for the CAN Controller
+ * @param	pCAN	: Pointer to CAN peripheral block
+ * @param	ewl		: expected limit
+ * @return	None
+ */
+STATIC INLINE void Chip_CAN_SetEWL(LPC_CAN_T *pCAN, uint32_t ewl)
+{
+	pCAN->EWL = ewl & CAN_EWL_BITMASK;
+}
+
+/**
+ * @brief	Get Error Warning Limit of the CAN Controller
+ * @param	pCAN	: Pointer to CAN peripheral block
+ * @return	Error warning limit value
+ */
+STATIC INLINE uint8_t Chip_CAN_GetEWL(LPC_CAN_T *pCAN)
+{
+	return CAN_EWL_VAL(pCAN->EWL);
+}
+
+/**
+ * @brief	Get global status register contents of the CAN Controller
+ * @param	pCAN	: Pointer to CAN peripheral block
+ * @return	Gloabl Status register contents (Or'ed bit values of CAN_GSR_*)
+ */
+STATIC INLINE uint32_t Chip_CAN_GetGlobalStatus(LPC_CAN_T *pCAN)
+{
+	return pCAN->GSR;
+}
+
+/**
+ * @brief	Get the status of the CAN Controller
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @return	Status (Or'ed bit values of CAN_SR_*(n) with n = CAN_BUFFER_1/2/3).
+ */
+STATIC INLINE uint32_t Chip_CAN_GetStatus(LPC_CAN_T *pCAN)
+{
+	return pCAN->SR;
+}
+
+/**
+ * @brief	Enable the CAN Interrupts
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @param	IntMask	: Interrupt Mask (Or-ed bits value of CAN_IER_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CAN_EnableInt(LPC_CAN_T *pCAN, uint32_t IntMask)
+{
+	pCAN->IER |= IntMask;
+}
+
+/**
+ * @brief	Disable the CAN Interrupts
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @param	IntMask	: Interrupt Mask (Or-ed bits value of CAN_IER_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CAN_DisableInt(LPC_CAN_T *pCAN, uint32_t IntMask)
+{
+	pCAN->IER &= (~IntMask) & CAN_IER_BITMASK;
+}
+
+/**
+ * @brief	Get interrupt status of the given CAN Controller
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @return	Status (Or'ed bit values of CAN_ICR_* )
+ */
+STATIC INLINE uint32_t Chip_CAN_GetIntStatus(LPC_CAN_T *pCAN)
+{
+	return pCAN->ICR;
+}
+
+/**
+ * @brief	Enable/Disable CAN controller FullCAN Interrupts
+ * @param	pCANAF		: Pointer to CAN AF Register block
+ * @param	NewState	: Enable/Disable
+ * @return	Nothing
+ */
+void Chip_CAN_ConfigFullCANInt(LPC_CANAF_T *pCANAF, FunctionalState NewState);
+
+/**
+ * @brief	Get FullCAN interrupt status of the given object
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	ObjID	: Object ID
+ * @return  Status
+ */
+uint32_t Chip_CAN_GetFullCANIntStatus(LPC_CANAF_T *pCANAF, uint8_t ObjID);
+
+/**
+ * @brief	Set CAN controller enter/exit to a given mode
+ * @param	pCAN		: Pointer to CAN controller register block
+ * @param	Mode		: Mode selected
+ * @param	NewState	: ENABLE: enter, DISABLE: exit
+ * @return	None
+ */
+void Chip_CAN_SetMode(LPC_CAN_T *pCAN, CAN_MODE_T Mode, FunctionalState NewState);
+
+/**
+ * @brief	Get current mode register settings of the CAN controller
+ * @param	pCAN	: Pointer to CAN peripheral block
+ * @return	Current Mode register value of the CAN Controller (Bit values of CAN_MOD_*)
+ */
+STATIC INLINE CAN_MODE_T Chip_CAN_GetMode(LPC_CAN_T *pCAN)
+{
+	return (CAN_MODE_T) (pCAN->MOD & CAN_MOD_BITMASK);
+}
+
+/**
+ * @brief	Set CAN AF Mode
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	AfMode	: Mode selected
+ * @return	None
+ */
+STATIC INLINE void Chip_CAN_SetAFMode(LPC_CANAF_T *pCANAF, CAN_AF_MODE_T AfMode)
+{
+	pCANAF->AFMR = AfMode;
+}
+
+/**
+ * @brief	Get CAN AF Mode
+ * @param	pCanAF	: Pointer to CAN AF Register block
+ * @return	Mode
+ */
+STATIC INLINE CAN_AF_MODE_T Chip_CAN_GetAFMode(LPC_CANAF_T *pCanAF)
+{
+	return (CAN_AF_MODE_T) pCanAF->AFMR;
+}
+
+/**
+ * @brief	Set CAN AF LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	pAFSections	: Pointer to buffer storing AF Section Data
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_SetAFLUT(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CANAF_LUT_T *pAFSections);
+
+/**
+ * @brief	Insert a FullCAN Entry into the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	pEntry	: Pointer to the entry which will be inserted
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_InsertFullCANEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CAN_STD_ID_ENTRY_T *pEntry);
+
+/**
+ * @brief	Insert an individual Standard Entry into the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	pEntry	: Pointer to the entry which will be inserted
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_InsertSTDEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CAN_STD_ID_ENTRY_T *pEntry);
+
+/**
+ * @brief	Insert an Group Standard Entry into the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	pEntry	: Pointer to the entry which will be inserted
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_InsertGroupSTDEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CAN_STD_ID_RANGE_ENTRY_T *pEntry);
+
+/**
+ * @brief	Insert an individual Extended Entry into the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	pEntry	: Pointer to the entry which will be inserted
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_InsertEXTEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CAN_EXT_ID_ENTRY_T *pEntry);
+
+/**
+ * @brief	Insert an Group Extended Entry into the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	pEntry	: Pointer to the entry which will be inserted
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_InsertGroupEXTEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CAN_EXT_ID_RANGE_ENTRY_T *pEntry);
+
+/**
+ * @brief	Remove a FullCAN Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry removed
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_RemoveFullCANEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, int16_t Position);
+
+/**
+ * @brief	Remove an individual Standard Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry removed
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_RemoveSTDEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, int16_t Position);
+
+/**
+ * @brief	Remove an Group Standard Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry removed
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_RemoveGroupSTDEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, int16_t Position);
+
+/**
+ * @brief	Remove an individual Extended  Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry removed
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_RemoveEXTEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, int16_t Position);
+
+/**
+ * @brief	Remove an Group Extended  Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry removed
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_RemoveGroupEXTEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, int16_t Position);
+
+/**
+ * @brief	Get the number of entries in the given section
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	SectionID	: Section ID
+ * @return	Number of entries
+ */
+uint16_t Chip_CAN_GetEntriesNum(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CANAF_RAM_SECTION_T SectionID);
+
+/**
+ * @brief	Read a FullCAN Entry into from current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	:  Position of the entry in the given section (started from 0)
+ * @param	pEntry		:  Pointer to the entry which will be read
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_ReadFullCANEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, uint16_t Position,
+								 CAN_STD_ID_ENTRY_T *pEntry);
+
+/**
+ * @brief	Read an individual Standard Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	:  Position of the entry in the given section (started from 0)
+ * @param	pEntry		:  Pointer to the entry which will be read
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_ReadSTDEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, uint16_t Position,
+							 CAN_STD_ID_ENTRY_T *pEntry);
+
+/**
+ * @brief	Read an Group Standard Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry in the given section (started from 0)
+ * @param	pEntry		: Pointer to the entry which will be read
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_ReadGroupSTDEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, uint16_t Position,
+								  CAN_STD_ID_RANGE_ENTRY_T *pEntry);
+
+/**
+ * @brief	Read an individual Extended Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry in the given section (started from 0)
+ * @param	pEntry		: Pointer to the entry which will be read
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_ReadEXTEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, uint16_t Position,
+							 CAN_EXT_ID_ENTRY_T *pEntry);
+
+/**
+ * @brief	Read an Group Extended Entry from the current LUT
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	Position	: Position of the entry in the given section (started from 0)
+ * @param	pEntry		: Pointer to the entry which will be read
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_ReadGroupEXTEntry(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, uint16_t Position,
+								  CAN_EXT_ID_RANGE_ENTRY_T *pEntry);
+
+/**
+ * @brief	Initialize CAN Interface
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @return	Nothing
+ */
+void Chip_CAN_Init(LPC_CAN_T *pCAN, LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam);
+
+/**
+ * @brief	De-Initialize CAN Interface
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @return	Nothing
+ */
+void Chip_CAN_DeInit(LPC_CAN_T *pCAN);
+
+/**
+ * @brief	Set CAN bitrate
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @param	BitRate	: Expected bitrate
+ * @return	SUCCESS/ERROR
+ */
+Status Chip_CAN_SetBitRate(LPC_CAN_T *pCAN, uint32_t BitRate);
+
+/**
+ * @brief	Get Free TxBuffer
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @return	Buffer ID
+ */
+CAN_BUFFER_ID_T Chip_CAN_GetFreeTxBuf(LPC_CAN_T *pCAN);
+
+/**
+ * @brief	Request the given CAN Controller to send message
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @param	TxBufID	: ID of the buffer which will be used for transmission
+ * @param	pMsg	: Pointer to the buffer of message which will be sent
+ * @return	SUCCESS (message information saved) or ERROR (no message received)
+ */
+Status Chip_CAN_Send(LPC_CAN_T *pCAN, CAN_BUFFER_ID_T TxBufID, CAN_MSG_T *pMsg);
+
+/**
+ * @brief	Get message received by the CAN Controller
+ * @param	pCAN	: Pointer to CAN controller register block
+ * @param	pMsg	: Pointer to the buffer storing the information of the received message
+ * @return	SUCCESS (message information saved) or ERROR (no message received)
+ */
+Status Chip_CAN_Receive(LPC_CAN_T *pCAN, CAN_MSG_T *pMsg);
+
+/**
+ * @brief	Get message received automatically by the AF
+ * @param	pCANAF	: Pointer to CAN AF Register block
+ * @param	pCANAFRam	: Pointer to CAN AF RAM Register block
+ * @param	ObjID	: Object ID
+ * @param	pMsg	: Pointer to the buffer storing the information of the received message
+ * @param	pSCC	: Pointer to the buffer storing the controller ID of the received message
+ * @return	SUCCESS (message information saved) or ERROR (no message received)
+ */
+Status Chip_CAN_FullCANReceive(LPC_CANAF_T *pCANAF,
+							   LPC_CANAF_RAM_T *pCANAFRam,
+							   uint8_t ObjID,
+							   CAN_MSG_T *pMsg,
+							   uint8_t *pSCC);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/chip.h b/hw/mcu/nxp/lpc_chip_40xx/inc/chip.h
new file mode 100644
index 000000000..e63ae952c
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/chip.h
@@ -0,0 +1,152 @@
+/*
+ * @brief LPC17xx/LPC40xx basic chip inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @ingroup CHIP_17XX_40XX_DRIVER_OPTIONS
+ * @{
+ */
+
+/**
+ * @brief	System oscillator rate
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the external oscillator for the board. If using the
+ * internal oscillator, this rate can be 0.
+ */
+extern const uint32_t OscRateIn;
+
+/**
+ * @brief	RTC oscillator rate
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the RTC oscillator for the board. This is
+ * usually 32KHz (32768). If not using the RTC, this rate can be 0.
+ */
+extern const uint32_t RTCOscRateIn;
+
+/**
+ * @}
+ */
+
+/** @defgroup SUPPORT_17XX_40XX_FUNC CHIP: LPC17xx/40xx support functions
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Current system clock rate, mainly used for sysTick
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	Set up and initialize hardware prior to call to main()
+ * @return	None
+ * @note	Chip_SystemInit() is called prior to the application and sets up
+ * system clocking prior to the application starting.
+ */
+void Chip_SystemInit(void);
+
+/**
+ * @brief	USB Pin and clock initialization
+ * Calling this function will initialize the USB pins and the clock
+ * @return	None
+ * @note	This function will assume that the chip is clocked by an
+ * external crystal oscillator of frequency 12MHz and the Oscillator
+ * is running.
+ */
+void Chip_USB_Init(void);
+
+/**
+ * @brief	Clock and PLL initialization based on the external oscillator
+ * @return	None
+ * @note	This function assumes an external crystal oscillator
+ * frequency of 12MHz.
+ */
+void Chip_SetupXtalClocking(void);
+
+/**
+ * @brief	Clock and PLL initialization based on the internal oscillator
+ * @return	None
+ */
+void Chip_SetupIrcClocking(void);
+
+/**
+ * @}
+ */
+
+#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X)
+
+#ifndef CORE_M3
+#error CORE_M3 is not defined for the LPC17xx architecture
+#error CORE_M3 should be defined as part of your compiler define list
+#endif
+
+#elif defined(CHIP_LPC40XX)
+
+#ifndef CORE_M4
+#error CORE_M4 is not defined for the LPC40xx architecture
+#error CORE_M4 should be defined as part of your compiler define list
+#endif
+
+#elif defined(CHIP_LPC40XX)
+#error CHIP_LPC175X_6X/CHIP_LPC177X_8X/CHIP_LPC40XX is not defined!
+#endif
+
+#if defined(CHIP_LPC175X_6X)
+#include "chip_lpc175x_6x.h"
+
+#elif defined(CHIP_LPC177X_8X)
+#include "chip_lpc177x_8x.h"
+
+#elif defined(CHIP_LPC40XX)
+#include "chip_lpc407x_8x.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h b/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h
new file mode 100644
index 000000000..c7280a8a6
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h
@@ -0,0 +1,190 @@
+/*
+ * @brief LPC175x/6x basic chip inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC175X_6X_H_
+#define __CHIP_LPC175X_6X_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(CORE_M3)
+#error CORE_M3 is not defined for the LPC175x/6x architecture
+#error CORE_M3 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC175X_6X
+#error CHIP_LPC175X_6X is not defined!
+#endif
+
+/** @defgroup PERIPH_175X_6X_BASE CHIP: LPC175x/6x Peripheral addresses and register set declarations
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#define LPC_GPIO0_BASE            0x2009C000
+#define LPC_GPIO1_BASE            0x2009C020
+#define LPC_GPIO2_BASE            0x2009C040
+#define LPC_GPIO3_BASE            0x2009C060
+#define LPC_GPIO4_BASE            0x2009C080
+
+/* APB0 peripheral */
+#define LPC_WWDT_BASE             0x40000000
+#define LPC_TIMER0_BASE           0x40004000
+#define LPC_TIMER1_BASE           0x40008000
+#define LPC_UART0_BASE            0x4000C000
+#define LPC_UART1_BASE            0x40010000
+#define LPC_PWM1_BASE             0x40018000
+#define LPC_I2C0_BASE             0x4001C000
+#define LPC_SPI_BASE              0x40020000
+#define LPC_RTC_BASE              0x40024000
+#define LPC_REGFILE_BASE          0x40024044
+#define LPC_GPIOINT_BASE          0x40028080
+#define LPC_IOCON_BASE            0x4002C000
+#define LPC_SSP1_BASE             0x40030000
+#define LPC_ADC_BASE              0x40034000
+#define LPC_CANAF_RAM_BASE        0x40038000
+#define LPC_CANAF_BASE            0x4003C000
+#define LPC_CANCR_BASE            0x40040000
+#define LPC_CAN1_BASE             0x40044000
+#define LPC_CAN2_BASE             0x40048000
+#define LPC_I2C1_BASE             0x4005C000
+
+/* APB1 peripheral */
+#define LPC_FMC_BASE              0x40084000
+#define LPC_SSP0_BASE             0x40088000
+#define LPC_DAC_BASE              0x4008C000
+#define LPC_TIMER2_BASE           0x40090000
+#define LPC_TIMER3_BASE           0x40094000
+#define LPC_UART2_BASE            0x40098000
+#define LPC_UART3_BASE            0x4009C000
+#define LPC_I2C2_BASE             0x400A0000
+#define LPC_I2S_BASE              0x400A8000
+#define LPC_RITIMER_BASE          0x400B0000
+#define LPC_MCPWM_BASE            0x400B8000
+#define LPC_QEI_BASE              0x400BC000
+#define LPC_SYSCTL_BASE           0x400FC000
+#define LPC_PMU_BASE              0x400FC0C0
+
+/* AHB peripheral */
+#define LPC_ENET_BASE             0x50000000
+#define LPC_GPDMA_BASE            0x50004000
+#define LPC_USB_BASE              0x5000C000
+
+/* Assign LPC_* names to structures mapped to addresses */
+#define LPC_PMU                   ((LPC_PMU_T              *) LPC_PMU_BASE)
+#define LPC_GPDMA                 ((LPC_GPDMA_T            *) LPC_GPDMA_BASE)
+#define LPC_USB                   ((LPC_USB_T              *) LPC_USB_BASE)
+#define LPC_ETHERNET              ((LPC_ENET_T             *) LPC_ENET_BASE)
+#define LPC_GPIO                  ((LPC_GPIO_T             *) LPC_GPIO0_BASE)
+#define LPC_GPIO1                 ((LPC_GPIO_T             *) LPC_GPIO1_BASE)
+#define LPC_GPIO2                 ((LPC_GPIO_T             *) LPC_GPIO2_BASE)
+#define LPC_GPIO3                 ((LPC_GPIO_T             *) LPC_GPIO3_BASE)
+#define LPC_GPIO4                 ((LPC_GPIO_T             *) LPC_GPIO4_BASE)
+#define LPC_GPIOINT               ((LPC_GPIOINT_T          *) LPC_GPIOINT_BASE)
+#define LPC_RTC                   ((LPC_RTC_T              *) LPC_RTC_BASE)
+#define LPC_REGFILE               ((LPC_REGFILE_T          *) LPC_REGFILE_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_T             *) LPC_WWDT_BASE)
+#define LPC_UART0                 ((LPC_USART_T            *) LPC_UART0_BASE)
+#define LPC_UART1                 ((LPC_USART_T            *) LPC_UART1_BASE)
+#define LPC_UART2                 ((LPC_USART_T            *) LPC_UART2_BASE)
+#define LPC_UART3                 ((LPC_USART_T            *) LPC_UART3_BASE)
+#define LPC_SPI                   ((LPC_SPI_T              *) LPC_SPI_BASE)
+#define LPC_SSP0                  ((LPC_SSP_T              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSP_T              *) LPC_SSP1_BASE)
+#define LPC_TIMER0                ((LPC_TIMER_T            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((LPC_TIMER_T            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((LPC_TIMER_T            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((LPC_TIMER_T            *) LPC_TIMER3_BASE)
+#define LPC_MCPWM                 ((LPC_MCPWM_T            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((LPC_I2C_T              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((LPC_I2C_T              *) LPC_I2C1_BASE)
+#define LPC_I2C2                  ((LPC_I2C_T              *) LPC_I2C2_BASE)
+#define LPC_I2S                   ((LPC_I2S_T              *) LPC_I2S_BASE)
+#define LPC_QEI                   ((LPC_QEI_T              *) LPC_QEI_BASE)
+#define LPC_DAC                   ((LPC_DAC_T              *) LPC_DAC_BASE)
+#define LPC_ADC                   ((LPC_ADC_T              *) LPC_ADC_BASE)
+#define LPC_IOCON                 ((LPC_IOCON_T            *) LPC_IOCON_BASE)
+#define LPC_SYSCTL                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE)
+#define LPC_SYSCON                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
+#define LPC_CANAF_RAM             ((LPC_CANAF_RAM_T        *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF                 ((LPC_CANAF_T            *) LPC_CANAF_BASE)
+#define LPC_CANCR                 ((LPC_CANCR_T            *) LPC_CANCR_BASE)
+#define LPC_CAN1                  ((LPC_CAN_T              *) LPC_CAN1_BASE)
+#define LPC_CAN2                  ((LPC_CAN_T              *) LPC_CAN2_BASE)
+#define LPC_RITIMER               ((LPC_RITIMER_T          *) LPC_RITIMER_BASE)
+#define LPC_FMC                   ((LPC_FMC_T              *) LPC_FMC_BASE)
+
+/* IRQ Handler Alias list */
+#define UART_IRQHandler           UART0_IRQHandler
+#define I2C_IRQHandler            I2C0_IRQHandler
+#define SSP_IRQHandler            SSP0_IRQHandler
+
+/**
+ * @}
+ */
+
+#include "sysctl_17xx_40xx.h"
+#include "clock_17xx_40xx.h"
+#include "iocon_17xx_40xx.h"
+#include "adc_17xx_40xx.h"
+#include "can_17xx_40xx.h"
+#include "dac_17xx_40xx.h"
+#include "enet_17xx_40xx.h"
+#include "gpdma_17xx_40xx.h"
+#include "gpio_17xx_40xx.h"
+#include "gpioint_17xx_40xx.h"
+#include "i2c_17xx_40xx.h"
+#include "i2s_17xx_40xx.h"
+#include "mcpwm_17xx_40xx.h"
+#include "pmu_17xx_40xx.h"
+#include "qei_17xx_40xx.h"
+#include "ritimer_17xx_40xx.h"
+#include "rtc_17xx_40xx.h"
+#include "spi_17xx_40xx.h"
+#include "ssp_17xx_40xx.h"
+#include "timer_17xx_40xx.h"
+#include "uart_17xx_40xx.h"
+#include "usb_17xx_40xx.h"
+#include "wwdt_17xx_40xx.h"
+#include "fmc_17xx_40xx.h"
+#include "romapi_17xx_40xx.h"
+/* FIXME : PWM drivers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC175X_6X_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h b/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h
new file mode 100644
index 000000000..8e3b65cd2
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h
@@ -0,0 +1,203 @@
+/*
+ * @brief LPC177x/8x basic chip inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC177X_8X_H_
+#define __CHIP_LPC177X_8X_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(CORE_M3)
+#error CORE_M3 is not defined for the LPC177x/8x architecture
+#error CORE_M3 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC177X_8X
+#error CHIP_LPC177X_8X is not defined!
+#endif
+
+/** @defgroup PERIPH_177X_8X_BASE CHIP: LPC177x/8x Peripheral addresses and register set declarations
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#define LPC_FMC_BASE              0x00200000
+#define LPC_EEPROM_BASE           0x00200080
+#define LPC_GPDMA_BASE            0x20080000
+#define LPC_ENET_BASE             0x20084000
+#define LPC_LCD_BASE              0x20088000
+#define LPC_USB_BASE              0x2008C000
+#define LPC_CRC_BASE              0x20090000
+#define LPC_SPIFI_BASE            0x20094000
+#define LPC_GPIO0_BASE            0x20098000
+#define LPC_GPIO1_BASE            0x20098020
+#define LPC_GPIO2_BASE            0x20098040
+#define LPC_GPIO3_BASE            0x20098060
+#define LPC_GPIO4_BASE            0x20098080
+#define LPC_GPIO5_BASE            0x200980A0
+#define LPC_EMC_BASE              0x2009C000
+#define LPC_RTC_BASE              0x40024000
+#define LPC_REGFILE_BASE          0x40024044
+#define LPC_WWDT_BASE             0x40000000
+#define LPC_UART0_BASE            0x4000C000
+#define LPC_UART1_BASE            0x40010000
+#define LPC_UART2_BASE            0x40098000
+#define LPC_UART3_BASE            0x4009C000
+#define LPC_UART4_BASE            0x400A4000
+#define LPC_SSP0_BASE             0x40088000
+#define LPC_SSP1_BASE             0x40030000
+#define LPC_SSP2_BASE             0x400AC000
+#define LPC_TIMER0_BASE           0x40004000
+#define LPC_TIMER1_BASE           0x40008000
+#define LPC_TIMER2_BASE           0x40090000
+#define LPC_TIMER3_BASE           0x40094000
+#define LPC_MCPWM_BASE            0x400B8000
+#define LPC_PWM0_BASE             0x40014000
+#define LPC_PWM1_BASE             0x40018000
+#define LPC_I2C0_BASE             0x4001C000
+#define LPC_I2C1_BASE             0x4005C000
+#define LPC_I2C2_BASE             0x400A0000
+#define LPC_I2S_BASE              0x400A8000
+#define LPC_CANAF_RAM_BASE        0x40038000
+#define LPC_CANAF_BASE            0x4003C000
+#define LPC_CANCR_BASE            0x40040000
+#define LPC_CAN1_BASE             0x40044000
+#define LPC_CAN2_BASE             0x40048000
+#define LPC_QEI_BASE              0x400BC000
+#define LPC_DAC_BASE              0x4008C000
+#define LPC_ADC_BASE              0x40034000
+#define LPC_GPIOINT_BASE          0x40028080
+#define LPC_IOCON_BASE            0x4002C000
+#define LPC_SDC_BASE              0x400C0000
+#define LPC_SYSCTL_BASE           0x400FC000
+#define LPC_PMU_BASE              0x400FC0C0
+
+/* Assign LPC_* names to structures mapped to addresses */
+#define LPC_PMU                   ((LPC_PMU_T              *) LPC_PMU_BASE)
+#define LPC_EEPROM                ((LPC_EEPROM_T           *) LPC_EEPROM_BASE)
+#define LPC_GPDMA                 ((LPC_GPDMA_T            *) LPC_GPDMA_BASE)
+#define LPC_EMC                   ((LPC_EMC_T              *) LPC_EMC_BASE)
+#define LPC_USB                   ((LPC_USB_T              *) LPC_USB_BASE)
+#define LPC_LCD                   ((LPC_LCD_T              *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((LPC_ENET_T             *) LPC_ENET_BASE)
+#define LPC_GPIO                  ((LPC_GPIO_T             *) LPC_GPIO0_BASE)
+#define LPC_GPIO1                 ((LPC_GPIO_T             *) LPC_GPIO1_BASE)
+#define LPC_GPIO2                 ((LPC_GPIO_T             *) LPC_GPIO2_BASE)
+#define LPC_GPIO3                 ((LPC_GPIO_T             *) LPC_GPIO3_BASE)
+#define LPC_GPIO4                 ((LPC_GPIO_T             *) LPC_GPIO4_BASE)
+#define LPC_GPIO5                 ((LPC_GPIO_T             *) LPC_GPIO5_BASE)
+#define LPC_GPIOINT               ((LPC_GPIOINT_T          *) LPC_GPIOINT_BASE)
+#define LPC_RTC                   ((LPC_RTC_T              *) LPC_RTC_BASE)
+#define LPC_REGFILE               ((LPC_REGFILE_T          *) LPC_REGFILE_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_T             *) LPC_WWDT_BASE)
+#define LPC_UART0                 ((LPC_USART_T            *) LPC_UART0_BASE)
+#define LPC_UART1                 ((LPC_USART_T            *) LPC_UART1_BASE)
+#define LPC_UART2                 ((LPC_USART_T            *) LPC_UART2_BASE)
+#define LPC_UART3                 ((LPC_USART_T            *) LPC_UART3_BASE)
+#define LPC_UART4                 ((LPC_USART_T            *) LPC_UART4_BASE)
+#define LPC_SSP0                  ((LPC_SSP_T              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSP_T              *) LPC_SSP1_BASE)
+#define LPC_SSP2                  ((LPC_SSP_T              *) LPC_SSP2_BASE)
+#define LPC_TIMER0                ((LPC_TIMER_T            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((LPC_TIMER_T            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((LPC_TIMER_T            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((LPC_TIMER_T            *) LPC_TIMER3_BASE)
+#define LPC_MCPWM                 ((LPC_MCPWM_T            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((LPC_I2C_T              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((LPC_I2C_T              *) LPC_I2C1_BASE)
+#define LPC_I2C2                  ((LPC_I2C_T              *) LPC_I2C2_BASE)
+#define LPC_I2S                   ((LPC_I2S_T              *) LPC_I2S_BASE)
+#define LPC_QEI                   ((LPC_QEI_T              *) LPC_QEI_BASE)
+#define LPC_DAC                   ((LPC_DAC_T              *) LPC_DAC_BASE)
+#define LPC_ADC                   ((LPC_ADC_T              *) LPC_ADC_BASE)
+#define LPC_IOCON                 ((LPC_IOCON_T            *) LPC_IOCON_BASE)
+#define LPC_SDC                   ((LPC_SDC_T              *) LPC_SDC_BASE)
+#define LPC_SYSCTL                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE)
+#define LPC_SYSCON                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
+#define LPC_CANAF_RAM             ((LPC_CANAF_RAM_T        *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF                 ((LPC_CANAF_T            *) LPC_CANAF_BASE)
+#define LPC_CANCR                 ((LPC_CANCR_T            *) LPC_CANCR_BASE)
+#define LPC_CAN1                  ((LPC_CAN_T              *) LPC_CAN1_BASE)
+#define LPC_CAN2                  ((LPC_CAN_T              *) LPC_CAN2_BASE)
+#define LPC_CRC                   ((LPC_CRC_T              *) LPC_CRC_BASE)
+#define LPC_FMC                   ((LPC_FMC_T              *) LPC_FMC_BASE)
+
+/* IRQ Handler Alias list */
+#define UART_IRQHandler           UART0_IRQHandler
+#define I2C_IRQHandler            I2C0_IRQHandler
+#define SSP_IRQHandler            SSP0_IRQHandler
+
+
+/**
+ * @}
+ */
+
+#include "sysctl_17xx_40xx.h"
+#include "clock_17xx_40xx.h"
+#include "iocon_17xx_40xx.h"
+#include "adc_17xx_40xx.h"
+#include "can_17xx_40xx.h"
+#include "crc_17xx_40xx.h"
+#include "dac_17xx_40xx.h"
+#include "eeprom_17xx_40xx.h"
+#include "emc_17xx_40xx.h"
+#include "enet_17xx_40xx.h"
+#include "gpdma_17xx_40xx.h"
+#include "gpio_17xx_40xx.h"
+#include "gpioint_17xx_40xx.h"
+#include "i2c_17xx_40xx.h"
+#include "i2s_17xx_40xx.h"
+#include "lcd_17xx_40xx.h"
+#include "mcpwm_17xx_40xx.h"
+#include "pmu_17xx_40xx.h"
+#include "qei_17xx_40xx.h"
+#include "rtc_17xx_40xx.h"
+#include "sdc_17xx_40xx.h"
+#include "sdmmc_17xx_40xx.h"
+#include "ssp_17xx_40xx.h"
+#include "timer_17xx_40xx.h"
+#include "uart_17xx_40xx.h"
+#include "usb_17xx_40xx.h"
+#include "wwdt_17xx_40xx.h"
+#include "fmc_17xx_40xx.h"
+#include "romapi_17xx_40xx.h"
+/* FIXME - missing PWM and possibly CREG drivers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC177X_8X_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h b/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h
new file mode 100644
index 000000000..aca840079
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h
@@ -0,0 +1,206 @@
+/*
+ * @brief LPC407x/8x basic chip inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_LPC40XX_H_
+#define __CHIP_LPC40XX_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(CORE_M4)
+#error CORE_M4 is not defined for the LPC407x/8x architecture
+#error CORE_M4 should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC40XX
+#error CHIP_LPC40XX is not defined!
+#endif
+
+/** @defgroup PERIPH_407X_8X_BASE CHIP: LPC407x/8x Peripheral addresses and register set declarations
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+#define LPC_FMC_BASE              0x00200000
+#define LPC_EEPROM_BASE           0x00200080
+#define LPC_GPDMA_BASE            0x20080000
+#define LPC_ENET_BASE             0x20084000
+#define LPC_LCD_BASE              0x20088000
+#define LPC_USB_BASE              0x2008C000
+#define LPC_CRC_BASE              0x20090000
+#define LPC_SPIFI_BASE            0x20094000
+#define LPC_GPIO0_BASE            0x20098000
+#define LPC_GPIO1_BASE            0x20098020
+#define LPC_GPIO2_BASE            0x20098040
+#define LPC_GPIO3_BASE            0x20098060
+#define LPC_GPIO4_BASE            0x20098080
+#define LPC_GPIO5_BASE            0x200980A0
+#define LPC_EMC_BASE              0x2009C000
+#define LPC_RTC_BASE              0x40024000
+#define LPC_REGFILE_BASE          0x40024044
+#define LPC_WWDT_BASE             0x40000000
+#define LPC_UART0_BASE            0x4000C000
+#define LPC_UART1_BASE            0x40010000
+#define LPC_UART2_BASE            0x40098000
+#define LPC_UART3_BASE            0x4009C000
+#define LPC_UART4_BASE            0x400A4000
+#define LPC_SSP0_BASE             0x40088000
+#define LPC_SSP1_BASE             0x40030000
+#define LPC_SSP2_BASE             0x400AC000
+#define LPC_TIMER0_BASE           0x40004000
+#define LPC_TIMER1_BASE           0x40008000
+#define LPC_TIMER2_BASE           0x40090000
+#define LPC_TIMER3_BASE           0x40094000
+#define LPC_MCPWM_BASE            0x400B8000
+#define LPC_PWM0_BASE             0x40014000
+#define LPC_PWM1_BASE             0x40018000
+#define LPC_I2C0_BASE             0x4001C000
+#define LPC_I2C1_BASE             0x4005C000
+#define LPC_I2C2_BASE             0x400A0000
+#define LPC_I2S_BASE              0x400A8000
+#define LPC_CANAF_RAM_BASE        0x40038000
+#define LPC_CANAF_BASE            0x4003C000
+#define LPC_CANCR_BASE            0x40040000
+#define LPC_CAN1_BASE             0x40044000
+#define LPC_CAN2_BASE             0x40048000
+#define LPC_QEI_BASE              0x400BC000
+#define LPC_DAC_BASE              0x4008C000
+#define LPC_ADC_BASE              0x40034000
+#define LPC_GPIOINT_BASE          0x40028080
+#define LPC_IOCON_BASE            0x4002C000
+#define LPC_SDC_BASE              0x400C0000
+#define LPC_SYSCTL_BASE           0x400FC000
+#define LPC_CMP_BASE              0x40020000
+#define LPC_PMU_BASE              0x400FC0C0
+
+/* Assign LPC_* names to structures mapped to addresses */
+#define LPC_PMU                   ((LPC_PMU_T              *) LPC_PMU_BASE)
+#define LPC_EEPROM                ((LPC_EEPROM_T           *) LPC_EEPROM_BASE)
+#define LPC_GPDMA                 ((LPC_GPDMA_T            *) LPC_GPDMA_BASE)
+#define LPC_EMC                   ((LPC_EMC_T              *) LPC_EMC_BASE)
+#define LPC_USB                   ((LPC_USB_T              *) LPC_USB_BASE)
+#define LPC_LCD                   ((LPC_LCD_T              *) LPC_LCD_BASE)
+#define LPC_ETHERNET              ((LPC_ENET_T             *) LPC_ENET_BASE)
+#define LPC_GPIO                  ((LPC_GPIO_T             *) LPC_GPIO0_BASE)
+#define LPC_GPIO1                 ((LPC_GPIO_T             *) LPC_GPIO1_BASE)
+#define LPC_GPIO2                 ((LPC_GPIO_T             *) LPC_GPIO2_BASE)
+#define LPC_GPIO3                 ((LPC_GPIO_T             *) LPC_GPIO3_BASE)
+#define LPC_GPIO4                 ((LPC_GPIO_T             *) LPC_GPIO4_BASE)
+#define LPC_GPIO5                 ((LPC_GPIO_T             *) LPC_GPIO5_BASE)
+#define LPC_GPIOINT               ((LPC_GPIOINT_T          *) LPC_GPIOINT_BASE)
+#define LPC_RTC                   ((LPC_RTC_T              *) LPC_RTC_BASE)
+#define LPC_REGFILE               ((LPC_REGFILE_T          *) LPC_REGFILE_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_T             *) LPC_WWDT_BASE)
+#define LPC_UART0                 ((LPC_USART_T            *) LPC_UART0_BASE)
+#define LPC_UART1                 ((LPC_USART_T            *) LPC_UART1_BASE)
+#define LPC_UART2                 ((LPC_USART_T            *) LPC_UART2_BASE)
+#define LPC_UART3                 ((LPC_USART_T            *) LPC_UART3_BASE)
+#define LPC_UART4                 ((LPC_USART_T            *) LPC_UART4_BASE)
+#define LPC_SSP0                  ((LPC_SSP_T              *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSP_T              *) LPC_SSP1_BASE)
+#define LPC_SSP2                  ((LPC_SSP_T              *) LPC_SSP2_BASE)
+#define LPC_TIMER0                ((LPC_TIMER_T            *) LPC_TIMER0_BASE)
+#define LPC_TIMER1                ((LPC_TIMER_T            *) LPC_TIMER1_BASE)
+#define LPC_TIMER2                ((LPC_TIMER_T            *) LPC_TIMER2_BASE)
+#define LPC_TIMER3                ((LPC_TIMER_T            *) LPC_TIMER3_BASE)
+#define LPC_MCPWM                 ((LPC_MCPWM_T            *) LPC_MCPWM_BASE)
+#define LPC_I2C0                  ((LPC_I2C_T              *) LPC_I2C0_BASE)
+#define LPC_I2C1                  ((LPC_I2C_T              *) LPC_I2C1_BASE)
+#define LPC_I2C2                  ((LPC_I2C_T              *) LPC_I2C2_BASE)
+#define LPC_I2S                   ((LPC_I2S_T              *) LPC_I2S_BASE)
+#define LPC_QEI                   ((LPC_QEI_T              *) LPC_QEI_BASE)
+#define LPC_DAC                   ((LPC_DAC_T              *) LPC_DAC_BASE)
+#define LPC_ADC                   ((LPC_ADC_T              *) LPC_ADC_BASE)
+#define LPC_IOCON                 ((LPC_IOCON_T            *) LPC_IOCON_BASE)
+#define LPC_SDC                   ((LPC_SDC_T              *) LPC_SDC_BASE)
+#define LPC_SYSCTL                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE)
+#define LPC_SYSCON                ((LPC_SYSCTL_T           *) LPC_SYSCTL_BASE) /* Alias for LPC_SYSCTL */
+#define LPC_CMP                   ((LPC_CMP_T              *) LPC_CMP_BASE)
+#define LPC_CANAF_RAM             ((LPC_CANAF_RAM_T        *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF                 ((LPC_CANAF_T            *) LPC_CANAF_BASE)
+#define LPC_CANCR                 ((LPC_CANCR_T            *) LPC_CANCR_BASE)
+#define LPC_CAN1                  ((LPC_CAN_T              *) LPC_CAN1_BASE)
+#define LPC_CAN2                  ((LPC_CAN_T              *) LPC_CAN2_BASE)
+#define LPC_CRC                   ((LPC_CRC_T              *) LPC_CRC_BASE)
+#define LPC_FMC                   ((LPC_FMC_T              *) LPC_FMC_BASE)
+
+/* IRQ Handler Alias list */
+#define UART_IRQHandler           UART0_IRQHandler
+#define I2C_IRQHandler            I2C0_IRQHandler
+#define SSP_IRQHandler            SSP0_IRQHandler
+
+/**
+ * @}
+ */
+
+#include "sysctl_17xx_40xx.h"
+#include "clock_17xx_40xx.h"
+#include "iocon_17xx_40xx.h"
+#include "adc_17xx_40xx.h"
+#include "can_17xx_40xx.h"
+#include "cmp_17xx_40xx.h"
+#include "crc_17xx_40xx.h"
+#include "dac_17xx_40xx.h"
+#include "eeprom_17xx_40xx.h"
+#include "emc_17xx_40xx.h"
+#include "enet_17xx_40xx.h"
+#include "gpdma_17xx_40xx.h"
+#include "gpio_17xx_40xx.h"
+#include "gpioint_17xx_40xx.h"
+#include "i2c_17xx_40xx.h"
+#include "i2s_17xx_40xx.h"
+#include "lcd_17xx_40xx.h"
+#include "pmu_17xx_40xx.h"
+#include "mcpwm_17xx_40xx.h"
+#include "qei_17xx_40xx.h"
+#include "rtc_17xx_40xx.h"
+#include "sdc_17xx_40xx.h"
+#include "sdmmc_17xx_40xx.h"
+#include "spifi_17xx_40xx.h"
+#include "ssp_17xx_40xx.h"
+#include "timer_17xx_40xx.h"
+#include "uart_17xx_40xx.h"
+#include "usb_17xx_40xx.h"
+#include "wwdt_17xx_40xx.h"
+#include "fmc_17xx_40xx.h"
+#include "romapi_17xx_40xx.h"
+#include "fpu_init.h"
+/* FIXME - missing PWM and possibly CREG drivers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_LPC40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h
new file mode 100644
index 000000000..b687114a8
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h
@@ -0,0 +1,896 @@
+/*
+ * @brief LPC17XX/40XX Clock control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CLOCK_17XX_40XX_H_
+#define __CLOCK_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CLOCK_17XX_40XX CHIP: LPC17xx/40xx Clock Driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#define SYSCTL_OSCRANGE_15_25 (1 << 4)	/*!< SCS register - main oscillator range 15 to 25MHz */
+#define SYSCTL_OSCEC          (1 << 5)	/*!< SCS register - main oscillator enable */
+#define SYSCTL_OSCSTAT        (1 << 6)	/*!< SCS register - main oscillator is ready status */
+
+/*!< Internal oscillator frequency */
+#if defined(CHIP_LPC175X_6X)
+#define SYSCTL_IRC_FREQ (4000000)
+#else
+#define SYSCTL_IRC_FREQ (12000000)
+#endif
+
+#define SYSCTL_PLL_ENABLE   (1 << 0)/*!< PLL enable flag */
+#if defined(CHIP_LPC175X_6X)
+#define SYSCTL_PLL_CONNECT (1 << 1)	/*!< PLL connect flag only applies to 175x/6x */
+#endif
+
+/**
+ * @brief	Enables or connects a PLL
+ * @param	PLLNum:	PLL number
+ * @param	flags:	SYSCTL_PLL_ENABLE or SYSCTL_PLL_CONNECT
+ * @return	Nothing
+ * @note	This will also perform a PLL feed sequence. Connect only applies to the
+ * LPC175x/6x devices.
+ */
+void Chip_Clock_EnablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags);
+
+/**
+ * @brief	Disables or disconnects a PLL
+ * @param	PLLNum:	PLL number
+ * @param	flags:	SYSCTL_PLL_ENABLE or SYSCTL_PLL_CONNECT
+ * @return	Nothing
+ * @note	This will also perform a PLL feed sequence. Connect only applies to the
+ * LPC175x/6x devices.
+ */
+void Chip_Clock_DisablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags);
+
+/**
+ * @brief	Sets up a PLL
+ * @param	PLLNum:		PLL number
+ * @param	msel:	PLL Multiplier value (Must be pre-decremented)
+ * @param	psel:	PLL Divider value (Must be pre-decremented)
+ * @note		See the User Manual for limitations on these values for stable PLL
+ * operation. Be careful with these values - they must be safe values for the
+ * msl, nsel, and psel registers so must be already decremented by 1 or the
+ * the correct value for psel (0 = div by 1, 1 = div by 2, etc.).
+ * @return	Nothing
+ */
+void Chip_Clock_SetupPLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t msel, uint32_t psel);
+
+#if defined(CHIP_LPC175X_6X)
+#define SYSCTL_PLL0STS_ENABLED   (1 << 24)	/*!< PLL0 enable flag */
+#define SYSCTL_PLL0STS_CONNECTED (1 << 25)	/*!< PLL0 connect flag */
+#define SYSCTL_PLL0STS_LOCKED    (1 << 26)	/*!< PLL0 connect flag */
+#define SYSCTL_PLL1STS_ENABLED   (1 << 8)	/*!< PLL1 enable flag */
+#define SYSCTL_PLL1STS_CONNECTED (1 << 9)	/*!< PLL1 connect flag */
+#define SYSCTL_PLL1STS_LOCKED    (1 << 10)	/*!< PLL1 connect flag */
+#else
+#define SYSCTL_PLLSTS_ENABLED   (1 << 8)	/*!< PLL enable flag */
+#define SYSCTL_PLLSTS_LOCKED    (1 << 10)	/*!< PLL connect flag */
+#endif
+
+/**
+ * @brief	Returns PLL status
+ * @param	PLLNum:		PLL number
+ * @return	Current enabled flags, Or'ed SYSCTL_PLLSTS_* states
+ * @note	Note flag positions for PLL0 and PLL1 differ on the LPC175x/6x devices.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetPLLStatus(CHIP_SYSCTL_PLL_T PLLNum)
+{
+	return LPC_SYSCTL->PLL[PLLNum].PLLSTAT;
+}
+
+/**
+ * @brief	Read PLL0 enable status
+ * @return	true of the PLL0 is enabled. false if not enabled
+ */
+STATIC INLINE bool Chip_Clock_IsMainPLLEnabled(void)
+{
+#if defined(CHIP_LPC175X_6X)
+	return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_ENABLED) != 0);
+#else
+	return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLLSTS_ENABLED) != 0);
+#endif
+}
+
+/**
+ * @brief	Read PLL1 enable status
+ * @return	true of the PLL1 is enabled. false if not enabled
+ */
+STATIC INLINE bool Chip_Clock_IsUSBPLLEnabled(void)
+{
+#if defined(CHIP_LPC175X_6X)
+	return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_ENABLED) != 0);
+#else
+	return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLLSTS_ENABLED) != 0);
+#endif
+}
+
+/**
+ * @brief	Read PLL0 lock status
+ * @return	true of the PLL0 is locked. false if not locked
+ */
+STATIC INLINE bool Chip_Clock_IsMainPLLLocked(void)
+{
+#if defined(CHIP_LPC175X_6X)
+	return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_LOCKED) != 0);
+#else
+	return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLLSTS_LOCKED) != 0);
+#endif
+}
+
+/**
+ * @brief	Read PLL1 lock status
+ * @return	true of the PLL1 is locked. false if not locked
+ */
+STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
+{
+#if defined(CHIP_LPC175X_6X)
+	return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_LOCKED) != 0);
+#else
+	return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLLSTS_LOCKED) != 0);
+#endif
+}
+
+#if defined(CHIP_LPC175X_6X)
+/**
+ * @brief	Read PLL0 connect status
+ * @return	true of the PLL0 is connected. false if not connected
+ */
+STATIC INLINE bool Chip_Clock_IsMainPLLConnected(void)
+{
+	return (bool) ((LPC_SYSCTL->PLL[0].PLLSTAT & SYSCTL_PLL0STS_CONNECTED) != 0);
+}
+
+/**
+ * @brief	Read PLL1 lock status
+ * @return	true of the PLL1 is connected. false if not connected
+ */
+STATIC INLINE bool Chip_Clock_IsUSBPLLConnected(void)
+{
+	return (bool) ((LPC_SYSCTL->PLL[1].PLLSTAT & SYSCTL_PLL1STS_CONNECTED) != 0);
+}
+#endif
+
+/**
+ * @brief	Enables the external Crystal oscillator
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_EnableCrystal(void)
+{
+	LPC_SYSCTL->SCS |= SYSCTL_OSCEC;
+}
+
+/**
+ * @brief	Checks if the external Crystal oscillator is enabled
+ * @return	true if enabled, false otherwise
+ */
+STATIC INLINE bool Chip_Clock_IsCrystalEnabled(void)
+{
+	return (LPC_SYSCTL->SCS & SYSCTL_OSCSTAT) != 0;
+}
+
+/**
+ * @brief Sets the external crystal oscillator range to 15Mhz - 25MHz
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_SetCrystalRangeHi(void)
+{
+	LPC_SYSCTL->SCS |= SYSCTL_OSCRANGE_15_25;
+}
+
+/**
+ * @brief Sets the external crystal oscillator range to 1Mhz - 20MHz
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_SetCrystalRangeLo(void)
+{
+	LPC_SYSCTL->SCS &= ~SYSCTL_OSCRANGE_15_25;
+}
+
+/**
+ * @brief	Feeds a PLL
+ * @param	PLLNum:	PLL number
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_FeedPLL(CHIP_SYSCTL_PLL_T PLLNum)
+{
+	LPC_SYSCTL->PLL[PLLNum].PLLFEED = 0xAA;
+	LPC_SYSCTL->PLL[PLLNum].PLLFEED = 0x55;
+}
+
+/**
+ * Power control for peripherals
+ */
+typedef enum CHIP_SYSCTL_CLOCK {
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_RSVD0,
+#else
+	SYSCTL_CLOCK_LCD,					/*!< LCD clock */
+#endif
+	SYSCTL_CLOCK_TIMER0,			/*!< Timer 0 clock */
+	SYSCTL_CLOCK_TIMER1,			/*!< Timer 1 clock */
+	SYSCTL_CLOCK_UART0,				/*!< UART 0 clock */
+	SYSCTL_CLOCK_UART1,				/*!< UART 1 clock */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_RSVD5,
+#else
+	SYSCTL_CLOCK_PWM0,				/*!< PWM0 clock */
+#endif
+	SYSCTL_CLOCK_PWM1,				/*!< PWM1 clock */
+	SYSCTL_CLOCK_I2C0,				/*!< I2C0 clock */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_SPI,					/*!< SPI clock */
+#else
+	SYSCTL_CLOCK_UART4,				/*!< UART 4 clock */
+#endif
+	SYSCTL_CLOCK_RTC,					/*!< RTC clock */
+	SYSCTL_CLOCK_SSP1,				/*!< SSP1 clock */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_RSVD11,
+#else
+	SYSCTL_CLOCK_EMC,					/*!< EMC clock */
+#endif
+	SYSCTL_CLOCK_ADC,					/*!< ADC clock */
+	SYSCTL_CLOCK_CAN1,				/*!< CAN1 clock */
+	SYSCTL_CLOCK_CAN2,				/*!< CAN2 clock */
+	SYSCTL_CLOCK_GPIO,				/*!< GPIO clock */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_RIT,				/*!< RIT clock */
+#else
+	SYSCTL_CLOCK_SPIFI,				/*!< SPIFI clock */
+#endif
+	SYSCTL_CLOCK_MCPWM,				/*!< MCPWM clock */
+	SYSCTL_CLOCK_QEI,					/*!< QEI clock */
+	SYSCTL_CLOCK_I2C1,				/*!< I2C1 clock */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_RSVD20,
+#else
+	SYSCTL_CLOCK_SSP2,				/*!< SSP2 clock */
+#endif
+	SYSCTL_CLOCK_SSP0,				/*!< SSP0 clock */
+	SYSCTL_CLOCK_TIMER2,			/*!< Timer 2 clock */
+	SYSCTL_CLOCK_TIMER3,			/*!< Timer 3 clock */
+	SYSCTL_CLOCK_UART2,				/*!< UART 2 clock */
+	SYSCTL_CLOCK_UART3,				/*!< UART 3 clock */
+	SYSCTL_CLOCK_I2C2,				/*!< I2C2 clock */
+	SYSCTL_CLOCK_I2S,					/*!< I2S clock */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLOCK_RSVD28,
+#else
+	SYSCTL_CLOCK_SDC,				/*!< SD Card interface clock */
+#endif
+	SYSCTL_CLOCK_GPDMA,				/*!< GP DMA clock */
+	SYSCTL_CLOCK_ENET,				/*!< EMAC/Ethernet clock */
+	SYSCTL_CLOCK_USB,					/*!< USB clock */
+	SYSCTL_CLOCK_RSVD32,
+	SYSCTL_CLOCK_RSVD33,
+	SYSCTL_CLOCK_RSVD34,
+#if defined(CHIP_LPC40XX)
+	SYSCTL_CLOCK_CMP,				/*!< Comparator clock (PCONP1) */
+#else
+	SYSCTL_CLOCK_RSVD35,
+#endif
+} CHIP_SYSCTL_CLOCK_T;
+
+/**
+ * @brief	Enables power and clocking for a peripheral
+ * @param	clk:	Clock to enable
+ * @return	Nothing
+ * @note	Only peripheral clocks that are defined in the PCONP registers of the clock
+ * and power controller can be enabled and disabled with this function.
+ * Some clocks need to be enabled elsewhere (ie, USB) and will return
+ * false to indicate it can't be enabled with this function.
+ */
+void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
+
+/**
+ * @brief	Disables power and clocking for a peripheral
+ * @param	clk:	Clock to disable
+ * @return	Nothing
+ * @note	Only peripheral clocks that are defined in the PCONP registers of the clock
+ * and power controller can be enabled and disabled with this function.
+ * Some clocks need to be disabled elsewhere (ie, USB) and will return
+ * false to indicate it can't be disabled with this function.
+ */
+void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk);
+
+/**
+ * @brief	Returns power enables state for a peripheral
+ * @param	clk:	Clock to check
+ * @return	true if the clock is enabled, false if disabled
+ */
+bool Chip_Clock_IsPeripheralClockEnabled(CHIP_SYSCTL_CLOCK_T clk);
+
+#if !defined(CHIP_LPC175X_6X)
+/**
+ * EMC clock divider values
+ */
+typedef enum CHIP_SYSCTL_EMC_DIV {
+	SYSCTL_EMC_DIV1 = 0,
+	SYSCTL_EMC_DIV2 = 1,
+} CHIP_SYSCTL_EMC_DIV_T;
+
+/**
+ * @brief	Selects a EMC divider rate
+ * @param	emcDiv:	Source clock for PLL
+ * @return	Nothing
+ * @note	This function controls division of the clock before it is used by the EMC.
+ * The EMC uses the same base clock as the CPU and the APB peripherals. The
+ * EMC clock can tun at half or the same as the CPU clock. This is intended to
+ * be used primarily when the CPU is running faster than the external bus can
+ * support.
+ */
+STATIC INLINE void Chip_Clock_SetEMCClockDiv(CHIP_SYSCTL_EMC_DIV_T emcDiv)
+{
+	LPC_SYSCTL->EMCCLKSEL = (uint32_t) emcDiv;
+}
+
+/**
+ * @brief	Get EMC divider rate
+ * @return	divider value
+ */
+STATIC INLINE uint32_t Chip_Clock_GetEMCClockDiv(void)
+{
+	return ((uint32_t) LPC_SYSCTL->EMCCLKSEL) + 1;
+}
+
+#endif
+
+/**
+ * Selectable CPU clock sources
+ */
+typedef enum CHIP_SYSCTL_CCLKSRC {
+	SYSCTL_CCLKSRC_SYSCLK,		/*!< Select Sysclk as the input to the CPU clock divider. */
+	SYSCTL_CCLKSRC_MAINPLL,		/*!< Select the output of the Main PLL as the input to the CPU clock divider. */
+} CHIP_SYSCTL_CCLKSRC_T;
+
+/**
+ * @brief	Sets the current CPU clock source
+ * @param   src     Source selected
+ * @return	Nothing
+ * @note	When setting the clock source to the PLL, it should
+ * be enabled and locked.
+ */
+void Chip_Clock_SetCPUClockSource(CHIP_SYSCTL_CCLKSRC_T src);
+
+/**
+ * @brief	Returns the current CPU clock source
+ * @return	CPU clock source
+ * @note	On 177x/8x and 407x/8x devices, this is also the peripheral
+ * clock source.
+ */
+CHIP_SYSCTL_CCLKSRC_T Chip_Clock_GetCPUClockSource(void);
+
+/**
+ * @brief	Sets the CPU clock divider
+ * @param	div:	CPU clock divider, between 1 and divider max
+ * @return	Nothing
+ * @note	The maximum divider for the 175x/6x is 256. The maximum divider for
+ * the 177x/8x and 407x/8x is 32. Note on 175x/6x devices, the divided CPU
+ * clock rate is used as the input to the peripheral clock dividers,
+ * while 177x/8x and 407x/8x devices use the undivided CPU clock rate.
+ */
+void Chip_Clock_SetCPUClockDiv(uint32_t div);
+
+/**
+ * @brief	Gets the CPU clock divider
+ * @return	CPU clock divider, between 1 and divider max
+ * @note	The maximum divider for the 175x/6x is 256. The maximum divider for
+ * the 177x/8x and 407x/8x is 32. Note on 175x/6x devices, the divided CPU
+ * clock rate is used as the input to the peripheral clock dividers,
+ * while 177x/8x and 407x/8x devices use the undivided CPU clock rate.
+ */
+uint32_t Chip_Clock_GetCPUClockDiv(void);
+
+#if !defined(CHIP_LPC175X_6X)
+/**
+ * Clock sources for the USB divider. On 175x/6x devices, only the USB
+ * PLL1 can be used as an input for the USB divider
+ */
+typedef enum CHIP_SYSCTL_USBCLKSRC {
+	SYSCTL_USBCLKSRC_SYSCLK,		/*!< SYSCLK clock as USB divider source */
+	SYSCTL_USBCLKSRC_MAINPLL,		/*!< PLL0 clock as USB divider source */
+	SYSCTL_USBCLKSRC_USBPLL,		/*!< PLL1 clock as USB divider source */
+	SYSCTL_USBCLKSRC_RESERVED
+} CHIP_SYSCTL_USBCLKSRC_T;
+
+/**
+ * @brief	Sets the USB clock divider source
+ * @param	src:	USB clock divider source clock
+ * @return	Nothing
+ * @note	This function doesn't apply for LPC175x/6x devices. The divider must be
+ * be selected with the selected source to give a valid USB clock with a
+ * rate of 48MHz.
+ */
+void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src);
+
+/**
+ * @brief	Gets the USB clock divider source
+ * @return	USB clock divider source clock
+ */
+STATIC INLINE CHIP_SYSCTL_USBCLKSRC_T Chip_Clock_GetUSBClockSource(void)
+{
+	return (CHIP_SYSCTL_USBCLKSRC_T) ((LPC_SYSCTL->USBCLKSEL >> 8) & 0x3);
+}
+
+#endif /* !defined(CHIP_LPC175X_6X)*/
+
+/**
+ * @brief	Sets the USB clock divider
+ * @param	div:	USB clock divider to generate 48MHz from USB source clock
+ * @return	Nothing
+ * @note	Divider values are between 1 and 32 (16 max for 175x/6x)
+ */
+void Chip_Clock_SetUSBClockDiv(uint32_t div);
+
+/**
+ * @brief	Gets the USB clock divider
+ * @return	USB clock divider
+ * @note	Divider values are between 1 and 32 (16 max for 175x/6x)
+ */
+uint32_t Chip_Clock_GetUSBClockDiv(void);
+
+/**
+ * PLL source clocks
+ */
+typedef enum CHIP_SYSCTL_PLLCLKSRC {
+	SYSCTL_PLLCLKSRC_IRC,			/*!< PLL is sourced from the internal oscillator (IRC) */
+	SYSCTL_PLLCLKSRC_MAINOSC,		/*!< PLL is sourced from the main oscillator */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_PLLCLKSRC_RTC,			/*!< PLL is sourced from the RTC oscillator */
+#else
+	SYSCTL_PLLCLKSRC_RESERVED1,
+#endif
+	SYSCTL_PLLCLKSRC_RESERVED2
+} CHIP_SYSCTL_PLLCLKSRC_T;
+
+/**
+ * @brief	Selects a input clock source for SYSCLK
+ * @param	src:	input clock source for SYSCLK
+ * @return	Nothing
+ * @note	SYSCLK is used for sourcing PLL0, SPIFI FLASH, the USB clock
+ * divider, and the CPU clock divider.
+ */
+STATIC INLINE void Chip_Clock_SetMainPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
+{
+	LPC_SYSCTL->CLKSRCSEL = src;
+}
+
+/**
+ * @brief	Returns the input clock source for SYSCLK
+ * @return	input clock source for SYSCLK
+ */
+STATIC INLINE CHIP_SYSCTL_PLLCLKSRC_T Chip_Clock_GetMainPLLSource(void)
+{
+	return (CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->CLKSRCSEL & 0x3);
+}
+
+#if defined(CHIP_LPC175X_6X)
+/**
+ * Clock and power peripheral clock divider rates used with the
+ * Clock_CLKDIVSEL_T clock types (devices only)
+ */
+typedef enum {
+	SYSCTL_CLKDIV_4,			/*!< Divider by 4 */
+	SYSCTL_CLKDIV_1,			/*!< Divider by 1 */
+	SYSCTL_CLKDIV_2,			/*!< Divider by 2 */
+	SYSCTL_CLKDIV_8,			/*!< Divider by 8, not for use with CAN */
+	SYSCTL_CLKDIV_6_CCAN = SYSCTL_CLKDIV_8	/*!< Divider by 6, CAN only */
+} CHIP_SYSCTL_CLKDIV_T;
+
+/**
+ * Peripheral clock selection for LPC175x/6x
+ * This is a list of clocks that can be divided on the 175x/6x
+ */
+typedef enum {
+	SYSCTL_PCLK_WDT,		/*!< Watchdog divider */
+	SYSCTL_PCLK_TIMER0,	/*!< Timer 0 divider */
+	SYSCTL_PCLK_TIMER1,	/*!< Timer 1 divider */
+	SYSCTL_PCLK_UART0,	/*!< UART 0 divider */
+	SYSCTL_PCLK_UART1,	/*!< UART 1 divider */
+	SYSCTL_PCLK_RSVD5,
+	SYSCTL_PCLK_PWM1,		/*!< PWM 1 divider */
+	SYSCTL_PCLK_I2C0,		/*!< I2C 0 divider */
+	SYSCTL_PCLK_SPI,		/*!< SPI divider */
+	SYSCTL_PCLK_RSVD9,
+	SYSCTL_PCLK_SSP1,		/*!< SSP 1 divider */
+	SYSCTL_PCLK_DAC,		/*!< DAC divider */
+	SYSCTL_PCLK_ADC,		/*!< ADC divider */
+	SYSCTL_PCLK_CAN1,		/*!< CAN 1 divider */
+	SYSCTL_PCLK_CAN2,		/*!< CAN 2 divider */
+	SYSCTL_PCLK_ACF,		/*!< ACF divider */
+	SYSCTL_PCLK_QEI,		/*!< QEI divider */
+	SYSCTL_PCLK_GPIOINT,	/*!< GPIOINT divider */
+	SYSCTL_PCLK_PCB,		/*!< PCB divider */
+	SYSCTL_PCLK_I2C1,		/*!< I2C 1 divider */
+	SYSCTL_PCLK_RSVD20,
+	SYSCTL_PCLK_SSP0,		/*!< SSP 0 divider */
+	SYSCTL_PCLK_TIMER2,	/*!< Timer 2 divider */
+	SYSCTL_PCLK_TIMER3,	/*!< Timer 3 divider */
+	SYSCTL_PCLK_UART2,	/*!< UART 2 divider */
+	SYSCTL_PCLK_UART3,	/*!< UART 3 divider */
+	SYSCTL_PCLK_I2C2,		/*!< I2C 2 divider */
+	SYSCTL_PCLK_I2S,		/*!< I2S divider */
+	SYSCTL_PCLK_RSVD28,
+	SYSCTL_PCLK_RIT,		/*!< Repetitive timer divider */
+	SYSCTL_PCLK_SYSCON,	/*!< SYSCON divider */
+	SYSCTL_PCLK_MCPWM		/*!< Motor control PWM divider */
+} CHIP_SYSCTL_PCLK_T;
+
+/**
+ * @brief	Selects a clock divider for a peripheral
+ * @param	clk:		Clock to set divider for
+ * @param	div:	Divider for the clock
+ * @return	Nothing
+ * @note	Selects the divider for a peripheral. A peripheral clock is generated
+ * from the CPU clock divided by its peripheral clock divider.
+ * Only peripheral clocks that are defined in the PCLKSEL registers of
+ * the clock and power controller can used this function.
+ * (LPC175X/6X only)
+ */
+void Chip_Clock_SetPCLKDiv(CHIP_SYSCTL_PCLK_T clk, CHIP_SYSCTL_CLKDIV_T div);
+
+/**
+ * @brief	Gets a clock divider for a peripheral
+ * @param	clk:		Clock to set divider for
+ * @return	The divider for the clock
+ * @note	Selects the divider for a peripheral. A peripheral clock is generated
+ * from the CPU clock divided by its peripheral clock divider.
+ * Only peripheral clocks that are defined in the PCLKSEL registers of
+ * the clock and power controller can used this function.
+ * (LPC175X/6X only)
+ */
+uint32_t Chip_Clock_GetPCLKDiv(CHIP_SYSCTL_PCLK_T clk);
+
+#else
+/**
+ * @brief	Sets a clock divider for all peripherals
+ * @param	div:	Divider for all peripherals, 0 = disable
+ * @return	Nothing
+ * @note	All the peripherals in the device use the same clock divider. The
+ * divider is based on the CPU's clock rate. Use 0 to disable all
+ * peripheral clocks or a divider of 1 to 15. (LPC177X/8X and 407X/8X)
+ */
+STATIC INLINE void Chip_Clock_SetPCLKDiv(uint32_t div)
+{
+	LPC_SYSCTL->PCLKSEL = div;
+}
+
+/**
+ * @brief	Gets the clock divider for all peripherals
+ * @return	Divider for all peripherals, 0 = disabled
+ * @note	All the peripherals in the device use the same clock divider. The
+ * divider is based on the CPU's clock rate. (LPC177X/8X and 407X/8X)
+ */
+STATIC INLINE uint32_t Chip_Clock_GetPCLKDiv(void)
+{
+	return LPC_SYSCTL->PCLKSEL & 0x1F;
+}
+
+#endif
+
+#if !defined(CHIP_LPC175X_6X)
+/**
+ * Clock sources for the SPIFI clock divider
+ */
+typedef enum CHIP_SYSCTL_SPIFICLKSRC {
+	SYSCTL_SPIFICLKSRC_SYSCLK,		/*!< SYSCLK clock as SPIFI divider source */
+	SYSCTL_SPIFICLKSRC_MAINPLL,		/*!< PLL0 clock as SPIFI divider source */
+	SYSCTL_SPIFICLKSRC_USBPLL,		/*!< PLL1 clock as SPIFI divider source */
+	SYSCTL_SPIFICLKSRC_RESERVED
+} CHIP_SYSCTL_SPIFICLKSRC_T;
+
+/**
+ * @brief	Sets the SPIFI clock divider source
+ * @param	src:	SPIFI clock divider source clock
+ * @return	Nothing
+ */
+void Chip_Clock_SetSPIFIClockSource(CHIP_SYSCTL_SPIFICLKSRC_T src);
+
+/**
+ * @brief	Gets the SPIFI clock divider source
+ * @return	SPIFI clock divider source clock
+ */
+STATIC INLINE CHIP_SYSCTL_SPIFICLKSRC_T Chip_Clock_GetSPIFIClockSource(void)
+{
+	return (CHIP_SYSCTL_SPIFICLKSRC_T) ((LPC_SYSCTL->SPIFICLKSEL >> 8) & 0x3);
+}
+
+/**
+ * @brief	Sets the SPIFI clock divider
+ * @param	div:	SPIFI clock divider, 0 to disable
+ * @return	Nothing
+ * @note	Divider values are between 1 and 31
+ */
+void Chip_Clock_SetSPIFIClockDiv(uint32_t div);
+
+/**
+ * @brief	Gets the SPIFI clock divider
+ * @return	SPIFI clock divider
+ * @note	Divider values are between 1 and 31, 0 is disabled
+ */
+STATIC INLINE uint32_t Chip_Clock_GetSPIFIClockDiv(void)
+{
+	return LPC_SYSCTL->SPIFICLKSEL & 0x1F;
+}
+
+/**
+ * @brief	Set the LCD clock prescaler
+ * @param	div:	Divider value, minimum of 1
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_SetLCDClockDiv(uint32_t div)
+{
+	LPC_SYSCTL->LCD_CFG = (div - 1);
+}
+
+/**
+ * @brief	Get the LCD clock prescaler
+ * @return	Current divider value
+ */
+STATIC INLINE uint32_t Chip_Clock_GetLCDClockDiv(void)
+{
+	return (LPC_SYSCTL->LCD_CFG & 0x1F) + 1;
+}
+
+#endif
+
+/**
+ * Clock sources for the CLKOUT pin
+ */
+typedef enum {
+	SYSCTL_CLKOUTSRC_CPU,			/*!< CPU clock as CLKOUT source */
+	SYSCTL_CLKOUTSRC_MAINOSC,		/*!< Main oscillator clock as CLKOUT source */
+	SYSCTL_CLKOUTSRC_IRC,			/*!< IRC oscillator clock as CLKOUT source */
+	SYSCTL_CLKOUTSRC_USB,			/*!< USB clock as CLKOUT source */
+	SYSCTL_CLKOUTSRC_RTC,			/*!< RTC clock as CLKOUT source */
+#if defined(CHIP_LPC175X_6X)
+	SYSCTL_CLKOUTSRC_RESERVED1,
+	SYSCTL_CLKOUTSRC_RESERVED2,
+#else
+	SYSCTL_CLKOUTSRC_SPIFI,		/*!< SPIFI clock as CLKOUT source */
+	SYSCTL_CLKOUTSRC_WATCHDOGOSC,	/*!< Watchdog oscillator as CLKOUT source */
+#endif
+	SYSCTL_CLKOUTSRC_RESERVED3
+} CHIP_SYSCTL_CLKOUTSRC_T;
+
+/**
+ * @brief	Selects a source clock and divider rate for the CLKOUT pin
+ * @param	src:	source selected
+ * @param	div:	Divider for the clock source on CLKOUT, 1 to 16
+ * @return	Nothing
+ * @note	This function will disable the CLKOUT signal if its enabled. Use
+ * Chip_Clock_EnableCLKOUT to re-enable CLKOUT after a call to this
+ * function.
+ */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
+
+/**
+ * @brief	Enables the clock on the CLKOUT pin
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_EnableCLKOUT(void)
+{
+	LPC_SYSCTL->CLKOUTCFG |= (1 << 8);
+}
+
+/**
+ * @brief	Disables the clock on the CLKOUT pin
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_DisableCLKOUT(void)
+{
+	LPC_SYSCTL->CLKOUTCFG &= ~(1 << 8);
+}
+
+/**
+ * @brief	Returns the CLKOUT activity indication status
+ * @return	true if CLKOUT is enabled, false if disabled and stopped
+ * @note	CLKOUT activity indication. Reads as true when CLKOUT is
+ * enabled. Read as false when CLKOUT has been disabled via
+ * the CLKOUT_EN bit and the clock has completed being stopped.
+ */
+STATIC INLINE bool Chip_Clock_IsCLKOUTEnabled(void)
+{
+	return (bool) ((LPC_SYSCTL->CLKOUTCFG & (1 << 9)) != 0);
+}
+
+/**
+ * @brief	Returns the main oscillator clock rate
+ * @return	main oscillator clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
+{
+	return OscRateIn;
+}
+
+/**
+ * @brief	Returns the internal oscillator (IRC) clock rate
+ * @return	internal oscillator (IRC) clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
+{
+	return SYSCTL_IRC_FREQ;
+}
+
+/**
+ * @brief	Returns the RTC oscillator clock rate
+ * @return	RTC oscillator clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
+{
+	return RTCOscRateIn;
+}
+
+/**
+ * @brief	Returns the current SYSCLK clock rate
+ * @return	SYSCLK clock rate
+ * @note	SYSCLK is used for sourcing PLL0, SPIFI FLASH, the USB clock
+ * divider, and the CPU clock divider.
+ */
+uint32_t Chip_Clock_GetSYSCLKRate(void);
+
+/**
+ * @brief	Return Main PLL (PLL0) input clock rate
+ * @return	PLL0 input clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetMainPLLInClockRate(void)
+{
+	return Chip_Clock_GetSYSCLKRate();
+}
+
+/**
+ * @brief	Return PLL0 (Main PLL) output clock rate
+ * @return	PLL0 output clock rate
+ */
+uint32_t Chip_Clock_GetMainPLLOutClockRate(void);
+
+/**
+ * @brief	Return USB PLL input clock rate
+ * @return	USB PLL input clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
+{
+	return Chip_Clock_GetMainOscRate();
+}
+
+/**
+ * @brief	Return USB PLL output clock rate
+ * @return	USB PLL output clock rate
+ */
+uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
+
+/**
+ * @brief	Return main clock rate
+ * @return	main clock rate
+ */
+uint32_t Chip_Clock_GetMainClockRate(void);
+
+/**
+ * @brief	Return system clock rate
+ * @return	system clock rate
+ */
+uint32_t Chip_Clock_GetSystemClockRate(void);
+
+/**
+ * @brief	Gets the USB clock (USB_CLK) rate
+ * @return	USB clock (USB_CLK) clock rate
+ * @note	The clock source and divider are used to generate the USB clock rate.
+ */
+uint32_t Chip_Clock_GetUSBClockRate(void);
+
+#if !defined(CHIP_LPC175X_6X)
+
+/**
+ * @brief	Returns the SPIFI clock rate
+ * @return	SPIFI clock clock rate
+ */
+uint32_t Chip_Clock_GetSPIFIClockRate(void);
+
+/**
+ * @brief	Returns clock rate for EMC
+ * @return	Clock rate for the peripheral
+ */
+STATIC INLINE uint32_t Chip_Clock_GetEMCClockRate(void)
+{
+	return Chip_Clock_GetSystemClockRate() / Chip_Clock_GetEMCClockDiv();
+}
+
+#endif
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+/**
+ * @brief	Returns clock rate for a peripheral (from peripheral clock)
+ * @param	clk:	Clock to get rate of
+ * @return	Clock rate for the peripheral
+ * @note	This covers most common peripheral clocks, but not every clock
+ * in the system. LPC177x/8x and LPC407x/8x devices use the same
+ * clock for all periphreals, while the LPC175x/6x have unique
+ * dividers (except to RTC ) that may alter the peripheral clock rate.
+ */
+uint32_t Chip_Clock_GetPeripheralClockRate(void);
+
+#else
+/**
+ * @brief	Returns clock rate for a peripheral (from peripheral clock)
+ * @param	clk:	Clock to get rate of
+ * @return	Clock rate for the peripheral
+ * @note	This covers most common peripheral clocks, but not every clock
+ * in the system. LPC177x/8x and LPC407x/8x devices use the same
+ * clock for all periphreals, while the LPC175x/6x have unique
+ * dividers (except to RTC ) that may alter the peripheral clock rate.
+ */
+uint32_t Chip_Clock_GetPeripheralClockRate(CHIP_SYSCTL_PCLK_T clk);
+
+/**
+ * @brief	Returns clock rate for RTC
+ * @return	Clock rate for the peripheral
+ */
+STATIC INLINE uint32_t Chip_Clock_GetRTCClockRate(void)
+{
+	return Chip_Clock_GetSystemClockRate() / 8;
+}
+
+#endif
+
+/**
+ * @brief	Returns clock rate for Ethernet
+ * @return	Clock rate for the peripheral
+ */
+STATIC INLINE uint32_t Chip_Clock_GetENETClockRate(void)
+{
+	return Chip_Clock_GetSystemClockRate();
+}
+
+/**
+ * @brief	Returns clock rate for GPDMA
+ * @return	Clock rate for the peripheral
+ */
+STATIC INLINE uint32_t Chip_Clock_GetGPDMAClockRate(void)
+{
+	return Chip_Clock_GetSystemClockRate();
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLOCK_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/cmp_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/cmp_17xx_40xx.h
new file mode 100644
index 000000000..91adff2d3
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/cmp_17xx_40xx.h
@@ -0,0 +1,408 @@
+/*
+ * @brief LPC40xx Comparator driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMP_17XX_40XX_H_
+#define __CMP_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMP_17XX_40XX CHIP: LPC40xx Comparator driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC40XX)
+
+/** The number of embeded comparators supported */
+#define CMP_NUM         2
+
+/**
+ * @brief Comparator (CMP) register block structure
+ */
+typedef struct {										/*!< Comparator structure                                   */
+	__IO uint32_t  CMP_CTRL;							/*!< Comparator block control register                      */
+	__IO uint32_t  CMP_CTRLx[CMP_NUM];					/*!< Specific comparator control register                          */
+} LPC_CMP_T;
+
+/**
+ * @brief Comparator control definition
+ */
+typedef enum {
+	CMP_ENCTRL_DISABLE,			/*!< Disable */
+	CMP_ENCTRL_DIS_IN_DS_PWD,	/*!< Disable in deep sleep mode and power down mode*/
+	CMP_ENCTRL_DIS_IN_PWD,		/*!< Disable in power down mode*/
+	CMP_ENCTRL_ENABLE,			/*!< Enable/Power-up*/
+} CMP_ENCTRL_T;
+
+/*!< Comparator control register Bitmask */
+#define CMP_CTRL_BITMASK     (0xF30F)
+/*!< The comparator current source control bitmask*/
+#define CMP_CTRL_PD_IREF_BITMASK            (0x03)
+/*!< Control the comparator current source (n is CMP_ENCTRL_T value)*/
+#define CMP_CTRL_PD_IREF(n)                 ((((uint32_t) (n)) & 0x03))
+/*!< The comparator bandgap reference control bitmask*/
+#define CMP_CTRL_PD_VBG_BITMASK             (((uint32_t) 0x03) << 2)
+/*!< Control the comparator  bandgap reference (n is CMP_ENCTRL_T value)*/
+#define CMP_CTRL_PD_VBG(n)                  ((((uint32_t) (n)) & 0x03) << 2)
+/*!< The CMP_ROSC ouput control bitmask */
+#define CMP_CTRL_ROSC_BITMASK               ((uint32_t) 0x300)
+/*!< The CMP_ROSC output is set by CMP1, reset by CMP0 */
+#define CMP_CTRL_ROSCCTL_CMP1               (0x00)
+/*!< The CMP_ROSC output is set by CMP0, reset by CMP1 */
+#define CMP_CTRL_ROSCCTL_CMP0               (((uint32_t) 0x01) << 8)
+/*!< The CMP_ROSC output is reset by the internal chip reset */
+#define CMP_CTRL_EXT_RESET_INTERNAL         (0x00)
+/*!< The CMP_ROSC output is reset by the CMP_RESET input */
+#define CMP_CTRL_EXT_RESET_CMPRESET         (((uint32_t) 0x01) << 9)
+/*!< Timer Capture input control bitmask */
+#define CMP_CTRL_TIMERCAPTURE_BITMASK       ((uint32_t) 0xF000)
+/*!< Selects the comparator 0 level output as the input for Timer0 capture input 2 */
+#define CMP_CTRL_T0CAP2_0LEVEL              (0x00)
+/*!< Selects the comparator 1 level output as the input for Timer0 capture input 2 */
+#define CMP_CTRL_T0CAP2_1LEVEL              (((uint32_t) 0x01) << 12)
+/*!< Selects the comparator 0 edge output as the input for Timer0 capture input 3 */
+#define CMP_CTRL_T0CAP3_0EDGE               (0x00)
+/*!< Selects the comparator 1 edge output as the input for Timer0 capture input 3 */
+#define CMP_CTRL_T0CAP3_1EDGE               (((uint32_t) 0x01) << 13)
+/*!< Selects the comparator 1 edge output as the input for Timer1 capture input 2 */
+#define CMP_CTRL_T1CAP2_1EDGE               (0x00)
+/*!< Selects the comparator 0 level output as the input for Timer1 capture input 2 */
+#define CMP_CTRL_T1CAP2_0LEVEL              (((uint32_t) 0x01) << 14)
+/*!< Selects the comparator 1 level output as the input for Timer1 capture input 3 */
+#define CMP_CTRL_T1CAP3_1LEVEL              (0x00)
+/*!< Selects the comparator 0 edge output as the input for Timer1 capture input 3 */
+#define CMP_CTRL_T1CAP3_0EDGE               (((uint32_t) 0x01) << 15)
+
+/*!< The comparator x control register Bitmask */
+#define CMP_CTRLx_BITMASK           ((uint32_t) 0x1F7FF77F)
+/*!< The comparator x enable bitmask*/
+#define CMP_CTRLx_EN_BITMASK            (0x03)
+/*!< Control the comparator x (n is CMP_ENCTRL_T value)*/
+#define CMP_CTRLx_EN(n)                 ((((uint32_t) (n)) & 0x03))
+/*!< Enable the output of compartor x */
+#define CMP_CTRLx_OE                    (((uint32_t) 0x01) << 2)
+/*!< The status of compartor x, reflects the comparator x output*/
+#define CMP_CTRLx_STAT                  (((uint32_t) 0x01) << 3)
+/*!< Comparator VM input control bitmask */
+#define CMP_CTRLx_VM_BITMASK            (((uint32_t) 0x07) << 4)
+/*!< Select the VM input*/
+#define CMP_CTRLx_VM(n)                 ((((uint32_t) (n)) & 0x07) << 4)
+/*!< Comparator VP input control bitmask */
+#define CMP_CTRLx_VP_BITMASK            (((uint32_t) 0x07) << 8)
+/*!< Select the VP input */
+#define CMP_CTRLx_VP(n)                 ((((uint32_t) (n)) & 0x07) << 8)
+/*!< Synchronize the Comparator x output with the internal bus clock for outpur to other peripherals */
+#define CMP_CTRLx_SYNC                  (((uint32_t) 0x01) << 12)
+/*!< Comparator Hysteresis control bitmask */
+#define CMP_CTRLx_HYS_BITMASK           (((uint32_t) 0x03) << 13)
+/*!< Determine the difference required between  the comparator inputs before the comparator output switch*/
+#define CMP_CTRLx_HYS(n)                ((((uint32_t) (n)) & 0x03) << 13)
+/*!< Interrupt control bitmask */
+#define CMP_CTRLx_INTCTRL_BITMASK       ((uint32_t) 0x78000)
+/*!< Comparator output is used as-is for generating interrupts. */
+#define CMP_CTRLx_INTPOL_NORMAL         (0x00)
+/*!< Comparator output is used inverted for generating interrupts. */
+#define CMP_CTRLx_INTPOL_INV            (((uint32_t) 0x01) << 15)
+/*!< Comparator x interrupt is edge triggered. */
+#define CMP_CTRLx_INTTYPE_EDGE          (0x00)
+/*!< Comparator x interrupt is level triggered.*/
+#define CMP_CTRLx_INTTYPE_LEVEL         (((uint32_t) 0x01) << 16)
+/*!< Comparator x interrupt edge control bitmask */
+#define CMP_CTRLx_INTEDGE_BITMASK       (((uint32_t) 0x03) << 17)
+/*!< Select edge on which triggered interrupt is active*/
+#define CMP_CTRLx_INTEDGE(n)            ((((uint32_t) (n)) & 0x03) << 17)
+/*!< Comparator interrupt flag */
+#define CMP_CTRLx_INTFLAG               (((uint32_t) 0x01) << 19)
+/*!< The VLAD Enable bitmask*/
+#define CMP_CTRLx_VLADEN_BITMASK        (((uint32_t) 0x03) << 20)
+/*!< Control the comparator x  (n is CMP_ENCTRL_T value)*/
+#define CMP_CTRLx_VLADEN(n)             ((((uint32_t) (n)) & 0x03) << 20)
+/*!< Select VREF_CMP pin as voltage reference for comparator voltage ladder */
+#define CMP_CTRLx_VLADREF_VREFCMP       (0x00)
+/*!< Select VDDA pin as voltage reference for comparator voltage ladder */
+#define CMP_CTRLx_VLADREF_VDDA          (((uint32_t) 0x01) << 22)
+/*!< Volatge ladder value bitmask */
+#define CMP_CTRLx_VSEL_BITMASK          ((uint32_t) ((0x1F) << 24))
+/*!< Voltage ladder value for Comparator */
+#define CMP_CTRLx_VSEL(n)               ((((uint32_t) (n)) & 0x1F) << 24)
+
+/**
+ * @brief Comparator VM/VP input definitions
+ */
+typedef enum {
+	CMP_INPUT_VREF_DIV,			/*!< Vref divider.*/
+	CMP_INPUT_CMPx_IN0,			/*!< Use the input 0 of the comparator*/
+	CMP_INPUT_CMPx_IN1,			/*!< Use the input 1 of the comparator*/
+	CMP_INPUT_CMPx_IN2,			/*!< Use the input 2 of the comparator*/
+	CMP_INPUT_CMPx_IN3,			/*!< Use the input 3 of the comparator*/
+	CMP_INPUT_CMP_OTHER_IN0,	/*!< Use the input 0 of the other comparator.*/
+	CMP_INPUT_INTERNAL_09VBG,	/*!< internal 0.9 V band gap reference.*/
+} CMP_INPUT_T;
+
+/**
+ * @brief Comparator hysteresis selection definitions
+ */
+typedef enum {
+	CMP_HYS_NONE = CMP_CTRLx_HYS(0),		/*!<No hysteresis (the output will switch as the voltages cross) */
+	CMP_HYS_5MV  = CMP_CTRLx_HYS(1),		/*!< 5mV hysteresis */
+	CMP_HYS_10MV = CMP_CTRLx_HYS(2),		/*!< 10mV hysteresis */
+	CMP_HYS_15MV = CMP_CTRLx_HYS(3),		/*!< 15mV hysteresis */
+} CMP_HYS_T;
+
+/**
+ * @brief Comparator interrupt edge selection definitions
+ */
+typedef enum {
+	CMP_INTEDGE_FALLING = CMP_CTRLx_INTEDGE(0),	/*!< Interrupt is active on falling edge */
+	CMP_INTEDGE_RISING  = CMP_CTRLx_INTEDGE(1),	/*!< Interrupt is active on rising edge */
+	CMP_INTEDGE_BOTH    = CMP_CTRLx_INTEDGE(2),	/*!< Interrupt is active on falling and rising edges */
+} CMP_INTEDGE_T;
+
+/**
+ * @brief	Initializes the CMP
+ * @return	Nothing
+ */
+void Chip_CMP_Init(void);
+
+/**
+ * @brief	Deinitializes the CMP
+ * @return	Nothing
+ */
+void Chip_CMP_DeInit(void);
+
+/**
+ * @brief	Enables comparator current source
+ * @param	en		: Enable mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_EnableCurrentSrc(CMP_ENCTRL_T en)
+{
+	LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_PD_IREF_BITMASK)) | CMP_CTRL_PD_IREF(en);
+}
+
+/**
+ * @brief	Enables comparator bandgap reference
+ * @param	en		: Enable mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_EnableBandGap(CMP_ENCTRL_T en)
+{
+	LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_PD_VBG_BITMASK)) | CMP_CTRL_PD_VBG(en);
+}
+
+/**
+ * @brief	Control CMP_ROSC
+ * @param	flag		: Or-ed bit value of CMP_CTRL_ROSCCTL_* and CMP_CTRL_EXT_RESET_*
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_ControlROSC(uint32_t flag)
+{
+	LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_ROSC_BITMASK)) | flag;
+}
+
+/**
+ * @brief	Control CMP_ROSC
+ * @param	flag		: Or-ed bit value of CMP_CTRL_T*CAP*
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_SetTimerCapInput(uint32_t flag)
+{
+	LPC_CMP->CMP_CTRL = (LPC_CMP->CMP_CTRL & (~CMP_CTRL_TIMERCAPTURE_BITMASK)) | flag;
+}
+
+/**
+ * @brief	Sets up voltage ladder
+ * @param	id				: Comparator ID
+ * @param	ladSel			: Voltage ladder value (0~31).
+ * @param	flag				:0(CMP_VREF used)/CMP_CTRLx_VLADREF_VDDA (VDDA used)
+ * @return	Nothing
+ * @note		VREF divider 0 = ladSel*VRef0/31
+ */
+STATIC INLINE void Chip_CMP_SetupVoltLadder(uint8_t id,
+											uint16_t ladSel, uint32_t flag)
+{
+	LPC_CMP->CMP_CTRLx[id] =
+		(LPC_CMP->CMP_CTRLx[id] & (~(CMP_CTRLx_VSEL_BITMASK | CMP_CTRLx_VLADREF_VDDA))) | CMP_CTRLx_VSEL(
+			ladSel) | flag;
+}
+
+/**
+ * @brief	Enables voltage ladder
+ * @param	id		: Comparator ID
+ * @param	en		: enable option
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_EnableVoltLadder(uint8_t id, CMP_ENCTRL_T en)
+{
+	LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_VLADEN_BITMASK)) | CMP_CTRLx_VLADEN(en);
+}
+
+/**
+ * @brief	Selects positive voltage input
+ * @param	id		: Comparator ID
+ * @param	input	: Selected input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_SetPosVoltRef(uint8_t id, CMP_INPUT_T input)
+{
+	LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_VP_BITMASK)) | CMP_CTRLx_VP(input);
+}
+
+/**
+ * @brief	Selects negative voltage input
+ * @param	id		: Comparator ID
+ * @param	input	: Selected input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_SetNegVoltRef(uint8_t id, CMP_INPUT_T input)
+{
+	LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_VM_BITMASK)) | CMP_CTRLx_VM(input);
+}
+
+/**
+ * @brief	Selects hysteresis level
+ * @param	id		: Comparator ID
+ * @param	hys		: Selected Hysteresis level
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_SetHysteresis(uint8_t id, CMP_HYS_T hys)
+{
+	LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_HYS_BITMASK)) | hys;
+}
+
+/**
+ * @brief	Enables specified comparator
+ * @param	id		: Comparator ID
+ * @param	en		: Enable mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_Enable(uint8_t id, CMP_ENCTRL_T en)
+{
+	LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_EN_BITMASK)) | CMP_CTRLx_EN(en);
+}
+
+/**
+ * @brief	Returns the current comparator status
+ * @param	id	: Comparator Id (0/1)
+ * @return	SET/RESET
+ */
+STATIC INLINE FlagStatus Chip_CMP_GetCmpStatus(uint8_t id)
+{
+	return (LPC_CMP->CMP_CTRLx[id] & CMP_CTRLx_STAT) ? SET : RESET;
+}
+
+/**
+ * @brief	Enable comparator output
+ * @param	id		: Comparator ID
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_EnableOuput(uint8_t id)
+{
+	LPC_CMP->CMP_CTRLx[id] |= CMP_CTRLx_OE;
+}
+
+/**
+ * @brief		Disable comparator output
+ * @param	id		: Comparator ID
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_DisableOutput(uint8_t id)
+{
+	LPC_CMP->CMP_CTRLx[id] &= ~CMP_CTRLx_OE;
+}
+
+/**
+ * @brief	Synchronizes Comparator output to bus clock
+ * @param	id		: Comparator ID
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_EnableSyncCmpOut(uint8_t id)
+{
+	LPC_CMP->CMP_CTRLx[id] |= CMP_CTRLx_SYNC;
+}
+
+/**
+ * @brief	Sets comparator output to be used directly (no sync)
+ * @param	id		: Comparator ID
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_DisableSyncCmpOut(uint8_t id)
+{
+	LPC_CMP->CMP_CTRLx[id] &= ~CMP_CTRLx_SYNC;
+}
+
+/**
+ * @brief	Sets up comparator interrupt
+ * @param	id		: Comparator ID
+ * @param	intFlag	: Or-ed value of CMP_CTRLx_INTTYPE_*, CMP_CTRLx_INTPOL_*
+ * @param	edgeSel	: the edge on which interrupt occurs.
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_ConfigInt(uint8_t id,
+									  uint32_t intFlag,
+									  CMP_INTEDGE_T edgeSel)
+{
+	LPC_CMP->CMP_CTRLx[id] = (LPC_CMP->CMP_CTRLx[id] & (~CMP_CTRLx_INTCTRL_BITMASK)) | intFlag | edgeSel;
+}
+
+/**
+ * @brief	Get the CMP interrupt status
+ * @param	id		: Comparator ID
+ * @return	SET/RESET
+ */
+STATIC INLINE FlagStatus Chip_CMP_GetIntStatus(uint8_t id)
+{
+	return (LPC_CMP->CMP_CTRLx[id] & CMP_CTRLx_INTFLAG) ? SET : RESET;
+}
+
+/**
+ * @brief	Clears the CMP interrupt
+ * @param	id		: Comparator ID
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CMP_ClearIntStatus(uint8_t id)
+{
+	LPC_CMP->CMP_CTRLx[id] |= CMP_CTRLx_INTFLAG;
+}
+
+#endif /* defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMP_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h b/hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h
new file mode 100644
index 000000000..7f55fbfc3
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h
@@ -0,0 +1,66 @@
+/*
+ * @brief LPC17xx/40xx selective CMSIS inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_H_
+#define __CMSIS_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Select correct CMSIS include file based on CHIP_* definition */
+#if defined(CHIP_LPC175X_6X)
+#include "cmsis_175x_6x.h"
+typedef LPC175X_6X_IRQn_Type IRQn_Type;
+#include "core_cm3.h"						/*!< Cortex-M3 processor and core peripherals */
+
+#elif defined(CHIP_LPC177X_8X)
+#include "cmsis_177x_8x.h"
+typedef LPC177X_8X_IRQn_Type IRQn_Type;
+#include "core_cm3.h"						/*!< Cortex-M3 processor and core peripherals */
+
+#elif defined(CHIP_LPC40XX)
+#include "cmsis_40xx.h"
+typedef LPC40XX_IRQn_Type IRQn_Type;
+#include "core_cm4.h"						/*!< Cortex-M4 processor and core peripherals */
+
+#else
+#error "No CHIP_* definition is defined"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h
new file mode 100644
index 000000000..8cbb0ead2
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h
@@ -0,0 +1,171 @@
+/*
+ * @brief Basic CMSIS include file for LPC40xx
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_40XX_H_
+#define __CMSIS_40XX_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMSIS_40XX CHIP: LPC40xx CMSIS include file
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+  #pragma diag_suppress 2525
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+//  #pragma push // FIXME not usable for IAR
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+#if !defined(CHIP_LPC40XX)
+#error Incorrect or missing device variant (CHIP_LPC40XX)
+#endif
+
+/** @defgroup CMSIS_40XX_IRQ CHIP_40XX: LPC40xx peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/* -------------------------  Cortex-M4 Processor Exceptions Numbers  ----------------------------- */
+	Reset_IRQn                    = -15,		/*!< 1 Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn           = -14,		/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                = -13,		/*!< 3 Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn         = -12,		/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                 = -11,		/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn               = -10,		/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition  */
+	SVCall_IRQn                   = -5,			/*!< 11 System Service Call via SVC instruction   */
+	DebugMonitor_IRQn             = -4,			/*!< 12 CDebug Monitor   */
+	PendSV_IRQn                   = -2,			/*!< 14 Pendable request for system service */
+	SysTick_IRQn                  = -1,			/*!< 15 System Tick Interrupt */
+
+	/* ---------------------------  LPC40xx Specific Interrupt Numbers  ------------------------------- */
+	WDT_IRQn                      = 0,			/*!< Watchdog Timer Interrupt                         */
+	TIMER0_IRQn                   = 1,			/*!< Timer0 Interrupt                                 */
+	TIMER1_IRQn                   = 2,			/*!< Timer1 Interrupt                                 */
+	TIMER2_IRQn                   = 3,			/*!< Timer2 Interrupt                                 */
+	TIMER3_IRQn                   = 4,			/*!< Timer3 Interrupt                                 */
+	UART0_IRQn                    = 5,			/*!< UART0 Interrupt                                  */
+	UART_IRQn                     = UART0_IRQn,	/*!< Alias for UART0 Interrupt                        */
+	UART1_IRQn                    = 6,			/*!< UART1 Interrupt                                  */
+	UART2_IRQn                    = 7,			/*!< UART2 Interrupt                                  */
+	UART3_IRQn                    = 8,			/*!< UART3 Interrupt                                  */
+	PWM1_IRQn                     = 9,			/*!< PWM1 Interrupt                                   */
+	I2C0_IRQn                     = 10,			/*!< I2C0 Interrupt                                   */
+	I2C_IRQn                      = I2C0_IRQn,	/*!< Alias for I2C0 Interrupt                         */
+	I2C1_IRQn                     = 11,			/*!< I2C1 Interrupt                                   */
+	I2C2_IRQn                     = 12,			/*!< I2C2 Interrupt                                   */
+	Reserved0_IRQn                = 13,			/*!< Reserved                                         */
+	SSP0_IRQn                     = 14,			/*!< SSP0 Interrupt                                   */
+	SSP_IRQn                      = SSP0_IRQn,	/*!< Alias for SSP0 Interrupt                         */
+	SSP1_IRQn                     = 15,			/*!< SSP1 Interrupt                                   */
+	PLL0_IRQn                     = 16,			/*!< PLL0 Lock (Main PLL) Interrupt                   */
+	RTC_IRQn                      = 17,			/*!< Real Time Clock Interrupt                        */
+	EINT0_IRQn                    = 18,			/*!< External Interrupt 0 Interrupt                   */
+	EINT1_IRQn                    = 19,			/*!< External Interrupt 1 Interrupt                   */
+	EINT2_IRQn                    = 20,			/*!< External Interrupt 2 Interrupt                   */
+	EINT3_IRQn                    = 21,			/*!< External Interrupt 3 Interrupt                   */
+	ADC_IRQn                      = 22,			/*!< A/D Converter Interrupt                          */
+	BOD_IRQn                      = 23,			/*!< Brown-Out Detect Interrupt                       */
+	USB_IRQn                      = 24,			/*!< USB Interrupt                                    */
+	CAN_IRQn                      = 25,			/*!< CAN Interrupt                                    */
+	DMA_IRQn                      = 26,			/*!< General Purpose DMA Interrupt                    */
+	I2S_IRQn                      = 27,			/*!< I2S Interrupt                                    */
+	ETHERNET_IRQn                 = 28,			/*!< Ethernet Interrupt                               */
+	SDC_IRQn                      = 29,			/*!< SD/MMC card I/F Interrupt                        */
+	MCPWM_IRQn                    = 30,			/*!< Motor Control PWM Interrupt                      */
+	QEI_IRQn                      = 31,			/*!< Quadrature Encoder Interface Interrupt           */
+	PLL1_IRQn                     = 32,			/*!< PLL1 Lock (USB PLL) Interrupt                    */
+	USBActivity_IRQn              = 33,			/*!< USB Activity interrupt                           */
+	CANActivity_IRQn              = 34,			/*!< CAN Activity interrupt                           */
+	UART4_IRQn                    = 35,			/*!< UART4 Interrupt                                  */
+	SSP2_IRQn                     = 36,			/*!< SSP2 Interrupt                                   */
+	LCD_IRQn                      = 37,			/*!< LCD Interrupt                                    */
+	GPIO_IRQn                     = 38,			/*!< GPIO Interrupt                                   */
+	PWM0_IRQn                     = 39,			/*!< PWM0 Interrupt                                   */
+	EEPROM_IRQn                   = 40,			/*!< EEPROM Interrupt                               */
+} LPC40XX_IRQn_Type;
+
+/**
+ * @}
+ */
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/** @defgroup CMSIS_40XX_COMMON CHIP: LPC40xx Cortex CMSIS definitions
+ * @{
+ */
+
+#define __CM4_REV              0x0001		/*!< Cortex-M4 Core Revision               */
+#define __MPU_PRESENT             1			/*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          5			/*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             1			/*!< FPU present or not                    */
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h
new file mode 100644
index 000000000..d65016c71
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h
new file mode 100644
index 000000000..83db95b5f
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h
new file mode 100644
index 000000000..0a18fafc3
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h
new file mode 100644
index 000000000..d213f0eed
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/crc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/crc_17xx_40xx.h
new file mode 100644
index 000000000..b182cdca0
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/crc_17xx_40xx.h
@@ -0,0 +1,236 @@
+/*
+ * @brief LPC17xx/40xx Cyclic Redundancy Check (CRC) Engine driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CRC_17XX_40XX_H_
+#define __CRC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CRC_17XX_40XX CHIP: LPC17xx/40xx Cyclic Redundancy Check Engine driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/**
+ * @brief CRC register block structure
+ */
+typedef struct {					/*!< CRC Structure */
+	__IO    uint32_t    MODE;		/*!< CRC Mode Register */
+	__IO    uint32_t    SEED;		/*!< CRC SEED Register */
+	union {
+		__I     uint32_t    SUM;	/*!< CRC Checksum Register. */
+		__O     uint32_t    WRDATA32;	/*!< CRC Data Register: write size 32-bit*/
+		__O     uint16_t    WRDATA16;	/*!< CRC Data Register: write size 16-bit*/
+		__O     uint8_t     WRDATA8;	/*!< CRC Data Register: write size 8-bit*/
+	};
+
+} LPC_CRC_T;
+
+/*
+ * @brief CRC MODE register description
+ */
+#define CRC_MODE_POLY_BITMASK   ((0x03))	/** CRC polynomial Bit mask */
+#define CRC_MODE_POLY_CCITT     (0x00)		/** Select CRC-CCITT polynomial */
+#define CRC_MODE_POLY_CRC16     (0x01)		/** Select CRC-16 polynomial */
+#define CRC_MODE_POLY_CRC32     (0x02)		/** Select CRC-32 polynomial */
+#define CRC_MODE_WRDATA_BITMASK (0x03 << 2)	/** CRC WR_Data Config Bit mask */
+#define CRC_MODE_WRDATA_BIT_RVS (1 << 2)	/** Select Bit order reverse for WR_DATA (per byte) */
+#define CRC_MODE_WRDATA_CMPL    (1 << 3)	/** Select One's complement for WR_DATA */
+#define CRC_MODE_SUM_BITMASK    (0x03 << 4)	/** CRC Sum Config Bit mask */
+#define CRC_MODE_SUM_BIT_RVS    (1 << 4)	/** Select Bit order reverse for CRC_SUM */
+#define CRC_MODE_SUM_CMPL       (1 << 5)	/** Select One's complement for CRC_SUM */
+
+#define MODE_CFG_CCITT          (0x00)	/** Pre-defined mode word for default CCITT setup */
+#define MODE_CFG_CRC16          (0x15)	/** Pre-defined mode word for default CRC16 setup */
+#define MODE_CFG_CRC32          (0x36)	/** Pre-defined mode word for default CRC32 setup */
+
+#define CRC_SEED_CCITT          (0x0000FFFF)/** Initial seed value for CCITT mode */
+#define CRC_SEED_CRC16          (0x00000000)/** Initial seed value for CRC16 mode */
+#define CRC_SEED_CRC32          (0xFFFFFFFF)/** Initial seed value for CRC32 mode */
+
+/**
+ * @brief CRC polynomial
+ */
+typedef enum IP_CRC_001_POLY {
+	CRC_POLY_CCITT = CRC_MODE_POLY_CCITT,	/**< CRC-CCIT polynomial */
+	CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16,	/**< CRC-16 polynomial */
+	CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32,	/**< CRC-32 polynomial */
+	CRC_POLY_LAST,
+} CRC_POLY_T;
+
+/**
+ * @brief	Initializes the CRC Engine
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Init(void) {}
+
+/**
+ * @brief	Deinitializes the CRC Engine
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Deinit(void) {}
+
+/**
+ * @brief	Set the polynomial used for the CRC calculation
+ * @param	poly	: The enumerated polynomial to be used
+ * @param	flags	: An Or'ed value of flags that setup the mode
+ * @return	Nothing
+ * @note	Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS,
+ * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL.
+ */
+STATIC INLINE void Chip_CRC_SetPoly(CRC_POLY_T poly, uint32_t flags)
+{
+	LPC_CRC->MODE = (uint32_t) poly | flags;
+}
+
+/**
+ * @brief	Engage the CRC engine with defaults based on the polynomial to be used
+ * @param	poly	: The enumerated polynomial to be used
+ * @return	Nothing
+ */
+void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly);
+
+/**
+ * @brief	Set the CRC Mode bits
+ * @param	mode	: Mode value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_SetMode(uint32_t mode)
+{
+	LPC_CRC->MODE = mode;
+}
+
+/**
+ * @brief	Get the CRC Mode bits
+ * @return	The current value of the CRC Mode bits
+ */
+STATIC INLINE uint32_t Chip_CRC_GetMode(void)
+{
+	return LPC_CRC->MODE;
+}
+
+/**
+ * @brief	Set the seed bits used by the CRC_SUM register
+ * @param	seed	: Seed value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_SetSeed(uint32_t seed)
+{
+	LPC_CRC->SEED = seed;
+}
+
+/**
+ * @brief	Get the CRC seed value
+ * @return	Seed value
+ */
+STATIC INLINE uint32_t Chip_CRC_GetSeed(void)
+{
+	return LPC_CRC->SEED;
+}
+
+/**
+ * @brief	Convenience function for writing 8-bit data to the CRC engine
+ * @param	data	: 8-bit data to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Write8(uint8_t data)
+{
+	LPC_CRC->WRDATA8 = data;
+}
+
+/**
+ * @brief	Convenience function for writing 16-bit data to the CRC engine
+ * @param	data	: 16-bit data to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Write16(uint16_t data)
+{
+	LPC_CRC->WRDATA16 = data;
+}
+
+/**
+ * @brief	Convenience function for writing 32-bit data to the CRC engine
+ * @param	data	: 32-bit data to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Write32(uint32_t data)
+{
+	LPC_CRC->WRDATA32 = data;
+}
+
+/**
+ * @brief	Gets the CRC Sum based on the Mode and Seed as previously configured
+ * @return	CRC Checksum value
+ */
+STATIC INLINE uint32_t Chip_CRC_Sum(void)
+{
+	return LPC_CRC->SUM;
+}
+
+/**
+ * @brief	Convenience function for computing a standard CCITT checksum from an 8-bit data block
+ * @param	data	: Pointer to the block of 8-bit data
+ * @param   bytes	: The number of bytes pointed to by data
+ * @return	Check sum value
+ */
+uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes);
+
+/**
+ * @brief	Convenience function for computing a standard CRC16 checksum from 16-bit data block
+ * @param	data	: Pointer to the block of 16-bit data
+ * @param   hwords	: The number of 16 byte entries pointed to by data
+ * @return	Check sum value
+ */
+uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords);
+
+/**
+ * @brief	Convenience function for computing a standard CRC32 checksum from 32-bit data block
+ * @param	data	: Pointer to the block of 32-bit data
+ * @param   words	: The number of 32-bit entries pointed to by data
+ * @return	Check sum value
+ */
+uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words);
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CRC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/dac_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/dac_17xx_40xx.h
new file mode 100644
index 000000000..1376d754b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/dac_17xx_40xx.h
@@ -0,0 +1,166 @@
+/*
+ * @brief LPC17xx/40xx D/A conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __DAC_17XX_40XX_H_
+#define __DAC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup DAC_17XX_40XX CHIP: LPC17xx/40xx D/A conversion driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief DAC register block structure
+ */
+typedef struct {			/*!< DAC Structure          */
+	__IO uint32_t  CR;		/*!< DAC register. Holds the conversion data. */
+	__IO uint32_t  CTRL;	/*!< DAC control register.  */
+	__IO uint32_t  CNTVAL;	/*!< DAC counter value register. */
+} LPC_DAC_T;
+
+/** After the selected settling time after this field is written with a
+   new VALUE, the voltage on the AOUT pin (with respect to VSSA)
+   is VALUE/1024 ? VREF */
+#define DAC_VALUE(n)        ((uint32_t) ((n & 0x3FF) << 6))
+/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
+ * and the maximum current is 700 microAmpere
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond
+ * and the maximum current is 350 microAmpere
+ */
+#define DAC_BIAS_EN         ((uint32_t) (1 << 16))
+/** Value to reload interrupt DMA counter */
+#define DAC_CCNT_VALUE(n)  ((uint32_t) (n & 0xffff))
+
+/** DCAR double buffering */
+#define DAC_DBLBUF_ENA      ((uint32_t) (1 << 1))
+/** DCAR Time out count enable */
+#define DAC_CNT_ENA         ((uint32_t) (1 << 2))
+/** DCAR DMA access */
+#define DAC_DMA_ENA         ((uint32_t) (1 << 3))
+/** DCAR DACCTRL mask bit */
+#define DAC_DACCTRL_MASK    ((uint32_t) (0x0F))
+
+/**
+ * @brief Current option in DAC configuration option
+ */
+typedef enum IP_DAC_CURRENT_OPT {
+	DAC_MAX_UPDATE_RATE_1MHz = 0,	/*!< Shorter settling times and higher power consumption;
+									    allows for a maximum update rate of 1 MHz */
+	DAC_MAX_UPDATE_RATE_400kHz		/*!< Longer settling times and lower power consumption;
+									    allows for a maximum update rate of 400 kHz */
+} DAC_CURRENT_OPT_T;
+
+/**
+ * @brief	Initial DAC configuration
+ *              - Maximum	current is 700 uA
+ *              - Value to AOUT is 0
+ * @param	pDAC	: pointer to LPC_DAC_T
+ * @return	Nothing
+ */
+void Chip_DAC_Init(LPC_DAC_T *pDAC);
+
+/**
+ * @brief	Shutdown DAC
+ * @param	pDAC	: pointer to LPC_DAC_T
+ * @return	Nothing
+ */
+void Chip_DAC_DeInit(LPC_DAC_T *pDAC);
+
+/**
+ * @brief	Update value to DAC buffer
+ * @param	pDAC		: pointer to LPC_DAC_T
+ * @param	dac_value	: value 10 bit to be converted to output
+ * @return	Nothing
+ */
+void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value);
+
+/**
+ * @brief	Set maximum update rate for DAC
+ * @param	pDAC	: pointer to LPC_DAC_T
+ * @param	bias	: Using Bias value, should be:
+ *              - 0 is 1MHz
+ *              - 1 is 400kHz
+ * @return	Nothing
+ */
+void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias);
+
+/**
+ * @brief	Enables the DMA operation and controls DMA timer
+ * @param	pDAC		: pointer to LPC_DAC_T
+ * @param	dacFlags	: An Or'ed value of the following DAC values:
+ *                  - DAC_DBLBUF_ENA :enable/disable DACR double buffering feature
+ *                  - DAC_CNT_ENA    :enable/disable timer out counter
+ *                  - DAC_DMA_ENA    :enable/disable DMA access
+ * @return	Nothing
+ * @note	Pass an Or'ed value of the DAC flags to enable those options.
+ */
+STATIC INLINE void Chip_DAC_ConfigDAConverterControl(LPC_DAC_T *pDAC, uint32_t dacFlags)
+{
+	uint32_t temp;
+
+	temp = pDAC->CTRL & ~DAC_DACCTRL_MASK;
+	pDAC->CTRL = temp | dacFlags;
+}
+
+/**
+ * @brief	Set reload value for interrupt/DMA counter
+ * @param	pDAC		: pointer to LPC_DAC_T
+ * @param	time_out	: time out to reload for interrupt/DMA counter
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_DAC_SetDMATimeOut(LPC_DAC_T *pDAC, uint32_t time_out)
+{
+	pDAC->CNTVAL = DAC_CCNT_VALUE(time_out);
+}
+
+/**
+ * @brief	Get status for interrupt/DMA time out
+ * @param	pDAC	: pointer to LPC_DAC_T
+ * @return	interrupt/DMA time out status, should be SET or RESET
+ */
+STATIC INLINE IntStatus Chip_DAC_GetIntStatus(LPC_DAC_T *pDAC)
+{
+	return (pDAC->CTRL & 0x01) ? SET : RESET;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/eeprom_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/eeprom_17xx_40xx.h
new file mode 100644
index 000000000..98bf820dc
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/eeprom_17xx_40xx.h
@@ -0,0 +1,320 @@
+/*
+ * @brief LPC17xx/40xx EEPROM driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EEPROM_17XX_40XX_H_
+#define __EEPROM_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EEPROM_17XX_40XX CHIP: LPC17xx/40xx EEPROM driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/**
+ * @brief EEPROM register block structure
+ */
+typedef struct {				/*  EEPROM Structure */
+	__IO uint32_t CMD;			/*!< EEPROM command register */
+	__IO uint32_t ADDR;			/*!< EEPROM address register */
+	__O  uint32_t WDATA;		/*!< EEPROM write data register */
+	__I  uint32_t RDATA;		/*!< EEPROM read data register */
+	__IO uint32_t WSTATE;		/*!< EEPROM wait state register */
+	__IO uint32_t CLKDIV;		/*!< EEPROM clock divider register */
+	__IO uint32_t PWRDWN;		/*!< EEPROM power-down register */
+	uint32_t RESERVED0[975];
+	__O  uint32_t INTENCLR;		/*!< EEPROM interrupt enable clear */
+	__O  uint32_t INTENSET;		/*!< EEPROM interrupt enable set */
+	__I  uint32_t INTSTAT;		/*!< EEPROM interrupt status */
+	__I  uint32_t INTEN;		/*!< EEPROM interrupt enable */
+	__O  uint32_t INTSTATCLR;	/*!< EEPROM interrupt status clear */
+	__O  uint32_t INTSTATSET;	/*!< EEPROM interrupt status set */
+} LPC_EEPROM_T;
+
+#define EEPROM_PAGE_SIZE                64		/*!< EEPROM byes per page */
+#define EEPROM_PAGE_NUM                 63		/*!<  EEPROM pages */
+
+/*
+ * @brief Macro defines for EEPROM command register
+ */
+#define EEPROM_CMD_8BITS_READ           (0)		/*!< EEPROM 8-bit read command */
+#define EEPROM_CMD_16BITS_READ          (1)		/*!< EEPROM 16-bit read command */
+#define EEPROM_CMD_32BITS_READ          (2)		/*!< EEPROM 32-bit read command */
+#define EEPROM_CMD_8BITS_WRITE          (3)		/*!< EEPROM 8-bit write command */
+#define EEPROM_CMD_16BITS_WRITE         (4)		/*!< EEPROM 16-bit write command */
+#define EEPROM_CMD_32BITS_WRITE         (5)		/*!< EEPROM 32-bit write command */
+#define EEPROM_CMD_ERASE_PRG_PAGE       (6)		/*!< EEPROM erase/program command */
+#define EEPROM_CMD_RDPREFETCH           (1 << 3)/*!< EEPROM read pre-fetch enable */
+
+/*
+ * @brief Macro defines for EEPROM power down register
+ */
+#define EEPROM_PWRDWN                   (1 << 0)
+
+/*
+ * @brief Macro defines for EEPROM interrupt related registers
+ */
+#define EEPROM_INT_ENDOFRW                 (1 << 26)
+#define EEPROM_INT_ENDOFPROG               (1 << 28)
+
+/**
+ * @brief EEPROM Mode type definition
+ */
+typedef enum IP_EEPROM_RWSIZE {
+	EEPROM_RWSIZE_8BITS = 1,
+	EEPROM_RWSIZE_16BITS = 2,
+	EEPROM_RWSIZE_32BITS = 4
+} EEPROM_RWSIZE_T;
+
+/**
+ * @brief	Put EEPROM device in power down mode
+ * @param	pEEPROM		: The base of EEPROM peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_EnablePowerDown(LPC_EEPROM_T *pEEPROM)
+{
+	pEEPROM->PWRDWN = EEPROM_PWRDWN;
+}
+
+/**
+ * @brief	Bring EEPROM device out of power down mode
+ * @param	pEEPROM		: The base of EEPROM peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_DisablePowerDown(LPC_EEPROM_T *pEEPROM)
+{
+	pEEPROM->PWRDWN = 0;
+}
+
+/**
+ * @brief	Initializes EEPROM
+ * @param	pEEPROM	: The base of EEPROM peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM);
+
+/**
+ * @brief	De-initializes EEPROM
+ * @param	pEEPROM	: The base of EEPROM peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_DeInit(LPC_EEPROM_T *pEEPROM)
+{
+	/* Enable EEPROM power down mode */
+	Chip_EEPROM_EnablePowerDown(pEEPROM);
+}
+
+/**
+ * @brief	Select an EEPROM command
+ * @param	pEEPROM	: pointer to EEPROM peripheral block
+ * @param	cmd	: EEPROM command.
+ * @return	Nothing
+ * @note	 cmd is or-ed bits value of EEPROM_CMD_[8|16|32]BITS_READ/EEPROM_CMD_[8|16|32]BITS_WRITE
+ * with EEPROM_CMD_RDPREFETCH flag.
+ *		Read and erase/program operations are started on the EEPROM device as a side-effect of calling this function.
+ * Write operations are started as a side-effect of writing data to data register.
+ */
+STATIC INLINE void Chip_EEPROM_SetCmd(LPC_EEPROM_T *pEEPROM, uint32_t cmd)
+{
+	pEEPROM->CMD = cmd;
+}
+
+/**
+ * @brief	Set EEPROM address
+ * @param	pEEPROM	: pointer to EEPROM peripheral block
+ * @param	pageAddr	: Page address.
+ * @param	pageOffset	: Page address.
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_SetAddr(LPC_EEPROM_T *pEEPROM, uint32_t pageAddr, uint32_t pageOffset)
+{
+	pEEPROM->ADDR = (pageAddr << 6) | pageOffset;
+}
+
+/**
+ * @brief	Write EEPROM data
+ * @param	pEEPROM	: pointer to EEPROM peripheral block
+ * @param	data	: EEPROM data.
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_WriteData(LPC_EEPROM_T *pEEPROM, uint32_t data)
+{
+	pEEPROM->WDATA = data;
+}
+
+/**
+ * @brief	Read EEPROM data
+ * @param	pEEPROM	: pointer to EEPROM peripheral block
+ * @return	data
+ */
+STATIC INLINE uint32_t Chip_EEPROM_ReadData(LPC_EEPROM_T *pEEPROM)
+{
+	return pEEPROM->RDATA;
+}
+
+/**
+ * @brief	Set EEPROM wait state
+ * @param	pEEPROM	: pointer to EEPROM peripheral block
+ * @param	ws	: Wait State value.
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_SetWaitState(LPC_EEPROM_T *pEEPROM, uint32_t ws)
+{
+	pEEPROM->WSTATE = ws;
+}
+
+/**
+ * @brief	Write data to EEPROM at specific address
+ * @param	pEEPROM		: The base of EEPROM peripheral on the chip
+ * @param	pageOffset	: offset of data in page register(0 - 63)
+ * @param	pageAddress: page address (0-62)
+ * @param	pData		: buffer that contain data that will be written to buffer
+ * @param	wsize			: Write size:<br>
+ *                  - EEPROM_RWSIZE_8BITS    : 8-bit read/write mode<br>
+ *                  - EEPROM_RWSIZE_16BITS   : 16-bit read/write mode<br>
+ *                  - EEPROM_RWSIZE_32BITS   : 32-bit read/write mode<br>
+ * @param	byteNum		: number written data (bytes)
+ * @return	SUCCESS on successful write of data, or ERROR
+ * @note	This function actually write data into EEPROM memory and automatically
+ * write into next page if current page is overflowed
+ */
+Status Chip_EEPROM_Write(LPC_EEPROM_T *pEEPROM, uint16_t pageOffset,
+						 uint16_t pageAddress,
+						 void *pData,
+						 EEPROM_RWSIZE_T wsize,
+						 uint32_t byteNum);
+
+/**
+ * @brief	Read data to EEPROM at specific address
+ * @param	pEEPROM		: The base of EEPROM peripheral on the chip
+ * @param	pageOffset	: offset of data in page register(0 - 63)
+ * @param	pageAddress: page address (0-62)
+ * @param	pData		: buffer that contain data read from read data register
+ * @param	rsize		: Read size:<br>
+ *                  - EEPROM_RWSIZE_8BITS    : 8-bit read/write mode<br>
+ *                  - EEPROM_RWSIZE_16BITS   : 16-bit read/write mode<br>
+ *                  - EEPROM_RWSIZE_32BITS   : 32-bit read/write mode<br>
+ * @param	byteNum		: number read data (bytes)
+ * @return	Nothing
+ */
+void Chip_EEPROM_Read(LPC_EEPROM_T *pEEPROM, uint16_t pageOffset,
+					  uint16_t pageAddress,
+					  void *pData,
+					  EEPROM_RWSIZE_T rsize,
+					  uint32_t byteNum);
+
+/**
+ * @brief	Erase a page at the specific address
+ * @param	pEEPROM		: The base of EEPROM peripheral on the chip
+ * @param	address		: EEPROM page address (0-62)
+ * @return	Nothing
+ */
+void Chip_EEPROM_Erase(LPC_EEPROM_T *pEEPROM, uint16_t address);
+
+/**
+ * @brief	Enable EEPROM interrupt
+ * @param	pEEPROM		: pointer to EEPROM peripheral block
+ * @param	mask		: interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_EnableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+	pEEPROM->INTENSET =  mask;
+}
+
+/**
+ * @brief	Disable EEPROM interrupt
+ * @param	pEEPROM		: pointer to EEPROM peripheral block
+ * @param	mask		: interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_DisableInt(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+	pEEPROM->INTENCLR =  mask;
+}
+
+/**
+ * @brief	Get the value of the EEPROM interrupt enable register
+ * @param	pEEPROM		: pointer to EEPROM peripheral block
+ * @return	Or-ed bits value of EEPROM_INT_*
+ */
+STATIC INLINE uint32_t Chip_EEPROM_GetIntEnable(LPC_EEPROM_T *pEEPROM)
+{
+	return pEEPROM->INTEN;
+}
+
+/**
+ * @brief	Get EEPROM interrupt status
+ * @param	pEEPROM		: pointer to EEPROM peripheral block
+ * @return	Or-ed bits value of EEPROM_INT_*
+ */
+STATIC INLINE uint32_t Chip_EEPROM_GetIntStatus(LPC_EEPROM_T *pEEPROM)
+{
+	return pEEPROM->INTSTAT;
+}
+
+/**
+ * @brief	Set EEPROM interrupt status
+ * @param	pEEPROM		: pointer to EEPROM peripheral block
+ * @param	mask		: interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_SetIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+	pEEPROM->INTSTATSET =  mask;
+}
+
+/**
+ * @brief	Clear EEPROM interrupt status
+ * @param	pEEPROM		: pointer to EEPROM peripheral block
+ * @param	mask		: interrupt mask (or-ed bits value of EEPROM_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_EEPROM_ClearIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+	pEEPROM->INTSTATCLR =  mask;
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EEPROM_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/emc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/emc_17xx_40xx.h
new file mode 100644
index 000000000..6fccf330d
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/emc_17xx_40xx.h
@@ -0,0 +1,358 @@
+/*
+ * @brief LPC17xx/40xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __EMC_17XX_40XX_H_
+#define __EMC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup EMC_17XX_40XX CHIP: LPC17xx/40xx External Memory Controller driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ * The EMC interface clocks must be enabled outside this driver prior to
+ * calling any function of this driver.
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/**
+ * @brief External Memory Controller (EMC) register block structure
+ */
+typedef struct {							/*!< EMC Structure          */
+	__IO uint32_t  CONTROL;					/*!< Controls operation of the memory controller. */
+	__I  uint32_t  STATUS;					/*!< Provides EMC status information. */
+	__IO uint32_t  CONFIG;					/*!< Configures operation of the memory controller. */
+	__I  uint32_t  RESERVED0[5];
+	__IO uint32_t  DYNAMICCONTROL;			/*!< Controls dynamic memory operation. */
+	__IO uint32_t  DYNAMICREFRESH;			/*!< Configures dynamic memory refresh operation. */
+	__IO uint32_t  DYNAMICREADCONFIG;		/*!< Configures the dynamic memory read strategy. */
+	__I  uint32_t  RESERVED1;
+	__IO uint32_t  DYNAMICRP;				/*!< Selects the precharge command period. */
+	__IO uint32_t  DYNAMICRAS;				/*!< Selects the active to precharge command period. */
+	__IO uint32_t  DYNAMICSREX;				/*!< Selects the self-refresh exit time. */
+	__IO uint32_t  DYNAMICAPR;				/*!< Selects the last-data-out to active command time. */
+	__IO uint32_t  DYNAMICDAL;				/*!< Selects the data-in to active command time. */
+	__IO uint32_t  DYNAMICWR;				/*!< Selects the write recovery time. */
+	__IO uint32_t  DYNAMICRC;				/*!< Selects the active to active command period. */
+	__IO uint32_t  DYNAMICRFC;				/*!< Selects the auto-refresh period. */
+	__IO uint32_t  DYNAMICXSR;				/*!< Selects the exit self-refresh to active command time. */
+	__IO uint32_t  DYNAMICRRD;				/*!< Selects the active bank A to active bank B latency. */
+	__IO uint32_t  DYNAMICMRD;				/*!< Selects the load mode register to active command time. */
+	__I  uint32_t  RESERVED2[9];
+	__IO uint32_t  STATICEXTENDEDWAIT;		/*!< Selects time for long static memory read and write transfers. */
+	__I  uint32_t  RESERVED3[31];
+	__IO uint32_t  DYNAMICCONFIG0;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS0;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED4[6];
+	__IO uint32_t  DYNAMICCONFIG1;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS1;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED5[6];
+	__IO uint32_t  DYNAMICCONFIG2;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS2;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED6[6];
+	__IO uint32_t  DYNAMICCONFIG3;			/*!< Selects the configuration information for dynamic memory chip select n. */
+	__IO uint32_t  DYNAMICRASCAS3;			/*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */
+	__I  uint32_t  RESERVED7[38];
+	__IO uint32_t  STATICCONFIG0;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN0;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN0;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD0;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG0;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR0;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN0;			/*!< Selects bus turnaround cycles */
+	__I  uint32_t  RESERVED8;
+	__IO uint32_t  STATICCONFIG1;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN1;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN1;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD1;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG1;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR1;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN1;			/*!< Selects bus turnaround cycles */
+	__I  uint32_t  RESERVED9;
+	__IO uint32_t  STATICCONFIG2;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN2;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN2;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD2;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG2;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR2;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN2;			/*!< Selects bus turnaround cycles */
+	__I  uint32_t  RESERVED10;
+	__IO uint32_t  STATICCONFIG3;			/*!< Selects the memory configuration for static chip select n. */
+	__IO uint32_t  STATICWAITWEN3;			/*!< Selects the delay from chip select n to write enable. */
+	__IO uint32_t  STATICWAITOEN3;			/*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */
+	__IO uint32_t  STATICWAITRD3;			/*!< Selects the delay from chip select n to a read access. */
+	__IO uint32_t  STATICWAITPAG3;			/*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */
+	__IO uint32_t  STATICWAITWR3;			/*!< Selects the delay from chip select n to a write access. */
+	__IO uint32_t  STATICWAITTURN3;			/*!< Selects bus turnaround cycles */
+} LPC_EMC_T;
+
+/**
+ * Dynamic Chip Select Address
+ */
+#define EMC_ADDRESS_DYCS0   (0xA0000000)
+#define EMC_ADDRESS_DYCS1   (0xB0000000)
+#define EMC_ADDRESS_DYCS2   (0xC0000000)
+#define EMC_ADDRESS_DYCS3   (0xD0000000)
+
+/**
+ * Static Chip Select Address
+ */
+#define EMC_ADDRESS_CS0     (0x80000000)
+#define EMC_ADDRESS_CS1     (0x90000000)
+#define EMC_ADDRESS_CS2     (0x98000000)
+#define EMC_ADDRESS_CS3     (0x9C000000)
+
+/**
+ * @brief EMC register support bitfields and mask
+ */
+/* Reserve for extending support to ARM9 or nextgen LPC */
+#define EMC_SUPPORT_ONLY_PL172	/*!< Reserve for extending support to ARM9 or nextgen LPC */
+
+#define EMC_CONFIG_ENDIAN_LITTLE    (0)		/*!< Value for EMC to operate in Little Endian Mode */
+#define EMC_CONFIG_ENDIAN_BIG         (1)	/*!< Value for EMC to operate in Big Endian Mode */
+
+#define EMC_CONFIG_BUFFER_ENABLE    (1 << 19)	/*!< EMC Buffer enable bit in EMC Dynamic Configuration register */
+#define EMC_CONFIG_WRITE_PROTECT    (1 << 20)	/*!< EMC Write protect bit in EMC Dynamic Configuration register */
+
+/* Dynamic Memory Configuration Register Bit Definitions */
+#define EMC_DYN_CONFIG_MD_BIT             (3)								/*!< Memory device bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_MD_SDRAM         (0 << EMC_DYN_CONFIG_MD_BIT)		/*!< Select device as SDRAM in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_MD_LPSDRAM       (1 << EMC_DYN_CONFIG_MD_BIT)		/*!< Select device as LPSDRAM in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_LPSDRAM_BIT      (12)							/*!< LPSDRAM bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_LPSDRAM          (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)	/*!< LPSDRAM value in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_DEV_SIZE_BIT     (9)									/*!< Device Size starting bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_16Mb    (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 16Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_64Mb    (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 64Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 128Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 256Mb Device Size value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)	/*!< 512Mb Device Size value in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_DEV_BUS_BIT      (7)									/*!< Device bus width starting bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_BUS_8        (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 8-bit bus width value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_BUS_16       (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 16-bit bus width value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DEV_BUS_32       (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)	/*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
+
+#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)									/*!< Device data bus width starting bit in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DATA_BUS_16      (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)	/*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */
+#define EMC_DYN_CONFIG_DATA_BUS_32      (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)	/*!< Device 32-bit bus width value in EMC Dynamic Configuration register */
+
+/*!< Memory configuration values in EMC Dynamic Configuration Register */
+#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS     ((0x0 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */
+#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS    ((0x0 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */
+#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS     ((0x1 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */
+#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS    ((0x1 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */
+#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS    ((0x1 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */
+#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */
+#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS    ((0x2 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */
+#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS    ((0x2 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */
+#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */
+#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */
+#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS    ((0x3 << 9) | (0x2 << 7))	/*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */
+#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))	/*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */
+#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS  ((0x4 << 9) | (0x1 << 7))	/*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */
+
+/*!< Dynamic Memory Mode Register Bit Definition */
+#define EMC_DYN_MODE_BURST_LEN_BIT      (0)	/*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_1        (0)	/*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_2        (1)	/*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_4        (2)	/*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_8        (3)	/*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_LEN_FULL     (7)	/*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */
+
+#define EMC_DYN_MODE_BURST_TYPE_BIT         (3)									/*!< Burst Type bit in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL  (0 << EMC_DYN_MODE_BURST_TYPE_BIT)	/*!< Burst Type Sequential in Dynamic Memory Mode Register */
+#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE  (1 << EMC_DYN_MODE_BURST_TYPE_BIT)	/*!< Burst Type Interleaved in Dynamic Memory Mode Register */
+
+/*!< CAS Latency in Dynamic Mode Register */
+#define EMC_DYN_MODE_CAS_BIT    (4)							/*!< CAS latency starting bit in Dynamic Memory Mode register */
+#define EMC_DYN_MODE_CAS_1      (1 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 1 cycle */
+#define EMC_DYN_MODE_CAS_2      (2 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 2 cycle */
+#define EMC_DYN_MODE_CAS_3      (3 << EMC_DYN_MODE_CAS_BIT)	/*!< value for CAS latency of 3 cycle */
+
+/*!< Operation Mode in Dynamic Mode register */
+#define EMC_DYN_MODE_OPMODE_BIT           (7)							/*!< Dynamic Mode Operation bit */
+#define EMC_DYN_MODE_OPMODE_STANDARD    (0 << EMC_DYN_MODE_OPMODE_BIT)	/*!< Value for Dynamic standard operation Mode */
+
+/*!< Write Burst Mode in Dynamic Mode register */
+#define EMC_DYN_MODE_WBMODE_BIT             (9)							/*!< Write Burst Mode bit */
+#define EMC_DYN_MODE_WBMODE_PROGRAMMED  (0 << EMC_DYN_MODE_WBMODE_BIT)	/*!< Write Burst Mode programmed */
+#define EMC_DYN_MODE_WBMODE_SINGLE_LOC  (1 << EMC_DYN_MODE_WBMODE_BIT)	/*!< Write Burst Mode Single LOC */
+
+/*!< Dynamic Memory Control Register Bit Definitions */
+#define EMC_DYN_CONTROL_ENABLE          (0x03)	/*!< Control Enable value */
+
+/*!< Static Memory Configuration Register Bit Definitions */
+#define EMC_STATIC_CONFIG_MEM_WIDTH_8       (0)	/*!< Static Memory Configuration - 8-bit width */
+#define EMC_STATIC_CONFIG_MEM_WIDTH_16      (1)	/*!< Static Memory Configuration - 16-bit width */
+#define EMC_STATIC_CONFIG_MEM_WIDTH_32      (2)	/*!< Static Memory Configuration - 32-bit width */
+
+#define EMC_STATIC_CONFIG_PAGE_MODE_BIT         (3)										/*!< Page Mode bit No */
+#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE      (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)	/*!< Value to enable Page Mode */
+
+#define EMC_STATIC_CONFIG_CS_POL_BIT            (6)									/*!< Chip Select bit No */
+#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH    (1 << EMC_STATIC_CONFIG_CS_POL_BIT)	/*!< Chip Select polarity - Active High */
+#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW     (0 << EMC_STATIC_CONFIG_CS_POL_BIT)	/*!< Chip Select polarity - Active Low */
+
+#define EMC_STATIC_CONFIG_BLS_BIT           (7)								/*!< BLS Configuration bit No */
+#define EMC_STATIC_CONFIG_BLS_HIGH          (1 << EMC_STATIC_CONFIG_BLS_BIT)	/*!< BLS High Configuration value */
+#define EMC_STATIC_CONFIG_BLS_LOW           (0 << EMC_STATIC_CONFIG_BLS_BIT)	/*!< BLS Low Configuration value */
+
+#define EMC_STATIC_CONFIG_EW_BIT            (8)								/*!< Ext Wait bit No */
+#define EMC_STATIC_CONFIG_EW_ENABLE         (1 << EMC_STATIC_CONFIG_EW_BIT)	/*!< Ext Wait Enabled value */
+#define EMC_STATIC_CONFIG_EW_DISABLE        (0 << EMC_STATIC_CONFIG_EW_BIT)	/*!< Ext Wait Diabled value */
+
+/*!< Q24.8 Fixed Point Helper */
+#define Q24_8_FP(x) ((x) * 256)
+#define EMC_NANOSECOND(x)   Q24_8_FP(x)
+#define EMC_CLOCK(x)        Q24_8_FP(-(x))
+
+/**
+ * @brief	EMC Dynamic Device Configuration structure used for IP drivers
+ */
+typedef struct {
+	uint32_t    BaseAddr;		/*!< Base Address */
+	uint8_t     RAS;			/*!< RAS value */
+	uint32_t    ModeRegister;	/*!< Mode Register value */
+	uint32_t    DynConfig;		/*!< Dynamic Configuration value */
+} IP_EMC_DYN_DEVICE_CONFIG_T;
+
+/**
+ * @brief EMC Dynamic Configure Struct
+ */
+typedef struct {
+	int32_t RefreshPeriod;							/*!< Refresh period */
+	uint32_t ReadConfig;							/*!< Clock*/
+	int32_t tRP;									/*!< Precharge Command Period */
+	int32_t tRAS;									/*!< Active to Precharge Command Period */
+	int32_t tSREX;									/*!< Self Refresh Exit Time */
+	int32_t tAPR;									/*!< Last Data Out to Active Time */
+	int32_t tDAL;									/*!< Data In to Active Command Time */
+	int32_t tWR;									/*!< Write Recovery Time */
+	int32_t tRC;									/*!< Active to Active Command Period */
+	int32_t tRFC;									/*!< Auto-refresh Period */
+	int32_t tXSR;									/*!< Exit Selt Refresh */
+	int32_t tRRD;									/*!< Active Bank A to Active Bank B Time */
+	int32_t tMRD;									/*!< Load Mode register command to Active Command */
+	IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4];		/*!< Device Configuration array */
+} IP_EMC_DYN_CONFIG_T;
+
+/**
+ * @brief EMC Static Configure Structure
+ */
+typedef struct {
+	uint8_t ChipSelect;		/*!< Chip select */
+	uint32_t Config;		/*!< Configuration value */
+	int32_t WaitWen;		/*!< Write Enable Wait */
+	int32_t WaitOen;		/*!< Output Enable Wait */
+	int32_t WaitRd;			/*!< Read Wait */
+	int32_t WaitPage;		/*!< Page Access Wait */
+	int32_t WaitWr;			/*!< Write Wait */
+	int32_t WaitTurn;		/*!< Turn around wait */
+} IP_EMC_STATIC_CONFIG_T;
+
+/**
+ * @brief	Dyanmic memory setup
+ * @param	Dynamic_Config	: Pointer to dynamic memory setup data
+ * @return	None
+ */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config);
+
+/**
+ * @brief	Static memory setup
+ * @param	Static_Config	: Pointer to static memory setup data
+ * @return	None
+ */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config);
+
+/**
+ * @brief	Enable Dynamic Memory Controller
+ * @param	Enable	: 1 = Enable Dynamic Memory Controller, 0 = Disable
+ * @return	None
+ */
+void Chip_EMC_Dynamic_Enable(uint8_t Enable);
+
+/**
+ * @brief	Mirror CS1 to CS0 and DYCS0
+ * @param	Enable	: 1 = Mirror, 0 = Normal Memory Map
+ * @return	None
+ */
+void Chip_EMC_Mirror(uint8_t Enable);
+
+/**
+ * @brief	Enable EMC
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ */
+void Chip_EMC_Enable(uint8_t Enable);
+
+/**
+ * @brief	Set EMC LowPower Mode
+ * @param	Enable	: 1 = Enable, 0 = Disable
+ * @return	None
+ * @note	This function should only be called when the memory
+ * controller is not busy (bit 0 of the status register is not set).
+ */
+void Chip_EMC_LowPowerMode(uint8_t Enable);
+
+/**
+ * @brief	Initialize EMC
+ * @param	Enable		: 1 = Enable, 0 = Disable
+ * @param	ClockRatio	: clock out ratio, 0 = 1:1, 1 = 1:2
+ * @param	EndianMode	: Endian Mode, 0 = Little, 1 = Big
+ * @return	None
+ */
+void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
+
+/**
+ * @brief	Set Static Memory Extended Wait in Clock
+ * @param	Wait16Clks	: Number of '16 clock' delay cycles
+ * @return	None
+ */
+STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
+{
+	LPC_EMC->STATICEXTENDEDWAIT = Wait16Clks;
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __EMC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/enet_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/enet_17xx_40xx.h
new file mode 100644
index 000000000..3bdb1f5b8
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/enet_17xx_40xx.h
@@ -0,0 +1,914 @@
+/*
+ * @brief LPC17xx/40xx Ethernet driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ENET_17XX_40XX_H_
+#define __ENET_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ENET_17XX_40XX CHIP: LPC17xx/40xx Ethernet driver (2)
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief Ethernet MAC register block structure
+ */
+typedef struct {
+	__IO uint32_t MAC1;			/*!< MAC Configuration register 1 */
+	__IO uint32_t MAC2;			/*!< MAC Configuration register 2 */
+	__IO uint32_t IPGT;			/*!< Back-to-Back Inter-Packet-Gap register */
+	__IO uint32_t IPGR;			/*!< Non Back-to-Back Inter-Packet-Gap register */
+	__IO uint32_t CLRT;			/*!< Collision window / Retry register */
+	__IO uint32_t MAXF;			/*!< Maximum Frame register */
+	__IO uint32_t SUPP;			/*!< PHY Support register */
+	__IO uint32_t TEST;			/*!< Test register */
+	__IO uint32_t MCFG;			/*!< MII Mgmt Configuration register */
+	__IO uint32_t MCMD;			/*!< MII Mgmt Command register */
+	__IO uint32_t MADR;			/*!< MII Mgmt Address register */
+	__O  uint32_t MWTD;			/*!< MII Mgmt Write Data register */
+	__I  uint32_t MRDD;			/*!< MII Mgmt Read Data register */
+	__I  uint32_t MIND;			/*!< MII Mgmt Indicators register */
+	uint32_t RESERVED0[2];
+	__IO uint32_t SA[3];		/*!< Station Address registers */
+} ENET_MAC_T;
+
+/**
+ * @brief Ethernet Transfer register Block Structure
+ */
+typedef struct {
+	__IO uint32_t DESCRIPTOR;		/*!< Descriptor base address register */
+	__IO uint32_t STATUS;			/*!< Status base address register */
+	__IO uint32_t DESCRIPTORNUMBER;	/*!< Number of descriptors register */
+	__IO uint32_t PRODUCEINDEX;		/*!< Produce index register */
+	__IO uint32_t CONSUMEINDEX;		/*!< Consume index register */
+} ENET_TRANSFER_INFO_T;
+
+/**
+ * @brief Ethernet Control register block structure
+ */
+typedef struct {
+	__IO uint32_t COMMAND;				/*!< Command register */
+	__I  uint32_t STATUS;				/*!< Status register */
+	ENET_TRANSFER_INFO_T RX;	/*!< Receive block registers */
+	ENET_TRANSFER_INFO_T TX;	/*!< Transmit block registers */
+	uint32_t RESERVED0[10];
+	__I  uint32_t TSV0;					/*!< Transmit status vector 0 register */
+	__I  uint32_t TSV1;					/*!< Transmit status vector 1 register */
+	__I  uint32_t RSV;					/*!< Receive status vector register */
+	uint32_t RESERVED1[3];
+	__IO uint32_t FLOWCONTROLCOUNTER;	/*!< Flow control counter register */
+	__I  uint32_t FLOWCONTROLSTATUS;	/*!< Flow control status register */
+} ENET_CONTROL_T;
+
+/**
+ * @brief Ethernet Receive Filter register block structure
+ */
+typedef struct {
+	__IO uint32_t CONTROL;			/*!< Receive filter control register */
+	__I  uint32_t WOLSTATUS;		/*!< Receive filter WoL status register */
+	__O  uint32_t WOLCLEAR;			/*!< Receive filter WoL clear register */
+	uint32_t RESERVED;
+	__IO uint32_t HashFilterL;		/*!< Hash filter table LSBs register */
+	__IO uint32_t HashFilterH;		/*!< Hash filter table MSBs register */
+} ENET_RXFILTER_T;
+
+/**
+ * @brief Ethernet Module Control register block structure
+ */
+typedef struct {
+	__I  uint32_t INTSTATUS;		/*!< Interrupt status register */
+	__IO uint32_t INTENABLE;		/*!< Interrupt enable register */
+	__O  uint32_t INTCLEAR;			/*!< Interrupt clear register */
+	__O  uint32_t INTSET;			/*!< Interrupt set register */
+	uint32_t RESERVED;
+	__IO uint32_t POWERDOWN;		/*!< Power-down register */
+} ENET_MODULE_CTRL_T;
+
+/**
+ * @brief Ethernet register block structure
+ */
+typedef struct {
+	ENET_MAC_T  MAC;				/*!< MAC registers */
+	uint32_t RESERVED1[45];
+	ENET_CONTROL_T CONTROL;		/*!< Control registers */
+	uint32_t RESERVED4[34];
+	ENET_RXFILTER_T RXFILTER;		/*!< RxFilter registers */
+	uint32_t RESERVED6[882];
+	ENET_MODULE_CTRL_T MODULE_CONTROL;	/*!< Module Control registers */
+} LPC_ENET_T;
+
+/*
+ * @brief MAC Configuration Register 1  bit definitions
+ */
+#define ENET_MAC1_MASK          0xcf1f		/*!< MAC1 register mask */
+#define ENET_MAC1_RXENABLE      0x00000001	/*!< Receive Enable */
+#define ENET_MAC1_PARF          0x00000002	/*!< Pass All Receive Frames */
+#define ENET_MAC1_RXFLOWCTRL    0x00000004	/*!< RX Flow Control */
+#define ENET_MAC1_TXFLOWCTRL    0x00000008	/*!< TX Flow Control */
+#define ENET_MAC1_LOOPBACK      0x00000010	/*!< Loop Back Mode */
+#define ENET_MAC1_RESETTX       0x00000100	/*!< Reset TX Logic */
+#define ENET_MAC1_RESETMCSTX    0x00000200	/*!< Reset MAC TX Control Sublayer */
+#define ENET_MAC1_RESETRX       0x00000400	/*!< Reset RX Logic */
+#define ENET_MAC1_RESETMCSRX    0x00000800	/*!< Reset MAC RX Control Sublayer */
+#define ENET_MAC1_SIMRESET      0x00004000	/*!< Simulation Reset */
+#define ENET_MAC1_SOFTRESET     0x00008000	/*!< Soft Reset MAC */
+
+/*
+ * @brief MAC Configuration Register 2 bit definitions
+ */
+#define ENET_MAC2_MASK          0x73ff		/*!< MAC2 register mask */
+#define ENET_MAC2_FULLDUPLEX    0x00000001	/*!< Full-Duplex Mode */
+#define ENET_MAC2_FLC           0x00000002	/*!< Frame Length Checking */
+#define ENET_MAC2_HFEN          0x00000004	/*!< Huge Frame Enable */
+#define ENET_MAC2_DELAYEDCRC    0x00000008	/*!< Delayed CRC Mode */
+#define ENET_MAC2_CRCEN         0x00000010	/*!< Append CRC to every Frame */
+#define ENET_MAC2_PADCRCEN      0x00000020	/*!< Pad all Short Frames */
+#define ENET_MAC2_VLANPADEN     0x00000040	/*!< VLAN Pad Enable */
+#define ENET_MAC2_AUTODETPADEN  0x00000080	/*!< Auto Detect Pad Enable */
+#define ENET_MAC2_PPENF         0x00000100	/*!< Pure Preamble Enforcement */
+#define ENET_MAC2_LPENF         0x00000200	/*!< Long Preamble Enforcement */
+#define ENET_MAC2_NOBACKOFF     0x00001000	/*!< No Backoff Algorithm */
+#define ENET_MAC2_BP_NOBACKOFF  0x00002000	/*!< Backoff Presurre / No Backoff */
+#define ENET_MAC2_EXCESSDEFER   0x00004000	/*!< Excess Defer */
+
+/*
+ * @brief Back-to-Back Inter-Packet-Gap Register bit definitions
+ */
+/** Programmable field representing the nibble time offset of the minimum possible period
+ * between the end of any transmitted packet to the beginning of the next */
+#define ENET_IPGT_BTOBINTEGAP(n) ((n) & 0x7F)
+
+/** Recommended value for Full Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define ENET_IPGT_FULLDUPLEX (ENET_IPGT_BTOBINTEGAP(0x15))
+
+/** Recommended value for Half Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define ENET_IPGT_HALFDUPLEX (ENET_IPGT_BTOBINTEGAP(0x12))
+
+/*
+ * @brief Non Back-to-Back Inter-Packet-Gap Register bit definitions
+ */
+
+/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
+#define ENET_IPGR_NBTOBINTEGAP2(n) ((n) & 0x7F)
+
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
+#define ENET_IPGR_P2_DEF (ENET_IPGR_NBTOBINTEGAP2(0x12))
+
+/** Programmable field representing the optional carrierSense window referenced in
+ * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
+#define ENET_IPGR_NBTOBINTEGAP1(n) (((n) & 0x7F) << 8)
+
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
+#define ENET_IPGR_P1_DEF ENET_IPGR_NBTOBINTEGAP1(0x0C)
+
+/*
+ * @brief Collision Window/Retry Register bit definitions
+ */
+/** Programmable field specifying the number of retransmission attempts following a collision before
+ * aborting the packet due to excessive collisions */
+#define ENET_CLRT_RETRANSMAX(n) ((n) & 0x0F)
+
+/** Programmable field representing the slot time or collision window during which collisions occur
+ * in properly configured networks */
+#define ENET_CLRT_COLLWIN(n) (((n) & 0x3F) << 8)
+
+/** Default value for Collision Window / Retry register */
+#define ENET_CLRT_DEF ((ENET_CLRT_RETRANSMAX(0x0F)) | (ENET_CLRT_COLLWIN(0x37)))
+
+/*
+ * @brief Maximum Frame Register bit definitions
+ */
+/** Represents a maximum receive frame of 1536 octets */
+#define ENET_MAXF_MAXFLEN(n) ((n) & 0xFFFF)
+#define ENET_MAXF_MAXFLEN_DEF (0x600)
+
+/* PHY Support Register */
+#define ENET_SUPP_100Mbps_SPEED 0x00000100		/*!< Reduced MII Logic Current Speed */
+
+/*
+ * @brief Test Register bit definitions
+ */
+#define ENET_TEST_SCPQ          0x00000001		/*!< Shortcut Pause Quanta */
+#define ENET_TEST_TESTPAUSE     0x00000002		/*!< Test Pause */
+#define ENET_TEST_TESTBP        0x00000004		/*!< Test Back Pressure */
+
+/*
+ * @brief MII Management Configuration Register bit definitions
+ */
+#define ENET_MCFG_SCANINC       0x00000001		/*!< Scan Increment PHY Address */
+#define ENET_MCFG_SUPPPREAMBLE  0x00000002		/*!< Suppress Preamble */
+#define ENET_MCFG_CLOCKSEL(n)   (((n) & 0x0F) << 2)	/*!< Clock Select Field */
+#define ENET_MCFG_RES_MII       0x00008000		/*!< Reset MII Management Hardware */
+#define ENET_MCFG_RESETMIIMGMT  2500000UL		/*!< MII Clock max */
+
+/*
+ * @brief MII Management Command Register bit definitions
+ */
+#define ENET_MCMD_READ          0x00000001		/*!< MII Read */
+#define ENET_MCMD_SCAN          0x00000002		/*!< MII Scan continuously */
+#define ENET_MII_WR_TOUT        0x00050000		/*!< MII Write timeout count */
+#define ENET_MII_RD_TOUT        0x00050000		/*!< MII Read timeout count */
+
+/*
+ * @brief MII Management Address Register bit definitions
+ */
+#define ENET_MADR_REGADDR(n)    ((n) & 0x1F)		/*!< MII Register Address field */
+#define ENET_MADR_PHYADDR(n)    (((n) & 0x1F) << 8)	/*!< PHY Address Field */
+
+/*
+ * @brief MII Management Write Data Register bit definitions
+ */
+#define ENET_MWTD_DATA(n)       ((n) & 0xFFFF)		/*!< Data field for MMI Management Write Data register */
+
+/**
+ * @brief MII Management Read Data Register bit definitions
+ */
+#define ENET_MRDD_DATA(n)       ((n) & 0xFFFF)		/*!< Data field for MMI Management Read Data register */
+
+/*
+ * @brief MII Management Indicators Register bit definitions
+ */
+#define ENET_MIND_BUSY          0x00000001		/*!< MII is Busy */
+#define ENET_MIND_SCANNING      0x00000002		/*!< MII Scanning in Progress */
+#define ENET_MIND_NOTVALID      0x00000004		/*!< MII Read Data not valid */
+#define ENET_MIND_MIILINKFAIL   0x00000008		/*!< MII Link Failed */
+
+/*
+ * @brief Command Register bit definitions
+ */
+#define ENET_COMMAND_RXENABLE           0x00000001		/*!< Enable Receive */
+#define ENET_COMMAND_TXENABLE           0x00000002		/*!< Enable Transmit */
+#define ENET_COMMAND_REGRESET           0x00000008		/*!< Reset Host Registers */
+#define ENET_COMMAND_TXRESET            0x00000010		/*!< Reset Transmit Datapath */
+#define ENET_COMMAND_RXRESET            0x00000020		/*!< Reset Receive Datapath */
+#define ENET_COMMAND_PASSRUNTFRAME      0x00000040		/*!< Pass Runt Frames */
+#define ENET_COMMAND_PASSRXFILTER       0x00000080		/*!< Pass RX Filter */
+#define ENET_COMMAND_TXFLOWCONTROL      0x00000100		/*!< TX Flow Control */
+#define ENET_COMMAND_RMII               0x00000200		/*!< Reduced MII Interface */
+#define ENET_COMMAND_FULLDUPLEX         0x00000400		/*!< Full Duplex */
+
+/*
+ * @brief Status Register bit definitions
+ */
+#define ENET_STATUS_RXSTATUS        0x00000001		/*!< Receive Channel Active Status */
+#define ENET_STATUS_TXSTATUS        0x00000002		/*!< Transmit Channel Active Status */
+
+/*
+ * @brief Transmit Status Vector 0 Register bit definitions
+ */
+#define ENET_TSV0_CRCERR        0x00000001	/*!< CRC error */
+#define ENET_TSV0_LCE           0x00000002	/*!< Length Check Error */
+#define ENET_TSV0_LOR           0x00000004	/*!< Length Out of Range */
+#define ENET_TSV0_DONE          0x00000008	/*!< Tramsmission Completed  */
+#define ENET_TSV0_MULTICAST     0x00000010	/*!< Multicast Destination */
+#define ENET_TSV0_BROADCAST     0x00000020	/*!< Broadcast Destination */
+#define ENET_TSV0_PACKETDEFER   0x00000040	/*!< Packet Deferred */
+#define ENET_TSV0_EXDF          0x00000080	/*!< Excessive Packet Deferral */
+#define ENET_TSV0_EXCOL         0x00000100	/*!< Excessive Collision */
+#define ENET_TSV0_LCOL          0x00000200	/*!< Late Collision Occured  */
+#define ENET_TSV0_GIANT         0x00000400	/*!< Giant Frame */
+#define ENET_TSV0_UNDERRUN      0x00000800	/*!< Buffer Underrun */
+#define ENET_TSV0_TOTALBYTES    0x0FFFF000	/*!< Total Bytes Transferred  */
+#define ENET_TSV0_CONTROLFRAME  0x10000000	/*!< Control Frame */
+#define ENET_TSV0_PAUSE         0x20000000	/*!< Pause Frame */
+#define ENET_TSV0_BACKPRESSURE  0x40000000	/*!< Backpressure Method Applied */
+#define ENET_TSV0_VLAN          0x80000000	/*!< VLAN Frame */
+
+/*
+ * @brief Transmit Status Vector 0 Register bit definitions
+ */
+#define ENET_TSV1_TBC       0x0000FFFF	/*!< Transmit Byte Count */
+#define ENET_TSV1_TCC       0x000F0000	/*!< Transmit Collision Count */
+
+/*
+ * @brief Receive Status Vector Register bit definitions
+ */
+#define ENET_RSV_RBC            0x0000FFFF	/*!< Receive Byte Count */
+#define ENET_RSV_PPI            0x00010000	/*!< Packet Previously Ignored */
+#define ENET_RSV_RXDVSEEN       0x00020000	/*!< RXDV Event Previously Seen */
+#define ENET_RSV_CESEEN         0x00040000	/*!< Carrier Event Previously Seen */
+#define ENET_RSV_RCV            0x00080000	/*!< Receive Code Violation */
+#define ENET_RSV_CRCERR         0x00100000	/*!< CRC Error */
+#define ENET_RSV_LCERR          0x00200000	/*!< Length Check Error */
+#define ENET_RSV_LOR            0x00400000	/*!< Length Out of Range */
+#define ENET_RSV_ROK            0x00800000	/*!< Frame Received OK */
+#define ENET_RSV_MULTICAST      0x01000000	/*!< Multicast Frame */
+#define ENET_RSV_BROADCAST      0x02000000	/*!< Broadcast Frame */
+#define ENET_RSV_DRIBBLENIBBLE  0x04000000	/*!< Dribble Nibble */
+#define ENET_RSV_CONTROLFRAME   0x08000000	/*!< Control Frame */
+#define ENET_RSV_PAUSE          0x10000000	/*!< Pause Frame */
+#define ENET_RSV_UO             0x20000000	/*!< Unsupported Opcode */
+#define ENET_RSV_VLAN           0x40000000	/*!< VLAN Frame */
+
+/*
+ * @brief Flow Control Counter Register bit definitions
+ */
+#define ENET_FLOWCONTROLCOUNTER_MC(n)   ((n) & 0xFFFF)			/*!< Mirror Counter */
+#define ENET_FLOWCONTROLCOUNTER_PT(n)   (((n) & 0xFFFF) << 16)	/*!< Pause Timer */
+
+/*
+ * @brief Flow Control Status Register bit definitions
+ */
+#define ENET_FLOWCONTROLSTATUS_MCC(n) ((n) & 0xFFFF)	/*!< Mirror Counter Current            */
+
+/*
+ * @brief Receive Filter Control Register bit definitions
+ */
+#define ENET_RXFILTERCTRL_AUE       0x00000001	/*!< Accept Unicast Frames Enable */
+#define ENET_RXFILTERCTRL_ABE       0x00000002	/*!< Accept Broadcast Frames Enable */
+#define ENET_RXFILTERCTRL_AME       0x00000004	/*!< Accept Multicast Frames Enable */
+#define ENET_RXFILTERCTRL_AUHE      0x00000008	/*!< Accept Unicast Hash Filter Frames */
+#define ENET_RXFILTERCTRL_AMHE      0x00000010	/*!< Accept Multicast Hash Filter Fram */
+#define ENET_RXFILTERCTRL_APE       0x00000020	/*!< Accept Perfect Match Enable */
+#define ENET_RXFILTERCTRL_MPEW      0x00001000	/*!< Magic Packet Filter WoL Enable */
+#define ENET_RXFILTERCTRL_RFEW      0x00002000	/*!< Perfect Filter WoL Enable */
+
+/*
+ * @brief Receive Filter WoL Status/Clear Register bit definitions
+ */
+#define ENET_RXFILTERWOLSTATUS_AUW          0x00000001	/*!< Unicast Frame caused WoL */
+#define ENET_RXFILTERWOLSTATUS_ABW          0x00000002	/*!< Broadcast Frame caused WoL */
+#define ENET_RXFILTERWOLSTATUS_AMW          0x00000004	/*!< Multicast Frame caused WoL */
+#define ENET_RXFILTERWOLSTATUS_AUHW         0x00000008	/*!< Unicast Hash Filter Frame WoL */
+#define ENET_RXFILTERWOLSTATUS_AMHW         0x00000010	/*!< Multicast Hash Filter Frame WoL */
+#define ENET_RXFILTERWOLSTATUS_APW          0x00000020	/*!< Perfect Filter WoL */
+#define ENET_RXFILTERWOLSTATUS_RFW          0x00000080	/*!< RX Filter caused WoL */
+#define ENET_RXFILTERWOLSTATUS_MPW          0x00000100	/*!< Magic Packet Filter caused WoL */
+#define ENET_RXFILTERWOLSTATUS_BITMASK      0x01BF		/*!< Receive Filter WoL Status/Clear bitmasl value */
+
+/*
+ * @brief Interrupt Status/Enable/Clear/Set Register bit definitions
+ */
+#define ENET_INT_RXOVERRUN      0x00000001	/*!< Overrun Error in RX Queue */
+#define ENET_INT_RXERROR        0x00000002	/*!< Receive Error */
+#define ENET_INT_RXFINISHED     0x00000004	/*!< RX Finished Process Descriptors */
+#define ENET_INT_RXDONE         0x00000008	/*!< Receive Done */
+#define ENET_INT_TXUNDERRUN     0x00000010	/*!< Transmit Underrun */
+#define ENET_INT_TXERROR        0x00000020	/*!< Transmit Error */
+#define ENET_INT_TXFINISHED     0x00000040	/*!< TX Finished Process Descriptors */
+#define ENET_INT_TXDONE         0x00000080	/*!< Transmit Done */
+#define ENET_INT_SOFT           0x00001000	/*!< Software Triggered Interrupt */
+#define ENET_INT_WAKEUP         0x00002000	/*!< Wakeup Event Interrupt */
+
+/*
+ * @brief Power Down Register bit definitions
+ */
+#define ENET_POWERDOWN_PD 0x80000000	/*!< Power Down MAC */
+
+/**
+ * @brief RX Descriptor structure
+ */
+typedef struct {
+	uint32_t Packet;		/*!< Base address of the data buffer for storing receive data */
+	uint32_t Control;		/*!< Control information */
+} ENET_RXDESC_T;
+
+/**
+ * @brief RX Descriptor Control structure type definition
+ */
+#define ENET_RCTRL_SIZE(n)       (((n) - 1) & 0x7FF)	/*!< Buffer size field */
+#define ENET_RCTRL_INT           0x80000000				/*!< Generate RxDone Interrupt */
+
+/**
+ * @brief RX Status structure
+ */
+typedef struct {
+	uint32_t StatusInfo;		/*!< Receive status return flags.*/
+	uint32_t StatusHashCRC;		/*!< The concatenation of the destination address hash CRC and the source
+								   address hash CRC */
+} ENET_RXSTAT_T;
+
+/*
+ * @brief RX Status Hash CRC Word definition
+ */
+#define ENET_RHASH_SA            0x000001FF				/*!< Hash CRC for Source Address */
+#define ENET_RHASH_DA            0x001FF000				/*!< Hash CRC for Destination Address */
+
+/* RX Status Information Word */
+#define ENET_RINFO_SIZE(n)       (((n) & 0x7FF) + 1)	/*!< Data size in bytes */
+#define ENET_RINFO_CTRL_FRAME    0x00040000				/*!< Control Frame */
+#define ENET_RINFO_VLAN          0x00080000				/*!< VLAN Frame */
+#define ENET_RINFO_FAIL_FILT     0x00100000				/*!< RX Filter Failed */
+#define ENET_RINFO_MCAST         0x00200000				/*!< Multicast Frame */
+#define ENET_RINFO_BCAST         0x00400000				/*!< Broadcast Frame */
+#define ENET_RINFO_CRC_ERR       0x00800000				/*!< CRC Error in Frame */
+#define ENET_RINFO_SYM_ERR       0x01000000				/*!< Symbol Error from PHY */
+#define ENET_RINFO_LEN_ERR       0x02000000				/*!< Length Error */
+#define ENET_RINFO_RANGE_ERR     0x04000000				/*!< Range Error (exceeded max. size) */
+#define ENET_RINFO_ALIGN_ERR     0x08000000				/*!< Alignment Error */
+#define ENET_RINFO_OVERRUN       0x10000000				/*!< Receive overrun */
+#define ENET_RINFO_NO_DESCR      0x20000000				/*!< No new Descriptor available */
+#define ENET_RINFO_LAST_FLAG     0x40000000				/*!< Last Fragment in Frame */
+#define ENET_RINFO_ERR           0x80000000				/*!< Error Occured (OR of all errors) */
+/** RX Error status mask */
+#define ENET_RINFO_ERR_MASK     (ENET_RINFO_FAIL_FILT | ENET_RINFO_CRC_ERR   | ENET_RINFO_SYM_ERR |	\
+								 ENET_RINFO_LEN_ERR   | ENET_RINFO_ALIGN_ERR | ENET_RINFO_OVERRUN)
+
+/**
+ * @brief TX Descriptor structure
+ */
+typedef struct {
+	uint32_t Packet;	/*!< Base address of the data buffer containing transmit data */
+	uint32_t Control;	/*!< Control information */
+} ENET_TXDESC_T;
+
+/*
+ * @brief TX Descriptor Control structure type definition
+ */
+#define ENET_TCTRL_SIZE(n)       (((n) - 1) & 0x7FF)	/*!< Size of data buffer in bytes */
+#define ENET_TCTRL_OVERRIDE      0x04000000				/*!< Override Default MAC Registers */
+#define ENET_TCTRL_HUGE          0x08000000				/*!< Enable Huge Frame */
+#define ENET_TCTRL_PAD           0x10000000				/*!< Pad short Frames to 64 bytes */
+#define ENET_TCTRL_CRC           0x20000000				/*!< Append a hardware CRC to Frame */
+#define ENET_TCTRL_LAST          0x40000000				/*!< Last Descriptor for TX Frame */
+#define ENET_TCTRL_INT           0x80000000				/*!< Generate TxDone Interrupt */
+
+/**
+ * @brief TX Status structure
+ */
+typedef struct {
+	uint32_t StatusInfo;	/*!< Receive status return flags.*/
+} ENET_TXSTAT_T;
+
+/* TX Status Information Word */
+#define ENET_TINFO_COL_CNT       0x01E00000		/*!< Collision Count */
+#define ENET_TINFO_DEFER         0x02000000		/*!< Packet Deferred (not an error) */
+#define ENET_TINFO_EXCESS_DEF    0x04000000		/*!< Excessive Deferral */
+#define ENET_TINFO_EXCESS_COL    0x08000000		/*!< Excessive Collision */
+#define ENET_TINFO_LATE_COL      0x10000000		/*!< Late Collision Occured */
+#define ENET_TINFO_UNDERRUN      0x20000000		/*!< Transmit Underrun */
+#define ENET_TINFO_NO_DESCR      0x40000000		/*!< No new Descriptor available */
+#define ENET_TINFO_ERR           0x80000000		/*!< Error Occured (OR of all errors) */
+
+/**
+ * @brief Maximum size of an ethernet buffer
+ */
+#define ENET_ETH_MAX_FLEN (1536)
+
+/**
+ * @brief ENET Buffer status definition
+ */
+typedef enum {
+	ENET_BUFF_EMPTY,			/* buffer is empty */
+	ENET_BUFF_PARTIAL_FULL,		/* buffer contains some packets */
+	ENET_BUFF_FULL,				/* buffer is full */
+} ENET_BUFF_STATUS_T;
+
+/**
+ * @brief	Resets the ethernet interface
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ * @note	Resets the ethernet interface. This should be called prior to
+ * Chip_ENET_Init with a small delay after this call.
+ */
+STATIC INLINE void Chip_ENET_Reset(LPC_ENET_T *pENET)
+{
+	/* This should be called prior to IP_ENET_Init. The MAC controller may
+	   not be ready for a call to init right away so a small delay should
+	   occur after this call. */
+	pENET->MAC.MAC1 = ENET_MAC1_RESETTX | ENET_MAC1_RESETMCSTX | ENET_MAC1_RESETRX |
+					  ENET_MAC1_RESETMCSRX | ENET_MAC1_SIMRESET | ENET_MAC1_SOFTRESET;
+	pENET->CONTROL.COMMAND = ENET_COMMAND_REGRESET | ENET_COMMAND_TXRESET | ENET_COMMAND_RXRESET |
+							 ENET_COMMAND_PASSRUNTFRAME;
+}
+
+/**
+ * @brief	Sets the address of the interface
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	macAddr	: Pointer to the 6 bytes used for the MAC address
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_SetADDR(LPC_ENET_T *pENET, const uint8_t *macAddr)
+{
+	/* Save MAC address */
+	pENET->MAC.SA[0] = ((uint32_t) macAddr[5] << 8) | ((uint32_t) macAddr[4]);
+	pENET->MAC.SA[1] = ((uint32_t) macAddr[3] << 8) | ((uint32_t) macAddr[2]);
+	pENET->MAC.SA[2] = ((uint32_t) macAddr[1] << 8) | ((uint32_t) macAddr[0]);
+}
+
+/**
+ * @brief	Sets up the PHY link clock divider and PHY address
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	div		: Divider index, not a divider value, see user manual
+ * @param	addr	: PHY address, used with MII read and write
+ * @return	Nothing
+ * @note	The MII clock divider rate is divided from the peripheral clock returned
+ * from the Chip_Clock_GetSystemClockRate() function. Use Chip_ENET_FindMIIDiv()
+ * with a desired clock rate to find the correct divider index value.
+ */
+void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr);
+
+/**
+ * @brief	Starts a PHY write via the MII
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	reg		: PHY register to write
+ * @param	data	: Data to write to PHY register
+ * @return	Nothing
+ * @note	Start a PHY write operation. Does not block, requires calling
+ * IP_ENET_IsMIIBusy to determine when write is complete.
+ */
+void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data);
+
+/**
+ * @brief	Starts a PHY read via the MII
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	reg		: PHY register to read
+ * @return	Nothing
+ * @note	Start a PHY read operation. Does not block, requires calling
+ * IP_ENET_IsMIIBusy to determine when read is complete and calling
+ * IP_ENET_ReadMIIData to get the data.
+ */
+void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg);
+
+/**
+ * @brief	Returns MII link (PHY) busy status
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Returns true if busy, otherwise false
+ */
+STATIC INLINE bool Chip_ENET_IsMIIBusy(LPC_ENET_T *pENET)
+{
+	return (pENET->MAC.MIND & ENET_MIND_BUSY) ? true : false;
+}
+
+/**
+ * @brief	Returns the value read from the PHY
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Read value from PHY
+ */
+uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET);
+
+/**
+ * @brief	Enables ethernet transmit
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_TXEnable(LPC_ENET_T *pENET)
+{
+	/* Descriptor list head pointers must be setup prior to enable */
+	pENET->CONTROL.COMMAND |= ENET_COMMAND_TXENABLE;
+}
+
+/**
+ * @brief Disables ethernet transmit
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_TXDisable(LPC_ENET_T *pENET)
+{
+	pENET->CONTROL.COMMAND &= ~ENET_COMMAND_TXENABLE;
+}
+
+/**
+ * @brief	Enables ethernet packet reception
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_RXEnable(LPC_ENET_T *pENET)
+{
+	/* Descriptor list head pointers must be setup prior to enable */
+	pENET->CONTROL.COMMAND |= ENET_COMMAND_RXENABLE;
+	pENET->MAC.MAC1 |= ENET_MAC1_RXENABLE;
+}
+
+/**
+ * @brief	Disables ethernet packet reception
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
+{
+	pENET->CONTROL.COMMAND &= ~ENET_COMMAND_RXENABLE;
+	pENET->MAC.MAC1 &= ~ENET_MAC1_RXENABLE;
+}
+
+/**
+ * @brief	Reset Tx Logic
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_ResetTXLogic(LPC_ENET_T *pENET)
+{
+	pENET->MAC.MAC1 |= ENET_MAC1_RESETTX;
+}
+
+/**
+ * @brief	Reset Rx Logic
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_ResetRXLogic(LPC_ENET_T *pENET)
+{
+	pENET->MAC.MAC1 |= ENET_MAC1_RESETRX;
+}
+
+/**
+ * @brief	Enable Rx Filter
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	mask	: Filter mask (Or-ed bit values of ENET_RXFILTERCTRL_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_EnableRXFilter(LPC_ENET_T *pENET, uint32_t mask)
+{
+	pENET->CONTROL.COMMAND &= ~ENET_COMMAND_PASSRXFILTER;
+	pENET->RXFILTER.CONTROL |=  mask;
+}
+
+/**
+ * @brief	Disable Rx Filter
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	mask	: Filter mask (Or-ed bit values of ENET_RXFILTERCTRL_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_DisableRXFilter(LPC_ENET_T *pENET, uint32_t mask)
+{
+	pENET->RXFILTER.CONTROL &= ~mask;
+}
+
+/**
+ * @brief	Sets full duplex operation for the interface
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_ENET_SetFullDuplex(LPC_ENET_T *pENET);
+
+/**
+ * @brief	Sets half duplex operation for the interface
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_ENET_SetHalfDuplex(LPC_ENET_T *pENET);
+
+/**
+ * @brief	Selects 100Mbps for the current speed
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_Set100Mbps(LPC_ENET_T *pENET)
+{
+	pENET->MAC.SUPP = ENET_SUPP_100Mbps_SPEED;
+}
+
+/**
+ * @brief	Selects 10Mbps for the current speed
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_Set10Mbps(LPC_ENET_T *pENET)
+{
+	pENET->MAC.SUPP = 0;
+}
+
+/**
+ * @brief	Configures the initial ethernet transmit descriptors
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	pDescs	: Pointer to TX descriptor list
+ * @param	pStatus	: Pointer to TX status list
+ * @param	descNum	: the number of desciptors
+ * @return	Nothing
+ */
+void Chip_ENET_InitTxDescriptors(LPC_ENET_T *pENET, ENET_TXDESC_T *pDescs,
+								 ENET_TXSTAT_T *pStatus,
+								 uint32_t descNum);
+
+/**
+ * @brief	Configures the initial ethernet receive descriptors
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	pDescs	: Pointer to TX descriptor list
+ * @param	pStatus	: Pointer to TX status list
+ * @param	descNum	: the number of desciptors
+ * @return	Nothing
+ */
+void Chip_ENET_InitRxDescriptors(LPC_ENET_T *pENET, ENET_RXDESC_T *pDescs,
+								 ENET_RXSTAT_T *pStatus,
+								 uint32_t descNum);
+
+/**
+ * @brief	Get the current Tx Produce Descriptor Index
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Tx Produce Index
+ */
+STATIC INLINE uint16_t Chip_ENET_GetTXProduceIndex(LPC_ENET_T *pENET)
+{
+	return pENET->CONTROL.TX.PRODUCEINDEX;
+}
+
+/**
+ * @brief	Get the current Tx Consume Descriptor Index
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Tx Consume Index
+ */
+STATIC INLINE uint16_t Chip_ENET_GetTXConsumeIndex(LPC_ENET_T *pENET)
+{
+	return pENET->CONTROL.TX.CONSUMEINDEX;
+}
+
+/**
+ * @brief	Get the current Rx Produce Descriptor Index
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Rx Produce Index
+ */
+STATIC INLINE uint16_t Chip_ENET_GetRXProduceIndex(LPC_ENET_T *pENET)
+{
+	return pENET->CONTROL.RX.PRODUCEINDEX;
+}
+
+/**
+ * @brief	Get the current Rx Consume Descriptor Index
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Rx Consume Index
+ */
+STATIC INLINE uint16_t Chip_ENET_GetRXConsumeIndex(LPC_ENET_T *pENET)
+{
+	return pENET->CONTROL.RX.CONSUMEINDEX;
+}
+
+/**
+ * @brief	Get the buffer status with the current Produce Index and Consume Index
+ * @param	pENET			: The base of ENET peripheral on the chip
+ * @param	produceIndex	: Produce Index
+ * @param	consumeIndex	: Consume Index
+ * @param	buffSize		: Buffer size
+ * @return	Status (One of status value: ENET_BUFF_EMPTY/ENET_BUFF_FULL/ENET_BUFF_PARTIAL_FULL)
+ */
+ENET_BUFF_STATUS_T Chip_ENET_GetBufferStatus(LPC_ENET_T *pENET, uint16_t produceIndex,
+											 uint16_t consumeIndex,
+											 uint16_t buffSize);
+
+/**
+ * @brief	Get the number of descriptors filled
+ * @param	pENET			: The base of ENET peripheral on the chip
+ * @param	produceIndex	: Produce Index
+ * @param	consumeIndex	: Consume Index
+ * @param	buffSize		: Buffer size
+ * @return	the number of descriptors
+ */
+uint32_t Chip_ENET_GetFillDescNum(LPC_ENET_T *pENET, uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize);
+
+/**
+ * @brief	Get the number of free descriptors
+ * @param	pENET			: The base of ENET peripheral on the chip
+ * @param	produceIndex	: Produce Index
+ * @param	consumeIndex	: Consume Index
+ * @param	buffSize		: Buffer size
+ * @return	the number of descriptors
+ */
+STATIC INLINE uint32_t Chip_ENET_GetFreeDescNum(LPC_ENET_T *pENET,
+												uint16_t produceIndex,
+												uint16_t consumeIndex,
+												uint16_t buffSize)
+{
+	return buffSize - 1 - Chip_ENET_GetFillDescNum(pENET, produceIndex, consumeIndex, buffSize);
+}
+
+/**
+ * @brief	Check if Tx buffer is full
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	true/false
+ */
+STATIC INLINE bool Chip_ENET_IsTxFull(LPC_ENET_T *pENET)
+{
+	return ((pENET->CONTROL.TX.CONSUMEINDEX == (pENET->CONTROL.TX.PRODUCEINDEX + 1)) ||
+			((pENET->CONTROL.TX.CONSUMEINDEX == 0) &&
+			 (pENET->CONTROL.TX.PRODUCEINDEX == pENET->CONTROL.TX.DESCRIPTORNUMBER))) ? true : false;
+}
+
+/**
+ * @brief	Check if Rx buffer is empty
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	true/false
+ */
+STATIC INLINE bool Chip_ENET_IsRxEmpty(LPC_ENET_T *pENET)
+{
+	uint32_t tem = pENET->CONTROL.RX.PRODUCEINDEX;
+	return (pENET->CONTROL.RX.CONSUMEINDEX != tem) ? false : true;
+}
+
+/**
+ * @brief	Increase the current Tx Produce Descriptor Index
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	The new index value
+ */
+uint16_t Chip_ENET_IncTXProduceIndex(LPC_ENET_T *pENET);
+
+/**
+ * @brief	Increase the current Rx Consume Descriptor Index
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	The new index value
+ */
+uint16_t Chip_ENET_IncRXConsumeIndex(LPC_ENET_T *pENET);
+
+/**
+ * @brief	Enable ENET interrupts
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	mask	: Interrupt mask  (Or-ed bit values of ENET_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_EnableInt(LPC_ENET_T *pENET, uint32_t mask)
+{
+	pENET->MODULE_CONTROL.INTENABLE |= mask;
+}
+
+/**
+ * @brief	Disable ENET interrupts
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	mask	: Interrupt mask  (Or-ed bit values of ENET_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_DisableInt(LPC_ENET_T *pENET, uint32_t mask)
+{
+	pENET->MODULE_CONTROL.INTENABLE &= ~mask;
+}
+
+/**
+ * @brief	Get the interrupt status
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	interrupt status (Or-ed bit values of ENET_INT_*)
+ */
+STATIC INLINE uint32_t Chip_ENET_GetIntStatus(LPC_ENET_T *pENET)
+{
+	return pENET->MODULE_CONTROL.INTSTATUS;
+}
+
+/**
+ * @brief	Clear the interrupt status
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	mask	: Interrupt mask  (Or-ed bit values of ENET_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_ENET_ClearIntStatus(LPC_ENET_T *pENET, uint32_t mask)
+{
+	pENET->MODULE_CONTROL.INTCLEAR = mask;
+}
+
+/**
+ * @brief	Initialize ethernet interface
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @param	useRMII	: true to setup interface for RMII, false for MII
+ * @return	Nothing
+ * @note	Performs basic initialization of the ethernet interface in a default
+ * state. This is enough to place the interface in a usable state, but
+ * may require more setup outside this function.
+ */
+void Chip_ENET_Init(LPC_ENET_T *pENET, bool useRMII);
+
+/**
+ * @brief	De-initialize the ethernet interface
+ * @param	pENET	: The base of ENET peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_ENET_DeInit(LPC_ENET_T *pENET);
+
+/**
+ * @brief	Find the divider index for a desired MII clock rate
+ * @param	pENET		: The base of ENET peripheral on the chip
+ * @param	clockRate	: Clock rate to get divider index for
+ * @return	MII divider index to get the closest clock rate for clockRate
+ * @note	Use this function to get a divider index for the Chip_ENET_SetupMII()
+ * function determined from the desired MII clock rate.
+ */
+uint32_t Chip_ENET_FindMIIDiv(LPC_ENET_T *pENET, uint32_t clockRate);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ENET_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/error.h b/hw/mcu/nxp/lpc_chip_40xx/inc/error.h
new file mode 100644
index 000000000..ee6c62b86
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/error.h
@@ -0,0 +1,184 @@
+/*
+ * @brief Error code returned by Boot ROM drivers/library functions
+ *  @ingroup Common
+ *
+ *  This file contains unified error codes to be used across driver,
+ *  middleware, applications, hal and demo software.
+ *
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_ERROR_H__
+#define __LPC_ERROR_H__
+
+/** Error code returned by Boot ROM drivers/library functions
+ *
+ *  Error codes are a 32-bit value with :
+ *      - The 16 MSB contains the peripheral code number
+ *      - The 16 LSB contains an error code number associated to that peripheral
+ *
+ */
+typedef enum {
+	/**\b 0x00000000*/ LPC_OK = 0,	/**< enum value returned on Success */
+	/**\b 0xFFFFFFFF*/ ERR_FAILED = -1,	/**< enum value returned on general failure */
+	/**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2,	/**< enum value returned on general timeout */
+	/**\b 0xFFFFFFFD*/ ERR_BUSY = -3,	/**< enum value returned when resource is busy */
+
+	/* ISP related errors */
+	ERR_ISP_BASE = 0x00000000,
+	/*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
+	/*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR,	/* Source address not on word boundary */
+	/*0x00000003*/ ERR_ISP_DST_ADDR_ERROR,	/* Destination address not on word or 256 byte boundary */
+	/*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
+	/*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
+	/*0x00000006*/ ERR_ISP_COUNT_ERROR,	/* Byte count is not multiple of 4 or is not a permitted value */
+	/*0x00000007*/ ERR_ISP_INVALID_SECTOR,
+	/*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
+	/*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
+	/*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
+	/*0x0000000B*/ ERR_ISP_BUSY,/* Flash programming hardware interface is busy */
+	/*0x0000000C*/ ERR_ISP_PARAM_ERROR,	/* Insufficient number of parameters */
+	/*0x0000000D*/ ERR_ISP_ADDR_ERROR,	/* Address not on word boundary */
+	/*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
+	/*0x0000000F*/ ERR_ISP_CMD_LOCKED,	/* Command is locked */
+	/*0x00000010*/ ERR_ISP_INVALID_CODE,/* Unlock code is invalid */
+	/*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
+	/*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
+	/*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
+
+	/* ROM API related errors */
+	ERR_API_BASE = 0x00010000,
+	/**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1,	/**< Invalid parameters*/
+	/**\b 0x00010002*/ ERR_API_INVALID_PARAM1,	/**< PARAM1 is invalid */
+	/**\b 0x00010003*/ ERR_API_INVALID_PARAM2,	/**< PARAM2 is invalid */
+	/**\b 0x00010004*/ ERR_API_INVALID_PARAM3,	/**< PARAM3 is invalid */
+	/**\b 0x00010005*/ ERR_API_MOD_INIT,/**< API is called before module init */
+
+	/* SPIFI API related errors */
+	ERR_SPIFI_BASE = 0x00020000,
+	/*0x00020001*/ ERR_SPIFI_DEVICE_ERROR = ERR_SPIFI_BASE + 1,
+	/*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
+	/*0x00020003*/ ERR_SPIFI_TIMEOUT,
+	/*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
+	/*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
+	/*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
+	/*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
+	/*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
+	/*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
+
+	/* Security API related errors */
+	ERR_SEC_BASE = 0x00030000,
+	/*0x00030001*/ ERR_SEC_AES_WRONG_CMD = ERR_SEC_BASE + 1,
+	/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
+	/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
+
+	/* USB device stack related errors */
+	ERR_USBD_BASE = 0x00040000,
+	/**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1,/**< invalid request */
+	/**\b 0x00040002*/ ERR_USBD_UNHANDLED,	/**< Callback did not process the event */
+	/**\b 0x00040003*/ ERR_USBD_STALL,	/**< Stall the endpoint on which the call back is called */
+	/**\b 0x00040004*/ ERR_USBD_SEND_ZLP,	/**< Send ZLP packet on the endpoint on which the call back is called */
+	/**\b 0x00040005*/ ERR_USBD_SEND_DATA,	/**< Send data packet on the endpoint on which the call back is called */
+	/**\b 0x00040006*/ ERR_USBD_BAD_DESC,	/**< Bad descriptor*/
+	/**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,	/**< Bad config descriptor*/
+	/**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,	/**< Bad interface descriptor*/
+	/**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
+	/**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF,/**< Bad alignment of buffer passed. */
+	/**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR,/**< Too many class handlers. */
+
+	/* CGU  related errors */
+	ERR_CGU_BASE = 0x00050000,
+	/*0x00050001*/ ERR_CGU_NOT_IMPL = ERR_CGU_BASE + 1,
+	/*0x00050002*/ ERR_CGU_INVALID_PARAM,
+	/*0x00050003*/ ERR_CGU_INVALID_SLICE,
+	/*0x00050004*/ ERR_CGU_OUTPUT_GEN,
+	/*0x00050005*/ ERR_CGU_DIV_SRC,
+	/*0x00050006*/ ERR_CGU_DIV_VAL,
+	/*0x00050007*/ ERR_CGU_SRC,
+
+	/* I2C related errors */
+	ERR_I2C_BASE = 0x00060000,
+	/*0x00060001*/ ERR_I2C_NAK = ERR_I2C_BASE + 1,
+	/*0x00060002*/ ERR_I2C_BUFFER_OVERFLOW,
+	/*0x00060003*/ ERR_I2C_BYTE_COUNT_ERR,
+	/*0x00060004*/ ERR_I2C_LOSS_OF_ARBRITRATION,
+	/*0x00060005*/ ERR_I2C_SLAVE_NOT_ADDRESSED,
+	/*0x00060006*/ ERR_I2C_LOSS_OF_ARBRITRATION_NAK_BIT,
+	/*0x00060007*/ ERR_I2C_GENERAL_FAILURE,
+	/*0x00060008*/ ERR_I2C_REGS_SET_TO_DEFAULT,
+	/*0x00060009*/ ERR_I2C_TIMEOUT,
+	/*0x0006000A*/ ERR_I2C_BUFFER_UNDERFLOW,
+
+	/* UART related errors */
+	ERR_UART_BASE = 0x00080000,
+	/**\b 0x00080001*/ ERR_UART_RXD_BUSY = ERR_UART_BASE + 1, /*!< Receive is busy */
+	/**\b 0x00080002*/ ERR_UART_TXD_BUSY, /*!< Transmit is busy */
+	/**\b 0x00080003*/ ERR_UART_OVERRUN_FRAME_PARITY_NOISE, /*!< Overrun, Frame, Parity , Receive Noise error */
+	/**\b 0x00080004*/ ERR_UART_UNDERRUN, /*!< Underrun */
+	/**\b 0x00080005*/ ERR_UART_PARAM, /*!< Parameter error */
+
+	ERR_DMA_BASE = 0x000D0000,
+	/*0x000D0001*/ ERR_DMA_ERROR_INT = ERR_DMA_BASE + 1,
+	/*0x000D0002*/ ERR_DMA_CHANNEL_NUMBER,
+	/*0x000D0003*/ ERR_DMA_CHANNEL_DISABLED,
+	/*0x000D0004*/ ERR_DMA_BUSY,
+	/*0x000D0005*/ ERR_DMA_NOT_ALIGNMENT,
+	/*0x000D0006*/ ERR_DMA_PING_PONG_EN,
+	/*0x000D0007*/ ERR_DMA_CHANNEL_VALID_PENDING,
+	
+	/* SPI related errors */
+	ERR_SPI_BASE = 0x000E0000,
+	/*0x000E0001*/ ERR_SPI_RXOVERRUN=ERR_SPI_BASE+1,
+	/*0x000E0002*/ ERR_SPI_TXUNDERRUN,
+	/*0x000E0003*/ ERR_SPI_SELNASSERT,
+	/*0x000E0004*/ ERR_SPI_SELNDEASSERT,
+	/*0x000E0005*/ ERR_SPI_CLKSTALL,
+	/*0x000E0006*/ ERR_SPI_PARAM,
+	/*0x000E0007*/ ERR_SPI_INVALID_LENGTH,
+
+	/* ADC related errors */
+	ERR_ADC_BASE = 0x000F0000,
+	/*0x000F0001*/ ERR_ADC_OVERRUN = ERR_ADC_BASE + 1,
+	/*0x000F0002*/ ERR_ADC_INVALID_CHANNEL,
+	/*0x000F0003*/ ERR_ADC_INVALID_SEQUENCE,
+	/*0x000F0004*/ ERR_ADC_INVALID_SETUP,
+	/*0x000F0005*/ ERR_ADC_PARAM,
+	/*0x000F0006*/ ERR_ADC_INVALID_LENGTH,
+	/*0x000F0007*/ ERR_ADC_NO_POWER
+} ErrorCode_t;
+
+#ifndef offsetof
+#define offsetof(s, m)   (int) &(((s *) 0)->m)
+#endif
+
+#define COMPILE_TIME_ASSERT(pred)    switch (0) { \
+	case 0:	\
+	case pred:; }
+
+#endif /* __LPC_ERROR_H__ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/fmc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/fmc_17xx_40xx.h
new file mode 100644
index 000000000..83979408b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/fmc_17xx_40xx.h
@@ -0,0 +1,133 @@
+/*
+ * @brief LPC17xx/40xx FLASH Memory Controller (FMC) driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FMC_17XX_40XX_H_
+#define __FMC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup FMC_17XX_40XX CHIP: LPC17xx/40xx FLASH Memory Controller driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief FLASH Memory Controller Unit register block structure
+ */
+typedef struct {		/*!< FMC Structure */
+	__I  uint32_t  RESERVED1[8];
+	__IO uint32_t  FMSSTART;
+	__IO uint32_t  FMSSTOP;
+	__I  uint32_t  RESERVED3;
+	__I  uint32_t  FMSW[4];
+	__I  uint32_t  RESERVED4[1001];
+	__I  uint32_t  FMSTAT;
+	__I  uint32_t  RESERVED5;
+	__O  uint32_t  FMSTATCLR;
+} LPC_FMC_T;
+
+/* Flash signature start and busy status bit */
+#define FMC_FLASHSIG_BUSY       (1UL << 17)
+
+/* Flash signature clear status bit */
+#define FMC_FLASHSIG_STAT       (1 << 2)
+
+/**
+ * @brief	Start computation of a signature for a FLASH memory range
+ * @param	start	: Starting FLASH address for computation, must be aligned on 16 byte boundary
+ * @param	stop	: Ending FLASH address for computation, must be aligned on 16 byte boundary
+ * @return	Nothing
+ * @note	Only bits 20..4 are used for the FLASH signature computation.
+ *			Use the Chip_FMC_IsSignatureBusy() function to determine when the
+ *			signature computation operation is complete and use the
+ *			Chip_FMC_GetSignature() function to get the computed signature.
+ */
+STATIC INLINE void Chip_FMC_ComputeSignature(uint32_t start, uint32_t stop)
+{
+	LPC_FMC->FMSSTART = (start >> 4);
+	LPC_FMC->FMSTATCLR = FMC_FLASHSIG_STAT;
+	LPC_FMC->FMSSTOP = (stop >> 4) | FMC_FLASHSIG_BUSY;
+}
+
+/**
+ * @brief	Start computation of a signature for a FLASH memory address and block count
+ * @param	start	: Starting FLASH address for computation, must be aligned on 16 byte boundary
+ * @param	blocks	: Number of 16 byte blocks used for computation
+ * @return	Nothing
+ * @note	Only bits 20..4 are used for the FLASH signature computation.
+ *			Use the Chip_FMC_IsSignatureBusy() function to determine when the
+ *			signature computation operation is complete and the
+ *			Chip_FMC_GetSignature() function to get the computed signature.
+ */
+STATIC INLINE void Chip_FMC_ComputeSignatureBlocks(uint32_t start, uint32_t blocks)
+{
+	Chip_FMC_ComputeSignature(start, (start + (blocks * 16)));
+}
+
+/**
+ * @brief	Clear signature generation completion flag
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_FMC_ClearSignatureBusy(void)
+{
+	LPC_FMC->FMSTATCLR = FMC_FLASHSIG_STAT;
+}
+
+/**
+ * @brief	Check for signature generation completion
+ * @return	true if the signature computation is running, false if finished
+ */
+STATIC INLINE bool Chip_FMC_IsSignatureBusy(void)
+{
+	return (bool) ((LPC_FMC->FMSTAT & FMC_FLASHSIG_STAT) == 0);
+}
+
+/**
+ * @brief	Returns the generated FLASH signature value
+ * @param	index	: Signature index to get - use 0 to FMSW0, 1 to FMSW1, etc.
+ * @return	the generated FLASH signature value
+ */
+STATIC INLINE uint32_t Chip_FMC_GetSignature(int index)
+{
+	return LPC_FMC->FMSW[index];
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FMC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/fpu_init.h b/hw/mcu/nxp/lpc_chip_40xx/inc/fpu_init.h
new file mode 100644
index 000000000..86e71c898
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/fpu_init.h
@@ -0,0 +1,52 @@
+/*
+ * @brief FPU init code
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __FPU_INIT_H_
+#define __FPU_INIT_H_
+
+/**
+ * @defgroup CHIP_FPU_CMX CHIP: FPU initialization
+ * @ingroup CHIP_Common
+ * Cortex FPU initialization
+ * @{
+ */
+
+/**
+ * @brief	Early initialization of the FPU
+ * @return	Nothing
+ */
+void fpuInit(void);
+
+/**
+ * @}
+ */
+
+#endif /* __FPU_INIT_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/gpdma_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/gpdma_17xx_40xx.h
new file mode 100644
index 000000000..8eea13402
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/gpdma_17xx_40xx.h
@@ -0,0 +1,450 @@
+/*
+ * @brief LPC17xx/40xx General Purpose DMA driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights. NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPDMA_17XX_40XX_H_
+#define __GPDMA_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPDMA_17XX_40XX CHIP: LPC17xx/40xx General Purpose DMA driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief Number of channels on GPDMA
+ */
+#define GPDMA_NUMBER_CHANNELS 8
+
+/**
+ * @brief GPDMA Channel register block structure
+ */
+typedef struct {
+	__IO uint32_t  SRCADDR;				/*!< DMA Channel Source Address Register */
+	__IO uint32_t  DESTADDR;			/*!< DMA Channel Destination Address Register */
+	__IO uint32_t  LLI;					/*!< DMA Channel Linked List Item Register */
+	__IO uint32_t  CONTROL;				/*!< DMA Channel Control Register */
+	__IO uint32_t  CONFIG;				/*!< DMA Channel Configuration Register */
+	__I  uint32_t  RESERVED1[3];
+} GPDMA_CH_T;
+
+/**
+ * @brief GPDMA register block
+ */
+typedef struct {						/*!< GPDMA Structure */
+	__I  uint32_t  INTSTAT;				/*!< DMA Interrupt Status Register */
+	__I  uint32_t  INTTCSTAT;			/*!< DMA Interrupt Terminal Count Request Status Register */
+	__O  uint32_t  INTTCCLEAR;			/*!< DMA Interrupt Terminal Count Request Clear Register */
+	__I  uint32_t  INTERRSTAT;			/*!< DMA Interrupt Error Status Register */
+	__O  uint32_t  INTERRCLR;			/*!< DMA Interrupt Error Clear Register */
+	__I  uint32_t  RAWINTTCSTAT;		/*!< DMA Raw Interrupt Terminal Count Status Register */
+	__I  uint32_t  RAWINTERRSTAT;		/*!< DMA Raw Error Interrupt Status Register */
+	__I  uint32_t  ENBLDCHNS;			/*!< DMA Enabled Channel Register */
+	__IO uint32_t  SOFTBREQ;			/*!< DMA Software Burst Request Register */
+	__IO uint32_t  SOFTSREQ;			/*!< DMA Software Single Request Register */
+	__IO uint32_t  SOFTLBREQ;			/*!< DMA Software Last Burst Request Register */
+	__IO uint32_t  SOFTLSREQ;			/*!< DMA Software Last Single Request Register */
+	__IO uint32_t  CONFIG;				/*!< DMA Configuration Register */
+	__IO uint32_t  SYNC;				/*!< DMA Synchronization Register */
+	__I  uint32_t  RESERVED0[50];
+	GPDMA_CH_T     CH[GPDMA_NUMBER_CHANNELS];
+} LPC_GPDMA_T;
+
+/**
+ * @brief Macro defines for DMA channel control registers
+ */
+#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))	/*!< Transfer size*/
+#define GPDMA_DMACCxControl_SBSize(n)       (((n & 0x07) << 12))	/*!< Source burst size*/
+#define GPDMA_DMACCxControl_DBSize(n)       (((n & 0x07) << 15))	/*!< Destination burst size*/
+#define GPDMA_DMACCxControl_SWidth(n)       (((n & 0x07) << 18))	/*!< Source transfer width*/
+#define GPDMA_DMACCxControl_DWidth(n)       (((n & 0x07) << 21))	/*!< Destination transfer width*/
+#define GPDMA_DMACCxControl_SI              ((1UL << 26))			/*!< Source increment*/
+#define GPDMA_DMACCxControl_DI              ((1UL << 27))			/*!< Destination increment*/
+#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1   0
+#define GPDMA_DMACCxControl_DestTransUseAHBMaster1  0
+#define GPDMA_DMACCxControl_Prot1           ((1UL << 28))			/*!< Indicates that the access is in user mode or privileged mode*/
+#define GPDMA_DMACCxControl_Prot2           ((1UL << 29))			/*!< Indicates that the access is bufferable or not bufferable*/
+#define GPDMA_DMACCxControl_Prot3           ((1UL << 30))			/*!< Indicates that the access is cacheable or not cacheable*/
+#define GPDMA_DMACCxControl_I               ((1UL << 31))			/*!< Terminal count interrupt enable bit */
+
+/**
+ * @brief Macro defines for DMA Configuration register
+ */
+#define GPDMA_DMACConfig_E              ((0x01))	/*!< DMA Controller enable*/
+#define GPDMA_DMACConfig_M              ((0x02))	/*!< AHB Master endianness configuration*/
+#define GPDMA_DMACConfig_BITMASK        ((0x03))
+
+/**
+ * @brief Macro defines for DMA Channel Configuration registers
+ */
+#define GPDMA_DMACCxConfig_E                    ((1UL << 0))			/*!< DMA control enable*/
+#define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n & 0x1F) << 1))		/*!< Source peripheral*/
+#define GPDMA_DMACCxConfig_DestPeripheral(n)    (((n & 0x1F) << 6))		/*!< Destination peripheral*/
+#define GPDMA_DMACCxConfig_TransferType(n)      (((n & 0x7) << 11))		/*!< This value indicates the type of transfer*/
+#define GPDMA_DMACCxConfig_IE                   ((1UL << 14))			/*!< Interrupt error mask*/
+#define GPDMA_DMACCxConfig_ITC                  ((1UL << 15))			/*!< Terminal count interrupt mask*/
+#define GPDMA_DMACCxConfig_L                    ((1UL << 16))			/*!< Lock*/
+#define GPDMA_DMACCxConfig_A                    ((1UL << 17))			/*!< Active*/
+#define GPDMA_DMACCxConfig_H                    ((1UL << 18))			/*!< Halt*/
+
+/**
+ * @brief GPDMA Interrupt Clear Status
+ */
+typedef enum {
+	GPDMA_STATCLR_INTTC,	/*!< GPDMA Interrupt Terminal Count Request Clear */
+	GPDMA_STATCLR_INTERR	/*!< GPDMA Interrupt Error Clear */
+} GPDMA_STATECLEAR_T;
+
+/**
+ * @brief GPDMA Type of Interrupt Status
+ */
+typedef enum {
+	GPDMA_STAT_INT,			/*!< GPDMA Interrupt Status */
+	GPDMA_STAT_INTTC,		/*!< GPDMA Interrupt Terminal Count Request Status */
+	GPDMA_STAT_INTERR,		/*!< GPDMA Interrupt Error Status */
+	GPDMA_STAT_RAWINTTC,	/*!< GPDMA Raw Interrupt Terminal Count Status */
+	GPDMA_STAT_RAWINTERR,	/*!< GPDMA Raw Error Interrupt Status */
+	GPDMA_STAT_ENABLED_CH	/*!< GPDMA Enabled Channel Status */
+} GPDMA_STATUS_T;
+
+/**
+ * @brief GPDMA Type of DMA controller
+ */
+typedef enum {
+	GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA              = ((0UL)),	/*!< Memory to memory - DMA control */
+	GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA              = ((1UL)),	/*!< Memory to peripheral - DMA control */
+	GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA              = ((2UL)),	/*!< Peripheral to memory - DMA control */
+	GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA              = ((3UL)),	/*!< Source peripheral to destination peripheral - DMA control */
+	GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL   = ((4UL)),	/*!< Source peripheral to destination peripheral - destination peripheral control */
+	GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL       = ((5UL)),	/*!< Memory to peripheral - peripheral control */
+	GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL       = ((6UL)),	/*!< Peripheral to memory - peripheral control */
+	GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL    = ((7UL))	/*!< Source peripheral to destination peripheral - source peripheral control */
+} GPDMA_FLOW_CONTROL_T;
+
+/**
+ * @brief GPDMA structure using for DMA configuration
+ */
+typedef struct {
+	uint32_t ChannelNum;	/*!< DMA channel number, should be in
+							 *  range from 0 to 7.
+							 *  Note: DMA channel 0 has the highest priority
+							 *  and DMA channel 7 the lowest priority.
+							 */
+	uint32_t TransferSize;	/*!< Length/Size of transfer */
+	uint32_t TransferWidth;	/*!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
+	uint32_t SrcAddr;		/*!< Physical Source Address, used in case TransferType is chosen as
+							 *   GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
+	uint32_t DstAddr;		/*!< Physical Destination Address, used in case TransferType is chosen as
+							 *   GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
+	uint32_t TransferType;	/*!< Transfer Type, should be one of the following:
+							 * - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
+							 * - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
+							 * - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
+							 * - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
+							 */
+} GPDMA_CH_CFG_T;
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+/**
+ * @brief GPDMA request connections
+ */
+#define GPDMA_CONN_MEMORY           ((0UL))         /*!< Memory */
+#define GPDMA_CONN_SDC              ((1UL))			/*!< SD card */
+#define GPDMA_CONN_SSP0_Tx          ((2UL))			/*!< SSP0 Tx */
+#define GPDMA_CONN_SSP0_Rx          ((3UL))			/*!< SSP0 Rx */
+#define GPDMA_CONN_SSP1_Tx          ((4UL))			/*!< SSP1 Tx */
+#define GPDMA_CONN_SSP1_Rx          ((5UL))			/*!< SSP1 Rx */
+#define GPDMA_CONN_SSP2_Tx          ((6UL))			/*!< SSP2 Tx */
+#define GPDMA_CONN_SSP2_Rx          ((7UL))			/*!< SSP2 Rx */
+#define GPDMA_CONN_ADC              ((8UL))			/*!< ADC */
+#define GPDMA_CONN_DAC              ((9UL))			/*!< DAC */
+#define GPDMA_CONN_UART0_Tx         ((10UL))		/*!< UART0 Tx */
+#define GPDMA_CONN_UART0_Rx         ((11UL))		/*!< UART0 Rx */
+#define GPDMA_CONN_UART1_Tx         ((12UL))		/*!< UART1 Tx */
+#define GPDMA_CONN_UART1_Rx         ((13UL))		/*!< UART1 Rx */
+#define GPDMA_CONN_UART2_Tx         ((14UL))		/*!< UART2 Tx */
+#define GPDMA_CONN_UART2_Rx         ((15UL))		/*!< UART2 Rx */
+#define GPDMA_CONN_MAT0_0           ((16UL))		/*!< MAT0.0 */
+#define GPDMA_CONN_MAT0_1           ((17UL))		/*!< MAT0.1 */
+#define GPDMA_CONN_MAT1_0           ((18UL))		/*!< MAT1.0 */
+#define GPDMA_CONN_MAT1_1           ((19UL))		/*!< MAT1.1 */
+#define GPDMA_CONN_MAT2_0           ((20UL))		/*!< MAT2.0 */
+#define GPDMA_CONN_MAT2_1           ((21UL))		/*!< MAT2.1 */
+#define GPDMA_CONN_I2S_Channel_0    ((22UL))		/*!< I2S channel 0 */
+#define GPDMA_CONN_I2S_Channel_1    ((23UL))		/*!< I2S channel 1 */
+#define GPDMA_CONN_UART3_Tx         ((26UL))		/*!< UART3 Tx */
+#define GPDMA_CONN_UART3_Rx         ((27UL))		/*!< UART3 Rx */
+#define GPDMA_CONN_UART4_Tx         ((28UL))		/*!< UART3 Tx */
+#define GPDMA_CONN_UART4_Rx         ((29UL))		/*!< UART3 Rx */
+#define GPDMA_CONN_MAT3_0           ((30UL))		/*!< MAT3.0 */
+#define GPDMA_CONN_MAT3_1           ((31UL))		/*!< MAT3.1 */
+
+#elif defined(CHIP_LPC175X_6X)
+/**
+ * @brief GPDMA request connections
+ */
+#define GPDMA_CONN_SSP0_Tx          ((0UL))			/**< SSP0 Tx */
+#define GPDMA_CONN_SSP0_Rx          ((1UL))			/**< SSP0 Rx */
+#define GPDMA_CONN_SSP1_Tx          ((2UL))			/**< SSP1 Tx */
+#define GPDMA_CONN_SSP1_Rx          ((3UL))			/**< SSP1 Rx */
+#define GPDMA_CONN_ADC              ((4UL))			/**< ADC */
+#define GPDMA_CONN_I2S_Channel_0    ((5UL))			/**< I2S channel 0 */
+#define GPDMA_CONN_I2S_Channel_1    ((6UL))			/**< I2S channel 1 */
+#define GPDMA_CONN_DAC              ((7UL))			/**< DAC */
+#define GPDMA_CONN_UART0_Tx         ((8UL))			/**< UART0 Tx */
+#define GPDMA_CONN_UART0_Rx         ((9UL))			/**< UART0 Rx */
+#define GPDMA_CONN_UART1_Tx         ((10UL))		/**< UART1 Tx */
+#define GPDMA_CONN_UART1_Rx         ((11UL))		/**< UART1 Rx */
+#define GPDMA_CONN_UART2_Tx         ((12UL))		/**< UART2 Tx */
+#define GPDMA_CONN_UART2_Rx         ((13UL))		/**< UART2 Rx */
+#define GPDMA_CONN_UART3_Tx         ((14UL))		/**< UART3 Tx */
+#define GPDMA_CONN_UART3_Rx         ((15UL))		/**< UART3 Rx */
+#define GPDMA_CONN_MAT0_0           ((16UL))		/**< MAT0.0 */
+#define GPDMA_CONN_MAT0_1           ((17UL))		/**< MAT0.1 */
+#define GPDMA_CONN_MAT1_0           ((18UL))		/**< MAT1.0 */
+#define GPDMA_CONN_MAT1_1           ((19UL))		/**< MAT1.1 */
+#define GPDMA_CONN_MAT2_0           ((20UL))		/**< MAT2.0 */
+#define GPDMA_CONN_MAT2_1           ((21UL))		/**< MAT2.1 */
+#define GPDMA_CONN_MAT3_0           ((22UL))		/**< MAT3.0 */
+#define GPDMA_CONN_MAT3_1           ((23UL))		/**< MAT3.1 */
+#define GPDMA_CONN_MEMORY           ((24UL))
+#endif
+
+/**
+ * @brief GPDMA Burst size in Source and Destination definitions
+ */
+#define GPDMA_BSIZE_1   ((0UL))	/*!< Burst size = 1 */
+#define GPDMA_BSIZE_4   ((1UL))	/*!< Burst size = 4 */
+#define GPDMA_BSIZE_8   ((2UL))	/*!< Burst size = 8 */
+#define GPDMA_BSIZE_16  ((3UL))	/*!< Burst size = 16 */
+#define GPDMA_BSIZE_32  ((4UL))	/*!< Burst size = 32 */
+#define GPDMA_BSIZE_64  ((5UL))	/*!< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL))	/*!< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL))	/*!< Burst size = 256 */
+
+/**
+ * @brief Width in Source transfer width and Destination transfer width definitions
+ */
+#define GPDMA_WIDTH_BYTE        ((0UL))	/*!< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD    ((1UL))	/*!< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD        ((2UL))	/*!< Width = 4 bytes */
+
+/**
+ * @brief Flow control definitions
+ */
+#define DMA_CONTROLLER 0		/*!< Flow control is DMA controller*/
+#define SRC_PER_CONTROLLER 1	/*!< Flow control is Source peripheral controller*/
+#define DST_PER_CONTROLLER 2	/*!< Flow control is Destination peripheral controller*/
+
+/**
+ * @brief DMA channel handle structure
+ */
+typedef struct {
+	FunctionalState ChannelStatus;	/*!< DMA channel status */
+} DMA_ChannelHandle_t;
+
+/**
+ * @brief Transfer Descriptor structure typedef
+ */
+typedef struct DMA_TransferDescriptor {
+	uint32_t src;	/*!< Source address */
+	uint32_t dst;	/*!< Destination address */
+	uint32_t lli;	/*!< Pointer to next descriptor structure */
+	uint32_t ctrl;	/*!< Control word that has transfer size, type etc. */
+} DMA_TransferDescriptor_t;
+
+/**
+ * @brief	Initialize the GPDMA
+ * @param	pGPDMA	: The base of GPDMA on the chip
+ * @return	Nothing
+ */
+void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);
+
+/**
+ * @brief	Shutdown the GPDMA
+ * @param	pGPDMA	: The base of GPDMA on the chip
+ * @return	Nothing
+ */
+void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);
+
+/**
+ * @brief	Initialize channel configuration strucutre
+ * @param	pGPDMA			: The base of GPDMA on the chip
+ * @param	GPDMACfg		: Pointer to configuration structure to be initialized
+ * @param	ChannelNum		: Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()*
+ * @param	src				: Address of Memory or one of GPDMA_CONN_MEMORY
+ *                              PeripheralConnection_ID , which is the source
+ * @param	dst				: Address of Memory or one of GPDMA_CONN_MEMORY
+ *                              PeripheralConnection_ID, which is the destination
+ * @param	Size			: The number of DMA transfers
+ * @param	TransferType	: Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
+ * @return	ERROR on error, SUCCESS on success
+ */
+int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
+							  GPDMA_CH_CFG_T *GPDMACfg,
+							  uint8_t  ChannelNum,
+							  uint32_t src,
+							  uint32_t dst,
+							  uint32_t Size,
+							  GPDMA_FLOW_CONTROL_T TransferType);
+
+/**
+ * @brief	Enable or Disable the GPDMA Channel
+ * @param	pGPDMA		: The base of GPDMA on the chip
+ * @param	channelNum	: The GPDMA channel : 0 - 7
+ * @param	NewState	: ENABLE to enable GPDMA or DISABLE to disable GPDMA
+ * @return	Nothing
+ */
+void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState);
+
+/**
+ * @brief	Stop a stream DMA transfer
+ * @param	pGPDMA		: The base of GPDMA on the chip
+ * @param	ChannelNum	: Channel Number to be closed
+ * @return	Nothing
+ */
+void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
+
+/**
+ * @brief	The GPDMA stream interrupt status checking
+ * @param	pGPDMA		: The base of GPDMA on the chip
+ * @param	ChannelNum	: Channel Number to be checked on interruption
+ * @return	Status:
+ *              - SUCCESS	: DMA transfer success
+ *              - ERROR		: DMA transfer failed
+ */
+Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
+
+/**
+ * @brief	Read the status from different registers according to the type
+ * @param	pGPDMA	: The base of GPDMA on the chip
+ * @param	type	: Status mode, should be:
+ *						- GPDMA_STAT_INT		: GPDMA Interrupt Status
+ *						- GPDMA_STAT_INTTC		: GPDMA Interrupt Terminal Count Request Status
+ *						- GPDMA_STAT_INTERR		: GPDMA Interrupt Error Status
+ *						- GPDMA_STAT_RAWINTTC	: GPDMA Raw Interrupt Terminal Count Status
+ *						- GPDMA_STAT_RAWINTERR	: GPDMA Raw Error Interrupt Status
+ *						- GPDMA_STAT_ENABLED_CH	: GPDMA Enabled Channel Status
+ * @param	channel	: The GPDMA channel : 0 - 7
+ * @return	SET is interrupt is pending or RESET if not pending
+ */
+IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel);
+
+/**
+ * @brief	Clear the Interrupt Flag from different registers according to the type
+ * @param	pGPDMA	: The base of GPDMA on the chip
+ * @param	type	: Flag mode, should be:
+ *						- GPDMA_STATCLR_INTTC	: GPDMA Interrupt Terminal Count Request
+ *						- GPDMA_STATCLR_INTERR	: GPDMA Interrupt Error
+ * @param	channel	: The GPDMA channel : 0 - 7
+ * @return	Nothing
+ */
+void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel);
+
+/**
+ * @brief	Get a free GPDMA channel for one DMA connection
+ * @param	pGPDMA					: The base of GPDMA on the chip
+ * @param	PeripheralConnection_ID	: Some chip fix each peripheral DMA connection on a specified channel ( have not used in 17xx/40xx )
+ * @return	The channel number which is selected
+ */
+uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA,
+								  uint32_t PeripheralConnection_ID);
+
+/**
+ * @brief	Do a DMA transfer M2M, M2P,P2M or P2P
+ * @param	pGPDMA		: The base of GPDMA on the chip
+ * @param	ChannelNum	: Channel used for transfer
+ * @param	src			: Address of Memory or PeripheralConnection_ID which is the source
+ * @param	dst			: Address of Memory or PeripheralConnection_ID which is the destination
+ * @param	TransferType: Select the transfer controller and the type of transfer. Should be:
+ *                               - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
+ *                               - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
+ * @param	Size		: The number of DMA transfers
+ * @return	ERROR on error, SUCCESS on success
+ */
+Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA,
+						   uint8_t ChannelNum,
+						   uint32_t src,
+						   uint32_t dst,
+						   GPDMA_FLOW_CONTROL_T TransferType,
+						   uint32_t Size);
+
+/**
+ * @brief	Do a DMA transfer using linked list of descriptors
+ * @param	pGPDMA			: The base of GPDMA on the chip
+ * @param	ChannelNum		: Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()*
+ * @param	DMADescriptor	: First node in the linked list of descriptors
+ * @param	TransferType	: Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
+ * @return	ERROR on error, SUCCESS on success
+ */
+Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
+							 uint8_t ChannelNum,
+							 const DMA_TransferDescriptor_t *DMADescriptor,
+							 GPDMA_FLOW_CONTROL_T TransferType);
+
+/**
+ * @brief	Prepare a single DMA descriptor
+ * @param	pGPDMA			: The base of GPDMA on the chip
+ * @param	DMADescriptor	: DMA Descriptor to be initialized
+ * @param	src				: Address of Memory or one of GPDMA_CONN_MEMORY
+ *                              PeripheralConnection_ID, which is the source
+ * @param	dst				: Address of Memory or one of GPDMA_CONN_MEMORY
+ *                              PeripheralConnection_ID, which is the destination
+ * @param	Size			: The number of DMA transfers
+ * @param	TransferType	: Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
+ * @param	NextDescriptor	: Pointer to next descriptor (0 if no more descriptors available)
+ * @return	ERROR on error, SUCCESS on success
+ */
+Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
+									DMA_TransferDescriptor_t *DMADescriptor,
+									uint32_t src,
+									uint32_t dst,
+									uint32_t Size,
+									GPDMA_FLOW_CONTROL_T TransferType,
+									const DMA_TransferDescriptor_t *NextDescriptor);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPDMA_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h
new file mode 100644
index 000000000..3ea66737b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h
@@ -0,0 +1,491 @@
+/*
+ * @brief LPC17xx/40xx GPIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIO_17XX_40XX_H_
+#define __GPIO_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIO_17XX_40XX CHIP: LPC17xx/40xx GPIO driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#define GPIO_PORT_BITS 32
+
+/**
+ * @brief GPIO port  (GPIO_PORT) for LPC175x_6x, LPC177x_8x and LPC407x_8x
+ */
+
+typedef struct {				/* GPIO_PORT Structure */
+	__IO uint32_t DIR;			/*!< Offset 0x0000: GPIO Port Direction control register */
+	uint32_t RESERVED0[3];
+	__IO uint32_t MASK;			/*!< Offset 0x0010: GPIO Mask register */
+	__IO uint32_t PIN;			/*!< Offset 0x0014: Pin value register using FIOMASK */
+	__IO uint32_t SET;			/*!< Offset 0x0018: Output Set register using FIOMASK */
+	__O  uint32_t CLR;			/*!< Offset 0x001C: Output Clear register using FIOMASK */
+} LPC_GPIO_T;
+
+/**
+ * @brief	Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/**
+ * @brief	De-Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/**
+ * @brief	Set a GPIO pin state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ * @note	This function replaces Chip_GPIO_WritePortBit()
+ */
+STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
+{
+	if (setting) {	/* Set Port */
+		pGPIO[port].SET |= 1UL << pin;
+	}
+	else {	/* Clear Port */
+		pGPIO[port].CLR |= 1UL << pin;
+	}
+}
+
+/**
+ * @brief	Set a GPIO port/bit state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
+{
+	Chip_GPIO_SetPinState(pGPIO, port, pin, setting);
+}
+
+/**
+ * @brief	Get a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: GPIO pin to get state for
+ * @return	true if the GPIO is high, false if low
+ * @note	This function replaces Chip_GPIO_ReadPortBit()
+ */
+STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (bool) ((pGPIO[port].PIN >> pin) & 1);
+}
+
+/**
+ * @brief	Read a GPIO state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	pin		: GPIO pin to read
+ * @return	true of the GPIO is high, false if low
+ * @note	It is recommended to use the Chip_GPIO_GetPinState() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin)
+{
+	return Chip_GPIO_GetPinState(pGPIO, port, pin);
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where a pin is located
+ * @param	pin		: GPIO pin to set direction on as output
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DIR |= 1UL << pin;
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: GPIO pin to set direction on as input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].DIR &= ~(1UL << pin);
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: GPIO pin to set direction for
+ * @param	output	: true for output, false for input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
+{
+	if (output) {
+		Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
+	}
+	else {
+		Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
+	}
+}
+
+/**
+ * @brief	Set a GPIO direction
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	bit		: GPIO bit to set
+ * @param	setting	: true for output, false for input
+ * @return	Nothing
+ * @note	It is recommended to use the Chip_GPIO_SetPinDIROutput(),
+ * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
+ * of this function.
+ */
+STATIC INLINE void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t bit, bool setting)
+{
+	Chip_GPIO_SetPinDIR(pGPIO, port, bit, setting);
+}
+
+/**
+ * @brief	Get GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: GPIO pin to get direction for
+ * @return	true if the GPIO is an output, false if input
+ */
+STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (bool) (((pGPIO[port].DIR) >> pin) & 1);
+}
+
+/**
+ * @brief	Read a GPIO direction (out or in)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	bit		: GPIO bit to read
+ * @return	true of the GPIO is an output, false if input
+ * @note	It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
+{
+	return Chip_GPIO_GetPinDIR(pGPIO, port, bit);
+}
+
+/**
+ * @brief	Set Direction for a GPIO port
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port Number
+ * @param	bitValue	: GPIO bit to set
+ * @param	out			: Direction value, 0 = input, !0 = output
+ * @return	None
+ * @note	Bits set to '0' are not altered. It is recommended to use the
+ * Chip_GPIO_SetPortDIR() function instead.
+ */
+STATIC INLINE void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
+{
+	Chip_GPIO_SetPinDIR(pGPIO, portNum, bitValue, out);
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pinMask	: GPIO pin mask to set direction on as output (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the output direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
+{
+	pGPIO[port].DIR |= pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pinMask	: GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
+{
+	pGPIO[port].DIR &= ~pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input or output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pinMask	: GPIO pin mask to set direction on (bits 0..b for pins 0..n)
+ * @param	outSet	: Direction value, false = set as inputs, true = set as outputs
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
+{
+	if (outSet) {
+		Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
+	}
+	else {
+		Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
+	}
+}
+
+/**
+ * @brief	Get GPIO direction for a all GPIO pins
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @return	a bitfield containing the input and output states for each pin
+ * @note	For pins 0..n, a high state in a bit corresponds to an output state for the
+ * same pin, while a low  state corresponds to an input state.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].DIR;
+}
+
+/**
+ * @brief	Set GPIO port mask value for GPIO masked read and write
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number
+ * @param	mask	: Mask value for read and write (only low bits are enabled)
+ * @return	Nothing
+ * @note	Controls which bits are set or unset when using the masked
+ * GPIO read and write functions. A low state indicates the pin is settable
+ * and readable via the masked write and read functions.
+ */
+STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask)
+{
+	pGPIO[port].MASK = mask;
+}
+
+/**
+ * @brief	Get GPIO port mask value used for GPIO masked read and write
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number
+ * @return	Returns value set with the Chip_GPIO_SetPortMask() function.
+ * @note	A high bit in the return value indicates that that GPIO pin for the
+ * port cannot be set using the masked write function.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].MASK;
+}
+
+/**
+ * @brief	Set all GPIO pin states, but mask via the MASK register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	pGPIO[port].PIN = value;
+}
+
+/**
+ * @brief	Get all GPIO pin states but mask via the MASK register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @return	Current (masked) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO[port].PIN;
+}
+
+/**
+ * @brief	Set all GPIO raw pin states (does not bypass masking on this chip!)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	Chip_GPIO_SetMaskedPortValue(pGPIO, port, value);
+}
+
+/**
+ * @brief	Get all GPIO raw pin states (does not bypass masking on this chip!)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @return	Current (raw) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return Chip_GPIO_GetMaskedPortValue(pGPIO, port);
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pins	: pins (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO[port].SET = pins;
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the high state
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port number
+ * @param	bitValue	: bit(s) in the port to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output. It is recommended to use the
+ * Chip_GPIO_SetPortOutHigh() function instead.
+ */
+STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
+{
+	Chip_GPIO_SetPortOutHigh(pGPIO,portNum,bitValue);
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip'
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: pin number (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].SET = (1 << pin);
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pins	: pins (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO[port].CLR = pins;
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the low state
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port number
+ * @param	bitValue	: bit(s) in the port to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
+{
+	Chip_GPIO_SetPortOutLow(pGPIO, portNum, bitValue);
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where pin is located
+ * @param	pin		: pin number (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO[port].CLR = (1 << pin);
+}
+
+/**
+ * @brief	Toggle an individual GPIO output pin to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO Port number where @a pin is located
+ * @param	pin		: pin number (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	bool setting = !Chip_GPIO_GetPinState(pGPIO, port, pin);
+	Chip_GPIO_SetPinState(pGPIO, port, pin, setting);
+}
+
+/**
+ * @brief	Read current bit states for the selected port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	portNum	: port number to read
+ * @return	Current value of GPIO port
+ * @note	The current states of the bits for the port are read, regardless of
+ * whether the GPIO port bits are input or output.
+ */
+STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
+{
+	return pGPIO[portNum].PIN;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/gpioint_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/gpioint_17xx_40xx.h
new file mode 100644
index 000000000..4f74323c4
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/gpioint_17xx_40xx.h
@@ -0,0 +1,227 @@
+/*
+ * @brief LPC17xx/40xx GPIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIOINT_17XX_40XX_H_
+#define __GPIOINT_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIOINT_17XX_40XX CHIP: LPC17xx/40xx GPIO Interrupt driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief GPIO Interupt registers for Portn
+ */
+typedef struct {
+	__I  uint32_t STATR;		/*!< GPIO Interrupt Status Register for Rising edge */
+	__I  uint32_t STATF;		/*!< GPIO Interrupt Status Register for Falling edge */
+	__O  uint32_t CLR;			/*!< GPIO Interrupt Clear  Register */
+	__IO uint32_t ENR;			/*!< GPIO Interrupt Enable Register 0 for Rising edge */
+	__IO uint32_t ENF;			/*!< GPIO Interrupt Enable Register 0 for Falling edge */
+} GPIOINT_PORT_T;
+
+/**
+ * @brief GPIO Interrupt register block structure
+ */
+typedef struct {
+	__I  uint32_t STATUS;		/*!< GPIO overall Interrupt Status Register */
+	GPIOINT_PORT_T IO0;			/*!< GPIO Interrupt Registers for Port 0 */
+	uint32_t RESERVED0[3];
+	GPIOINT_PORT_T IO2;			/*!< GPIO Interrupt Registers for Port 2 */
+} LPC_GPIOINT_T;
+
+/**
+ * @brief	GPIO interrupt capable ports
+ */
+typedef enum {
+	GPIOINT_PORT0,             /*!< GPIO PORT 0 */
+	GPIOINT_PORT2 = 2          /*!< GPIO PORT 2 */
+}LPC_GPIOINT_PORT_T;
+
+/**
+ * @brief	Initialize GPIO interrupt block
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @return	Nothing
+ * @note	This function enables the clock to IOCON, GPIO and GPIOINT
+ * 			peripheral blocks.
+ */
+STATIC INLINE void Chip_GPIOINT_Init(LPC_GPIOINT_T *pGPIOINT)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/**
+ * @brief	De-Initialize GPIO Interrupt block
+ * @param	pGPIOINT	: The base of GPIO interrupt peripheral on the chip
+ * @return	Nothing
+ * @note	This function disables the clock to IOCON, GPIO and GPIOINT
+ * 			peripheral blocks This function should not be called
+ * 			if IOCON or GPIO needs to be used after calling this function.
+ */
+STATIC INLINE void Chip_GPIOINT_DeInit(LPC_GPIOINT_T *pGPIOINT)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+/**
+ * @brief	Enable interrupts on falling edge of given @a pins
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @param	pins		: Pins set to 1 will have falling edge interrupt enabled,
+ * 						  Pins set to 0 will have falling edge interrupt disabled
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIOINT_SetIntFalling(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port, uint32_t pins)
+{
+	if (port == GPIOINT_PORT0) {
+		pGPIOINT->IO0.ENF = pins;
+	} else {
+		pGPIOINT->IO2.ENF = pins;
+	}
+}
+
+/**
+ * @brief	Enable interrupts on rising edge of given @a pins
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @param	pins		: Pins set to 1 will have rising edge interrupt enabled,
+ * 						  Pins set to 0 will have rising edge interrupt disabled
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIOINT_SetIntRising(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port, uint32_t pins)
+{
+	if (port == GPIOINT_PORT0) {
+		pGPIOINT->IO0.ENR = pins;
+	} else {
+		pGPIOINT->IO2.ENR = pins;
+	}
+}
+
+/**
+ * @brief	Get the pins that has falling edge interrupt enabled
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @return	Pins that are configured for Falling edge interrupt enabled
+ */
+STATIC INLINE uint32_t Chip_GPIOINT_GetIntFalling(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
+{
+	if (port == GPIOINT_PORT0) {
+		return pGPIOINT->IO0.ENF;
+	} else {
+		return pGPIOINT->IO2.ENF;
+	}
+}
+
+/**
+ * @brief	Get pins that has rising edge interrupt enabled
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @return	Pins that are configured for rising edge interrupt enabled
+ */
+STATIC INLINE uint32_t Chip_GPIOINT_GetIntRising(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
+{
+	if (port == GPIOINT_PORT0) {
+		return pGPIOINT->IO0.ENR;
+	} else {
+		return pGPIOINT->IO2.ENR;
+	}
+}
+
+/**
+ * @brief	Get status of the pins for falling edge
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @return	Pins that has detected falling edge
+ */
+STATIC INLINE uint32_t Chip_GPIOINT_GetStatusFalling(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
+{
+	if (port == GPIOINT_PORT0) {
+		return pGPIOINT->IO0.STATF;
+	} else {
+		return pGPIOINT->IO2.STATF;
+	}
+}
+
+/**
+ * @brief	Get status of the pins for rising edge
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @return	Pins that has detected rising edge
+ */
+STATIC INLINE uint32_t Chip_GPIOINT_GetStatusRising(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
+{
+	if (port == GPIOINT_PORT0) {
+		return pGPIOINT->IO0.STATR;
+	} else {
+		return pGPIOINT->IO2.STATR;
+	}
+}
+
+/**
+ * @brief	Clear the falling and rising edge interrupt for given @a pins
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @param	pins		: Pins to clear the interrupts for
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIOINT_ClearIntStatus(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port, uint32_t pins)
+{
+	if (port == GPIOINT_PORT0) {
+		pGPIOINT->IO0.CLR = pins;
+	} else {
+		pGPIOINT->IO2.CLR = pins;
+	}
+}
+
+/**
+ * @brief	Checks if an interrupt is pending on a given port
+ * @param	pGPIOINT	: The base address of GPIO interrupt block
+ * @param	port		: GPIOINT port (GPIOINT_PORT0 or GPIOINT_PORT2)
+ * @return	true if any pin in given port has a pending interrupt
+ */
+STATIC INLINE bool Chip_GPIOINT_IsIntPending(LPC_GPIOINT_T *pGPIOINT, LPC_GPIOINT_PORT_T port)
+{
+	return ((pGPIOINT->STATUS & (1 << (int)port)) != 0);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIOINT_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/i2c_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/i2c_17xx_40xx.h
new file mode 100644
index 000000000..451fb027f
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/i2c_17xx_40xx.h
@@ -0,0 +1,541 @@
+/*
+ * @brief LPC17xx/40xx I2C driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __I2C_17XX_40XX_H_
+#define __I2C_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup I2C_17XX_40XX CHIP: LPC17xx/40xx I2C driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief I2C register block structure
+ */
+typedef struct {				/* I2C0 Structure         */
+	__IO uint32_t CONSET;		/*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+	__I  uint32_t STAT;			/*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+	__IO uint32_t DAT;			/*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+	__IO uint32_t ADR0;			/*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__IO uint32_t SCLH;			/*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+	__IO uint32_t SCLL;			/*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+	__O  uint32_t CONCLR;		/*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+	__IO uint32_t MMCTRL;		/*!< Monitor mode control register. */
+	__IO uint32_t ADR1;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__IO uint32_t ADR2;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__IO uint32_t ADR3;			/*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+	__I  uint32_t DATA_BUFFER;	/*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+	__IO uint32_t MASK[4];		/*!< I2C Slave address mask register */
+} LPC_I2C_T;
+
+/**
+ * @brief	Return values for SLAVE handler
+ * @note
+ * Chip drivers will usally be designed to match their events with this value
+ */
+#define RET_SLAVE_TX    6	/**< Return value, when 1 byte TX'd successfully */
+#define RET_SLAVE_RX    5	/**< Return value, when 1 byte RX'd successfully */
+#define RET_SLAVE_IDLE  2	/**< Return value, when slave enter idle mode */
+#define RET_SLAVE_BUSY  0	/**< Return value, when slave is busy */
+
+/**
+ * @brief I2C state handle return values
+ */
+#define I2C_STA_STO_RECV            0x20
+
+/*
+ * @brief I2C Control Set register description
+ */
+#define I2C_I2CONSET_AA             ((0x04))/*!< Assert acknowledge flag */
+#define I2C_I2CONSET_SI             ((0x08))/*!< I2C interrupt flag */
+#define I2C_I2CONSET_STO            ((0x10))/*!< STOP flag */
+#define I2C_I2CONSET_STA            ((0x20))/*!< START flag */
+#define I2C_I2CONSET_I2EN           ((0x40))/*!< I2C interface enable */
+
+/*
+ * @brief I2C Control Clear register description
+ */
+#define I2C_I2CONCLR_AAC            ((1 << 2))	/*!< Assert acknowledge Clear bit */
+#define I2C_I2CONCLR_SIC            ((1 << 3))	/*!< I2C interrupt Clear bit */
+#define I2C_I2CONCLR_STOC           ((1 << 4))	/*!< I2C STOP Clear bit */
+#define I2C_I2CONCLR_STAC           ((1 << 5))	/*!< START flag Clear bit */
+#define I2C_I2CONCLR_I2ENC          ((1 << 6))	/*!< I2C interface Disable bit */
+
+/*
+ * @brief	I2C Common Control register description
+ */
+#define I2C_CON_AA            (1UL << 2)	/*!< Assert acknowledge bit */
+#define I2C_CON_SI            (1UL << 3)	/*!< I2C interrupt bit */
+#define I2C_CON_STO           (1UL << 4)	/*!< I2C STOP bit */
+#define I2C_CON_STA           (1UL << 5)	/*!< START flag bit */
+#define I2C_CON_I2EN          (1UL << 6)	/*!< I2C interface bit */
+
+/*
+ * @brief I2C Status Code definition (I2C Status register)
+ */
+#define I2C_STAT_CODE_BITMASK       ((0xF8))/*!< Return Code mask in I2C status register */
+#define I2C_STAT_CODE_ERROR         ((0xFF))/*!< Return Code error mask in I2C status register */
+
+/*
+ * @brief I2C return status code definitions
+ */
+#define I2C_I2STAT_NO_INF                       ((0xF8))/*!< No relevant information */
+#define I2C_I2STAT_BUS_ERROR                    ((0x00))/*!< Bus Error */
+
+/*
+ * @brief I2C Master transmit mode
+ */
+#define I2C_I2STAT_M_TX_START                   ((0x08))/*!< A start condition has been transmitted */
+#define I2C_I2STAT_M_TX_RESTART                 ((0x10))/*!< A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_NACK               ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_DAT_ACK                 ((0x28))/*!< Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))/*!< Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
+
+/*
+ * @brief I2C Master receive mode
+ */
+#define I2C_I2STAT_M_RX_START                   ((0x08))/*!< A start condition has been transmitted */
+#define I2C_I2STAT_M_RX_RESTART                 ((0x10))/*!< A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))/*!< Arbitration lost */
+#define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_NACK               ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_RX_DAT_ACK                 ((0x50))/*!< Data has been received, ACK has been returned */
+#define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))/*!< Data has been received, NACK has been returned */
+
+/*
+ * @brief I2C Slave receive mode
+ */
+#define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))/*!< Own slave address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA          ((0x68))/*!< Arbitration lost in SLA+R/W as master */
+// #define I2C_I2STAT_S_RX_SLAW_ACK				((0x68)) /*!< Own SLA+W has been received, ACK returned */
+#define I2C_I2STAT_S_RX_GENCALL_ACK             ((0x70))/*!< General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL      ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
+// #define I2C_I2STAT_S_RX_GENCALL_ACK				((0x78)) /*!< General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK         ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK     ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX   ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
+														   SLV/TRX (Slave Transmit) */
+
+/*
+ * @brief I2C Slave transmit mode
+ */
+#define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA          ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
+// #define I2C_I2STAT_S_TX_SLAR_ACK				((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_DAT_ACK                 ((0xB8))/*!< Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))/*!< Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
+#define I2C_SLAVE_TIME_OUT                      0x10000000UL/*!< Time out in case of using I2C slave mode */
+
+/*
+ * @brief I2C Data register definition
+ */
+#define I2C_I2DAT_BITMASK           ((0xFF))/*!< Mask for I2DAT register */
+#define I2C_I2DAT_IDLE_CHAR         (0xFF)	/*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
+											     its sending data length that can be supported */
+
+/*
+ * @brief I2C Monitor mode control register description
+ */
+#define I2C_I2MMCTRL_MM_ENA         ((1 << 0))			/**< Monitor mode enable */
+#define I2C_I2MMCTRL_ENA_SCL        ((1 << 1))			/**< SCL output enable */
+#define I2C_I2MMCTRL_MATCH_ALL      ((1 << 2))			/**< Select interrupt register match */
+#define I2C_I2MMCTRL_BITMASK        ((0x07))		/**< Mask for I2MMCTRL register */
+
+/*
+ * @brief I2C Data buffer register description
+ */
+#define I2DATA_BUFFER_BITMASK       ((0xFF))/*!< I2C Data buffer register bit mask */
+
+/*
+ * @brief I2C Slave Address registers definition
+ */
+#define I2C_I2ADR_GC                ((1 << 0))	/*!< General Call enable bit */
+#define I2C_I2ADR_BITMASK           ((0xFF))/*!< I2C Slave Address registers bit mask */
+
+/*
+ * @brief I2C Mask Register definition
+ */
+#define I2C_I2MASK_MASK(n)          ((n & 0xFE))/*!< I2C Mask Register mask field */
+
+/*
+ * @brief I2C SCL HIGH duty cycle Register definition
+ */
+#define I2C_I2SCLH_BITMASK          ((0xFFFF))	/*!< I2C SCL HIGH duty cycle Register bit mask */
+
+/*
+ * @brief I2C SCL LOW duty cycle Register definition
+ */
+#define I2C_I2SCLL_BITMASK          ((0xFFFF))	/*!< I2C SCL LOW duty cycle Register bit mask */
+
+/*
+ * @brief I2C status values
+ */
+#define I2C_SETUP_STATUS_ARBF   (1 << 8)	/**< Arbitration false */
+#define I2C_SETUP_STATUS_NOACKF (1 << 9)	/**< No ACK returned */
+#define I2C_SETUP_STATUS_DONE   (1 << 10)	/**< Status DONE */
+
+/*
+ * @brief I2C state handle return values
+ */
+#define I2C_OK                      0x00
+#define I2C_BYTE_SENT               0x01
+#define I2C_BYTE_RECV               0x02
+#define I2C_LAST_BYTE_RECV          0x04
+#define I2C_SEND_END                0x08
+#define I2C_RECV_END                0x10
+#define I2C_STA_STO_RECV            0x20
+
+#define I2C_ERR                     (0x10000000)
+#define I2C_NAK_RECV                (0x10000000 | 0x01)
+
+#define I2C_CheckError(ErrorCode)   (ErrorCode & 0x10000000)
+
+/*
+ * @brief I2C monitor control configuration defines
+ */
+#define I2C_MONITOR_CFG_SCL_OUTPUT  I2C_I2MMCTRL_ENA_SCL		/**< SCL output enable */
+#define I2C_MONITOR_CFG_MATCHALL    I2C_I2MMCTRL_MATCH_ALL		/**< Select interrupt register match */
+
+/**
+ * @brief	I2C Slave Identifiers
+ */
+typedef enum {
+	I2C_SLAVE_GENERAL,	/**< Slave ID for general calls */
+	I2C_SLAVE_0,		/**< Slave ID fo Slave Address 0 */
+	I2C_SLAVE_1,		/**< Slave ID fo Slave Address 1 */
+	I2C_SLAVE_2,		/**< Slave ID fo Slave Address 2 */
+	I2C_SLAVE_3,		/**< Slave ID fo Slave Address 3 */
+	I2C_SLAVE_NUM_INTERFACE	/**< Number of slave interfaces */
+} I2C_SLAVE_ID;
+
+/**
+ * @brief	I2C transfer status
+ */
+typedef enum {
+	I2C_STATUS_DONE,	/**< Transfer done successfully */
+	I2C_STATUS_NAK,		/**< NAK received during transfer */
+	I2C_STATUS_ARBLOST,	/**< Aribitration lost during transfer */
+	I2C_STATUS_BUSERR,	/**< Bus error in I2C transfer */
+	I2C_STATUS_BUSY,	/**< I2C is busy doing transfer */
+} I2C_STATUS_T;
+
+/**
+ * @brief Master transfer data structure definitions
+ */
+typedef struct {
+	uint8_t slaveAddr;		/**< 7-bit I2C Slave address */
+	const uint8_t *txBuff;	/**< Pointer to array of bytes to be transmitted */
+	int     txSz;			/**< Number of bytes in transmit array,
+							   if 0 only receive transfer will be carried on */
+	uint8_t *rxBuff;		/**< Pointer memory where bytes received from I2C be stored */
+	int     rxSz;			/**< Number of bytes to received,
+							   if 0 only transmission we be carried on */
+	I2C_STATUS_T status;	/**< Status of the current I2C transfer */
+} I2C_XFER_T;
+
+/**
+ * @brief	I2C interface IDs
+ * @note
+ * All Chip functions will take this as the first parameter,
+ * I2C_NUM_INTERFACE must never be used for calling any Chip
+ * functions, it is only used to find the number of interfaces
+ * available in the Chip.
+ */
+typedef enum I2C_ID {
+	I2C0,				/**< ID I2C0 */
+	I2C1,				/**< ID I2C1 */
+	I2C2,				/**< ID I2C2 */
+	I2C_NUM_INTERFACE	/**< Number of I2C interfaces in the chip */
+} I2C_ID_T;
+
+/**
+ * @brief	I2C master events
+ */
+typedef enum {
+	I2C_EVENT_WAIT = 1,	/**< I2C Wait event */
+	I2C_EVENT_DONE,		/**< Done event that wakes up Wait event */
+	I2C_EVENT_LOCK,		/**< Re-entrency lock event for I2C transfer */
+	I2C_EVENT_UNLOCK,	/**< Re-entrency unlock event for I2C transfer */
+	I2C_EVENT_SLAVE_RX,	/**< Slave receive event */
+	I2C_EVENT_SLAVE_TX,	/**< Slave transmit event */
+} I2C_EVENT_T;
+
+/**
+ * @brief	Event handler function type
+ */
+typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);
+
+/**
+ * @brief	Initializes the LPC_I2C peripheral with specified parameter.
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_Init(I2C_ID_T id);
+
+/**
+ * @brief	De-initializes the I2C peripheral registers to their default reset values
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_DeInit(I2C_ID_T id);
+
+/**
+ * @brief	Set up clock rate for LPC_I2C peripheral.
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	clockrate	: Target clock rate value to initialized I2C peripheral (Hz)
+ * @return	Nothing
+ * @note
+ * Parameter @a clockrate for I2C0 should be from 1000 up to 1000000
+ * (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. If the @a clockrate
+ * is more than 400 KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()
+ * must be called prior to calling this function.
+ */
+void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);
+
+/**
+ * @brief	Get current clock rate for LPC_I2C peripheral.
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	The current I2C peripheral clock rate
+ */
+uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);
+
+/**
+ * @brief	Transmit and Receive data in master mode
+ * @param	id		: I2C peripheral selected (I2C0, I2C1 etc)
+ * @param	xfer	: Pointer to a I2C_XFER_T structure see notes below
+ * @return
+ * Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes
+ * not sent due to error, xfer->rxSz will have the number of bytes yet
+ * to be received.
+ * @note
+ * The parameter @a xfer should have its member @a slaveAddr initialized
+ * to the 7-Bit slave address to which the master will do the xfer, Bit0
+ * to bit6 should have the address and Bit8 is ignored. During the transfer
+ * no code (like event handler) must change the content of the memory
+ * pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
+ * initialized to the memory from which the I2C must pick the data to be
+ * transfered to slave and the number of bytes to send respectively, similarly
+ * @a rxBuff and @a rxSz must have pointer to memroy where data received
+ * from slave be stored and the number of data to get from slave respectilvely.
+ */
+int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);
+
+/**
+ * @brief	Transmit data to I2C slave using I2C Master mode
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 .. etc)
+ * @param	slaveAddr	: Slave address to which the data be written
+ * @param	buff		: Pointer to buffer having the array of data
+ * @param	len			: Number of bytes to be transfered from @a buff
+ * @return	Number of bytes successfully transfered
+ */
+int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);
+
+/**
+ * @brief	Transfer a command to slave and receive data from slave after a repeated start
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	slaveAddr	: Slave address of the I2C device
+ * @param	cmd			: Command (Address/Register) to be written
+ * @param	buff		: Pointer to memory that will hold the data received
+ * @param	len			: Number of bytes to receive
+ * @return	Number of bytes successfully received
+ */
+int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);
+
+/**
+ * @brief	Get pointer to current function handling the events
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Pointer to function handing events of I2C
+ */
+I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);
+
+/**
+ * @brief	Set function that must handle I2C events
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	event		: Pointer to function that will handle the event (Should not be NULL)
+ * @return	1 when successful, 0 when a transfer is on going with its own event handler
+ */
+int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);
+
+/**
+ * @brief	Set function that must handle I2C events
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	slaveAddr	: Slave address from which data be read
+ * @param	buff		: Pointer to memory where data read be stored
+ * @param	len			: Number of bytes to read from slave
+ * @return	Number of bytes read successfully
+ */
+int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);
+
+/**
+ * @brief	Default event handler for polling operation
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	event	: Event ID of the event that called the function
+ * @return	Nothing
+ */
+void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);
+
+/**
+ * @brief	Default event handler for interrupt base operation
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	event	: Event ID of the event that called the function
+ * @return	Nothing
+ */
+void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);
+
+/**
+ * @brief	I2C Master transfer state change handler
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ * @note	Usually called from the appropriate Interrupt handler
+ */
+void Chip_I2C_MasterStateHandler(I2C_ID_T id);
+
+/**
+ * @brief	Disable I2C peripheral's operation
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_Disable(I2C_ID_T id);
+
+/**
+ * @brief	Checks if master xfer in progress
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	1 if master xfer in progress 0 otherwise
+ * @note
+ * This API is generally used in interrupt handler
+ * of the application to decide whether to call
+ * master state handler or to call slave state handler
+ */
+int Chip_I2C_IsMasterActive(I2C_ID_T id);
+
+/**
+ * @brief	Setup a slave I2C device
+ * @param	id			: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @param	sid			: I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)
+ * @param	xfer		: Pointer to transfer structure (see note below for more info)
+ * @param	event		: Event handler for slave transfers
+ * @param	addrMask	: Address mask to use along with slave address (see notes below for more info)
+ * @return	Nothing
+ * @note
+ * Parameter @a xfer should point to a valid I2C_XFER_T structure object
+ * and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),
+ * Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will
+ * be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers
+ * where slave can receive or send the data from, size of which will be provided by
+ * @a rxSz and @a txSz respectively. Function pointed to by @a event will be called
+ * for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully
+ * from the master and stored inside memory pointed by xfer->rxBuff, incremented
+ * the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of
+ * data from xfer->txBuff was sent to master successfully, incremented the pointer
+ * and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers
+ * with the slave).<br>
+ * <br>Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1
+ * to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as
+ * don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then
+ * 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered
+ * slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual
+ * address which was received from master.<br>
+ * <br><b>General Call Handling</b><br>
+ * Slave can receive data from master using general call address (0x00). General call
+ * handling must be setup as given below
+ *      - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL
+ *          - xfer->slaveAddr ignored, argument @a addrMask ignored
+ *          - function provided by @a event will registered to be called when slave received data using addr 0x00
+ *          - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer
+ *      - To handle General Call only (No other slaves are configured)
+ *          - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
+ *          - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL
+ *          - provide @a addrMask (typically 0, if not you better be knowing what you are doing)
+ *      - To handler General Call when other slave is active
+ *          - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
+ *          - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]
+ *          - Set Bit0 of @a xfer->slaveAddr as 1
+ *          - Provide appropriate @a addrMask
+ *          - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC
+ * @warning
+ * If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler
+ * will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer
+ * then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be
+ * called to notify this. For more info see section below<br>
+ * <br><b> Last data handling in slave </b><br>
+ * If the user wants to implement a slave which will read a byte from a specific location over and over
+ * again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read
+ * the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from
+ * xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another
+ * byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will
+ * occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte
+ * event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer
+ * and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte
+ * in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and
+ * the process repeats.
+ */
+void Chip_I2C_SlaveSetup(I2C_ID_T id,
+						 I2C_SLAVE_ID sid,
+						 I2C_XFER_T *xfer,
+						 I2C_EVENTHANDLER_T event,
+						 uint8_t addrMask);
+
+/**
+ * @brief	I2C Slave event handler
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	Nothing
+ */
+void Chip_I2C_SlaveStateHandler(I2C_ID_T id);
+
+/**
+ * @brief	I2C peripheral state change checking
+ * @param	id		: I2C peripheral ID (I2C0, I2C1 ... etc)
+ * @return	1 if I2C peripheral @a id has changed its state,
+ *          0 if there is no state change
+ * @note
+ * This function must be used by the application when
+ * the polling has to be done based on state change.
+ */
+int Chip_I2C_IsStateChanged(I2C_ID_T id);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2C_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/i2s_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/i2s_17xx_40xx.h
new file mode 100644
index 000000000..7fe254a27
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/i2s_17xx_40xx.h
@@ -0,0 +1,534 @@
+/*
+ * @brief LPC17xx/40xx I2S driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __I2S_17XX_40XX_H_
+#define __I2S_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup I2S_17XX_40XX CHIP: LPC17xx/40xx I2S driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief I2S DMA request channel define
+ */
+typedef enum {
+	I2S_DMA_REQUEST_CHANNEL_1,	/*!< DMA request channel 1 */
+	I2S_DMA_REQUEST_CHANNEL_2,	/*!< DMA request channel 2 */
+	I2S_DMA_REQUEST_CHANNEL_NUM,/*!< The number of DMA request channels */
+} I2S_DMA_CHANNEL_T;
+
+/**
+ * @brief I2S register block structure
+ */
+typedef struct {				/*!< I2S Structure */
+	__IO uint32_t DAO;			/*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
+	__IO uint32_t DAI;			/*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
+	__O uint32_t TXFIFO;		/*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
+	__I uint32_t RXFIFO;		/*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
+	__I uint32_t STATE;			/*!< I2S Status Feedback Register. Contains status information about the I2S interface */
+	__IO uint32_t DMA[I2S_DMA_REQUEST_CHANNEL_NUM];	/*!< I2S DMA Configuration Registers. Contains control information for DMA request channels */
+	__IO uint32_t IRQ;			/*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
+	__IO uint32_t TXRATE;		/*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+	__IO uint32_t RXRATE;		/*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
+	__IO uint32_t TXBITRATE;	/*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
+	__IO uint32_t RXBITRATE;	/*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
+	__IO uint32_t TXMODE;		/*!< I2S Transmit mode control */
+	__IO uint32_t RXMODE;		/*!< I2S Receive mode control */
+} LPC_I2S_T;
+
+/*
+ * @brief I2S configuration parameter defines
+ */
+/* I2S Wordwidth bit */
+#define I2S_WORDWIDTH_8     (0UL << 0)	/*!< 8 bit Word */
+#define I2S_WORDWIDTH_16    (1UL << 0)	/*!< 16 bit word */
+#define I2S_WORDWIDTH_32    (3UL << 0)	/*!< 32 bit word */
+
+/* I2S Channel bit */
+#define I2S_STEREO          (0UL << 2)	/*!< Stereo audio */
+#define I2S_MONO            (1UL << 2)	/*!< Mono audio */
+
+/* I2S Master/Slave mode bit */
+#define I2S_MASTER_MODE     (0UL << 5)	/*!< I2S in master mode */
+#define I2S_SLAVE_MODE      (1UL << 5)	/*!< I2S in slave mode */
+
+/* I2S Stop bit */
+#define I2S_STOP_ENABLE     (0UL << 3)	/*!< I2S stop enable mask */
+#define I2S_STOP_DISABLE    (1UL << 3)	/*!< I2S stop disable mask */
+
+/* I2S Reset bit */
+#define I2S_RESET_ENABLE    (1UL << 4)	/*!< I2S reset enable mask */
+#define I2S_RESET_DISABLE   (0UL << 4)	/*!< I2S reset disable mask */
+
+/* I2S Mute bit */
+#define I2S_MUTE_ENABLE     (1UL << 15)	/*!< I2S mute enable mask */
+#define I2S_MUTE_DISABLE    (0UL << 15)	/*!< I2S mute disbale mask */
+
+/*
+ * @brief Macro defines for DAO-Digital Audio Output register
+ */
+/* I2S wordwide - the number of bytes in data*/
+#define I2S_DAO_WORDWIDTH_8     ((uint32_t) (0))	/*!< DAO 8 bit	*/
+#define I2S_DAO_WORDWIDTH_16    ((uint32_t) (1))	/*!< DAO 16 bit	*/
+#define I2S_DAO_WORDWIDTH_32    ((uint32_t) (3))	/*!< DAO 32 bit	*/
+#define I2S_DAO_WORDWIDTH_MASK  ((uint32_t) (3))
+
+/* I2S control mono or stereo format */
+#define I2S_DAO_MONO            ((uint32_t) (1 << 2))	/*!< DAO mono audio mask */
+
+/* I2S control stop mode */
+#define I2S_DAO_STOP            ((uint32_t) (1 << 3))	/*!< DAO stop mask */
+
+/* I2S control reset mode */
+#define I2S_DAO_RESET           ((uint32_t) (1 << 4))	/*!< DAO reset mask */
+
+/* I2S control master/slave mode */
+#define I2S_DAO_SLAVE           ((uint32_t) (1 << 5))	/*!< DAO slave mode mask */
+
+/* I2S word select half period minus one */
+#define I2S_DAO_WS_HALFPERIOD(n)    ((uint32_t) (((n) & 0x1FF) << 6))	/*!< DAO Word select set macro */
+#define I2S_DAO_WS_HALFPERIOD_MASK  ((uint32_t) ((0x1FF) << 6))		/*!< DAO Word select mask */
+
+/* I2S control mute mode */
+#define I2S_DAO_MUTE            ((uint32_t) (1 << 15))	/*!< DAO mute mask */
+
+/*
+ * @brief Macro defines for DAI-Digital Audio Input register
+ */
+/* I2S wordwide - the number of bytes in data*/
+#define I2S_DAI_WORDWIDTH_8     ((uint32_t) (0))	/*!< DAI 8 bit	*/
+#define I2S_DAI_WORDWIDTH_16    ((uint32_t) (1))	/*!< DAI 16 bit	*/
+#define I2S_DAI_WORDWIDTH_32    ((uint32_t) (3))	/*!< DAI 32 bit	*/
+#define I2S_DAI_WORDWIDTH_MASK  ((uint32_t) (3))	/*!< DAI word wide mask */
+
+/* I2S control mono or stereo format */
+#define I2S_DAI_MONO            ((uint32_t) (1 << 2))	/*!< DAI mono mode mask */
+
+/* I2S control stop mode */
+#define I2S_DAI_STOP            ((uint32_t) (1 << 3))	/*!< DAI stop bit mask */
+
+/* I2S control reset mode */
+#define I2S_DAI_RESET           ((uint32_t) (1 << 4))	/*!< DAI reset bit mask */
+
+/* I2S control master/slave mode */
+#define I2S_DAI_SLAVE           ((uint32_t) (1 << 5))	/*!< DAI slave mode mask */
+
+/* I2S word select half period minus one (9 bits)*/
+#define I2S_DAI_WS_HALFPERIOD(n)    ((uint32_t) (((n) & 0x1FF) << 6))	/*!< DAI Word select set macro */
+#define I2S_DAI_WS_HALFPERIOD_MASK  ((uint32_t) ((0x1FF) << 6))		/*!< DAI Word select mask */
+
+/*
+ * @brief Macro defines for STAT register (Status Feedback register)
+ */
+#define I2S_STATE_IRQ       ((uint32_t) (1))/*!< I2S Status Receive or Transmit Interrupt */
+#define I2S_STATE_DMA1      ((uint32_t) (1 << 1))	/*!< I2S Status Receive or Transmit DMA1 */
+#define I2S_STATE_DMA2      ((uint32_t) (1 << 2))	/*!< I2S Status Receive or Transmit DMA2 */
+#define I2S_STATE_RX_LEVEL(n)   ((uint32_t) ((n & 1F) << 8))/*!< I2S Status Current level of the Receive FIFO (5 bits)*/
+#define I2S_STATE_TX_LEVEL(n)   ((uint32_t) ((n & 1F) << 16))	/*!< I2S Status Current level of the Transmit FIFO (5 bits)*/
+
+/*
+ * @brief Macro defines for DMA1 register (DMA1 Configuration register)
+ */
+#define I2S_DMA1_RX_ENABLE      ((uint32_t) (1))/*!< I2S control DMA1 for I2S receive */
+#define I2S_DMA1_TX_ENABLE      ((uint32_t) (1 << 1))	/*!< I2S control DMA1 for I2S transmit */
+#define I2S_DMA1_RX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 8))	/*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA1_TX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 16))	/*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+
+/*
+ * @brief Macro defines for DMA2 register (DMA2 Configuration register)
+ */
+#define I2S_DMA2_RX_ENABLE      ((uint32_t) (1))/*!< I2S control DMA2 for I2S receive */
+#define I2S_DMA2_TX_ENABLE      ((uint32_t) (1 << 1))	/*!< I2S control DMA1 for I2S transmit */
+#define I2S_DMA2_RX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 8))	/*!< I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA2_TX_DEPTH(n)    ((uint32_t) ((n & 0x1F) << 16))	/*!< I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+
+/*
+ * @brief Macro defines for IRQ register (Interrupt Request Control register)
+ */
+
+#define I2S_IRQ_RX_ENABLE       ((uint32_t) (1))/*!< I2S control I2S receive interrupt */
+#define I2S_IRQ_TX_ENABLE       ((uint32_t) (1 << 1))	/*!< I2S control I2S transmit interrupt */
+#define I2S_IRQ_RX_DEPTH(n)     ((uint32_t) ((n & 0x0F) << 8))	/*!< I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_RX_DEPTH_MASK   ((uint32_t) ((0x0F) << 8))
+#define I2S_IRQ_TX_DEPTH(n)     ((uint32_t) ((n & 0x0F) << 16))	/*!< I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_TX_DEPTH_MASK   ((uint32_t) ((0x0F) << 16))
+
+/*
+ * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
+ */
+#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))	/*!< I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))	/*!< I2S Transmit MCLK rate denominator */
+#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))	/*!< I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))	/*!< I2S Receive MCLK rate denominator */
+
+/*
+ * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
+ */
+#define I2S_TXBITRATE(n)    ((uint32_t) (n & 0x3F))
+#define I2S_RXBITRATE(n)    ((uint32_t) (n & 0x3F))
+
+/*
+ * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
+ */
+#define I2S_TXMODE_CLKSEL(n)    ((uint32_t) (n & 0x03))	/*!< I2S Transmit select clock source (2 bits)*/
+#define I2S_TXMODE_4PIN_ENABLE  ((uint32_t) (1 << 2))	/*!< I2S Transmit control 4-pin mode */
+#define I2S_TXMODE_MCENA        ((uint32_t) (1 << 3))	/*!< I2S Transmit control the TX_MCLK output */
+#define I2S_RXMODE_CLKSEL(n)    ((uint32_t) (n & 0x03))	/*!< I2S Receive select clock source */
+#define I2S_RXMODE_4PIN_ENABLE  ((uint32_t) (1 << 2))	/*!< I2S Receive control 4-pin mode */
+#define I2S_RXMODE_MCENA        ((uint32_t) (1 << 3))	/*!< I2S Receive control the TX_MCLK output */
+
+/**
+ * @brief I2S Audio Format Structure
+ */
+typedef struct {
+	uint32_t SampleRate;	/*!< Sample Rate */
+	uint8_t ChannelNumber;	/*!< Channel Number - 1 is mono, 2 is stereo */
+	uint8_t WordWidth;		/*!< Word Width - 8, 16 or 32 bits */
+} I2S_AUDIO_FORMAT_T;
+
+/**
+ * @brief	Initialize for I2S
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_I2S_Init(LPC_I2S_T *pI2S);
+
+/**
+ * @brief	Shutdown I2S
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ * @note	Reset all relative registers (DMA, transmit/receive control, interrupt) to default value
+ */
+void Chip_I2S_DeInit(LPC_I2S_T *pI2S);
+
+/**
+ * @brief	Send a 32-bit data to TXFIFO for transmition
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	data	: Data to be transmited
+ * @return	Nothing
+ * @note	The function writes to TXFIFO without checking any condition.
+ */
+STATIC INLINE void Chip_I2S_Send(LPC_I2S_T *pI2S, uint32_t data)
+{
+	pI2S->TXFIFO = data;
+}
+
+/**
+ * @brief	Get received data from RXFIFO
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Data received in RXFIFO
+ * @note	The function reads from RXFIFO without checking any condition.
+ */
+STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_T *pI2S)
+{
+	return pI2S->RXFIFO;
+}
+
+/**
+ * @brief	Start transmit data
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_TxStart(LPC_I2S_T *pI2S)
+{
+	pI2S->DAO &= ~(I2S_DAO_RESET | I2S_DAO_STOP | I2S_DAO_MUTE);
+}
+
+/**
+ * @brief	Start receive data
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_RxStart(LPC_I2S_T *pI2S)
+{
+	pI2S->DAI &= ~(I2S_DAI_RESET | I2S_DAI_STOP);
+}
+
+/**
+ * @brief	Disables accesses on FIFOs, places the transmit channel in mute mode
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_TxPause(LPC_I2S_T *pI2S)
+{
+	pI2S->DAO |= I2S_DAO_STOP;
+}
+
+/**
+ * @brief	Disables accesses on FIFOs, places the transmit channel in mute mode
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_RxPause(LPC_I2S_T *pI2S)
+{
+	pI2S->DAI |= I2S_DAI_STOP;
+}
+
+/**
+ * @brief	Mute the Transmit channel
+ * @param	pI2S		: The base of I2S peripheral on the chip
+ * @return	Nothing
+ * @note	The data output from I2S transmit channel is always zeroes
+ */
+STATIC INLINE void Chip_I2S_EnableMute(LPC_I2S_T *pI2S)
+{
+	pI2S->DAO |= I2S_DAO_MUTE;
+}
+
+/**
+ * @brief	Un-Mute the I2S channel
+ * @param	pI2S		: The base of I2S peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_I2S_DisableMute(LPC_I2S_T *pI2S)
+{
+	pI2S->DAO &= ~I2S_DAO_MUTE;
+}
+
+/**
+ * @brief	Stop I2S asynchronously
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ * @note	Pause, resets the transmit channel and FIFO asynchronously
+ */
+STATIC INLINE void Chip_I2S_TxStop(LPC_I2S_T *pI2S)
+{
+	pI2S->DAO &= ~I2S_DAO_MUTE;
+	pI2S->DAO |= I2S_DAO_STOP | I2S_DAO_RESET;
+}
+
+/**
+ * @brief	Stop I2S asynchronously
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Nothing
+ * @note	Pause, resets the transmit channel and FIFO asynchronously
+ */
+STATIC INLINE void Chip_I2S_RxStop(LPC_I2S_T *pI2S)
+{
+	pI2S->DAI |= I2S_DAI_STOP | I2S_DAI_RESET;
+}
+
+/**
+ * @brief	Set the I2S transmit mode
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	clksel	: Clock source selection for the receive bit clock divider
+ * @param	fpin	: Receive 4-pin mode selection
+ * @param	mcena	: Enable for the RX_MCLK output
+ * @return	Nothing
+ * @note	In addition to master and slave modes, which are independently configurable for
+ * the transmitter and the receiver, several different clock sources are possible,
+ * including variations that share the clock and/or WS between the transmitter and
+ * receiver. It also allows using I2S with fewer pins, typically four.
+ */
+STATIC INLINE void Chip_I2S_TxModeConfig(LPC_I2S_T *pI2S,
+										 uint32_t clksel,
+										 uint32_t fpin,
+										 uint32_t mcena)
+{
+	pI2S->TXMODE = clksel | fpin | mcena;
+}
+
+/**
+ * @brief	Set the I2S receive mode
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @param	clksel	: Clock source selection for the receive bit clock divider
+ * @param	fpin	: Receive 4-pin mode selection
+ * @param	mcena	: Enable for the RX_MCLK output
+ * @return	Nothing
+ * @note	In addition to master and slave modes, which are independently configurable for
+ * the transmitter and the receiver, several different clock sources are possible,
+ * including variations that share the clock and/or WS between the transmitter and
+ * receiver. It also allows using I2S with fewer pins, typically four.
+ */
+STATIC INLINE void Chip_I2S_RxModeConfig(LPC_I2S_T *pI2S,
+										 uint32_t clksel,
+										 uint32_t fpin,
+										 uint32_t mcena)
+{
+	pI2S->RXMODE = clksel | fpin | mcena;
+}
+
+/**
+ * @brief	Get the current level of the Transmit FIFO
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Current level of the Transmit FIFO
+ */
+STATIC INLINE uint8_t Chip_I2S_GetTxLevel(LPC_I2S_T *pI2S)
+{
+	return (pI2S->STATE >> 16) & 0xF;
+}
+
+/**
+ * @brief	Get the current level of the Receive FIFO
+ * @param	pI2S	: The base of I2S peripheral on the chip
+ * @return	Current level of the Receive FIFO
+ */
+STATIC INLINE uint8_t Chip_I2S_GetRxLevel(LPC_I2S_T *pI2S)
+{
+	return (pI2S->STATE >> 8) & 0xF;
+}
+
+/**
+ * @brief	Set the clock frequency for I2S interface
+ * @param	pI2S			: The base of I2S peripheral on the chip
+ * @param	div	: Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
+ * @return	Nothing
+ * @note	The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.
+ * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz
+ */
+STATIC INLINE void Chip_I2S_SetTxBitRate(LPC_I2S_T *pI2S, uint32_t div)
+{
+	pI2S->TXBITRATE = div;
+}
+
+/**
+ * @brief	Set the clock frequency for I2S interface
+ * @param	pI2S			: The base of I2S peripheral on the chip
+ * @param	div	: Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface
+ * @return	Nothing
+ * @note	The value depends on the audio sample rate desired and the data size and format(stereo/mono) used.
+ * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz
+ */
+STATIC INLINE void Chip_I2S_SetRxBitRate(LPC_I2S_T *pI2S, uint32_t div)
+{
+	pI2S->RXBITRATE = div;
+}
+
+/**
+ * @brief	Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK
+ * @param	pI2S		: The base of I2S peripheral on the chip
+ * @param	xDiv	: I2S transmit MCLK rate numerator
+ * @param	yDiv	: I2S transmit MCLK rate denominator
+ * @return	Nothing
+ * @note	Values of the numerator (X) and the denominator (Y) must be chosen to
+ * produce a frequency twice that desired for the transmitter MCLK, which
+ * must be an integer multiple of the transmitter bit clock rate.
+ * The equation for the fractional rate generator is:
+ * MCLK = PCLK * (X/Y) /2
+ * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
+ * greater than or equal to X.
+ */
+STATIC INLINE void Chip_I2S_SetTxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv)
+{
+	pI2S->TXRATE = yDiv | (xDiv << 8);
+}
+
+/**
+ * @brief	Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK
+ * @param	pI2S		: The base of I2S peripheral on the chip
+ * @param	xDiv	: I2S transmit MCLK rate numerator
+ * @param	yDiv	: I2S transmit MCLK rate denominator
+ * @return	Nothing
+ * @note	Values of the numerator (X) and the denominator (Y) must be chosen to
+ * produce a frequency twice that desired for the transmitter MCLK, which
+ * must be an integer multiple of the transmitter bit clock rate.
+ * The equation for the fractional rate generator is:
+ * MCLK = PCLK * (X/Y) /2
+ * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be
+ * greater than or equal to X.
+ */
+STATIC INLINE void Chip_I2S_SetRxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv)
+{
+	pI2S->RXRATE = yDiv | (xDiv << 8);
+}
+
+/**
+ * @brief   Configure I2S for Audio Format input
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	format	: Audio Format
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2S_TxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format);
+
+/**
+ * @brief   Configure I2S for Audio Format input
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	format	: Audio Format
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_I2S_RxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format);
+
+/**
+ * @brief   Enable/Disable Interrupt with a specific FIFO depth
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	newState		: ENABLE or DISABLE interrupt
+ * @param	depth		: FIFO level creating an irq request
+ * @return	Nothing
+ */
+void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth);
+
+/**
+ * @brief   Enable/Disable Interrupt with a specific FIFO depth
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	newState		: ENABLE or DISABLE interrupt
+ * @param	depth		: FIFO level creating an irq request
+ * @return	Nothing
+ */
+void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth);
+
+/**
+ * @brief   Enable/Disable DMA with a specific FIFO depth
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	dmaNum			: Should be
+ *								- I2S_DMA_REQUEST_CHANNEL_1 : Using DMA1
+ *								- I2S_DMA_REQUEST_CHANNEL_2 : Using DMA2
+ * @param	newState		: ENABLE or DISABLE interrupt
+ * @param	depth		: FIFO level creating an irq request
+ * @return	Nothing
+ */
+void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth);
+
+/**
+ * @brief   Enable/Disable DMA with a specific FIFO depth
+ * @param	pI2S			: The base I2S peripheral on the chip
+ * @param	dmaNum			: Should be
+ *								- I2S_DMA_REQUEST_CHANNEL_1 : Using DMA1
+ *								- I2S_DMA_REQUEST_CHANNEL_2 : Using DMA2
+ * @param	newState		: ENABLE or DISABLE interrupt
+ * @param	depth		: FIFO level creating an irq request
+ * @return	Nothing
+ */
+void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2S_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/iap.h b/hw/mcu/nxp/lpc_chip_40xx/inc/iap.h
new file mode 100644
index 000000000..a90e87c9b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/iap.h
@@ -0,0 +1,184 @@
+/*
+ * @brief Common IAP support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __IAP_H_
+#define __IAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup COMMON_IAP CHIP: Common Chip ISP/IAP commands and return codes
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/* IAP command definitions */
+#define IAP_PREWRRITE_CMD           50	/*!< Prepare sector for write operation command */
+#define IAP_WRISECTOR_CMD           51	/*!< Write Sector command */
+#define IAP_ERSSECTOR_CMD           52	/*!< Erase Sector command */
+#define IAP_BLANK_CHECK_SECTOR_CMD  53	/*!< Blank check sector */
+#define IAP_REPID_CMD               54	/*!< Read PartID command */
+#define IAP_READ_BOOT_CODE_CMD      55	/*!< Read Boot code version */
+#define IAP_COMPARE_CMD             56	/*!< Compare two RAM address locations */
+#define IAP_REINVOKE_ISP_CMD        57	/*!< Reinvoke ISP */
+#define IAP_READ_UID_CMD            58	/*!< Read UID */
+#define IAP_ERASE_PAGE_CMD          59	/*!< Erase page */
+#define IAP_EEPROM_WRITE            61	/*!< EEPROM Write command */
+#define IAP_EEPROM_READ             62	/*!< EEPROM READ command */
+
+/* IAP response definitions */
+#define IAP_CMD_SUCCESS             0	/*!< Command is executed successfully */
+#define IAP_INVALID_COMMAND         1	/*!< Invalid command */
+#define IAP_SRC_ADDR_ERROR          2	/*!< Source address is not on word boundary */
+#define IAP_DST_ADDR_ERROR          3	/*!< Destination address is not on a correct boundary */
+#define IAP_SRC_ADDR_NOT_MAPPED     4	/*!< Source address is not mapped in the memory map */
+#define IAP_DST_ADDR_NOT_MAPPED     5	/*!< Destination address is not mapped in the memory map */
+#define IAP_COUNT_ERROR             6	/*!< Byte count is not multiple of 4 or is not a permitted value */
+#define IAP_INVALID_SECTOR          7	/*!< Sector number is invalid or end sector number is greater than start sector number */
+#define IAP_SECTOR_NOT_BLANK        8	/*!< Sector is not blank */
+#define IAP_SECTOR_NOT_PREPARED     9	/*!< Command to prepare sector for write operation was not executed */
+#define IAP_COMPARE_ERROR           10	/*!< Source and destination data not equal */
+#define IAP_BUSY                    11	/*!< Flash programming hardware interface is busy */
+#define IAP_PARAM_ERROR             12	/*!< nsufficient number of parameters or invalid parameter */
+#define IAP_ADDR_ERROR              13	/*!< Address is not on word boundary */
+#define IAP_ADDR_NOT_MAPPED         14	/*!< Address is not mapped in the memory map */
+#define IAP_CMD_LOCKED              15	/*!< Command is locked */
+#define IAP_INVALID_CODE            16	/*!< Unlock code is invalid */
+#define IAP_INVALID_BAUD_RATE       17	/*!< Invalid baud rate setting */
+#define IAP_INVALID_STOP_BIT        18	/*!< Invalid stop bit setting */
+#define IAP_CRP_ENABLED             19	/*!< Code read protection enabled */
+
+/* IAP_ENTRY API function type */
+typedef void (*IAP_ENTRY_T)(unsigned int[5], unsigned int[4]);
+
+/**
+ * @brief	Prepare sector for write operation
+ * @param	strSector	: Start sector number
+ * @param	endSector	: End sector number
+ * @return	Status code to indicate the command is executed successfully or not
+ * @note	This command must be executed before executing "Copy RAM to flash"
+ *			or "Erase Sector" command.
+ *			The end sector must be greater than or equal to start sector number
+ */
+uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector);
+
+/**
+ * @brief	Copy RAM to flash
+ * @param	dstAdd		: Destination flash address where data bytes are to be written
+ * @param	srcAdd		: Source flash address where data bytes are to be read
+ * @param	byteswrt	: Number of bytes to be written
+ * @return	Status code to indicate the command is executed successfully or not
+ * @note	The addresses should be a 256 byte boundary and the number of bytes
+ *			should be 256 | 512 | 1024 | 4096
+ */
+uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt);
+
+/**
+ * @brief	Erase sector
+ * @param	strSector	: Start sector number
+ * @param	endSector	: End sector number
+ * @return	Status code to indicate the command is executed successfully or not
+ * @note	The end sector must be greater than or equal to start sector number
+ */
+uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector);
+
+/**
+ * @brief Blank check a sector or multiples sector of on-chip flash memory
+ * @param	strSector	: Start sector number
+ * @param	endSector	: End sector number
+ * @return	Offset of the first non blank word location if the status code is SECTOR_NOT_BLANK
+ * @note	The end sector must be greater than or equal to start sector number
+ */
+// FIXME - There are two return value (result[0] & result[1]
+// Result0:Offset of the first non blank word location if the Status Code is
+// SECTOR_NOT_BLANK.
+// Result1:Contents of non blank word location.
+uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector);
+
+/**
+ * @brief	Read part identification number
+ * @return	Part identification number
+ */
+uint32_t Chip_IAP_ReadPID(void);
+
+/**
+ * @brief	Read boot code version number
+ * @return	Boot code version number
+ */
+uint8_t Chip_IAP_ReadBootCode(void);
+
+/**
+ * @brief	Compare the memory contents at two locations
+ * @param	dstAdd		: Destination of the RAM address of data bytes to be compared
+ * @param	srcAdd		: Source of the RAM address of data bytes to be compared
+ * @param	bytescmp	: Number of bytes to be compared
+ * @return	Offset of the first mismatch of the status code is COMPARE_ERROR
+ * @note	The addresses should be a word boundary and number of bytes should be
+ *			a multiply of 4
+ */
+uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp);
+
+/**
+ * @brief	IAP reinvoke ISP to invoke the bootloader in ISP mode
+ * @return	none
+ */
+uint8_t Chip_IAP_ReinvokeISP(void);
+
+/**
+ * @brief	Read the unique ID
+ * @return	Status code to indicate the command is executed successfully or not
+ */
+uint32_t Chip_IAP_ReadUID(void);
+
+/**
+ * @brief	Erase a page or multiple papers of on-chip flash memory
+ * @param	strPage	: Start page number
+ * @param	endPage	: End page number
+ * @return	Status code to indicate the command is executed successfully or not
+ * @note	The page number must be greater than or equal to start page number
+ */
+// FIXME - There are four return value
+// Result0:The first 32-bit word (at the lowest address)
+// Result1:The second 32-bit word.
+// Result2:The third 32-bit word.
+// Result3:The fourth 32-bit word.
+uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IAP_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h
new file mode 100644
index 000000000..8d5f055be
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h
@@ -0,0 +1,274 @@
+/*
+ * @brief LPC17xx/40xx IOCON registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __IOCON_17XX_40XX_H_
+#define __IOCON_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup IOCON_17XX_40XX CHIP: LPC17xx/40xx I/O configuration driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/** 
+ * @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format 
+ */ 
+typedef struct {
+	uint32_t pingrp:3;		/* Pin group */
+	uint32_t pinnum:5;		/* Pin number */
+	uint32_t modefunc:24;	/* Function and mode. */
+} PINMUX_GRP_T;
+
+/**
+ * @brief IOCON register block
+ */
+typedef struct {
+#if defined(CHIP_LPC175X_6X)
+	__IO uint32_t PINSEL[11];
+	uint32_t RESERVED0[5];
+	__IO uint32_t PINMODE[10];
+	__IO uint32_t PINMODE_OD[5];
+	__IO uint32_t I2CPADCFG;
+#else
+	__IO uint32_t p[5][32];
+#endif
+} LPC_IOCON_T;
+
+/**
+ * IOCON function and mode selection definitions
+ * See the User Manual for specific modes and functions supoprted by the
+ * various LPC11xx devices. Functionality can vary per device.
+ */
+#define IOCON_FUNC0             0x0				/*!< Selects pin function 0 */
+#define IOCON_FUNC1             0x1				/*!< Selects pin function 1 */
+#define IOCON_FUNC2             0x2				/*!< Selects pin function 2 */
+#define IOCON_FUNC3             0x3				/*!< Selects pin function 3 */
+#if defined(CHIP_LPC175X_6X)
+#define IOCON_MODE_INACT        (0x2 << 2)		/*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN     (0x3 << 2)		/*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP       (0x0 << 2)		/*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER     (0x1 << 2)		/*!< Selects pin repeater function */
+#else
+#define IOCON_FUNC4             0x4				/*!< Selects pin function 4 */
+#define IOCON_FUNC5             0x5				/*!< Selects pin function 5 */
+#define IOCON_FUNC6             0x6				/*!< Selects pin function 6 */
+#define IOCON_FUNC7             0x7				/*!< Selects pin function 7 */
+#define IOCON_MODE_INACT        (0x0 << 3)		/*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN     (0x1 << 3)		/*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP       (0x2 << 3)		/*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER     (0x3 << 3)		/*!< Selects pin repeater function */
+#define IOCON_HYS_EN            (0x1 << 5)		/*!< Enables hysteresis */
+#define IOCON_INV_EN            (0x1 << 6)		/*!< Enables invert function on input */
+#define IOCON_ADMODE_EN         (0x0 << 7)		/*!< Enables analog input function (analog pins only) */
+#define IOCON_DIGMODE_EN        (0x1 << 7)		/*!< Enables digital function (analog pins only) */
+#define IOCON_FILT_DIS          (0x1 << 8)		/*!< Disables noise pulses filtering (10nS glitch filter) */
+#define IOCON_HS_DIS            (0x1 << 8)		/*!< I2C glitch filter and slew rate disabled */
+#define IOCON_HIDRIVE_EN        (0x1 << 9)		/*!< Sink current is 20 mA */
+#define IOCON_FASTSLEW_EN       (0x1 << 9)		/*!< Enables fast slew */
+#define IOCON_OPENDRAIN_EN      (0x1 << 10)		/*!< Enables open-drain function */
+#define IOCON_DAC_EN            (0x1 << 16)		/*!< Enables DAC function */
+#endif
+
+/**
+ * IOCON function and mode selection definitions (old)
+ * For backwards compatibility.
+ */
+#define FUNC0					0x0				/** Function 0  */
+#define FUNC1					0x1				/** Function 1  */
+#define FUNC2					0x2				/** Function 2	*/
+#define FUNC3					0x3				/** Function 3	*/
+#if defined(CHIP_LPC175X_6X)
+#define MD_PLN					(0x2)
+#define MD_PDN					(0x3)
+#define MD_PUP					(0x0)
+#define MD_BUK					(0x1)
+
+#else
+#define MD_PLN					(0x0 << 3)
+#define MD_PDN					(0x1 << 3)
+#define MD_PUP					(0x2 << 3)
+#define MD_BUK					(0x3 << 3)
+#define MD_HYS_ENA				(0x1 << 5)		/*!< Macro to enable hysteresis- use with Chip_IOCON_PinMux */
+#define MD_HYS_DIS				(0x0 << 5)		/*!< Macro to disable hysteresis- use with Chip_IOCON_PinMux */
+#define MD_IINV_ENA				(0x1 << 6)		/*!< Macro to enable input inversion- use with Chip_IOCON_PinMux */
+#define MD_IINV_DIS				(0x0 << 6)		/*!< Macro to disable input inversion- use with Chip_IOCON_PinMux */
+#define MD_OD_ENA				(0x1 << 10)		/*!< Macro to enable simulated open drain mode- use with Chip_IOCON_PinMux */
+#define MD_OD_DIS				(0x0 << 10)		/*!< Macro to disable simulated open drain mode- use with Chip_IOCON_PinMux */
+#define MD_HS_ENA				(0x0 << 8)		/*!< Macro to enable I2C 50ns glitch filter and slew rate control- use with Chip_IOCON_PinMux */
+#define MD_HS_DIS				(0x1 << 8)		/*!< Macro to disable I2C 50ns glitch filter and slew rate control- use with Chip_IOCON_PinMux */
+#define MD_ANA_ENA				(0x0 << 7)		/*!< Macro to enable analog mode (ADC)- use with Chip_IOCON_PinMux */
+#define MD_ANA_DIS				(0x1 << 7)		/*!< Macro to disable analog mode (ADC)- use with Chip_IOCON_PinMux */
+#define MD_FILT_ENA				(0x0 << 8)		/*!< Macro to enable input filter- use with Chip_IOCON_PinMux */
+#define MD_FILT_DIS				(0x1 << 8)		/*!< Macro to disable input filter- use with Chip_IOCON_PinMux */
+#define MD_DAC_ENA				(0x1 << 16)		/*!< Macro to enable DAC- use with Chip_IOCON_PinMux */
+#define MD_DAC_DIS				(0x0 << 16)		/*!< Macro to disable DAC- use with Chip_IOCON_PinMux */
+#define MD_STD_SLEW_RATE		(0x0 << 9)		/*!< Macro to enable standard mode, slew rate control is enabled - use with Chip_IOCON_PinMux */
+#define MD_FAST_SLEW_RATE		(0x1 << 9)		/*!< Macro to enable fast mode, slew rate control is disabled - use with Chip_IOCON_PinMux */
+#define MD_HD_ENA				(0x1 << 9)		/*!< Macro to enable high drive output- use with Chip_IOCON_PinMux */
+#define MD_HD_DIS				(0x0 << 9)		/*!< Macro to disable high drive output- use with Chip_IOCON_PinMux */
+#define FUNC4					0x4				/** Function 4  */
+#define FUNC5					0x5				/** Function 5  */
+#define FUNC6					0x6				/** Function 6	*/
+#define FUNC7					0x7				/** Function 7	*/
+#endif /* defined(CHIP_LPC175X_6X)*/
+
+/**
+ * @brief	Initialize the IOCON peripheral
+ * @param	pIOCON	: The base of IOCON peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_Init(LPC_IOCON_T *pIOCON)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
+}
+
+#if defined(CHIP_LPC175X_6X)
+/* PINSEL and PINMODE register index calculation.*/
+#define IOCON_REG_INDEX(port, pin)		(2 * port + (pin / 16))
+/* Bit position calculation in PINSEL and PINMODE register.*/
+#define IOCON_BIT_INDEX(pin)			((pin % 16) * 2)
+
+/**
+ * @brief	Sets I/O Control pin mux
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port		: GPIO port to mux
+ * @param	pin			: GPIO pin to mux
+ * @param	modefunc	: OR'ed values or type IOCON_*
+ * @return	Nothing
+ */
+void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc);
+
+/**
+ * @brief	Setup pin modes and function
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port 		: port number
+ * @param	pin			: gpio pin number
+ * @param	mode		: OR'ed values or type IOCON_*
+ * @param	func		: Pin function, value of type IOCON_FUNC0 to IOCON_FUNC3
+ * @return	Nothing
+ */
+void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t mode, uint8_t func);
+
+/**
+ * @brief	Enable open drain mode
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port 		: port number
+ * @param	pin			: gpio pin number
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_EnableOD(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin)
+{
+	pIOCON->PINMODE_OD[port] |= (0x01UL << pin);
+}
+
+/**
+ * @brief	Disable open drain mode
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port 		: port number
+ * @param	pin			: gpio pin number
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_DisableOD(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin)
+{
+	pIOCON->PINMODE_OD[port] &= ~(0x01UL << pin);
+}
+
+/**
+ * @brief I2C pin configuration definitions 
+ */
+typedef enum {
+	I2CPADCFG_STD_MODE = 0x00,                  /*!< Standard I2C mode */
+	I2CPADCFG_FAST_MODE = I2CPADCFG_STD_MODE,   /*!< Fast mode */
+	I2CPADCFG_FAST_MODE_PLUS = 0x05,            /*!< Fast mode plus */
+	I2CPADCFG_NON_I2C = 0x0A,                  /*!< For non-I2C use*/
+} IOCON_I2CPINS_CONFIG;
+
+/**
+ * @brief Configure I2C pad pins (P0.27 and P0.28)
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	cfg 		: pin configurations
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_SetI2CPad(LPC_IOCON_T *pIOCON, IOCON_I2CPINS_CONFIG cfg)
+{
+	pIOCON->I2CPADCFG = cfg;
+}
+
+#else
+/**
+ * @brief	Sets I/O Control pin mux
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port		: GPIO port to mux
+ * @param	pin			: GPIO pin to mux
+ * @param	modefunc	: OR'ed values or type IOCON_*
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+	pIOCON->p[port][pin] = modefunc;
+}
+
+/**
+ * @brief	Setup pin modes and function
+ * @param	pIOCON		: The base of IOCON peripheral on the chip
+ * @param	port 		: port number
+ * @param	pin			: gpio pin number
+ * @param	mode		: OR'ed values or type IOCON_*
+ * @param	func		: Pin function, value of type IOCON_FUNC0 to IOCON_FUNC7
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t mode, uint8_t func)
+{
+	Chip_IOCON_PinMuxSet(pIOCON, port, pin, (mode | func));
+}
+#endif /* defined(CHIP_LPC175X_6X) */
+
+/**
+ * @brief	Set all I/O Control pin muxing
+ * @param	pIOCON	    : The base of IOCON peripheral on the chip
+ * @param	pinArray    : Pointer to array of pin mux selections
+ * @param	arrayLength : Number of entries in pinArray
+ * @return	Nothing
+ */
+void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IOCON_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/lcd_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/lcd_17xx_40xx.h
new file mode 100644
index 000000000..c6a1628cd
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/lcd_17xx_40xx.h
@@ -0,0 +1,387 @@
+/*
+ * @brief LPC17xx/40xx LCD driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LCD_17XX_40XX_H_
+#define __LCD_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup LCD_17XX_40XX CHIP: LPC17xx/40xx LCD driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/**
+ * @brief LCD Controller register block structure
+ */
+typedef struct {				/*!< LCD Structure          */
+	__IO uint32_t  TIMH;		/*!< Horizontal Timing Control register */
+	__IO uint32_t  TIMV;		/*!< Vertical Timing Control register */
+	__IO uint32_t  POL;			/*!< Clock and Signal Polarity Control register */
+	__IO uint32_t  LE;			/*!< Line End Control register */
+	__IO uint32_t  UPBASE;		/*!< Upper Panel Frame Base Address register */
+	__IO uint32_t  LPBASE;		/*!< Lower Panel Frame Base Address register */
+	__IO uint32_t  CTRL;		/*!< LCD Control register   */
+	__IO uint32_t  INTMSK;		/*!< Interrupt Mask register */
+	__I  uint32_t  INTRAW;		/*!< Raw Interrupt Status register */
+	__I  uint32_t  INTSTAT;		/*!< Masked Interrupt Status register */
+	__O  uint32_t  INTCLR;		/*!< Interrupt Clear register */
+	__I  uint32_t  UPCURR;		/*!< Upper Panel Current Address Value register */
+	__I  uint32_t  LPCURR;		/*!< Lower Panel Current Address Value register */
+	__I  uint32_t  RESERVED0[115];
+	__IO uint16_t PAL[256];		/*!< 256x16-bit Color Palette registers */
+	__I  uint32_t  RESERVED1[256];
+	__IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */
+	__IO uint32_t  CRSR_CTRL;	/*!< Cursor Control register */
+	__IO uint32_t  CRSR_CFG;	/*!< Cursor Configuration register */
+	__IO uint32_t  CRSR_PAL0;	/*!< Cursor Palette register 0 */
+	__IO uint32_t  CRSR_PAL1;	/*!< Cursor Palette register 1 */
+	__IO uint32_t  CRSR_XY;		/*!< Cursor XY Position register */
+	__IO uint32_t  CRSR_CLIP;	/*!< Cursor Clip Position register */
+	__I  uint32_t  RESERVED2[2];
+	__IO uint32_t  CRSR_INTMSK;	/*!< Cursor Interrupt Mask register */
+	__O  uint32_t  CRSR_INTCLR;	/*!< Cursor Interrupt Clear register */
+	__I  uint32_t  CRSR_INTRAW;	/*!< Cursor Raw Interrupt Status register */
+	__I  uint32_t  CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */
+} LPC_LCD_T;
+
+/**
+ * @brief LCD Palette entry format
+ */
+typedef struct {
+	uint32_t Rl : 5;
+	uint32_t Gl : 5;
+	uint32_t Bl : 5;
+	uint32_t Il : 1;
+	uint32_t Ru : 5;
+	uint32_t Gu : 5;
+	uint32_t Bu : 5;
+	uint32_t Iu : 1;
+} LCD_PALETTE_ENTRY_T;
+
+/**
+ * @brief LCD Panel type
+ */
+typedef enum {
+	LCD_TFT = 0x02,		/*!< standard TFT */
+	LCD_MONO_4 = 0x01,	/*!< 4-bit STN mono */
+	LCD_MONO_8 = 0x05,	/*!< 8-bit STN mono */
+	LCD_CSTN = 0x00		/*!< color STN */
+} LCD_PANEL_OPT_T;
+
+/**
+ * @brief LCD Color Format
+ */
+typedef enum {
+	LCD_COLOR_FORMAT_RGB = 0,
+	LCD_COLOR_FORMAT_BGR
+} LCD_COLOR_FORMAT_OPT_T;
+
+/** LCD Interrupt control mask register bits */
+#define LCD_INTMSK_FUFIM   0x2	/*!< FIFO underflow interrupt enable */
+#define LCD_INTMSK_LNBUIM  0x4	/*!< LCD next base address update interrupt enable */
+#define LCD_INTMSK_VCOMPIM 0x8	/*!< Vertical compare interrupt enable */
+#define LCD_INTMSK_BERIM   0x10	/*!< AHB master error interrupt enable */
+
+#define CLCDC_LCDCTRL_ENABLE    _BIT(0)		/*!< LCD control enable bit */
+#define CLCDC_LCDCTRL_PWR       _BIT(11)	/*!< LCD control power enable bit */
+
+/**
+ * @brief A structure for LCD Configuration
+ */
+typedef struct {
+	uint8_t  HBP;	/*!< Horizontal back porch in clocks */
+	uint8_t  HFP;	/*!< Horizontal front porch in clocks */
+	uint8_t  HSW;	/*!< HSYNC pulse width in clocks */
+	uint16_t PPL;	/*!< Pixels per line */
+	uint8_t  VBP;	/*!< Vertical back porch in clocks */
+	uint8_t  VFP;	/*!< Vertical front porch in clocks */
+	uint8_t  VSW;	/*!< VSYNC pulse width in clocks */
+	uint16_t LPP;	/*!< Lines per panel */
+	uint8_t  IOE;	/*!< Invert output enable, 1 = invert */
+	uint8_t  IPC;	/*!< Invert panel clock, 1 = invert */
+	uint8_t  IHS;	/*!< Invert HSYNC, 1 = invert */
+	uint8_t  IVS;	/*!< Invert VSYNC, 1 = invert */
+	uint8_t  ACB;	/*!< AC bias frequency in clocks (not used) */
+	uint8_t  BPP;	/*!< Maximum bits per pixel the display supports */
+	LCD_PANEL_OPT_T  LCD;	/*!< LCD panel type */
+	LCD_COLOR_FORMAT_OPT_T  color_format;	/*!<BGR or RGB */
+	uint8_t  Dual;	/*!< Dual panel, 1 = dual panel display */
+} LCD_CONFIG_T;
+
+/**
+ * @brief LCD Cursor Size
+ */
+typedef enum {
+	LCD_CURSOR_32x32 = 0,
+	LCD_CURSOR_64x64
+} LCD_CURSOR_SIZE_OPT_T;
+
+/**
+ * @brief	Initialize the LCD controller
+ * @param	pLCD				: The base of LCD peripheral on the chip
+ * @param	LCD_ConfigStruct	: Pointer to LCD configuration
+ * @return  LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error
+ */
+void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_CONFIG_T *LCD_ConfigStruct);
+
+/**
+ * @brief	Shutdown the LCD controller
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @return  Nothing
+ */
+void Chip_LCD_DeInit(LPC_LCD_T *pLCD);
+
+/**
+ * @brief	Power-on the LCD Panel (power pin)
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_PowerOn(LPC_LCD_T *pLCD)
+{
+	volatile int i;
+	pLCD->CTRL |= CLCDC_LCDCTRL_PWR;
+	for (i = 0; i < 1000000; i++) {}
+	pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
+}
+
+/**
+ * @brief	Power-off the LCD Panel (power pin)
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_PowerOff(LPC_LCD_T *pLCD)
+{
+	volatile int i;
+	pLCD->CTRL &= ~CLCDC_LCDCTRL_PWR;
+	for (i = 0; i < 1000000; i++) {}
+	pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
+}
+
+/**
+ * @brief	Enable/Disable the LCD Controller
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Enable(LPC_LCD_T *pLCD)
+{
+	pLCD->CTRL |= CLCDC_LCDCTRL_ENABLE;
+}
+
+/**
+ * @brief	Enable/Disable the LCD Controller
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Disable(LPC_LCD_T *pLCD)
+{
+	pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
+}
+
+/**
+ * @brief	Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame
+ *			Buffer for Dual Panel
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	buffer	: address of buffer
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_SetUPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)
+{
+	pLCD->UPBASE = (uint32_t) buffer;
+}
+
+/**
+ * @brief	Set LCD Lower Panel Frame Buffer for Dual Panel
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	buffer	: address of buffer
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_SetLPFrameBuffer(LPC_LCD_T *pLCD, void *buffer)
+{
+	pLCD->LPBASE = (uint32_t) buffer;
+}
+
+/**
+ * @brief	Configure Cursor
+ * @param	pLCD		: The base of LCD peripheral on the chip
+ * @param	cursor_size	: specify size of cursor
+ *                  - LCD_CURSOR_32x32	:cursor size is 32x32 pixels
+ *                  - LCD_CURSOR_64x64	:cursor size is 64x64 pixels
+ * @param	sync		: cursor sync mode
+ *                  - TRUE	:cursor sync to the frame sync pulse
+ *                  - FALSE	:cursor async mode
+ * @return	None
+ */
+void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync);
+
+/**
+ * @brief	Enable Cursor
+ * @param	pLCD		: The base of LCD peripheral on the chip
+ * @param	cursor_num	: specify number of cursor is going to be written
+ *							this param must < 4
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_Enable(LPC_LCD_T *pLCD, uint8_t cursor_num)
+{
+	pLCD->CRSR_CTRL = (cursor_num << 4) | 1;
+}
+
+/**
+ * @brief	Disable Cursor
+ * @param	pLCD		: The base of LCD peripheral on the chip
+ * @param	cursor_num	: specify number of cursor is going to be written
+ *							this param must < 4
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_Disable(LPC_LCD_T *pLCD, uint8_t cursor_num)
+{
+	pLCD->CRSR_CTRL = (cursor_num << 4);
+}
+
+/**
+ * @brief	Load Cursor Palette
+ * @param	pLCD			: The base of LCD peripheral on the chip
+ * @param	palette_color	: cursor palette 0 value
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(LPC_LCD_T *pLCD, uint32_t palette_color)
+{
+	/* 7:0 - Red
+	   15:8 - Green
+	   23:16 - Blue
+	   31:24 - Not used*/
+	pLCD->CRSR_PAL0 = (uint32_t) palette_color;
+}
+
+/**
+ * @brief	Load Cursor Palette
+ * @param	pLCD			: The base of LCD peripheral on the chip
+ * @param	palette_color	: cursor palette 1 value
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(LPC_LCD_T *pLCD, uint32_t palette_color)
+{
+	/* 7:0 - Red
+	       15:8 - Green
+	       23:16 - Blue
+	       31:24 - Not used*/
+	pLCD->CRSR_PAL1 = (uint32_t) palette_color;
+}
+
+/**
+ * @brief	Set Cursor Position
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	x		: horizontal position
+ * @param	y		: vertical position
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_SetPos(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)
+{
+	pLCD->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16);
+}
+
+/**
+ * @brief	Set Cursor Clipping Position
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	x		: horizontal position, should be in range: 0..63
+ * @param	y		: vertical position, should be in range: 0..63
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_Cursor_SetClip(LPC_LCD_T *pLCD, uint16_t x, uint16_t y)
+{
+	pLCD->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8);
+}
+
+/**
+ * @brief	Enable Controller Interrupt
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	ints	: OR'ed interrupt bits to enable
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_EnableInts(LPC_LCD_T *pLCD, uint32_t ints)
+{
+	pLCD->INTMSK = ints;
+}
+
+/**
+ * @brief	Disable Controller Interrupt
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	ints	: OR'ed interrupt bits to disable
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_DisableInts(LPC_LCD_T *pLCD, uint32_t ints)
+{
+	pLCD->INTMSK = pLCD->INTMSK & ~(ints);
+}
+
+/**
+ * @brief	Clear Controller Interrupt
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	ints	: OR'ed interrupt bits to clear
+ * @return	None
+ */
+STATIC INLINE void Chip_LCD_ClearInts(LPC_LCD_T *pLCD, uint32_t ints)
+{
+	pLCD->INTCLR = pLCD->INTMSK & (ints);
+}
+
+/**
+ * @brief	Write Cursor Image into Internal Cursor Image Buffer
+ * @param	pLCD		: The base of LCD peripheral on the chip
+ * @param	cursor_num	: Cursor index
+ * @param	Image		: Pointer to image data
+ * @return	None
+ */
+void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image);
+
+/**
+ * @brief	Load LCD Palette
+ * @param	pLCD	: The base of LCD peripheral on the chip
+ * @param	palette	: Address of palette table to load
+ * @return	None
+ */
+void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette);
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __LCD_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/lpc_types.h b/hw/mcu/nxp/lpc_chip_40xx/inc/lpc_types.h
new file mode 100644
index 000000000..14c7b6050
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/lpc_types.h
@@ -0,0 +1,216 @@
+/*
+ * @brief Common types used in LPC functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __LPC_TYPES_H_
+#define __LPC_TYPES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/** @defgroup LPC_Types CHIP: LPC Common Types
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/** @defgroup LPC_Types_Public_Types LPC Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Boolean Type definition
+ */
+#if !defined(__cplusplus)
+// typedef enum {false = 0, true = !false} bool;
+#endif
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum {
+	NONE_BLOCKING = 0,		/**< None Blocking type */
+	BLOCKING,				/**< Blocking type */
+} TRANSFER_BLOCK_T;
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t (*PFI)();
+
+/**
+ * @}
+ */
+
+/** @defgroup LPC_Types_Public_Macros  LPC Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1 << (n))
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f, v) ((v) << (f))
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void *) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array)  (sizeof(array) / sizeof(array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/**
+ * @}
+ */
+
+/* Old Type Definition compatibility */
+/** @addtogroup LPC_Types_Public_Types
+ * @{
+ */
+
+/** LPC type for character type */
+typedef char CHAR;
+
+/** LPC type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** LPC type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** LPC type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** LPC type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** LPC type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** LPC type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** LPC type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** LPC type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+#ifdef __CODE_RED
+#define BOOL_32 bool
+#define BOOL_16 bool
+#define BOOL_8  bool
+#else
+/** 32 bit boolean type */
+typedef bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef bool BOOL_8;
+#endif
+
+#ifdef __CC_ARM
+#define INLINE  __inline
+#else
+#define INLINE inline
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* __LPC_TYPES_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/mcpwm_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/mcpwm_17xx_40xx.h
new file mode 100644
index 000000000..a0a8b37d5
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/mcpwm_17xx_40xx.h
@@ -0,0 +1,80 @@
+/*
+ * @brief LPC17xx/40xx Motor Control PWM driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __MCPWM_17XX_40XX_H_
+#define __MCPWM_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup MCPWM_17XX_40XX CHIP: LPC17xx/40xx Motor Control PWM driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief Motor Control PWM register block structure
+ */
+typedef struct {					/*!< MCPWM Structure        */
+	__I  uint32_t  CON;				/*!< PWM Control read address */
+	__O  uint32_t  CON_SET;			/*!< PWM Control set address */
+	__O  uint32_t  CON_CLR;			/*!< PWM Control clear address */
+	__I  uint32_t  CAPCON;			/*!< Capture Control read address */
+	__O  uint32_t  CAPCON_SET;		/*!< Capture Control set address */
+	__O  uint32_t  CAPCON_CLR;		/*!< Event Control clear address */
+	__IO uint32_t TC[3];			/*!< Timer Counter register */
+	__IO uint32_t LIM[3];			/*!< Limit register         */
+	__IO uint32_t MAT[3];			/*!< Match register         */
+	__IO uint32_t  DT;				/*!< Dead time register     */
+	__IO uint32_t  CCP;				/*!< Communication Pattern register */
+	__I  uint32_t CAP[3];			/*!< Capture register       */
+	__I  uint32_t  INTEN;			/*!< Interrupt Enable read address */
+	__O  uint32_t  INTEN_SET;		/*!< Interrupt Enable set address */
+	__O  uint32_t  INTEN_CLR;		/*!< Interrupt Enable clear address */
+	__I  uint32_t  CNTCON;			/*!< Count Control read address */
+	__O  uint32_t  CNTCON_SET;		/*!< Count Control set address */
+	__O  uint32_t  CNTCON_CLR;		/*!< Count Control clear address */
+	__I  uint32_t  INTF;			/*!< Interrupt flags read address */
+	__O  uint32_t  INTF_SET;		/*!< Interrupt flags set address */
+	__O  uint32_t  INTF_CLR;		/*!< Interrupt flags clear address */
+	__O  uint32_t  CAP_CLR;			/*!< Capture clear address  */
+} LPC_MCPWM_T;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCPWM_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/pmu_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/pmu_17xx_40xx.h
new file mode 100644
index 000000000..7255df228
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/pmu_17xx_40xx.h
@@ -0,0 +1,135 @@
+/*
+ * @brief LPC17xx_40xx PMU chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __PMU_17XX_40XX_H_
+#define __PMU_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup PMU_17XX_40XX CHIP: LPC17xx_40xx PMU driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief LPC17xx_40xx Power Management Unit register block structure
+ */
+typedef struct {
+	__IO uint32_t PCON;		/*!< Offset: 0x000 Power control Register (R/W) */
+} LPC_PMU_T;
+
+/**
+ * @brief LPC17xx_40xx low power mode type definitions
+ */
+typedef enum CHIP_PMU_MCUPOWER {
+	PMU_MCU_SLEEP = 0,		/*!< Sleep mode */
+	PMU_MCU_DEEP_SLEEP,		/*!< Deep Sleep mode */
+	PMU_MCU_POWER_DOWN,		/*!< Power down mode */
+	PMU_MCU_DEEP_PWRDOWN	/*!< Deep power down mode */
+} CHIP_PMU_MCUPOWER_T;
+
+/**
+ * PMU PCON register bit fields & masks
+ */
+#define PMU_PCON_PM0_FLAG			(1 << 0)
+#define PMU_PCON_PM1_FLAG			(1 << 1)
+#define PMU_PCON_BODRPM_FLAG		(1 << 2)
+#define PMU_PCON_BOGD_FLAG			(1 << 3)
+#define PMU_PCON_BORD_FLAG			(1 << 4)
+#define PMU_PCON_SMFLAG          	(1 << 8)	/*!< Sleep mode flag */
+#define PMU_PCON_DSFLAG          	(1 << 9)	/*!< Deep Sleep mode flag */
+#define PMU_PCON_PDFLAG             (1 << 10)	/*!< Power-down flag */
+#define PMU_PCON_DPDFLAG            (1 << 11)	/*!< Deep power-down flag */
+
+/**
+ * @brief	Enter MCU Sleep mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
+ * and memories are active.
+ */
+void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Enter MCU Deep Sleep mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	In Deep-sleep mode, the peripherals receive no internal clocks.
+ * The flash is in stand-by mode. The SRAM memory and all peripheral registers
+ * as well as the processor maintain their internal states. The WWDT, WKT,
+ * and BOD can remain active to wake up the system on an interrupt.
+ */
+void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Enter MCU Power down mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	In Power-down mode, the peripherals receive no internal clocks.
+ * The internal SRAM memory and all peripheral registers as well as the
+ * processor maintain their internal states. The flash memory is powered
+ * down. The WWDT, WKT, and BOD can remain active to wake up the system
+ * on an interrupt.
+ */
+void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Enter MCU Deep Power down mode
+ * @param	pPMU	: Pointer to PMU register block
+ * @return	None
+ * @note	For maximal power savings, the entire system is shut down
+ * except for the general purpose registers in the PMU and the self
+ * wake-up timer. Only the general purpose registers in the PMU maintain
+ * their internal states. The part can wake up on a pulse on the WAKEUP
+ * pin or when the self wake-up timer times out. On wake-up, the part
+ * reboots.
+ */
+void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
+
+/**
+ * @brief	Place the MCU in a low power state
+ * @param	pPMU		: Pointer to PMU register block
+ * @param	SleepMode	: Sleep mode
+ * @return	None
+ */
+void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PMU_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/qei_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/qei_17xx_40xx.h
new file mode 100644
index 000000000..ae2bb9352
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/qei_17xx_40xx.h
@@ -0,0 +1,86 @@
+/*
+ * @brief LPC17xx/40xx Quadrature Encoder Interface driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __QEI_17XX_40XX_H_
+#define __QEI_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup QEI_17XX_40XX CHIP: LPc17xx/40xx Quadrature Encoder Interface driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief Quadrature Encoder Interface register block structure
+ */
+typedef struct {				/*!< QEI Structure          */
+	__O  uint32_t  CON;			/*!< Control register       */
+	__I  uint32_t  STAT;		/*!< Encoder status register */
+	__IO uint32_t  CONF;		/*!< Configuration register */
+	__I  uint32_t  POS;			/*!< Position register      */
+	__IO uint32_t  MAXPOS;		/*!< Maximum position register */
+	__IO uint32_t  CMPOS0;		/*!< position compare register 0 */
+	__IO uint32_t  CMPOS1;		/*!< position compare register 1 */
+	__IO uint32_t  CMPOS2;		/*!< position compare register 2 */
+	__I  uint32_t  INXCNT;		/*!< Index count register   */
+	__IO uint32_t  INXCMP0;		/*!< Index compare register 0 */
+	__IO uint32_t  LOAD;		/*!< Velocity timer reload register */
+	__I  uint32_t  TIME;		/*!< Velocity timer register */
+	__I  uint32_t  VEL;			/*!< Velocity counter register */
+	__I  uint32_t  CAP;			/*!< Velocity capture register */
+	__IO uint32_t  VELCOMP;		/*!< Velocity compare register */
+	__IO uint32_t  FILTERPHA;	/*!< Digital filter register on input phase A (QEI_A) */
+	__IO uint32_t  FILTERPHB;	/*!< Digital filter register on input phase B (QEI_B) */
+	__IO uint32_t  FILTERINX;	/*!< Digital filter register on input index (QEI_IDX) */
+	__IO uint32_t  WINDOW;		/*!< Index acceptance window register */
+	__IO uint32_t  INXCMP1;		/*!< Index compare register 1 */
+	__IO uint32_t  INXCMP2;		/*!< Index compare register 2 */
+	__I  uint32_t  RESERVED0[993];
+	__O  uint32_t  IEC;			/*!< Interrupt enable clear register */
+	__O  uint32_t  IES;			/*!< Interrupt enable set register */
+	__I  uint32_t  INTSTAT;		/*!< Interrupt status register */
+	__I  uint32_t  IE;			/*!< Interrupt enable register */
+	__O  uint32_t  CLR;			/*!< Interrupt status clear register */
+	__O  uint32_t  SET;			/*!< Interrupt status set register */
+} LPC_QEI_T;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QEI_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/ring_buffer.h b/hw/mcu/nxp/lpc_chip_40xx/inc/ring_buffer.h
new file mode 100644
index 000000000..8c205fd3a
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/ring_buffer.h
@@ -0,0 +1,188 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RING_BUFFER_H_
+#define __RING_BUFFER_H_
+
+#include "lpc_types.h"
+
+/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief Ring buffer structure
+ */
+typedef struct {
+	void *data;
+	int count;
+	int itemSz;
+	uint32_t head;
+	uint32_t tail;
+} RINGBUFF_T;
+
+/**
+ * @def		RB_VHEAD(rb)
+ * volatile typecasted head index
+ */
+#define RB_VHEAD(rb)              (*(volatile uint32_t *) &(rb)->head)
+
+/**
+ * @def		RB_VTAIL(rb)
+ * volatile typecasted tail index
+ */
+#define RB_VTAIL(rb)              (*(volatile uint32_t *) &(rb)->tail)
+
+/**
+ * @brief	Initialize ring buffer
+ * @param	RingBuff	: Pointer to ring buffer to initialize
+ * @param	buffer		: Pointer to buffer to associate with RingBuff
+ * @param	itemSize	: Size of each buffer item size
+ * @param	count		: Size of ring buffer
+ * @note	Memory pointed by @a buffer must have correct alignment of
+ * 			@a itemSize, and @a count must be a power of 2 and must at
+ * 			least be 2 or greater.
+ * @return	Nothing
+ */
+int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
+
+/**
+ * @brief	Resets the ring buffer to empty
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Nothing
+ */
+STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff)
+{
+	RingBuff->head = RingBuff->tail = 0;
+}
+
+/**
+ * @brief	Return size the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Size of the ring buffer in bytes
+ */
+STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff)
+{
+	return RingBuff->count;
+}
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Number of items in the ring buffer
+ */
+STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
+{
+	return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff);
+}
+
+/**
+ * @brief	Return number of free items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	Number of free items in the ring buffer
+ */
+STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff)
+{
+	return RingBuff->count - RingBuffer_GetCount(RingBuff);
+}
+
+/**
+ * @brief	Return number of items in the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	1 if the ring buffer is full, otherwise 0
+ */
+STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff)
+{
+	return (RingBuffer_GetCount(RingBuff) >= RingBuff->count);
+}
+
+/**
+ * @brief	Return empty status of ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @return	1 if the ring buffer is empty, otherwise 0
+ */
+STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
+{
+	return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff);
+}
+
+/**
+ * @brief	Insert a single item into ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: pointer to item
+ * @return	1 when successfully inserted,
+ *			0 on error (Buffer not initialized using
+ *			RingBuffer_Init() or attempted to insert
+ *			when buffer is full)
+ */
+int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data);
+
+/**
+ * @brief	Insert an array of items into ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: Pointer to first element of the item array
+ * @param	num			: Number of items in the array
+ * @return	number of items successfully inserted,
+ *			0 on error (Buffer not initialized using
+ *			RingBuffer_Init() or attempted to insert
+ *			when buffer is full)
+ */
+int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num);
+
+/**
+ * @brief	Pop an item from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: Pointer to memory where popped item be stored
+ * @return	1 when item popped successfuly onto @a data,
+ * 			0 When error (Buffer not initialized using
+ * 			RingBuffer_Init() or attempted to pop item when
+ * 			the buffer is empty)
+ */
+int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data);
+
+/**
+ * @brief	Pop an array of items from the ring buffer
+ * @param	RingBuff	: Pointer to ring buffer
+ * @param	data		: Pointer to memory where popped items be stored
+ * @param	num			: Max number of items array @a data can hold
+ * @return	Number of items popped onto @a data,
+ * 			0 on error (Buffer not initialized using RingBuffer_Init()
+ * 			or attempted to pop when the buffer is empty)
+ */
+int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num);
+
+
+/**
+ * @}
+ */
+
+#endif /* __RING_BUFFER_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/ritimer_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/ritimer_17xx_40xx.h
new file mode 100644
index 000000000..2aa2b4fe1
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/ritimer_17xx_40xx.h
@@ -0,0 +1,199 @@
+/*
+ * @brief LPC17xx/40xx RITimer driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RITIMER_17XX_40XX_H_
+#define __RITIMER_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RIT_17XX_40XX CHIP: LPC17xx/40xx Repetitive Interrupt Timer driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC175X_6X)
+
+/**
+ * @brief Repetitive Interrupt Timer register block structure
+ */
+typedef struct {				/*!< RITIMER Structure      */
+	__IO uint32_t  COMPVAL;		/*!< Compare register       */
+	__IO uint32_t  MASK;		/*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
+	__IO uint32_t  CTRL;		/*!< Control register.      */
+	__IO uint32_t  COUNTER;		/*!< 32-bit counter         */
+#if defined(CHIP_LPC1347)
+	__IO uint32_t  COMPVAL_H;	/*!< Compare upper register */
+	__IO uint32_t  MASK_H;		/*!< Mask upper register    */
+	__I  uint32_t  RESERVED0[1];
+	__IO uint32_t  COUNTER_H;	/*!< Counter upper register */
+#endif
+} LPC_RITIMER_T;
+
+/*
+ * @brief RITIMER register support bitfields and mask
+ */
+
+/*
+ * RIT control register
+ */
+/**	Set by H/W when the counter value equals the masked compare value */
+#define RIT_CTRL_INT    ((uint32_t) (1))
+/** Set timer enable clear to 0 when the counter value equals the masked compare value  */
+#define RIT_CTRL_ENCLR  ((uint32_t) _BIT(1))
+/** Set timer enable on debug */
+#define RIT_CTRL_ENBR   ((uint32_t) _BIT(2))
+/** Set timer enable */
+#define RIT_CTRL_TEN    ((uint32_t) _BIT(3))
+
+/**
+ * @brief	Initialize the RIT
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+void Chip_RIT_Init(LPC_RITIMER_T *pRITimer);
+
+/**
+ * @brief	Shutdown the RIT
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer);
+
+/**
+ * @brief	Enable Timer
+ * @param	pRITimer		: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Enable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL |= RIT_CTRL_TEN;
+}
+
+/**
+ * @brief	Disable Timer
+ * @param	pRITimer		: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_Disable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL &= ~RIT_CTRL_TEN;
+}
+
+/**
+ * @brief	Enable timer debug
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_TimerDebugEnable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL |= RIT_CTRL_ENBR;
+}
+
+/**
+ * @brief	Disable timer debug
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_TimerDebugDisable(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL &= ~RIT_CTRL_ENBR;
+}
+
+/**
+ * @brief	Check whether interrupt flag is set or not
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	Current interrupt status, either ET or UNSET
+ */
+IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer);
+
+/**
+ * @brief	Set a tick value for the interrupt to time out
+ * @param	pRITimer	: RITimer peripheral selected
+ * @param	val			: value (in ticks) of the interrupt to be set
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_SetCOMPVAL(LPC_RITIMER_T *pRITimer, uint32_t val)
+{
+	pRITimer->COMPVAL = val;
+}
+
+/**
+ * @brief	Enables or clears the RIT or interrupt
+ * @param	pRITimer	: RITimer peripheral selected
+ * @param	val			: RIT to be set, one or more RIT_CTRL_* values
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_EnableCTRL(LPC_RITIMER_T *pRITimer, uint32_t val)
+{
+	pRITimer->CTRL |= val;
+}
+
+/**
+ * @brief	Clears the RIT interrupt
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	None
+ */
+STATIC INLINE void Chip_RIT_ClearInt(LPC_RITIMER_T *pRITimer)
+{
+	pRITimer->CTRL |= RIT_CTRL_INT;
+}
+
+/**
+ * @brief	Returns the current RIT Counter value
+ * @param	pRITimer	: RITimer peripheral selected
+ * @return	the current timer counter value
+ */
+STATIC INLINE uint32_t Chip_RIT_GetCounter(LPC_RITIMER_T *pRITimer)
+{
+	return pRITimer->COUNTER;
+}
+
+/**
+ * @brief	Set timer interval value
+ * @param	pRITimer		: RITimer peripheral selected
+ * @param	time_interval	: timer interval value (ms)
+ * @return	None
+ */
+void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval);
+
+#endif /* defined(CHIP_LPC175X_6X) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RITIMER_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/romapi_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/romapi_17xx_40xx.h
new file mode 100644
index 000000000..95cbd1441
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/romapi_17xx_40xx.h
@@ -0,0 +1,91 @@
+/*
+ * @brief LPC17xx/40xx ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __ROMAPI_17XX40XX_H_
+#define __ROMAPI_17XX40XX_H_
+
+#include "iap.h"
+#include "error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ROMAPI_407X_8X CHIP: LPC17XX/40XX ROM API declarations and functions
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if !defined(CHIP_LPC175X_6X)
+/**
+ * @brief LPC17XX/40XX High level ROM API structure
+ */
+typedef struct {
+	const uint32_t usbdApiBase;			/*!< USBD API function table base address */
+	const uint32_t reserved0;			/*!< Reserved */
+	const uint32_t reserved1;			/*!< Reserved */
+	const uint32_t reserved2;			/*!< Reserved */
+	const uint32_t reserved3;			/*!< Reserved */
+	const uint32_t reserved4;			/*!< Reserved */
+	const uint32_t reserved5;			/*!< Reserved */
+	const uint32_t reserved6;			/*!< Reserved */
+	const uint32_t reserved7;			/*!< Reserved */
+	const uint32_t reserved8;			/*!< Reserved */
+	const uint32_t reserved9;			/*!< Reserved */
+	const uint32_t reserved10;		/*!< Reserved */
+} LPC_ROM_API_T;
+
+/* Pointer to ROM API function address */
+#define LPC_ROM_API_BASE_LOC	0x1FFF1FF8
+#define LPC_ROM_API		(*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC)
+
+#endif /* !defined(CHIP_LPC175X_6X) */
+
+/* Pointer to ROM IAP entry functions */
+#define IAP_ENTRY_LOCATION		0X1FFF1FF1
+
+/**
+ * @brief LPC17XX/40XX IAP_ENTRY API function type
+ */
+static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4])
+{
+	((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ROMAPI_17XX40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/rtc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/rtc_17xx_40xx.h
new file mode 100644
index 000000000..4d437f227
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/rtc_17xx_40xx.h
@@ -0,0 +1,646 @@
+/*
+ * @brief LPC17xx/40xx RTC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __RTC_17XX_40XX_H_
+#define __RTC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup RTC_17XX_40XX CHIP: LPC17xx/40xx Real Time Clock driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+#define RTC_EV_SUPPORT      1				/* Event Monitor/Recorder support */
+#endif
+
+/**
+ * @brief RTC time type option
+ */
+typedef enum {
+	RTC_TIMETYPE_SECOND,		/*!< Second */
+	RTC_TIMETYPE_MINUTE,		/*!< Month */
+	RTC_TIMETYPE_HOUR,			/*!< Hour */
+	RTC_TIMETYPE_DAYOFMONTH,	/*!< Day of month */
+	RTC_TIMETYPE_DAYOFWEEK,		/*!< Day of week */
+	RTC_TIMETYPE_DAYOFYEAR,		/*!< Day of year */
+	RTC_TIMETYPE_MONTH,			/*!< Month */
+	RTC_TIMETYPE_YEAR,			/*!< Year */
+	RTC_TIMETYPE_LAST
+} RTC_TIMEINDEX_T;
+
+#if RTC_EV_SUPPORT
+/**
+ * @brief Event Channel Identifier definitions
+ */
+typedef enum {
+	RTC_EV_CHANNEL_1 = 0,
+	RTC_EV_CHANNEL_2,
+	RTC_EV_CHANNEL_3,
+	RTC_EV_CHANNEL_NUM,
+} RTC_EV_CHANNEL_T;
+#endif /*RTC_EV_SUPPORT*/
+
+/**
+ * @brief Real Time Clock register block structure
+ */
+typedef struct {							/*!< RTC Structure          */
+	__IO uint32_t  ILR;						/*!< Interrupt Location Register */
+	__I  uint32_t  RESERVED0;
+	__IO uint32_t  CCR;						/*!< Clock Control Register */
+	__IO uint32_t  CIIR;					/*!< Counter Increment Interrupt Register */
+	__IO uint32_t  AMR;						/*!< Alarm Mask Register    */
+	__I  uint32_t  CTIME[3];				/*!< Consolidated Time Register 0,1,2 */
+	__IO uint32_t  TIME[RTC_TIMETYPE_LAST];	/*!< Timer field registers */
+	__IO uint32_t  CALIBRATION;				/*!< Calibration Value Register */
+	__IO uint32_t GPREG[5];					/*!< General Purpose Storage Registers */
+	__IO uint32_t RTC_AUXEN;				/*!< RTC Auxiliary Enable register */
+	__IO uint32_t RTC_AUX;					/*!< RTC Auxiliary control register*/
+	__IO uint32_t  ALRM[RTC_TIMETYPE_LAST];	/*!< Alarm field registers */
+#if RTC_EV_SUPPORT
+	__IO uint32_t ERSTATUS;					/*!< Event Monitor/Recorder Status register*/
+	__IO uint32_t ERCONTROL;				/*!< Event Monitor/Recorder Control register*/
+	__I  uint32_t ERCOUNTERS;				/*!< Event Monitor/Recorder Counters register*/
+	__I  uint32_t RESERVED2;
+	__I  uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM];			/*!<Event Monitor/Recorder First Stamp registers*/
+	__I  uint32_t RESERVED3;
+	__I  uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM];			/*!<Event Monitor/Recorder Last Stamp registers*/
+#endif /*RTC_EV_SUPPORT*/
+} LPC_RTC_T;
+
+/**
+ * @brief Register File register block structure
+ */
+typedef struct {
+	__IO uint32_t REGFILE[5];	/*!< General purpose storage register */
+} LPC_REGFILE_T;
+
+/*
+ * @brief ILR register definitions
+ */
+/** ILR register mask */
+#define RTC_ILR_BITMASK         ((0x00000003))
+/** Bit inform the source interrupt is counter increment*/
+#define RTC_IRL_RTCCIF          ((1 << 0))
+/** Bit inform the source interrupt is alarm match*/
+#define RTC_IRL_RTCALF          ((1 << 1))
+
+/*
+ * @brief CCR register definitions
+ */
+/** CCR register mask */
+#define RTC_CCR_BITMASK         ((0x00000013))
+/** Clock enable */
+#define RTC_CCR_CLKEN           ((1 << 0))
+/** Clock reset */
+#define RTC_CCR_CTCRST          ((1 << 1))
+/** Calibration counter enable */
+#define RTC_CCR_CCALEN          ((1 << 4))
+
+/*
+ * @brief CIIR and AMR register definitions
+ */
+/** Counter Increment Interrupt bit for second */
+#define RTC_AMR_CIIR_IMSEC          ((1 << 0))
+/** Counter Increment Interrupt bit for minute */
+#define RTC_AMR_CIIR_IMMIN          ((1 << 1))
+/** Counter Increment Interrupt bit for hour */
+#define RTC_AMR_CIIR_IMHOUR         ((1 << 2))
+/** Counter Increment Interrupt bit for day of month */
+#define RTC_AMR_CIIR_IMDOM          ((1 << 3))
+/** Counter Increment Interrupt bit for day of week */
+#define RTC_AMR_CIIR_IMDOW          ((1 << 4))
+/** Counter Increment Interrupt bit for day of year */
+#define RTC_AMR_CIIR_IMDOY          ((1 << 5))
+/** Counter Increment Interrupt bit for month */
+#define RTC_AMR_CIIR_IMMON          ((1 << 6))
+/** Counter Increment Interrupt bit for year */
+#define RTC_AMR_CIIR_IMYEAR         ((1 << 7))
+/** CIIR bit mask */
+#define RTC_AMR_CIIR_BITMASK        ((0xFF))
+
+/*
+ * @brief RTC_AUX register definitions
+ */
+/** RTC Oscillator Fail detect flag */
+#define RTC_AUX_RTC_OSCF        ((1 << 4))
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+/** RTC_ALARM pin control flag */
+#define RTC_AUX_RTC_PDOUT       ((1 << 6))
+#endif
+
+/*
+ * @brief RTC_AUXEN register definitions
+ */
+/** Oscillator Fail Detect interrupt enable*/
+#define RTC_AUXEN_RTC_OSCFEN    ((1 << 4))
+
+/*
+ * @brief Consolidated Time Register 0 definitions
+ */
+#define RTC_CTIME0_SECONDS_MASK     ((0x3F))
+#define RTC_CTIME0_MINUTES_MASK     ((0x3F00))
+#define RTC_CTIME0_HOURS_MASK       ((0x1F0000))
+#define RTC_CTIME0_DOW_MASK         ((0x7000000))
+
+/*
+ * @brief Consolidated Time Register 1 definitions
+ */
+#define RTC_CTIME1_DOM_MASK         ((0x1F))
+#define RTC_CTIME1_MONTH_MASK       ((0xF00))
+#define RTC_CTIME1_YEAR_MASK        ((0xFFF0000))
+
+/*
+ * @brief Consolidated Time Register 2 definitions
+ */
+#define RTC_CTIME2_DOY_MASK         ((0xFFF))
+
+/*
+ * @brief Time Counter Group and Alarm register group
+ */
+/** SEC register mask */
+#define RTC_SEC_MASK            (0x0000003F)
+/** MIN register mask */
+#define RTC_MIN_MASK            (0x0000003F)
+/** HOUR register mask */
+#define RTC_HOUR_MASK           (0x0000001F)
+/** DOM register mask */
+#define RTC_DOM_MASK            (0x0000001F)
+/** DOW register mask */
+#define RTC_DOW_MASK            (0x00000007)
+/** DOY register mask */
+#define RTC_DOY_MASK            (0x000001FF)
+/** MONTH register mask */
+#define RTC_MONTH_MASK          (0x0000000F)
+/** YEAR register mask */
+#define RTC_YEAR_MASK           (0x00000FFF)
+
+#define RTC_SECOND_MAX      59	/*!< Maximum value of second */
+#define RTC_MINUTE_MAX      59	/*!< Maximum value of minute*/
+#define RTC_HOUR_MAX        23	/*!< Maximum value of hour*/
+#define RTC_MONTH_MIN       1	/*!< Minimum value of month*/
+#define RTC_MONTH_MAX       12	/*!< Maximum value of month*/
+#define RTC_DAYOFMONTH_MIN  1	/*!< Minimum value of day of month*/
+#define RTC_DAYOFMONTH_MAX  31	/*!< Maximum value of day of month*/
+#define RTC_DAYOFWEEK_MAX   6	/*!< Maximum value of day of week*/
+#define RTC_DAYOFYEAR_MIN   1	/*!< Minimum value of day of year*/
+#define RTC_DAYOFYEAR_MAX   366	/*!< Maximum value of day of year*/
+#define RTC_YEAR_MAX        4095/*!< Maximum value of year*/
+
+/*
+ * @brief Calibration register
+ */
+/** Calibration value */
+#define RTC_CALIBRATION_CALVAL_MASK     ((0x1FFFF))
+/** Calibration direction */
+#define RTC_CALIBRATION_LIBDIR          ((1 << 17))
+/** Calibration max value */
+#define RTC_CALIBRATION_MAX             ((0x20000))
+/** Calibration definitions */
+#define RTC_CALIB_DIR_FORWARD           ((uint8_t) (0))
+#define RTC_CALIB_DIR_BACKWARD          ((uint8_t) (1))
+
+#if RTC_EV_SUPPORT
+/*
+ * @brief Event Monitor/Recorder Control register
+ */
+/**  Event Monitor/Recorder Control register mask */
+#define RTC_ERCTRL_BITMASK          ((uint32_t) 0xC0F03C0F)
+/** Enable event interrupt and wakeup */
+#define RTC_ERCTRL_INTWAKE_EN       ((uint32_t) (1 << 0))
+/** Enables automatically clearing the RTC general purpose registers when an event occurs*/
+#define RTC_ERCTRL_GPCLEAR_EN       ((uint32_t) (1 << 1))
+/** Select polarity for a channel event on the input pin.*/
+#define RTC_ERCTRL_POL_NEGATIVE     (0)		/* Event as positive edge */
+#define RTC_ERCTRL_POL_POSITIVE     ((uint32_t) (1 << 2))	/* Event as negative edge */
+/** Enable event input.*/
+#define RTC_ERCTRL_INPUT_EN         ((uint32_t) (1 << 3))
+/** Configure a specific channel */
+#define RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch)   ((uint32_t) (0x0F << (10 * ch)))
+#define RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) ((uint32_t) (flag << (10 * ch)))
+
+/** Enable Event Monitor/Recorder and select its operating frequency.*/
+#define RTC_ERCTRL_MODE_MASK                (((uint32_t) 3) << 30)
+#define RTC_ERCTRL_MODE_CLK_DISABLE         (((uint32_t) 0) << 30)
+#define RTC_ERCTRL_MODE_16HZ                (((uint32_t) 1) << 30)
+#define RTC_ERCTRL_MODE_64HZ                (((uint32_t) 2) << 30)
+#define RTC_ERCTRL_MODE_1KHZ                (((uint32_t) 3) << 30)
+#define RTC_ERCTRL_MODE(n)                  (((uint32_t) n) << 30)
+
+/*
+ * @brief Event Monitor/Recorder Status register
+ */
+/** Event Flag for a specific channel */
+#define RTC_ERSTATUS_CHANNEL_EV(ch)               ((uint32_t) (1 << ch))		/* At least 1 event has occurred on a specific channel */
+/** General purpose registers have been asynchronous cleared. */
+#define RTC_ERSTATUS_GPCLEARED            ((uint32_t) (1 << 3))
+/** An interrupt/wakeup request is pending.*/
+#define RTC_ERSTATUS_WAKEUP            ((uint32_t) (((uint32_t) 1) << 31))
+
+/*
+ * @brief Event Monitor/Recorder Counter register
+ */
+/** Value of the counter for Events occurred on a specific channel */
+#define RTC_ER_COUNTER(ch, n)            ((uint32_t) ((n >> (8 * ch)) & 0x07))
+
+/*
+ * @brief Event Monitor/Recorder TimeStamp register
+ */
+#define RTC_ER_TIMESTAMP_SEC(n)             ((uint32_t) (n & 0x3F))
+#define RTC_ER_TIMESTAMP_MIN(n)             ((uint32_t) ((n >> 6) & 0x3F))
+#define RTC_ER_TIMESTAMP_HOUR(n)            ((uint32_t) ((n >> 12) & 0x1F))
+#define RTC_ER_TIMESTAMP_DOY(n)             ((uint32_t) ((n >> 17) & 0x1FF))
+
+/**
+ * @brief Event Monitor/Recorder Mode definition
+ */
+typedef enum IP_RTC_EV_MODE {
+	RTC_EV_MODE_DISABLE = 0,		/*!< Event Monitor/Recoder is disabled */
+	RTC_EV_MODE_ENABLE_16HZ =  1,	/*!< Event Monitor/Recoder is enabled and use 16Hz sample clock for event input */
+	RTC_EV_MODE_ENABLE_64HZ = 2,	/*!< Event Monitor/Recoder is enabled and use 64Hz sample clock for event input */
+	RTC_EV_MODE_ENABLE_1KHZ = 3,	/*!< Event Monitor/Recoder is enabled and use 1kHz sample clock for event input */
+	RTC_EV_MODE_LAST,
+} RTC_EV_MODE_T;
+
+/**
+ * @brief Event Monitor/Recorder Timestamp structure
+ */
+typedef struct {
+	uint8_t     sec;		/*!<   Second */
+	uint8_t     min;		/*!<   Minute */
+	uint8_t     hour;		/*!<   Hour */
+	uint16_t    dayofyear;	/*!<   Day of year */
+} RTC_EV_TIMESTAMP_T;
+
+#endif /*RTC_EV_SUPPORT*/
+
+/**
+ * @brief RTC enumeration
+ */
+
+/** @brief RTC interrupt source */
+typedef enum {
+	RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF,	/*!<  Counter Increment Interrupt */
+	RTC_INT_ALARM = RTC_IRL_RTCALF				/*!< The alarm interrupt */
+} RTC_INT_OPT_T;
+
+typedef struct {
+	uint32_t time[RTC_TIMETYPE_LAST];
+} RTC_TIME_T;
+
+/**
+ * @brief	Reset clock tick counter in the RTC peripheral
+ * @param	pRTC	: RTC peripheral selected
+ * @return	None
+ */
+void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC);
+
+/**
+ * @brief	Start/Stop RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	NewState	: New State of this function, should be:
+ *							- ENABLE	:The time counters are enabled
+ *							- DISABLE	:The time counters are disabled
+ * @return	None
+ */
+void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState);
+
+/**
+ * @brief	Enable/Disable Counter increment interrupt for a time type in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	cntrMask	: Or'ed bit values for time types (RTC_AMR_CIIR_IM*)
+ * @param	NewState	: ENABLE or DISABLE
+ * @return	None
+ */
+void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState);
+
+/**
+ * @brief	Enable/Disable Alarm interrupt for a time type in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	alarmMask	: Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*)
+ * @param	NewState	: ENABLE or DISABLE
+ * @return	None
+ */
+void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState);
+
+/**
+ * @brief	Set current time value for a time type in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	Timetype	: time field index type to set
+ * @param	TimeValue	: Value to palce in time field
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_SetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
+{
+	pRTC->TIME[Timetype] = TimeValue;
+}
+
+/**
+ * @brief	Get current time value for a type time type
+ * @param	pRTC		: RTC peripheral selected
+ * @param	Timetype	: Time field index type to get
+ * @return	Value of time field according to specified time type
+ */
+STATIC INLINE uint32_t Chip_RTC_GetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype)
+{
+	return pRTC->TIME[Timetype];
+}
+
+/**
+ * @brief	Set full time in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	pFullTime	: Pointer to full time data
+ * @return	None
+ */
+void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
+
+/**
+ * @brief	Get full time from the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	pFullTime	: Pointer to full time record to fill
+ * @return	None
+ */
+void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
+
+/**
+ * @brief	Set alarm time value for a time type
+ * @param	pRTC		: RTC peripheral selected
+ * @param	Timetype	: Time index field to set
+ * @param	ALValue		: Alarm time value to set
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_SetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
+{
+	pRTC->ALRM[Timetype] = ALValue;
+}
+
+/**
+ * @brief	Get alarm time value for a time type
+ * @param	pRTC		: RTC peripheral selected
+ * @param	Timetype	: Time index field to get
+ * @return	Value of Alarm time according to specified time type
+ */
+STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype)
+{
+	return pRTC->ALRM[Timetype];
+}
+
+/**
+ * @brief	Set full alarm time in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	pFullTime	: Pointer to full time record to set alarm
+ * @return	None
+ */
+void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
+
+/**
+ * @brief	Get full alarm time in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	pFullTime	: Pointer to full time record to fill
+ * @return	None
+ */
+void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
+
+/**
+ * @brief	Write value to General purpose registers
+ * @param	pRegFile	: RegFile peripheral selected
+ * @param	index		: General purpose register index
+ * @param	value		: Value to write
+ * @return	None
+ * @note	These General purpose registers can be used to store important
+ * information when the main power supply is off. The value in these
+ * registers is not affected by chip reset. These registers are
+ * powered in the RTC power domain.
+ */
+STATIC INLINE void Chip_REGFILE_Write(LPC_REGFILE_T *pRegFile, uint8_t index, uint32_t value)
+{
+	pRegFile->REGFILE[index] = value;
+}
+
+/**
+ * @brief	Read value from General purpose registers
+ * @param	pRegFile	: RegFile peripheral selected
+ * @param	index		: General purpose register index
+ * @return	Read Value
+ * @note	These General purpose registers can be used to store important
+ * information when the main power supply is off. The value in these
+ * registers is not affected by chip reset. These registers are
+ * powered in the RTC power domain.
+ */
+STATIC INLINE uint32_t Chip_REGFILE_Read(LPC_REGFILE_T *pRegFile, uint8_t index)
+{
+	return pRegFile->REGFILE[index];
+}
+
+/**
+ * @brief	Enable/Disable calibration counter in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	NewState	: New State of this function, should be:
+ *							- ENABLE	:The calibration counter is enabled and counting
+ *							- DISABLE	:The calibration counter is disabled and reset to zero
+ * @return	None
+ */
+void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState);
+
+/**
+ * @brief	Configures Calibration in the RTC peripheral
+ * @param	pRTC		: RTC peripheral selected
+ * @param	CalibValue	: Calibration value, should be in range from 0 to 131,072
+ * @param	CalibDir	: Calibration Direction, should be:
+ *							- RTC_CALIB_DIR_FORWARD		:Forward calibration
+ *							- RTC_CALIB_DIR_BACKWARD	:Backward calibration
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_CalibConfig(LPC_RTC_T *pRTC, uint32_t CalibValue, uint8_t CalibDir)
+{
+	pRTC->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK)
+						| ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
+}
+
+/**
+ * @brief	Clear specified Location interrupt pending in the RTC peripheral
+ * @param	pRTC	: RTC peripheral selected
+ * @param	IntType	: Interrupt location type, should be:
+ *						- RTC_INT_COUNTER_INCREASE	:Clear Counter Increment Interrupt pending.
+ *						- RTC_INT_ALARM				:Clear alarm interrupt pending
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_ClearIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
+{
+	pRTC->ILR = IntType;
+}
+
+/**
+ * @brief	Check whether if specified location interrupt in the RTC peripheral is set or not
+ * @param	pRTC	: RTC peripheral selected
+ * @param	IntType	: Interrupt location type, should be:
+ *						- RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt.
+ *						- RTC_INT_ALARM: Alarm generated an interrupt.
+ * @return	New state of specified Location interrupt in RTC peripheral, SET OR RESET
+ */
+STATIC INLINE IntStatus Chip_RTC_GetIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
+{
+	return (pRTC->ILR & IntType) ? SET : RESET;
+}
+
+#if RTC_EV_SUPPORT
+
+/**
+ * @brief	Configure a specific event channel
+ * @param	pRTC	: RTC peripheral selected
+ * @param	ch		: Channel number
+ * @param	flag	: Configuration flag
+ * @return	None
+ * @note	flag is or-ed bit value of RTC_ERCTRL_INTWAKE_EN,RTC_ERCTRL_GPCLEAR_EN,
+ *       RTC_ERCTRL_POL_POSITIVE and RTC_ERCTRL_INPUT_EN.
+ */
+STATIC INLINE void Chip_RTC_EV_Config(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, uint32_t flag)
+{
+	uint32_t temp;
+
+	temp = pRTC->ERCONTROL & (~(RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch))) & RTC_ERCTRL_BITMASK;
+	pRTC->ERCONTROL = temp | (RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) & RTC_ERCTRL_BITMASK);
+}
+
+/**
+ * @brief	Enable/Disable and select clock frequency for Event Monitor/Recorder
+ * @param	pRTC	: RTC peripheral selected
+ * @param	mode	: selected mode
+ * @return	None
+ */
+STATIC INLINE void Chip_RTC_EV_SetMode(LPC_RTC_T *pRTC, RTC_EV_MODE_T mode)
+{
+	uint32_t temp;
+
+	temp = pRTC->ERCONTROL & (~RTC_ERCTRL_MODE_MASK) & RTC_ERCTRL_BITMASK;
+	pRTC->ERCONTROL = temp | RTC_ERCTRL_MODE(mode);
+}
+
+/**
+ * @brief	Get Event Monitor/Recorder Status
+ * @param	pRTC	: RTC peripheral selected
+ * @return	Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP
+ */
+STATIC INLINE uint8_t Chip_RTC_EV_GetStatus(LPC_RTC_T *pRTC)
+{
+	return pRTC->ERSTATUS & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
+}
+
+/**
+ * @brief	Clear Event Monitor/Recorder Status
+ * @param	pRTC	: RTC peripheral selected
+ * @param	flag	: Or-ed bit value of RTC_ERSTATUS_GPCLEARED and RTC_ERSTATUS_WAKEUP
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_RTC_EV_ClearStatus(LPC_RTC_T *pRTC, uint32_t flag)
+{
+	pRTC->ERSTATUS = flag & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
+}
+
+/**
+ * @brief	Get status of a specific event channel
+ * @param	pRTC	: RTC peripheral selected
+ * @param	ch		: Channel number
+ * @return	SET (At least 1 event occurred on the channel), RESET: no event occured.
+ */
+STATIC INLINE FlagStatus Chip_RTC_EV_GetChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
+{
+	return (pRTC->ERSTATUS & RTC_ERSTATUS_CHANNEL_EV(ch)) ? SET : RESET;
+}
+
+/**
+ * @brief	Clear status of a specific event channel
+ * @param	pRTC	: RTC peripheral selected
+ * @param	ch		: Channel number
+ * @return	Nothing.
+ */
+STATIC INLINE void Chip_RTC_EV_ClearChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
+{
+	pRTC->ERSTATUS = RTC_ERSTATUS_CHANNEL_EV(ch);
+}
+
+/**
+ * @brief	Get counter value of a specific event channel
+ * @param	pRTC	: RTC peripheral selected
+ * @param	ch		: Channel number
+ * @return	counter value
+ */
+STATIC INLINE uint8_t Chip_RTC_EV_GetCounter(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
+{
+	return RTC_ER_COUNTER(ch, pRTC->ERCOUNTERS);
+}
+
+/**
+ * @brief	Get first time stamp of a specific event channel
+ * @param	pRTC		: RTC peripheral selected
+ * @param	ch			: Channel number
+ * @param	pTimeStamp	: pointer to Timestamp buffer
+ * @return	Nothing.
+ */
+void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp);
+
+/**
+ * @brief	Get last time stamp of a specific event channel
+ * @param	pRTC		: RTC peripheral selected
+ * @param	ch			: Channel number
+ * @param	pTimeStamp	: pointer to Timestamp buffer
+ * @return	Nothing.
+ */
+void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp);
+
+#endif /*RTC_EV_SUPPORT*/
+
+/**
+ * @brief	Initialize the RTC peripheral
+ * @param	pRTC	: RTC peripheral selected
+ * @return	None
+ */
+void Chip_RTC_Init(LPC_RTC_T *pRTC);
+
+/**
+ * @brief	De-initialize the RTC peripheral
+ * @param	pRTC	: RTC peripheral selected
+ * @return	None
+ */
+void Chip_RTC_DeInit(LPC_RTC_T *pRTC);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __RTC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/sdc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/sdc_17xx_40xx.h
new file mode 100644
index 000000000..9fb0d5181
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/sdc_17xx_40xx.h
@@ -0,0 +1,583 @@
+/*
+ * @brief LPC17xx/40xx SD Card Interface driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SDC_17XX_40XX_H_
+#define __SDC_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SDC_17XX_40XX CHIP: LPC17xx/40xx SD Card Interafce driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * SD/MMC card Interface
+ * @{
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/**
+ * @brief SD/MMC card Interface (SDC) register block structure
+ */
+typedef struct {
+	__IO uint32_t POWER;		/*!< Power Control register */
+	__IO uint32_t CLOCK;		/*!< Clock control regsiter */
+	__IO uint32_t ARGUMENT;		/*!< Command argument register */
+	__IO uint32_t COMMAND;		/*!< Command register */
+	__I  uint32_t RESPCMD;		/*!< Command response register */
+	__I  uint32_t RESPONSE[4];	/*!< Response registers */
+	__IO uint32_t DATATIMER;	/*!< Data timer register */
+	__IO uint32_t DATALENGTH;	/*!< Data length register */
+	__IO uint32_t DATACTRL;		/*!< Data control register */
+	__I  uint32_t DATACNT;		/*!< Data count register */
+	__I  uint32_t STATUS;		/*!< Status register */
+	__O  uint32_t CLEAR;		/*!< Clear register */
+	__IO uint32_t MASK0;		/*!< Mask 0 register */
+	uint32_t RESERVED0[2];
+	__I  uint32_t FIFOCNT;		/*!< FIFO count register */
+	uint32_t RESERVED1[13];
+	__IO uint32_t FIFO[16];		/*!< FIFO registers */
+} LPC_SDC_T;
+
+/**
+ * @brief SDC Power Control Register bit definitions
+ */
+/** SDC Power Control Register Bitmask */
+#define SDC_PWR_BITMASK         ((uint32_t) 0xC3)
+/** SDC Power Control Bit Mask */
+#define SDC_PWR_CTRL_BITMASK    (((uint32_t) 0x03) << 0)
+/** SDC Power Control */
+#define SDC_PWR_CTRL(n)         (((uint32_t) (n & 0x03)) << 0)
+/** SD_CMD Output Control */
+#define SDC_PWR_OPENDRAIN       (((uint32_t) 1) << 6)
+/** Rod Control */
+#define SDC_PWR_ROD             (((uint32_t) 1) << 7)
+
+/**
+ * @brief SDC Clock Control Register bit definitions
+ */
+/** SDC Clock Control Register Bitmask */
+#define SDC_CLOCK_BITMASK       ((uint32_t) 0xFFF)
+/** SDC Clock Divider Bitmask */
+#define SDC_CLOCK_CLKDIV_BITMASK    (((uint32_t) 0xFF ) << 0)
+/** Set SDC Clock Divide value */
+#define SDC_CLOCK_CLKDIV(n)     (((uint32_t) (n & 0x0FF)) << 0)
+
+/**
+ * @brief SDC Command Register bit definitions
+ */
+/** SDC Command Register Bitmask */
+#define SDC_COMMAND_BITMASK     ((uint32_t) 0x7FF)
+/** SDC Command Index Bitmask */
+#define SDC_COMMAND_INDEX_BITMASK   ((uint32_t) 0x3F)
+/** Set SDC Command Index */
+#define SDC_COMMAND_INDEX(n)        ((uint32_t) n & 0x3F)
+/** No response is expected */
+#define SDC_COMMAND_NO_RSP          (((uint32_t) 0 ) << 6)
+/** Short response is expected */
+#define SDC_COMMAND_SHORT_RSP       (((uint32_t) 1 ) << 6)
+/** Long response is expected */
+#define SDC_COMMAND_LONG_RSP        (((uint32_t) 3 ) << 6)
+/** Response bit mask */
+#define SDC_COMMAND_RSP_BITMASK     (((uint32_t) 3 ) << 6)
+/** Mark that command timer is disabled and CPSM waits for interrupt request */
+#define SDC_COMMAND_INTERRUPT       (((uint32_t) 1 ) << 8)
+/** Mark that CPSM waits for CmdPend before starting sending a command*/
+#define SDC_COMMAND_PENDING     (((uint32_t) 1 ) << 9)
+/** Enable CPSM */
+#define SDC_COMMAND_ENABLE          (((uint32_t) 1 ) << 10)
+
+/**
+ * @brief SDC Command Response Register bit definitions
+ */
+/** SDC Command Response value */
+#define SDC_RESPCOMMAND_VAL(n)      ((uint32_t) n & 0x3F)
+
+/**
+ * @brief SDC Data Length Register bit definitions
+ */
+/** SDC Data Length set */
+#define SDC_DATALENGTH_LEN(n)       ((uint32_t) n & 0xFFFF)
+
+/**
+ * @brief SDC Data Control Register bit definitions
+ */
+/** SDC Data Control Register Bitmask */
+#define SDC_DATACTRL_BITMASK        ((uint32_t) 0xFF)
+/** Enable Data Transfer */
+#define SDC_DATACTRL_ENABLE             (((uint32_t) 1 ) << 0)
+/** Mark that Data is transfer from card to controller */
+#define SDC_DATACTRL_DIR_FROMCARD       (((uint32_t) 1 ) << 1)
+/** Mark that Data is transfer from controller to card */
+#define SDC_DATACTRL_DIR_TOCARD         ((uint32_t) 0)
+/** Mark that the transfer mode is Stream Data Transfer */
+#define SDC_DATACTRL_XFER_MODE_STREAM   (((uint32_t) 1 ) << 2)
+/** Mark that the transfer mode is Block Data Transfer */
+#define SDC_DATACTRL_XFER_MODE_BLOCK    ((uint32_t) 0)
+/** Enable DMA */
+#define SDC_DATACTRL_DMA_ENABLE         (((uint32_t) 1 ) << 3)
+/** Set Data Block size */
+#define SDC_DATACTRL_BLOCKSIZE(n)       (((uint32_t) (n & 0x0F) ) << 4)
+/** Get Data Block size value */
+#define SDC_DATACTRL_BLOCKSIZE_VAL(n)   (((uint32_t) 1) << n)
+
+/**
+ * @brief SDC Data Counter Register bit definitions
+ */
+#define SDC_DATACNT_VAL(n)          ((uint32_t) n & 0xFFFF)
+
+/**
+ * @brief SDC Status Register bit definitions
+ */
+/** Command Response received (CRC check failed) */
+#define SDC_STATUS_CMDCRCFAIL     (((uint32_t) 1 ) << 0)
+/** Data block sent/received (CRC check failed). */
+#define SDC_STATUS_DATACRCFAIL     (((uint32_t) 1 ) << 1)
+/** Command response timeout.. */
+#define SDC_STATUS_CMDTIMEOUT     (((uint32_t) 1 ) << 2)
+/** Data timeout. */
+#define SDC_STATUS_DATATIMEOUT     (((uint32_t) 1 ) << 3)
+/** Transmit FIFO underrun error. */
+#define SDC_STATUS_TXUNDERRUN     (((uint32_t) 1 ) << 4)
+/** Receive FIFO overrun error. */
+#define SDC_STATUS_RXOVERRUN     (((uint32_t) 1 ) << 5)
+/** Command response received (CRC check passed). */
+#define SDC_STATUS_CMDRESPEND     (((uint32_t) 1 ) << 6)
+/** Command sent (no response required).*/
+#define SDC_STATUS_CMDSENT     (((uint32_t) 1 ) << 7)
+/** Data end (data counter is zero).*/
+#define SDC_STATUS_DATAEND     (((uint32_t) 1 ) << 8)
+/** Start bit not detected on all data signals in wide bus mode..*/
+#define SDC_STATUS_STARTBITERR     (((uint32_t) 1 ) << 9)
+/** Data block sent/received (CRC check passed).*/
+#define SDC_STATUS_DATABLOCKEND     (((uint32_t) 1 ) << 10)
+/** Command transfer in progress.*/
+#define SDC_STATUS_CMDACTIVE     (((uint32_t) 1 ) << 11)
+/** Data transmit in progress.*/
+#define SDC_STATUS_TXACTIVE     (((uint32_t) 1 ) << 12)
+/** Data receive in progress.*/
+#define SDC_STATUS_RXACTIVE     (((uint32_t) 1 ) << 13)
+/** Transmit FIFO half empty.*/
+#define SDC_STATUS_TXFIFOHALFEMPTY     (((uint32_t) 1 ) << 14)
+/** Receive FIFO half full.*/
+#define SDC_STATUS_RXFIFOHALFFULL     (((uint32_t) 1 ) << 15)
+/** Transmit FIFO full.*/
+#define SDC_STATUS_TXFIFOFULL     (((uint32_t) 1 ) << 16)
+/** Receive FIFO full.*/
+#define SDC_STATUS_RXFIFOFULL     (((uint32_t) 1 ) << 17)
+/** Transmit FIFO empty.*/
+#define SDC_STATUS_TXFIFOEMPTY     (((uint32_t) 1 ) << 18)
+/** Receive FIFO empty.*/
+#define SDC_STATUS_RXFIFOEMPTY     (((uint32_t) 1 ) << 19)
+/** Data available in transmit FIFO.*/
+#define SDC_STATUS_TXDATAAVLBL     (((uint32_t) 1 ) << 20)
+/** Data available in receive FIFO.*/
+#define SDC_STATUS_RXDATAAVLBL     (((uint32_t) 1 ) << 21)
+/** Command Error Status */
+#define SDC_STATUS_CMDERR    (SDC_STATUS_CMDCRCFAIL | SDC_STATUS_CMDTIMEOUT | SDC_STATUS_STARTBITERR)
+/** Data Error Status */
+#define SDC_STATUS_DATAERR    (SDC_STATUS_DATACRCFAIL | SDC_STATUS_DATATIMEOUT | SDC_STATUS_TXUNDERRUN \
+							   | SDC_STATUS_RXOVERRUN | SDC_STATUS_STARTBITERR)
+/** FIFO Status*/
+#define SDC_STATUS_FIFO    (SDC_STATUS_TXFIFOHALFEMPTY | SDC_STATUS_RXFIFOHALFFULL \
+							| SDC_STATUS_TXFIFOFULL  | SDC_STATUS_RXFIFOFULL \
+							| SDC_STATUS_TXFIFOEMPTY | SDC_STATUS_RXFIFOEMPTY \
+							| SDC_STATUS_DATABLOCKEND)
+
+/** Data Transfer Status*/
+#define SDC_STATUS_DATA    (SDC_STATUS_DATAEND )
+
+/**
+ * @brief SDC Clear Register bit definitions
+ */
+/** Clear all status flag*/
+#define SDC_CLEAR_ALL       ((uint32_t) 0x7FF)
+/** Clears CmdCrcFail flag.*/
+#define SDC_CLEAR_CMDCRCFAIL     (((uint32_t) 1 ) << 0)
+/** Clears DataCrcFail flag. */
+#define SDC_CLEAR_DATACRCFAIL     (((uint32_t) 1 ) << 1)
+/** Clears CmdTimeOut flag. */
+#define SDC_CLEAR_CMDTIMEOUT     (((uint32_t) 1 ) << 2)
+/** Clears DataTimeOut flag. */
+#define SDC_CLEAR_DATATIMEOUT     (((uint32_t) 1 ) << 3)
+/** Clears TxUnderrun flag. */
+#define SDC_CLEAR_TXUNDERRUN     (((uint32_t) 1 ) << 4)
+/**Clears RxOverrun flag. */
+#define SDC_CLEAR_RXOVERRUN     (((uint32_t) 1 ) << 5)
+/** Clears CmdRespEnd flag. */
+#define SDC_CLEAR_CMDRESPEND     (((uint32_t) 1 ) << 6)
+/** Clears CmdSent flag.*/
+#define SDC_CLEAR_CMDSENT     (((uint32_t) 1 ) << 7)
+/**Clears DataEnd flag.*/
+#define SDC_CLEAR_DATAEND     (((uint32_t) 1 ) << 8)
+/** Clears StartBitErr flag.*/
+#define SDC_CLEAR_STARTBITERR     (((uint32_t) 1 ) << 9)
+/** Clears DataBlockEnd flag.*/
+#define SDC_CLEAR_DATABLOCKEND     (((uint32_t) 1 ) << 10)
+
+/**
+ * @brief SDC Interrupt Mask Register bit definitions
+ */
+/** Mask CmdCrcFail flag.*/
+#define SDC_MASK0_CMDCRCFAIL     (((uint32_t) 1 ) << 0)
+/** Mask DataCrcFail flag. */
+#define SDC_MASK0_DATACRCFAIL     (((uint32_t) 1 ) << 1)
+/** Mask CmdTimeOut flag. */
+#define SDC_MASK0_CMDTIMEOUT     (((uint32_t) 1 ) << 2)
+/** Mask DataTimeOut flag. */
+#define SDC_MASK0_DATATIMEOUT     (((uint32_t) 1 ) << 3)
+/** Mask TxUnderrun flag. */
+#define SDC_MASK0_TXUNDERRUN     (((uint32_t) 1 ) << 4)
+/** Mask RxOverrun flag. */
+#define SDC_MASK0_RXOVERRUN     (((uint32_t) 1 ) << 5)
+/** Mask CmdRespEnd flag. */
+#define SDC_MASK0_CMDRESPEND     (((uint32_t) 1 ) << 6)
+/** Mask CmdSent flag.*/
+#define SDC_MASK0_CMDSENT     (((uint32_t) 1 ) << 7)
+/** Mask DataEnd flag.*/
+#define SDC_MASK0_DATAEND     (((uint32_t) 1 ) << 8)
+/** Mask StartBitErr flag.*/
+#define SDC_MASK0_STARTBITERR     (((uint32_t) 1 ) << 9)
+/** Mask DataBlockEnd flag.*/
+#define SDC_MASK0_DATABLOCKEND     (((uint32_t) 1 ) << 10)
+/** Mask CmdActive flag.*/
+#define SDC_MASK0_CMDACTIVE     (((uint32_t) 1 ) << 11)
+/** Mask TxActive flag.*/
+#define SDC_MASK0_TXACTIVE     (((uint32_t) 1 ) << 12)
+/** Mask RxActive flag.*/
+#define SDC_MASK0_RXACTIVE     (((uint32_t) 1 ) << 13)
+/** Mask TxFifoHalfEmpty flag.*/
+#define SDC_MASK0_TXFIFOHALFEMPTY     (((uint32_t) 1 ) << 14)
+/** Mask RxFifoHalfFull flag.*/
+#define SDC_MASK0_RXFIFOHALFFULL     (((uint32_t) 1 ) << 15)
+/** Mask TxFifoFull flag.*/
+#define SDC_MASK0_TXFIFOFULL     (((uint32_t) 1 ) << 16)
+/** Mask RxFifoFull flag.*/
+#define SDC_MASK0_RXFIFOFULL     (((uint32_t) 1 ) << 17)
+/** Mask TxFifoEmpty flag.*/
+#define SDC_MASK0_TXFIFOEMPTY     (((uint32_t) 1 ) << 18)
+/** Mask RxFifoEmpty flag.*/
+#define SDC_MASK0_RXFIFOEMPTY     (((uint32_t) 1 ) << 19)
+/** Mask TxDataAvlbl flag.*/
+#define SDC_MASK0_TXDATAAVLBL     (((uint32_t) 1 ) << 20)
+/** Mask RxDataAvlbl flag.*/
+#define SDC_MASK0_RXDATAAVLBL     (((uint32_t) 1 ) << 21)
+/** CMD error interrupt mask */
+#define SDC_MASK0_CMDERR    (SDC_MASK0_CMDCRCFAIL | SDC_MASK0_CMDTIMEOUT | SDC_MASK0_STARTBITERR)
+/** Data Transmit Error interrupt mask */
+#define SDC_MASK0_TXDATAERR    (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_TXUNDERRUN | \
+								SDC_MASK0_STARTBITERR)
+
+/** Data Receive Error interrupt mask */
+#define SDC_MASK0_RXDATAERR    (SDC_MASK0_DATACRCFAIL | SDC_MASK0_DATATIMEOUT | SDC_MASK0_RXOVERRUN | \
+								SDC_MASK0_STARTBITERR)
+/** TX FIFO interrupt mask*/
+#define SDC_MASK0_TXFIFO    (SDC_MASK0_TXFIFOHALFEMPTY | SDC_MASK0_DATABLOCKEND )
+/** RX FIFO interrupt mask*/
+#define SDC_MASK0_RXFIFO    (SDC_MASK0_RXFIFOHALFFULL  | SDC_MASK0_DATABLOCKEND )
+
+/** Data Transfer interrupt mask*/
+#define SDC_MASK0_DATA    (SDC_MASK0_DATAEND | SDC_MASK0_DATABLOCKEND )
+
+/**
+ * @brief SDC FIFO Counter Register bit definitions
+ */
+#define SDC_FIFOCNT_VAL(n)          ((uint32_t) n & 0x7FFF)
+
+/* The number of bytes used to store card status*/
+#define SDC_CARDSTATUS_BYTENUM              ((uint32_t) 4)
+
+/**
+ * @brief SDC Card bus clock rate definitions
+ */
+/* Card bus clock in Card Identification Mode */
+#define SDC_IDENT_CLOCK_RATE         (400000)	/* 400KHz */
+/* Card bus clock in Data Transfer Mode */
+#define SDC_TRAN_CLOCK_RATE        (20000000)	/* 20MHz */
+
+/**
+ * @brief SDC Power Control Options
+ */
+typedef enum SDC_PWR_CTRL {
+	SDC_POWER_OFF = 0,		/*!< Power-off */
+	SDC_POWER_UP = 2,		/*!< Power-up */
+	SDC_POWER_ON = 3,		/*!< Power-on */
+} SDC_PWR_CTRL_T;
+
+/**
+ * @brief SDC Clock Control Options
+ */
+typedef enum SDC_CLOCK_CTRL {
+	SDC_CLOCK_ENABLE = 8,			/*!< Enable SD Card Bus Clock */
+	SDC_CLOCK_POWER_SAVE = 9,		/*!< Disable SD_CLK output when bus is idle */
+	SDC_CLOCK_DIVIDER_BYPASS = 10,	/*!< Enable bypass of clock divide logic */
+	SDC_CLOCK_WIDEBUS_MODE = 11,	/*!< Enable wide bus mode (SD_DAT[3:0] is used instead of SD_DAT[0]) */
+} SDC_CLOCK_CTRL_T;
+
+/**
+ * @brief SDC Response type
+ */
+typedef enum SDC_RESPONSE {
+	SDC_NO_RESPONSE = SDC_COMMAND_NO_RSP,		/*!< No response */
+	SDC_SHORT_RESPONSE = SDC_COMMAND_SHORT_RSP,	/*!< Short response */
+	SDC_LONG_RESPONSE = SDC_COMMAND_LONG_RSP,	/*!< Long response */
+} SDC_RESPONSE_T;
+
+/**
+ * @brief SDC Data Transfer Direction definitions
+ */
+typedef enum SDC_TRANSFER_DIR {
+	SDC_TRANSFER_DIR_FROMCARD = SDC_DATACTRL_DIR_FROMCARD,	/*!< Transfer from card */
+	SDC_TRANSFER_DIR_TOCARD = SDC_DATACTRL_DIR_TOCARD,		/*!< Transfer to card */
+} SDC_TRANSFER_DIR_T;
+
+/**
+ * @brief SDC Data Transfer Mode definitions
+ */
+typedef enum SDC_TRANSFER_MODE {
+	SDC_TRANSFER_MODE_STREAM = SDC_DATACTRL_XFER_MODE_STREAM,	/*!< Stream transfer mode */
+	SDC_TRANSFER_MODE_BLOCK = SDC_DATACTRL_XFER_MODE_BLOCK,		/*!< Block transfer mode */
+} SDC_TRANSFER_MODE_T;
+
+/**
+ * @brief SDC Data Block size definitions (in bytes)
+ */
+typedef enum SDC_BLOCK_SIZE {
+	SDC_BLOCK_SIZE_1 = 0,		/*!< Block size - 1 byte */
+	SDC_BLOCK_SIZE_2,			/*!< Block size - 2 bytes */
+	SDC_BLOCK_SIZE_4,			/*!< Block size - 4 bytes */
+	SDC_BLOCK_SIZE_8,			/*!< Block size - 8 bytes */
+	SDC_BLOCK_SIZE_16,			/*!< Block size - 16 bytes */
+	SDC_BLOCK_SIZE_32,			/*!< Block size - 32 bytes */
+	SDC_BLOCK_SIZE_64,			/*!< Block size - 64 bytes */
+	SDC_BLOCK_SIZE_128,			/*!< Block size - 128 bytes */
+	SDC_BLOCK_SIZE_256,			/*!< Block size - 256 bytes */
+	SDC_BLOCK_SIZE_512,			/*!< Block size - 512 bytes */
+	SDC_BLOCK_SIZE_1024,		/*!< Block size - 1024 bytes */
+	SDC_BLOCK_SIZE_2048,		/*!< Block size - 2048 bytes */
+} SDC_BLOCK_SIZE_T;
+
+/**
+ * @brief SDC Return code definitions
+ */
+typedef enum CHIP_SDC_RET_CODE {
+	SDC_RET_OK = 0,
+	SDC_RET_CMD_FAILED = -1,
+	SDC_RET_BAD_PARAMETERS = -2,
+	SDC_RET_BUS_NOT_IDLE = -3,
+	SDC_RET_TIMEOUT = -4,
+	SDC_RET_ERR_STATE = -5,
+	SDC_RET_NOT_READY = -6,
+	SDC_RET_FAILED = -7,
+} CHIP_SDC_RET_CODE_T;
+
+/**
+ * @brief SDC Command Response structure
+ */
+typedef struct {
+	uint8_t CmdIndex;						/*!< Command Index of the command response received */
+	uint32_t Data[SDC_CARDSTATUS_BYTENUM];	/* Card Status which can be stored in 1 or 4 bytes */
+} SDC_RESP_T;
+
+/**
+ * @brief SDC Data Transfer Setup structure
+ */
+typedef struct {
+	uint16_t BlockNum;						/*!< The number of block which will be transfered */
+	SDC_BLOCK_SIZE_T BlockSize;		/*!< Data Block Length */
+	SDC_TRANSFER_DIR_T Dir;			/*!< Direction */
+	SDC_TRANSFER_MODE_T  Mode;		/*!< Mode */
+	bool     DMAUsed;						/*!< true: DMA used */
+	uint32_t Timeout;						/*!< Data Transfer timeout periods (in Card Bus Clock)*/
+} SDC_DATA_TRANSFER_T;
+
+/**
+ * @brief	Set the power state of SDC peripheral
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	pwrMode	: Power mode
+ * @param	flag	: Output control flag
+ * @return	Nothing
+ * @note	When the external power supply is switched on, the software first enters the power-up
+ *  state, and waits until the supply output is stable before moving to the power-on state.
+ *  During the power-up state, SD_PWR is set HIGH. The card bus outlets are disabled
+ *  during both states.
+ *  flag is or-ed bit value of SDC_PWR_OPENDRAIN and SDC_PWR_ROD
+ */
+void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag);
+
+/**
+ * @brief	Set clock divider value for SDC peripheral
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	div		: clock divider
+ * @return	Nothing
+ * @note	While the SD card interface is in identification mode, the SD_CLK frequency must be less
+ *  than 400 kHz. The clock frequency can be changed to the maximum card bus frequency
+ *  when relative card addresses are assigned to all cards.
+ *	SD_CLK frequency = MCLK / [2x(ClkDiv+1)].
+ */
+void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div);
+
+/**
+ * @brief	Set or Reset clock control of SDC peripheral
+ * @param	pSDC		: Pointer to SDC register block
+ * @param	ctrlType	: Clock Control type
+ * @param	NewState	: New State to set
+ * @return	Nothing
+ */
+void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
+						   FunctionalState NewState);
+
+/**
+ * @brief	Set the clock frequency for SDC peripheral
+ * @param	pSDC	: Pointer to SDC peripheral base address
+ * @param	freq	: Expected clock frequency
+ * @return	None
+ */
+void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq);
+
+/**
+ * @brief	Set SDC Command Information
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	Cmd	    : Command value
+ * @param   Arg     : Argument for the command
+ * @return	Nothing
+ */
+void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg);
+
+/**
+ * @brief	Reset SDC Command Information
+ * @param	pSDC	: Pointer to SDC register block
+ * @return	Nothing
+ */
+void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC);
+
+/**
+ * @brief	Get SDC Response
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	pResp	: Pointer to buffer storing response data
+ * @return	Nothing
+ */
+void Chip_SDC_GetResp(LPC_SDC_T *pSDC, SDC_RESP_T *pResp);
+
+/**
+ * @brief	Set SDC Data Timeout Period
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	timeout	: Data timeout value in card bus clock periods
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SDC_SetDataTimer(LPC_SDC_T *pSDC, uint32_t timeout)
+{
+	pSDC->DATATIMER = timeout;
+}
+
+/**
+ * @brief	Set SDC Data Transfer Information
+ * @param	pSDC		: Pointer to SDC register block
+ * @param	pTransfer	: Pointer to Data Transfer structure
+ * @return	Nothing
+ */
+void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer);
+
+/**
+ * @brief	Write Data to FIFO
+ * @param	pSDC		: Pointer to SDC register block
+ * @param	pSrc		: Pointer to data buffer
+ * @param	bFirstHalf	: true (write to the first half of FIFO) false (write to the second half of FIFO)
+ * @return	Nothing
+ */
+void Chip_SDC_WriteFIFO(LPC_SDC_T *pSDC, uint32_t *pSrc, bool bFirstHalf);
+
+/**
+ * @brief	Write Data to FIFO
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	pDst	: The buffer hold the data read
+ * @param	bFirstHalf : true (read the first half of FIFO) false (read the second half of FIFO)
+ * @return	Nothing
+ */
+void Chip_SDC_ReadFIFO(LPC_SDC_T *pSDC, uint32_t *pDst, bool bFirstHalf);
+
+/**
+ * @brief	Get status of SDC Peripheral
+ * @param	pSDC	: Pointer to SDC register block
+ * @return	Status (Or-ed bit value of SDC_STATUS_*)
+ */
+STATIC INLINE uint32_t Chip_SDC_GetStatus(LPC_SDC_T *pSDC)
+{
+	return pSDC->STATUS;
+}
+
+/**
+ * @brief	Clear status of SDC Peripheral
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	flag	: Status flag(s) to be cleared (Or-ed bit value of SDC_CLEAR_*)
+ * @return	None
+ */
+STATIC INLINE void Chip_SDC_ClearStatus(LPC_SDC_T *pSDC, uint32_t flag)
+{
+	pSDC->CLEAR = flag;
+}
+
+/**
+ * @brief	Set interrupt mask for SDC Peripheral
+ * @param	pSDC	: Pointer to SDC register block
+ * @param	mask	: Interrupt mask (Or-ed bit value of SDC_MASK0_*)
+ * @return	None
+ */
+STATIC INLINE void Chip_SDC_SetIntMask(LPC_SDC_T *pSDC, uint32_t mask)
+{
+	pSDC->MASK0 = mask;
+}
+
+/**
+ * @brief	Initialize the SDC card controller
+ * @param	pSDC	: Pointer to SDC register block
+ * @return	None
+ */
+void Chip_SDC_Init(LPC_SDC_T *pSDC);
+
+/**
+ * @brief	Deinitialise SDC peripheral
+ * @param	pSDC	: Pointer to SDC peripheral base address
+ * @return	None
+ */
+void Chip_SDC_DeInit(LPC_SDC_T *pSDC);
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SDC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc.h b/hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc.h
new file mode 100644
index 000000000..878246787
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc.h
@@ -0,0 +1,450 @@
+/*
+ * @brief    Common definitions used in SD/MMC cards
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SDMMC_H
+#define __SDMMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CHIP_SDMMC_Definitions CHIP: Common SD/MMC definitions
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief OCR Register definitions
+ */
+/** Support voltage range 2.0-2.1 (this bit is reserved in SDC)*/
+#define SDC_OCR_20_21               (((uint32_t) 1) << 8)
+/** Support voltage range 2.1-2.2 (this bit is reserved in SDC)*/
+#define SDC_OCR_21_22               (((uint32_t) 1) << 9)
+/** Support voltage range 2.2-2.3 (this bit is reserved in SDC)*/
+#define SDC_OCR_22_23               (((uint32_t) 1) << 10)
+/** Support voltage range 2.3-2.4 (this bit is reserved in SDC)*/
+#define SDC_OCR_23_24               (((uint32_t) 1) << 11)
+/** Support voltage range 2.4-2.5 (this bit is reserved in SDC)*/
+#define SDC_OCR_24_25               (((uint32_t) 1) << 12)
+/** Support voltage range 2.5-2.6 (this bit is reserved in SDC)*/
+#define SDC_OCR_25_26               (((uint32_t) 1) << 13)
+/** Support voltage range 2.6-2.7 (this bit is reserved in SDC)*/
+#define SDC_OCR_26_27               (((uint32_t) 1) << 14)
+/** Support voltage range 2.7-2.8 */
+#define SDC_OCR_27_28               (((uint32_t) 1) << 15)
+/** Support voltage range 2.8-2.9*/
+#define SDC_OCR_28_29               (((uint32_t) 1) << 16)
+/** Support voltage range 2.9-3.0 */
+#define SDC_OCR_29_30               (((uint32_t) 1) << 17)
+/** Support voltage range 3.0-3.1 */
+#define SDC_OCR_30_31               (((uint32_t) 1) << 18)
+/** Support voltage range 3.1-3.2 */
+#define SDC_OCR_31_32               (((uint32_t) 1) << 19)
+/** Support voltage range 3.2-3.3 */
+#define SDC_OCR_32_33               (((uint32_t) 1) << 20)
+/** Support voltage range 3.3-3.4 */
+#define SDC_OCR_33_34               (((uint32_t) 1) << 21)
+/** Support voltage range 3.4-3.5 */
+#define SDC_OCR_34_35               (((uint32_t) 1) << 22)
+/** Support voltage range 3.5-3.6 */
+#define SDC_OCR_35_36               (((uint32_t) 1) << 23)
+/** Support voltage range 2.7-3.6 */
+#define SDC_OCR_27_36               ((uint32_t) 0x00FF8000)
+/** Card Capacity Status (CCS). (this bit is reserved in MMC) */
+#define SDC_OCR_HC_CCS              (((uint32_t) 1) << 30)
+/** Card power up status bit */
+#define SDC_OCR_IDLE                (((uint32_t) 1) << 31)
+#define SDC_OCR_BUSY                (((uint32_t) 0) << 31)
+
+/* SD/MMC commands - this matrix shows the command, response types, and
+   supported card type for that command.
+   Command                 Number Resp  SD  MMC
+   ----------------------- ------ ----- --- ---
+   Reset (go idle)         CMD0   NA    x   x
+   Send op condition       CMD1   R3        x
+   All send CID            CMD2   R2    x   x
+   Send relative address   CMD3   R1        x
+   Send relative address   CMD3   R6    x
+   Program DSR             CMD4   NA        x
+   Select/deselect card    CMD7   R1b       x
+   Select/deselect card    CMD7   R1    x
+   Send CSD                CMD9   R2    x   x
+   Send CID                CMD10  R2    x   x
+   Read data until stop    CMD11  R1    x   x
+   Stop transmission       CMD12  R1/b  x   x
+   Send status             CMD13  R1    x   x
+   Go inactive state       CMD15  NA    x   x
+   Set block length        CMD16  R1    x   x
+   Read single block       CMD17  R1    x   x
+   Read multiple blocks    CMD18  R1    x   x
+   Write data until stop   CMD20  R1        x
+   Setblock count          CMD23  R1        x
+   Write single block      CMD24  R1    x   x
+   Write multiple blocks   CMD25  R1    x   x
+   Program CID             CMD26  R1        x
+   Program CSD             CMD27  R1    x   x
+   Set write protection    CMD28  R1b   x   x
+   Clear write protection  CMD29  R1b   x   x
+   Send write protection   CMD30  R1    x   x
+   Erase block start       CMD32  R1    x
+   Erase block end         CMD33  R1    x
+   Erase block start       CMD35  R1        x
+   Erase block end         CMD36  R1        x
+   Erase blocks            CMD38  R1b       x
+   Fast IO                 CMD39  R4        x
+   Go IRQ state            CMD40  R5        x
+   Lock/unlock             CMD42  R1b       x
+   Application command     CMD55  R1        x
+   General command         CMD56  R1b       x
+
+ *** SD card application commands - these must be preceded with ***
+ *** MMC CMD55 application specific command first               ***
+   Set bus width           ACMD6  R1    x
+   Send SD status          ACMD13 R1    x
+   Send number WR blocks   ACMD22 R1    x
+   Set WR block erase cnt  ACMD23 R1    x
+   Send op condition       ACMD41 R3    x
+   Set clear card detect   ACMD42 R1    x
+   Send CSR                ACMD51 R1    x */
+
+/**
+ * @brief  SD/MMC application specific commands for SD cards only - these
+ * must be preceded by the SDMMC CMD55 to work correctly
+ */
+typedef enum {
+	SD_SET_BUS_WIDTH,		/*!< Set the SD bus width */
+	SD_SEND_STATUS,			/*!< Send the SD card status */
+	SD_SEND_WR_BLOCKS,		/*!< Send the number of written clocks */
+	SD_SET_ERASE_COUNT,		/*!< Set the number of blocks to pre-erase */
+	SD_SENDOP_COND,			/*!< Send the OCR register (init) */
+	SD_CLEAR_CARD_DET,		/*!< Set or clear the 50K detect pullup */
+	SD_SEND_SCR,			/*!< Send the SD configuration register */
+	SD_INVALID_APP_CMD		/*!< Invalid SD application command */
+} SD_APP_CMD_T;
+
+/**
+ * @brief  Possible SDMMC response types
+ */
+typedef enum {
+	SDMMC_RESPONSE_R1,		/*!< Typical status */
+	SDMMC_RESPONSE_R1B,		/*!< Typical status with busy */
+	SDMMC_RESPONSE_R2,		/*!< CID/CSD registers (CMD2 and CMD10) */
+	SDMMC_RESPONSE_R3,		/*!< OCR register (CMD1, ACMD41) */
+	SDMMC_RESPONSE_R4,		/*!< Fast IO response word */
+	SDMMC_RESPONSE_R5,		/*!< Go IRQ state response word */
+	SDMMC_RESPONSE_R6,		/*!< Published RCA response */
+	SDMMC_RESPONSE_NONE		/*!< No response expected */
+} SDMMC_RESPONSE_T;
+
+/**
+ * @brief  Possible SDMMC card state types
+ */
+typedef enum {
+	SDMMC_IDLE_ST = 0,	/*!< Idle state */
+	SDMMC_READY_ST,		/*!< Ready state */
+	SDMMC_IDENT_ST,		/*!< Identification State */
+	SDMMC_STBY_ST,		/*!< standby state */
+	SDMMC_TRAN_ST,		/*!< transfer state */
+	SDMMC_DATA_ST,		/*!< Sending-data State */
+	SDMMC_RCV_ST,		/*!< Receive-data State */
+	SDMMC_PRG_ST,		/*!< Programming State */
+	SDMMC_DIS_ST		/*!< Disconnect State */
+} SDMMC_STATE_T;
+
+/* Function prototype for event setup function */
+typedef void (*SDMMC_EVSETUP_FUNC_T)(void *);
+
+/* Function prototype for wait for event function */
+typedef uint32_t (*SDMMC_EVWAIT_FUNC_T)(void);
+
+/* Function prototype for milliSecond delay function */
+typedef void (*SDMMC_MSDELAY_FUNC_T)(uint32_t);
+
+/**
+ * @brief SD/MMC Card specific setup data structure
+ */
+typedef struct {
+	uint32_t response[4];						/*!< Most recent response */
+	uint32_t cid[4];							/*!< CID of acquired card  */
+	uint32_t csd[4];							/*!< CSD of acquired card */
+	uint32_t ext_csd[512 / 4];					/*!< Ext CSD */
+	uint32_t card_type;							/*!< Card Type */
+	uint16_t rca;								/*!< Relative address assigned to card */
+	uint32_t speed;								/*!< Speed */
+	uint32_t block_len;							/*!< Card sector size */
+	uint32_t device_size;						/*!< Device Size */
+	uint32_t blocknr;							/*!< Block Number */
+	uint32_t clk_rate;							/*! Clock rate */
+	SDMMC_EVSETUP_FUNC_T evsetup_cb;			/*!< Function to setup event information */
+	SDMMC_EVWAIT_FUNC_T waitfunc_cb;			/*!< Function to wait for event */
+	SDMMC_MSDELAY_FUNC_T msdelay_func;			/*!< Function to sleep in ms */
+} SDMMC_CARD_T;
+
+/**
+ * @brief SD/MMC commands, arguments and responses
+ * Standard SD/MMC commands (3.1)       type  argument     response
+ */
+/* class 1 */
+#define MMC_GO_IDLE_STATE         0		/* bc                          */
+#define MMC_SEND_OP_COND          1		/* bcr  [31:0]  OCR        R3  */
+#define MMC_ALL_SEND_CID          2		/* bcr                     R2  */
+#define MMC_SET_RELATIVE_ADDR     3		/* ac   [31:16] RCA        R1  */
+#define MMC_SET_DSR               4		/* bc   [31:16] RCA            */
+#define MMC_SELECT_CARD           7		/* ac   [31:16] RCA        R1  */
+#define MMC_SEND_EXT_CSD          8		/* bc                      R1  */
+#define MMC_SEND_CSD              9		/* ac   [31:16] RCA        R2  */
+#define MMC_SEND_CID             10		/* ac   [31:16] RCA        R2  */
+#define MMC_STOP_TRANSMISSION    12		/* ac                      R1b */
+#define MMC_SEND_STATUS          13		/* ac   [31:16] RCA        R1  */
+#define MMC_GO_INACTIVE_STATE    15		/* ac   [31:16] RCA            */
+
+/* class 2 */
+#define MMC_SET_BLOCKLEN         16		/* ac   [31:0]  block len  R1  */
+#define MMC_READ_SINGLE_BLOCK    17		/* adtc [31:0]  data addr  R1  */
+#define MMC_READ_MULTIPLE_BLOCK  18		/* adtc [31:0]  data addr  R1  */
+
+/* class 3 */
+#define MMC_WRITE_DAT_UNTIL_STOP 20		/* adtc [31:0]  data addr  R1  */
+
+/* class 4 */
+#define MMC_SET_BLOCK_COUNT      23		/* adtc [31:0]  data addr  R1  */
+#define MMC_WRITE_BLOCK          24		/* adtc [31:0]  data addr  R1  */
+#define MMC_WRITE_MULTIPLE_BLOCK 25		/* adtc                    R1  */
+#define MMC_PROGRAM_CID          26		/* adtc                    R1  */
+#define MMC_PROGRAM_CSD          27		/* adtc                    R1  */
+
+/* class 6 */
+#define MMC_SET_WRITE_PROT       28		/* ac   [31:0]  data addr  R1b */
+#define MMC_CLR_WRITE_PROT       29		/* ac   [31:0]  data addr  R1b */
+#define MMC_SEND_WRITE_PROT      30		/* adtc [31:0]  wpdata addr R1  */
+
+/* class 5 */
+#define MMC_ERASE_GROUP_START    35		/* ac   [31:0]  data addr  R1  */
+#define MMC_ERASE_GROUP_END      36		/* ac   [31:0]  data addr  R1  */
+#define MMC_ERASE                37		/* ac                      R1b */
+#define SD_ERASE_WR_BLK_START    32		/* ac   [31:0]  data addr  R1  */
+#define SD_ERASE_WR_BLK_END      33		/* ac   [31:0]  data addr  R1  */
+#define SD_ERASE                 38		/* ac                      R1b */
+
+/* class 9 */
+#define MMC_FAST_IO              39		/* ac   <Complex>          R4  */
+#define MMC_GO_IRQ_STATE         40		/* bcr                     R5  */
+
+/* class 7 */
+#define MMC_LOCK_UNLOCK          42		/* adtc                    R1b */
+
+/* class 8 */
+#define MMC_APP_CMD              55		/* ac   [31:16] RCA        R1  */
+#define MMC_GEN_CMD              56		/* adtc [0]     RD/WR      R1b */
+
+/* SD commands                           type  argument     response */
+/* class 8 */
+/* This is basically the same command as for MMC with some quirks. */
+#define SD_SEND_RELATIVE_ADDR     3		/* ac                      R6  */
+#define SD_CMD8                   8		/* bcr  [31:0]  OCR        R3  */
+
+/* Application commands */
+#define SD_APP_SET_BUS_WIDTH      6		/* ac   [1:0]   bus width  R1   */
+#define SD_APP_OP_COND           41		/* bcr  [31:0]  OCR        R1 (R4)  */
+#define SD_APP_SEND_SCR          51		/* adtc                    R1   */
+
+/**
+ * @brief MMC status in R1<br>
+ * Type<br>
+ *   e : error bit<br>
+ *   s : status bit<br>
+ *   r : detected and set for the actual command response<br>
+ *   x : detected and set during command execution. the host must poll
+ *       the card by sending status command in order to read these bits.
+ * Clear condition<br>
+ *   a : according to the card state<br>
+ *   b : always related to the previous command. Reception of
+ *       a valid command will clear it (with a delay of one command)<br>
+ *   c : clear by read<br>
+ */
+
+#define R1_OUT_OF_RANGE         (1UL << 31)	/* er, c */
+#define R1_ADDRESS_ERROR        (1 << 30)	/* erx, c */
+#define R1_BLOCK_LEN_ERROR      (1 << 29)	/* er, c */
+#define R1_ERASE_SEQ_ERROR      (1 << 28)	/* er, c */
+#define R1_ERASE_PARAM          (1 << 27)	/* ex, c */
+#define R1_WP_VIOLATION         (1 << 26)	/* erx, c */
+#define R1_CARD_IS_LOCKED       (1 << 25)	/* sx, a */
+#define R1_LOCK_UNLOCK_FAILED   (1 << 24)	/* erx, c */
+#define R1_COM_CRC_ERROR        (1 << 23)	/* er, b */
+#define R1_ILLEGAL_COMMAND      (1 << 22)	/* er, b */
+#define R1_CARD_ECC_FAILED      (1 << 21)	/* ex, c */
+#define R1_CC_ERROR             (1 << 20)	/* erx, c */
+#define R1_ERROR                (1 << 19)	/* erx, c */
+#define R1_UNDERRUN             (1 << 18)	/* ex, c */
+#define R1_OVERRUN              (1 << 17)	/* ex, c */
+#define R1_CID_CSD_OVERWRITE    (1 << 16)	/* erx, c, CID/CSD overwrite */
+#define R1_WP_ERASE_SKIP        (1 << 15)	/* sx, c */
+#define R1_CARD_ECC_DISABLED    (1 << 14)	/* sx, a */
+#define R1_ERASE_RESET          (1 << 13)	/* sr, c */
+#define R1_STATUS(x)            (x & 0xFFFFE000)
+#define R1_CURRENT_STATE(x)     ((x & 0x00001E00) >> 9)	/* sx, b (4 bits) */
+#define R1_READY_FOR_DATA       (1 << 8)	/* sx, a */
+#define R1_APP_CMD              (1 << 5)	/* sr, c */
+
+/**
+ * @brief SD/MMC card OCR register bits
+ */
+#define OCR_ALL_READY           (1UL << 31)	/* Card Power up status bit */
+#define OCR_HC_CCS              (1 << 30)	/* High capacity card */
+#define OCR_VOLTAGE_RANGE_MSK   (0x00FF8000)
+
+#define SD_SEND_IF_ARG          0x000001AA
+#define SD_SEND_IF_ECHO_MSK     0x000000FF
+#define SD_SEND_IF_RESP         0x000000AA
+
+/**
+ * @brief R3 response definitions
+ */
+#define CMDRESP_R3_OCR_VAL(n)           (((uint32_t) n) & 0xFFFFFF)
+#define CMDRESP_R3_S18A                 (((uint32_t) 1 ) << 24)
+#define CMDRESP_R3_HC_CCS               (((uint32_t) 1 ) << 30)
+#define CMDRESP_R3_INIT_COMPLETE        (((uint32_t) 1 ) << 31)
+
+/**
+ * @brief R6 response definitions
+ */
+#define CMDRESP_R6_RCA_VAL(n)           (((uint32_t) (n >> 16)) & 0xFFFF)
+#define CMDRESP_R6_CARD_STATUS(n)       (((uint32_t) (n & 0x1FFF)) | \
+										 ((n & (1 << 13)) ? (1 << 19) : 0) | \
+										 ((n & (1 << 14)) ? (1 << 22) : 0) | \
+										 ((n & (1 << 15)) ? (1 << 23) : 0))
+
+/**
+ * @brief R7 response definitions
+ */
+/** Echo-back of check-pattern */
+#define CMDRESP_R7_CHECK_PATTERN(n)     (((uint32_t) n ) & 0xFF)
+/** Voltage accepted */
+#define CMDRESP_R7_VOLTAGE_ACCEPTED     (((uint32_t) 1 ) << 8)
+
+/**
+ * @brief CMD3 command definitions
+ */
+/** Card Address */
+#define CMD3_RCA(n)         (((uint32_t) (n & 0xFFFF) ) << 16)
+
+/**
+ * @brief CMD7 command definitions
+ */
+/** Card Address */
+#define CMD7_RCA(n)         (((uint32_t) (n & 0xFFFF) ) << 16)
+
+/**
+ * @brief CMD8 command definitions
+ */
+/** Check pattern */
+#define CMD8_CHECKPATTERN(n)            (((uint32_t) (n & 0xFF) ) << 0)
+/** Recommended pattern */
+#define CMD8_DEF_PATTERN                    (0xAA)
+/** Voltage supplied.*/
+#define CMD8_VOLTAGESUPPLIED_27_36     (((uint32_t) 1 ) << 8)
+
+/**
+ * @brief CMD9 command definitions
+ */
+#define CMD9_RCA(n)         (((uint32_t) (n & 0xFFFF) ) << 16)
+
+/**
+ * @brief CMD13 command definitions
+ */
+#define CMD13_RCA(n)            (((uint32_t) (n & 0xFFFF) ) << 16)
+
+/**
+ * @brief APP_CMD command definitions
+ */
+#define CMD55_RCA(n)            (((uint32_t) (n & 0xFFFF) ) << 16)
+
+/**
+ * @brief ACMD41 command definitions
+ */
+#define ACMD41_OCR(n)                   (((uint32_t) n) & 0xFFFFFF)
+#define ACMD41_S18R                     (((uint32_t) 1 ) << 24)
+#define ACMD41_XPC                      (((uint32_t) 1 ) << 28)
+#define ACMD41_HCS                      (((uint32_t) 1 ) << 30)
+
+/**
+ * @brief ACMD6 command definitions
+ */
+#define ACMD6_BUS_WIDTH(n)              ((uint32_t) n & 0x03)
+#define ACMD6_BUS_WIDTH_1               (0)
+#define ACMD6_BUS_WIDTH_4               (2)
+
+/** @brief Card type defines
+ */
+#define CARD_TYPE_SD    (1 << 0)
+#define CARD_TYPE_4BIT  (1 << 1)
+#define CARD_TYPE_8BIT  (1 << 2)
+#define CARD_TYPE_HC    (OCR_HC_CCS)/*!< high capacity card > 2GB */
+
+/**
+ * @brief SD/MMC sector size in bytes
+ */
+#define MMC_SECTOR_SIZE     512
+
+/**
+ * @brief Typical enumeration clock rate
+ */
+#define SD_MMC_ENUM_CLOCK       400000
+
+/**
+ * @brief Max MMC clock rate
+ */
+#define MMC_MAX_CLOCK           20000000
+
+/**
+ * @brief Type 0 MMC card max clock rate
+ */
+#define MMC_LOW_BUS_MAX_CLOCK   26000000
+
+/**
+ * @brief Type 1 MMC card max clock rate
+ */
+#define MMC_HIGH_BUS_MAX_CLOCK  52000000
+
+/**
+ * @brief Max SD clock rate
+ */
+#define SD_MAX_CLOCK            25000000
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __SDMMC_H */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc_17xx_40xx.h
new file mode 100644
index 000000000..75c2f2b36
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/sdmmc_17xx_40xx.h
@@ -0,0 +1,202 @@
+/*
+ * @brief LPC17xx/40xx SDMMC Card Interface driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SDMMC_17XX_40XX_H_
+#define __SDMMC_17XX_40XX_H_
+
+#include "sdmmc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SDMMC_17XX_40XX CHIP: LPC17xx/40xx SDMMC card driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*
+ * SD/MMC Response type definitions
+ */
+#define CMDRESP_NONE_TYPE       (SDC_COMMAND_NO_RSP)
+#define CMDRESP_R1_TYPE         (SDC_COMMAND_SHORT_RSP)
+#define CMDRESP_R1b_TYPE        (SDC_COMMAND_SHORT_RSP)
+#define CMDRESP_R2_TYPE         (SDC_COMMAND_LONG_RSP)
+#define CMDRESP_R3_TYPE         (SDC_COMMAND_SHORT_RSP)
+#define CMDRESP_R6_TYPE         (SDC_COMMAND_SHORT_RSP)
+#define CMDRESP_R7_TYPE         (SDC_COMMAND_SHORT_RSP)
+
+#ifdef SDC_DMA_ENABLE
+
+/**
+ * @brief SDC Event structure
+ */
+typedef struct {
+	uint8_t DmaChannel;		/*!< DMA Channel used for transfer data */
+} SDMMC_EVENT_T;
+
+#else
+
+/**
+ * @brief SDC Event structure
+ */
+typedef struct {
+	void *Buffer;		/*!< Pointer to data buffer */
+	uint32_t Size;		/*!< Transfer size */
+	uint32_t Index;		/*!< Current transfer index */
+	uint8_t  Dir;		/*!< Transfer direction 0: transmit, 1: receive */
+} SDMMC_EVENT_T;
+#endif /* SDC_DMA_ENABLE */
+
+/*
+ * SD command values (Command Index, Response)
+ */
+#define SD_GO_IDLE_STATE           (SDC_COMMAND_INDEX(MMC_GO_IDLE_STATE) | CMDRESP_NONE_TYPE | SDC_COMMAND_INTERRUPT)	/*!< GO_IDLE_STATE(MMC) or RESET(SD) */
+#define SD_CMD1_SEND_OP_COND       (SDC_COMMAND_INDEX(MMC_SEND_OP_COND) | CMDRESP_R3_TYPE | 0)					/*!< SEND_OP_COND(MMC) or ACMD41(SD) */
+#define SD_CMD2_ALL_SEND_CID       (SDC_COMMAND_INDEX(MMC_ALL_SEND_CID) | CMDRESP_R2_TYPE | 0)					/*!< ALL_SEND_CID */
+#define SD_CMD3_SET_RELATIVE_ADDR  (SDC_COMMAND_INDEX(MMC_SET_RELATIVE_ADDR) | CMDRESP_R1_TYPE | 0)				/*!< SET_RELATE_ADDR */
+#define SD_CMD3_SEND_RELATIVE_ADDR (SDC_COMMAND_INDEX(SD_SEND_RELATIVE_ADDR) | CMDRESP_R6_TYPE | 0)				/*!< SEND_RELATE_ADDR */
+#define SD_CMD7_SELECT_CARD        (SDC_COMMAND_INDEX(MMC_SELECT_CARD) | CMDRESP_R1b_TYPE | 0)					/*!< SELECT/DESELECT_CARD */
+#define SD_CMD8_SEND_IF_COND       (SDC_COMMAND_INDEX(SD_CMD8) | CMDRESP_R7_TYPE | 0)							/*!< SEND_IF_COND */
+#define SD_CMD9_SEND_CSD           (SDC_COMMAND_INDEX(MMC_SEND_CSD) | CMDRESP_R2_TYPE | 0)						/*!< SEND_CSD */
+#define SD_CMD12_STOP_TRANSMISSION (SDC_COMMAND_INDEX(MMC_STOP_TRANSMISSION) | CMDRESP_R1_TYPE | 0)				/*!< STOP_TRANSMISSION */
+#define SD_CMD13_SEND_STATUS       (SDC_COMMAND_INDEX(MMC_SEND_STATUS) | CMDRESP_R1_TYPE | 0)					/*!< SEND_STATUS */
+
+/* Block-Oriented Read Commands (class 2) */
+#define SD_CMD16_SET_BLOCKLEN      (SDC_COMMAND_INDEX(MMC_SET_BLOCKLEN) | CMDRESP_R1_TYPE | 0)					/*!< SET_BLOCK_LEN */
+#define SD_CMD17_READ_SINGLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_SINGLE_BLOCK) | CMDRESP_R1_TYPE | 0)				/*!< READ_SINGLE_BLOCK */
+#define SD_CMD18_READ_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_MULTIPLE_BLOCK) | CMDRESP_R1_TYPE | 0)			/*!< READ_MULTIPLE_BLOCK */
+
+/* Block-Oriented Write Commands (class 4) */
+#define SD_CMD24_WRITE_BLOCK       (SDC_COMMAND_INDEX(MMC_WRITE_BLOCK) | CMDRESP_R1_TYPE | 0)					/*!< WRITE_BLOCK */
+#define SD_CMD25_WRITE_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_MULTIPLE_BLOCK) | CMDRESP_R1_TYPE | 0)		/*!< WRITE_MULTIPLE_BLOCK */
+
+/* Erase Commands (class 5) */
+#define SD_CMD32_ERASE_WR_BLK_START (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_START) | CMDRESP_R1_TYPE | 0)			/*!< ERASE_WR_BLK_START */
+#define SD_CMD33_ERASE_WR_BLK_END   (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_END) | CMDRESP_R1_TYPE | 0)				/*!< ERASE_WR_BLK_END */
+#define SD_CMD38_ERASE              (SDC_COMMAND_INDEX(SD_ERASE) | CMDRESP_R1b_TYPE | 0)						/*!< ERASE */
+
+/* Application-Specific Commands (class 8) */
+#define SD_CMD55_APP_CMD           (SDC_COMMAND_INDEX(MMC_APP_CMD) | CMDRESP_R1_TYPE | 0)						/*!< APP_CMD */
+#define SD_ACMD6_SET_BUS_WIDTH     (SDC_COMMAND_INDEX(SD_APP_SET_BUS_WIDTH) | CMDRESP_R1_TYPE | 0)				/*!< SET_BUS_WIDTH */
+#define SD_ACMD13_SEND_SD_STATUS   (SDC_COMMAND_INDEX(MMC_SEND_STATUS) | CMDRESP_R1_TYPE | 0)					/*!< SEND_SD_STATUS */
+#define SD_ACMD41_SD_SEND_OP_COND  (SDC_COMMAND_INDEX(SD_APP_OP_COND) | CMDRESP_R3_TYPE | 0)					/*!< SD_SEND_OP_COND */
+
+/**
+ * @brief	SD card interrupt service routine
+ * @param	pSDC	: Pointer to SDC peripheral base address
+ * @param	txBuf	: Pointer to TX Buffer (If it is NULL, dont send data to card)
+ * @param	txCnt	: Pointer to buffer storing the current transmit index
+ * @param	rxBuf	: Pointer to RX Buffer (If it is NULL, dont read data from card)
+ * @param	rxCnt	: Pointer to buffer storing the current receive index
+ * @return	Positive value: Data transfer
+ *          Negative value: Error in data transfer
+ *          Zero: Data transfer completed
+ */
+int32_t Chip_SDMMC_IRQHandler (LPC_SDC_T *pSDC, uint8_t *txBuf, uint32_t *txCnt,
+							   uint8_t *rxBuf, uint32_t *rxCnt);
+
+/**
+ * @brief	Function to enumerate the SD/MMC/SDHC/MMC+ cards
+ * @param	pSDC	    : Pointer to SDC peripheral base address
+ * @param	pCardInfo	: Pointer to pre-allocated card info structure
+ * @return	1 if a card is acquired, otherwise 0
+ */
+int32_t Chip_SDMMC_Acquire(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
+
+/**
+ * @brief	Get card's current state (idle, transfer, program, etc.)
+ * @param	pSDC	    : Pointer to SDC peripheral base address
+ * @param	pCardInfo	: Pointer to pre-allocated card info structure
+ * @return	Current SD card  state
+ */
+SDMMC_STATE_T Chip_SDMMC_GetCardState(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
+
+/**
+ * @brief	Get 'card status' of SD Memory card
+ * @param	pSDC	    : Pointer to SDC peripheral base address
+ * @param	pCardInfo	: Pointer to pre-allocated card info structure
+ * @return	Current SD card status
+ */
+uint32_t Chip_SDMMC_GetCardStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo);
+
+/**
+ * @brief	Get 'sd status' of SD Memory card
+ * @param	pSDC	    : Pointer to SDC peripheral base address
+ * @param	pCardInfo	: Pointer to pre-allocated card info structure
+ * @param	pStatus		: Pointer to buffer storing status (it must be 64-byte-length)
+ * @return	Number of bytes read
+ */
+int32_t Chip_SDMMC_GetSDStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo, uint32_t *pStatus);
+
+/**
+ * @brief	Performs the read of data from the SD/MMC card
+ * @param	pSDC		: The base of SDC peripheral on the chip
+ * @param	pCardInfo	: Pointer to Card information structure
+ * @param	buffer		: Pointer to data buffer to copy to
+ * @param	startblock	: Start block number
+ * @param	blockNum	: Number of block to read
+ * @return	Bytes read, or 0 on error
+ */
+int32_t Chip_SDMMC_ReadBlocks(LPC_SDC_T *pSDC,
+							  SDMMC_CARD_T *pCardInfo,
+							  void *buffer,
+							  int32_t startblock,
+							  int32_t blockNum);
+
+/**
+ * @brief	Performs write of data to the SD/MMC card
+ * @param	pSDC		: The base of SDC peripheral on the chip
+ * @param	pCardInfo	: Pointer to Card information structure
+ * @param	buffer		: Pointer to data buffer to copy to
+ * @param	startblock	: Start block number
+ * @param	blockNum	: Number of block to write
+ * @return	Number of bytes actually written, or 0 on error
+ */
+int32_t Chip_SDMMC_WriteBlocks(LPC_SDC_T *pSDC,
+							   SDMMC_CARD_T *pCardInfo,
+							   void *buffer,
+							   int32_t startblock,
+							   int32_t blockNum);
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SDC_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/spi_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/spi_17xx_40xx.h
new file mode 100644
index 000000000..56f766454
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/spi_17xx_40xx.h
@@ -0,0 +1,416 @@
+/*
+ * @brief LPC17xx/40xx SPI driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SPI_17XX_40XX_H_
+#define __SPI_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SPI_17XX_40XX CHIP: LPC17xx/40xx SPI driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC175X_6X)
+
+/**
+ * @brief SPI register block structure
+ */
+typedef struct {					/*!< SPI Structure          */
+	__IO uint32_t  CR;				/*!< SPI Control Register. This register controls the operation of the SPI. */
+	__I  uint32_t  SR;				/*!< SPI Status Register. This register shows the status of the SPI. */
+	__IO uint32_t  DR;				/*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */
+	__IO uint32_t  CCR;				/*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
+	__I  uint32_t  RESERVED0[3];
+	__IO uint32_t  INT;				/*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
+} LPC_SPI_T;
+
+/*
+ * Macro defines for SPI Control register
+ */
+/* SPI CFG Register BitMask */
+#define SPI_CR_BITMASK       ((uint32_t) 0xFFC)
+/** Enable of controlling the number of bits per transfer  */
+#define SPI_CR_BIT_EN         ((uint32_t) (1 << 2))
+/** Mask of field of bit controlling */
+#define SPI_CR_BITS_MASK      ((uint32_t) 0xF00)
+/** Set the number of bits per a transfer */
+#define SPI_CR_BITS(n)        ((uint32_t) ((n << 8) & 0xF00))	/* n is in range 8-16 */
+/** SPI Clock Phase Select*/
+#define SPI_CR_CPHA_FIRST     ((uint32_t) (0))	/*Capture data on the first edge, Change data on the following edge*/
+#define SPI_CR_CPHA_SECOND    ((uint32_t) (1 << 3))	/*Change data on the first edge, Capture data on the following edge*/
+/** SPI Clock Polarity Select*/
+#define SPI_CR_CPOL_LO        ((uint32_t) (0))	/* The rest state of the clock (between frames) is low.*/
+#define SPI_CR_CPOL_HI        ((uint32_t) (1 << 4))	/* The rest state of the clock (between frames) is high.*/
+/** SPI Slave Mode Select */
+#define SPI_CR_SLAVE_EN       ((uint32_t) 0)
+/** SPI Master Mode Select */
+#define SPI_CR_MASTER_EN      ((uint32_t) (1 << 5))
+/** SPI MSB First mode enable */
+#define SPI_CR_MSB_FIRST_EN   ((uint32_t) 0)	/*Data will be transmitted and received in standard order (MSB first).*/
+/** SPI LSB First mode enable */
+#define SPI_CR_LSB_FIRST_EN   ((uint32_t) (1 << 6))	/*Data will be transmitted and received in reverse order (LSB first).*/
+/** SPI interrupt enable */
+#define SPI_CR_INT_EN         ((uint32_t) (1 << 7))
+
+/*
+ * Macro defines for SPI Status register
+ */
+/** SPI STAT Register BitMask */
+#define SPI_SR_BITMASK        ((uint32_t) 0xF8)
+/** Slave abort Flag */
+#define SPI_SR_ABRT           ((uint32_t) (1 << 3))	/* When 1, this bit indicates that a slave abort has occurred. */
+/* Mode fault Flag */
+#define SPI_SR_MODF           ((uint32_t) (1 << 4))	/* when 1, this bit indicates that a Mode fault error has occurred. */
+/** Read overrun flag*/
+#define SPI_SR_ROVR           ((uint32_t) (1 << 5))	/* When 1, this bit indicates that a read overrun has occurred. */
+/** Write collision flag. */
+#define SPI_SR_WCOL           ((uint32_t) (1 << 6))	/* When 1, this bit indicates that a write collision has occurred.. */
+/** SPI transfer complete flag. */
+#define SPI_SR_SPIF           ((uint32_t) (1 << 7))		/* When 1, this bit indicates when a SPI data transfer is complete.. */
+/** SPI error flag */
+#define SPI_SR_ERROR          (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
+/*
+ * Macro defines for SPI Test Control Register register
+ */
+/*Enable SPI Test Mode */
+#define SPI_TCR_TEST(n)       ((uint32_t) ((n & 0x3F) << 1))
+
+/*
+ * Macro defines for SPI Interrupt register
+ */
+/** SPI interrupt flag */
+#define SPI_INT_SPIF          ((uint32_t) (1 << 0))
+
+/**
+ * Macro defines for SPI Data register
+ */
+/** Receiver Data  */
+#define SPI_DR_DATA(n)        ((uint32_t) ((n) & 0xFFFF))
+
+/** @brief SPI Mode*/
+typedef enum {
+	SPI_MODE_MASTER = SPI_CR_MASTER_EN,			/* Master Mode */
+	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN,			/* Slave Mode */
+} SPI_MODE_T;
+
+/** @brief SPI Clock Mode*/
+typedef enum {
+	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST,		/**< CPHA = 0, CPOL = 0 */
+	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST,		/**< CPHA = 0, CPOL = 1 */
+	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND,	/**< CPHA = 1, CPOL = 0 */
+	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND,	/**< CPHA = 1, CPOL = 1 */
+	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,/**< alias */
+	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,/**< alias */
+	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,/**< alias */
+	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,/**< alias */
+} SPI_CLOCK_MODE_T;
+
+/** @brief SPI Data Order Mode*/
+typedef enum {
+	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN,			/* Standard Order */
+	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN,			/* Reverse Order */
+} SPI_DATA_ORDER_T;
+
+/*
+ * @brief Number of bits per frame
+ */
+typedef enum {
+	SPI_BITS_8 = SPI_CR_BITS(8),		/**< 8 bits/frame */
+	SPI_BITS_9 = SPI_CR_BITS(9),		/**< 9 bits/frame */
+	SPI_BITS_10 = SPI_CR_BITS(10),		/**< 10 bits/frame */
+	SPI_BITS_11 = SPI_CR_BITS(11),		/**< 11 bits/frame */
+	SPI_BITS_12 = SPI_CR_BITS(12),		/**< 12 bits/frame */
+	SPI_BITS_13 = SPI_CR_BITS(13),		/**< 13 bits/frame */
+	SPI_BITS_14 = SPI_CR_BITS(14),		/**< 14 bits/frame */
+	SPI_BITS_15 = SPI_CR_BITS(15),		/**< 15 bits/frame */
+	SPI_BITS_16 = SPI_CR_BITS(16),		/**< 16 bits/frame */
+} SPI_BITS_T;
+
+/** SPI callback function type*/
+typedef void (*SPI_CALLBACK_T)(void);
+/*
+ * @brief SPI config format
+ */
+typedef struct {
+	SPI_BITS_T bits;						/*!< bits/frame */
+	SPI_CLOCK_MODE_T clockMode;	/*!< Format config: clock phase/polarity */
+	SPI_DATA_ORDER_T dataOrder;	/*!< Data order (MSB first/LSB first) */
+} SPI_CONFIG_FORMAT_T;
+
+/*
+ * @brief SPI data setup structure
+ */
+typedef struct {
+	uint8_t      *pTxData;					/*!< Pointer to transmit data */
+	uint8_t      *pRxData;					/*!< Pointer to receive data */
+	uint32_t  cnt;							/*!< Transfer counter */
+	uint32_t  length;						/*!< Length of transfer data */
+	SPI_CALLBACK_T    fnBefFrame;				/*!< Function to call before sending frame */
+	SPI_CALLBACK_T    fnAftFrame;				/*!< Function to call after sending frame */
+	SPI_CALLBACK_T    fnBefTransfer;			/*!< Function to call before starting a transfer */
+	SPI_CALLBACK_T    fnAftTransfer;			/*!< Function to call after a transfer complete */
+} SPI_DATA_SETUP_T;
+
+/**
+ * @brief	Get the current status of SPI controller
+ * @return	SPI controller status (Or-ed value of SPI_SR_*)
+ */
+STATIC INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI)
+{
+	return pSPI->SR;
+}
+
+/**
+ * @brief	Send SPI 16-bit data
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @param	data	: Transmit Data
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SPI_SendFrame(LPC_SPI_T *pSPI, uint16_t data)
+{
+	pSPI->DR = SPI_DR_DATA(data);
+}
+
+/**
+ * @brief	Get received SPI data
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @return	receive data
+ */
+STATIC INLINE uint16_t Chip_SPI_ReceiveFrame(LPC_SPI_T *pSPI)
+{
+	return SPI_DR_DATA(pSPI->DR);
+}
+
+/**
+ * @brief	Set up output clocks per bit for SPI bus
+ * @param	pSPI		: The base of SPI peripheral on the chip
+ * @param	counter	: the number of SPI peripheral clock cycles that make up an SPI clock
+ * @return	 Nothing
+ * @note	The counter must be an even number greater than or equal to 8. <br>
+ *		The SPI SCK rate = PCLK_SPI / counter.
+ */
+STATIC INLINE void Chip_SPI_SetClockCounter(LPC_SPI_T *pSPI, uint32_t counter)
+{
+	pSPI->CCR = counter;
+}
+
+/**
+ * @brief   Set up the SPI frame format
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	format			: Pointer to Frame format structure
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SPI_SetFormat(LPC_SPI_T *pSPI, SPI_CONFIG_FORMAT_T *format)
+{
+	pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | format->bits | format->clockMode | format->dataOrder;
+}
+
+/**
+ * @brief	Get the number of bits transferred in each frame
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @return	 the number of bits transferred in each frame
+ */
+STATIC INLINE SPI_BITS_T Chip_SPI_GetDataSize(LPC_SPI_T *pSPI)
+{
+	return (pSPI->CR & SPI_CR_BIT_EN) ? ((SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;
+}
+
+/**
+ * @brief	Get the current CPHA & CPOL setting
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @return	CPHA & CPOL setting
+ */
+STATIC INLINE SPI_CLOCK_MODE_T Chip_SPI_GetClockMode(LPC_SPI_T *pSPI)
+{
+	return (SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));
+}
+
+/**
+ * @brief	Set the SPI working as master or slave mode
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @return	 Operating mode
+ */
+STATIC INLINE SPI_MODE_T Chip_SPI_GetMode(LPC_SPI_T *pSPI)
+{
+	return (SPI_MODE_T) (pSPI->CR & (1 << 5));
+}
+
+/**
+ * @brief   Set the SPI operating modes, master or slave
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	mode		: master mode/slave mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SPI_SetMode(LPC_SPI_T *pSPI, SPI_MODE_T mode)
+{
+	pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;
+}
+
+/**
+ * @brief   Set the clock frequency for SPI interface
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	bitRate		: The SPI bit rate
+ * @return	Nothing
+ */
+void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate);
+
+/**
+ * @brief   Enable SPI interrupt
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SPI_Int_Enable(LPC_SPI_T *pSPI)
+{
+	pSPI->CR |= SPI_CR_INT_EN;
+}
+
+/**
+ * @brief   Disable SPI interrupt
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SPI_Int_Disable(LPC_SPI_T *pSPI)
+{
+	pSPI->CR &= ~SPI_CR_INT_EN;
+}
+
+/**
+ * @brief	Get the interrupt status
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @return	SPI interrupt Status (Or-ed bit value of SPI_INT_*)
+ */
+STATIC INLINE uint32_t Chip_SPI_Int_GetStatus(LPC_SPI_T *pSPI)
+{
+	return pSPI->INT;
+}
+
+/**
+ * @brief	Clear the interrupt status
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @param	mask	: SPI interrupt mask (Or-ed bit value of SPI_INT_*)
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SPI_Int_ClearStatus(LPC_SPI_T *pSPI, uint32_t mask)
+{
+	pSPI->INT = mask;
+}
+
+/**
+ * @brief   Initialize the SPI
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SPI_Init(LPC_SPI_T *pSPI);
+
+/**
+ * @brief	Deinitialise the SPI
+ * @param	pSPI	: The base of SPI peripheral on the chip
+ * @return	Nothing
+ * @note	The SPI controller is disabled
+ */
+void Chip_SPI_DeInit(LPC_SPI_T *pSPI);
+
+/**
+ * @brief   Clean all data in RX FIFO of SPI
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI);
+
+/**
+ * @brief   SPI Interrupt Read/Write with 8-bit frame width
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	xf_setup		: Pointer to a SPI_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SPI Interrupt Read/Write with 16-bit frame width
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	xf_setup		: Pointer to a SPI_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SPI Polling Read/Write in blocking mode
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	pXfSetup		: Pointer to a SPI_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. It starts with writing phase and after that,
+ * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
+ * through xf_setup param.
+ */
+uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup);
+
+/**
+ * @brief   SPI Polling Write in blocking mode
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: Buffer length
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. First, a writing operation will send
+ * the needed data. After that, a dummy reading operation is generated to clear data buffer
+ */
+uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   SPI Polling Read in blocking mode
+ * @param	pSPI			: The base SPI peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: The length of buffer
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. First, a dummy writing operation is generated
+ * to clear data buffer. After that, a reading operation will receive the needed data
+ */
+uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len);
+
+#endif /* defined(CHIP_LPC175X_6X) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SPI_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/spifi_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/spifi_17xx_40xx.h
new file mode 100644
index 000000000..01807ac82
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/spifi_17xx_40xx.h
@@ -0,0 +1,79 @@
+/*
+ * @brief LPC17xx/40xx SPIFI driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SPIFI_17XX_40XX_H_
+#define __SPIFI_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SPIFI_17XX_40XX CHIP: LPC17xx/40xx SPIFI Driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if defined(CHIP_LPC40XX)
+
+/** SPIFI memory base address */
+#define SPIFLASH_BASE_ADDRESS                 (0x28000000)
+/** SPIFI API ROM address */
+#define SPIFI_ROM_PTR                         (0x1FFF1954)
+
+/**
+ * @brief	Initialize the SPIFI
+ * @return	None
+ */
+STATIC INLINE void Chip_SPIFI_Init(void)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SPIFI);
+}
+
+/**
+ * @brief	Shutdown the SPIFI
+ * @return	None
+ */
+STATIC INLINE void Chip_SPIFI_DeInit(void)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SPIFI);
+}
+
+#endif /* defined(CHIP_LPC40XX) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SPIFI_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/ssp_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/ssp_17xx_40xx.h
new file mode 100644
index 000000000..aadec567b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/ssp_17xx_40xx.h
@@ -0,0 +1,598 @@
+/*
+ * @brief LPC17xx/40xx SSP driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SSP_17XX_40XX_H_
+#define __SSP_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SSP_17XX_40XX CHIP: LPC17xx/40xx SSP driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief SSP register block structure
+ */
+typedef struct {			/*!< SSPn Structure         */
+	__IO uint32_t CR0;		/*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
+	__IO uint32_t CR1;		/*!< Control Register 1. Selects master/slave and other modes. */
+	__IO uint32_t DR;		/*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+	__I  uint32_t SR;		/*!< Status Register        */
+	__IO uint32_t CPSR;		/*!< Clock Prescale Register */
+	__IO uint32_t IMSC;		/*!< Interrupt Mask Set and Clear Register */
+	__I  uint32_t RIS;		/*!< Raw Interrupt Status Register */
+	__I  uint32_t MIS;		/*!< Masked Interrupt Status Register */
+	__O  uint32_t ICR;		/*!< SSPICR Interrupt Clear Register */
+	__IO uint32_t DMACR;	/*!< SSPn DMA control register */
+} LPC_SSP_T;
+
+/**
+ * Macro defines for CR0 register
+ */
+
+/** SSP data size select, must be 4 bits to 16 bits */
+#define SSP_CR0_DSS(n)          ((uint32_t) ((n) & 0xF))
+/** SSP control 0 Motorola SPI mode */
+#define SSP_CR0_FRF_SPI         ((uint32_t) (0 << 4))
+/** SSP control 0 TI synchronous serial mode */
+#define SSP_CR0_FRF_TI          ((uint32_t) (1 << 4))
+/** SSP control 0 National Micro-wire mode */
+#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
+/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
+   bus clock high between frames, (0) = low */
+#define SSP_CR0_CPOL_LO     ((uint32_t) (0))
+#define SSP_CR0_CPOL_HI     ((uint32_t) (1 << 6))
+/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
+   on the second clock transition of the frame, (0) = first */
+#define SSP_CR0_CPHA_FIRST  ((uint32_t) (0))
+#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
+/** SSP serial clock rate value load macro, divider rate is
+   PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK     ((uint32_t) (0xFFFF))
+/** SSP serial clock rate value load macro, divider rate is
+   PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n)      ((uint32_t) ((n & 0xFF) << 8))
+
+/**
+ * Macro defines for CR1 register
+ */
+
+/** SSP control 1 loopback mode enable bit */
+#define SSP_CR1_LBM_EN      ((uint32_t) (1 << 0))
+/** SSP control 1 enable bit */
+#define SSP_CR1_SSP_EN      ((uint32_t) (1 << 1))
+/** SSP control 1 slave enable */
+#define SSP_CR1_SLAVE_EN    ((uint32_t) (1 << 2))
+#define SSP_CR1_MASTER_EN   ((uint32_t) (0))
+/** SSP control 1 slave out disable bit, disables transmit line in slave
+   mode */
+#define SSP_CR1_SO_DISABLE  ((uint32_t) (1 << 3))
+/** SSP CR1 bit mask */
+#define SSP_CR1_BITMASK     ((uint32_t) (0x0F))
+
+/** SSP CPSR bit mask */
+#define SSP_CPSR_BITMASK    ((uint32_t) (0xFF))
+/**
+ * Macro defines for DR register
+ */
+
+/** SSP data bit mask */
+#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
+
+/**
+ * Macro defines for SR register
+ */
+
+/** SSP SR bit mask */
+#define SSP_SR_BITMASK  ((uint32_t) (0x1F))
+
+/** ICR bit mask */
+#define SSP_ICR_BITMASK ((uint32_t) (0x03))
+
+/**
+ * @brief SSP Type of Status
+ */
+typedef enum _SSP_STATUS {
+	SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
+	SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
+	SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
+	SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
+	SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
+} SSP_STATUS_T;
+
+/**
+ * @brief SSP Type of Interrupt Mask
+ */
+typedef enum _SSP_INTMASK {
+	SSP_RORIM = ((uint32_t)(1 << 0)),	/**< Overun */
+	SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
+	SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
+	SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
+	SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
+} SSP_INTMASK_T;
+
+/**
+ * @brief SSP Type of Mask Interrupt Status
+ */
+typedef enum _SSP_MASKINTSTATUS {
+	SSP_RORMIS = ((uint32_t)(1 << 0)),	/**< Overun */
+	SSP_RTMIS = ((uint32_t)(1 << 1)),	/**< TimeOut */
+	SSP_RXMIS = ((uint32_t)(1 << 2)),	/**< Rx FIFO is at least half full */
+	SSP_TXMIS = ((uint32_t)(1 << 3)),	/**< Tx FIFO is at least half empty */
+	SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
+} SSP_MASKINTSTATUS_T;
+
+/**
+ * @brief SSP Type of Raw Interrupt Status
+ */
+typedef enum _SSP_RAWINTSTATUS {
+	SSP_RORRIS = ((uint32_t)(1 << 0)),	/**< Overun */
+	SSP_RTRIS = ((uint32_t)(1 << 1)),	/**< TimeOut */
+	SSP_RXRIS = ((uint32_t)(1 << 2)),	/**< Rx FIFO is at least half full */
+	SSP_TXRIS = ((uint32_t)(1 << 3)),	/**< Tx FIFO is at least half empty */
+	SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
+} SSP_RAWINTSTATUS_T;
+
+typedef enum _SSP_INTCLEAR {
+	SSP_RORIC = 0x0,
+	SSP_RTIC = 0x1,
+	SSP_INT_CLEAR_BITMASK = 0x3,
+} SSP_INTCLEAR_T;
+
+typedef enum _SSP_DMA {
+	SSP_DMA_RX = (1u),	/**< DMA RX Enable */
+	SSP_DMA_TX = (1u << 1),	/**< DMA TX Enable */
+	SSP_DMA_BITMASK = ((uint32_t)(0x3)),
+} SSP_DMA_T;
+
+/*
+ * @brief SSP clock format
+ */
+typedef enum CHIP_SSP_CLOCK_FORMAT {
+	SSP_CLOCK_CPHA0_CPOL0 = (0 << 6),		/**< CPHA = 0, CPOL = 0 */
+	SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),		/**< CPHA = 0, CPOL = 1 */
+	SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),		/**< CPHA = 1, CPOL = 0 */
+	SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),		/**< CPHA = 1, CPOL = 1 */
+	SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
+	SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
+	SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
+	SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
+} CHIP_SSP_CLOCK_MODE_T;
+
+/*
+ * @brief SSP frame format
+ */
+typedef enum CHIP_SSP_FRAME_FORMAT {
+	SSP_FRAMEFORMAT_SPI = (0 << 4),			/**< Frame format: SPI */
+	CHIP_SSP_FRAME_FORMAT_TI = (1u << 4),			/**< Frame format: TI SSI */
+	SSP_FRAMEFORMAT_MICROWIRE = (2u << 4),	/**< Frame format: Microwire */
+} CHIP_SSP_FRAME_FORMAT_T;
+
+/*
+ * @brief Number of bits per frame
+ */
+typedef enum CHIP_SSP_BITS {
+	SSP_BITS_4 = (3u << 0),		/*!< 4 bits/frame */
+	SSP_BITS_5 = (4u << 0),		/*!< 5 bits/frame */
+	SSP_BITS_6 = (5u << 0),		/*!< 6 bits/frame */
+	SSP_BITS_7 = (6u << 0),		/*!< 7 bits/frame */
+	SSP_BITS_8 = (7u << 0),		/*!< 8 bits/frame */
+	SSP_BITS_9 = (8u << 0),		/*!< 9 bits/frame */
+	SSP_BITS_10 = (9u << 0),	/*!< 10 bits/frame */
+	SSP_BITS_11 = (10u << 0),	/*!< 11 bits/frame */
+	SSP_BITS_12 = (11u << 0),	/*!< 12 bits/frame */
+	SSP_BITS_13 = (12u << 0),	/*!< 13 bits/frame */
+	SSP_BITS_14 = (13u << 0),	/*!< 14 bits/frame */
+	SSP_BITS_15 = (14u << 0),	/*!< 15 bits/frame */
+	SSP_BITS_16 = (15u << 0),	/*!< 16 bits/frame */
+} CHIP_SSP_BITS_T;
+
+/*
+ * @brief SSP config format
+ */
+typedef struct SSP_ConfigFormat {
+	CHIP_SSP_BITS_T bits;					/*!< Format config: bits/frame */
+	CHIP_SSP_CLOCK_MODE_T clockMode;	/*!< Format config: clock phase/polarity */
+	CHIP_SSP_FRAME_FORMAT_T frameFormat;	/*!< Format config: SPI/TI/Microwire */
+} SSP_ConfigFormat;
+
+/**
+ * @brief	Enable SSP operation
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 |= SSP_CR1_SSP_EN;
+}
+
+/**
+ * @brief	Disable SSP operation
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
+}
+
+/**
+ * @brief	Enable loopback mode
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ * @note	Serial input is taken from the serial output (MOSI or MISO) rather
+ * than the serial input pin
+ */
+STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 |= SSP_CR1_LBM_EN;
+}
+
+/**
+ * @brief	Disable loopback mode
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ * @note	Serial input is taken from the serial output (MOSI or MISO) rather
+ * than the serial input pin
+ */
+STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
+{
+	pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
+}
+
+/**
+ * @brief	Get the current status of SSP controller
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	Stat	: Type of status, should be :
+ *						- SSP_STAT_TFE
+ *						- SSP_STAT_TNF
+ *						- SSP_STAT_RNE
+ *						- SSP_STAT_RFF
+ *						- SSP_STAT_BSY
+ * @return	 SSP controller status, SET or RESET
+ */
+STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
+{
+	return (pSSP->SR & Stat) ? SET : RESET;
+}
+
+/**
+ * @brief	Get the masked interrupt status
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 SSP Masked Interrupt Status Register value
+ * @note	The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
+ */
+STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
+{
+	return pSSP->MIS;
+}
+
+/**
+ * @brief	Get the raw interrupt status
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	RawInt	: Interrupt condition to be get status, shoud be :
+ *						- SSP_RORRIS
+ *						- SSP_RTRIS
+ *						- SSP_RXRIS
+ *						- SSP_TXRIS
+ * @return	 Raw interrupt status corresponding to interrupt condition , SET or RESET
+ * @note	Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
+ */
+STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
+{
+	return (pSSP->RIS & RawInt) ? SET : RESET;
+}
+
+/**
+ * @brief	Get the number of bits transferred in each frame
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 the number of bits transferred in each frame minus one
+ * @note	The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
+ */
+STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
+{
+	return SSP_CR0_DSS(pSSP->CR0);
+}
+
+/**
+ * @brief	Clear the corresponding interrupt condition(s) in the SSP controller
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	IntClear: Type of cleared interrupt, should be :
+ *						- SSP_RORIC
+ *						- SSP_RTIC
+ * @return	 Nothing
+ * @note	Software can clear one or more interrupt condition(s) in the SSP controller
+ */
+STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
+{
+	pSSP->ICR = IntClear;
+}
+
+/**
+ * @brief	Enable interrupt for the SSP
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
+{
+	pSSP->IMSC |= SSP_TXIM;
+}
+
+/**
+ * @brief	Disable interrupt for the SSP
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
+{
+	pSSP->IMSC &= (~SSP_TXIM);
+}
+
+/**
+ * @brief	Get received SSP data
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 SSP 16-bit data received
+ */
+STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
+{
+	return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
+}
+
+/**
+ * @brief	Send SSP 16-bit data
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	tx_data	: SSP 16-bit data to be transmited
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
+{
+	pSSP->DR = SSP_DR_BITMASK(tx_data);
+}
+
+/**
+ * @brief	Set up output clocks per bit for SSP bus
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @param	clk_rate	fs: The number of prescaler-output clocks per bit on the bus, minus one
+ * @param	prescale	: The factor by which the Prescaler divides the SSP peripheral clock PCLK
+ * @return	 Nothing
+ * @note	The bit frequency is PCLK / (prescale x[clk_rate+1])
+ */
+void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
+
+/**
+ * @brief	Set up the SSP frame format
+ * @param	pSSP		: The base of SSP peripheral on the chip
+ * @param	bits		: The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
+ * @param	frameFormat	: Frame format, should be :
+ *							- SSP_FRAMEFORMAT_SPI
+ *							- SSP_FRAME_FORMAT_TI
+ *							- SSP_FRAMEFORMAT_MICROWIRE
+ * @param	clockMode	: Select Clock polarity and Clock phase, should be :
+ *							- SSP_CLOCK_CPHA0_CPOL0
+ *							- SSP_CLOCK_CPHA0_CPOL1
+ *							- SSP_CLOCK_CPHA1_CPOL0
+ *							- SSP_CLOCK_CPHA1_CPOL1
+ * @return	 Nothing
+ * @note	Note: The clockFormat is only used in SPI mode
+ */
+STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
+{
+	pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
+}
+
+/**
+ * @brief	Set the SSP working as master or slave mode
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @param	mode	: Operating mode, should be
+ *						- SSP_MODE_MASTER
+ *						- SSP_MODE_SLAVE
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
+{
+	pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
+}
+
+/**
+ * @brief	Enable DMA for SSP
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_DMA_Enable(LPC_SSP_T *pSSP)
+{
+	pSSP->DMACR |= SSP_DMA_BITMASK;
+}
+
+/**
+ * @brief	Disable DMA for SSP
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	 Nothing
+ */
+STATIC INLINE void Chip_SSP_DMA_Disable(LPC_SSP_T *pSSP)
+{
+	pSSP->DMACR &= ~SSP_DMA_BITMASK;
+}
+
+/*
+ * @brief SSP mode
+ */
+typedef enum CHIP_SSP_MODE {
+	SSP_MODE_MASTER = (0 << 2),	/**< Master mode */
+	SSP_MODE_SLAVE = (1u << 2),	/**< Slave mode */
+} CHIP_SSP_MODE_T;
+
+/*
+ * @brief SPI address
+ */
+typedef struct {
+	uint8_t port;	/*!< Port Number */
+	uint8_t pin;	/*!< Pin number */
+} SPI_Address_t;
+
+/*
+ * @brief SSP data setup structure
+ */
+typedef struct {
+	void      *tx_data;	/*!< Pointer to transmit data */
+	uint32_t  tx_cnt;	/*!< Transmit counter */
+	void      *rx_data;	/*!< Pointer to transmit data */
+	uint32_t  rx_cnt;	/*!< Receive counter */
+	uint32_t  length;	/*!< Length of transfer data */
+} Chip_SSP_DATA_SETUP_T;
+
+/** SSP configuration parameter defines */
+/** Clock phase control bit */
+#define SSP_CPHA_FIRST          SSP_CR0_CPHA_FIRST
+#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
+
+/** Clock polarity control bit */
+/* There's no bug here!!!
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
+ * That means the active clock is in HI state.
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
+ * high between frames. That means the active clock is in LO state.
+ */
+#define SSP_CPOL_HI             SSP_CR0_CPOL_LO
+#define SSP_CPOL_LO             SSP_CR0_CPOL_HI
+
+/** SSP master mode enable */
+#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
+#define SSP_MASTER_MODE         SSP_CR1_MASTER_EN
+
+/**
+ * @brief   Clean all data in RX FIFO of SSP
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
+
+/**
+ * @brief   SSP Interrupt Read/Write with 8-bit frame width
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SSP Interrupt Read/Write with 16-bit frame width
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	SUCCESS or ERROR
+ */
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SSP Polling Read/Write in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	xf_setup		: Pointer to a SSP_DATA_SETUP_T structure that contains specified
+ *                          information about transmit/receive data	configuration
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. It starts with writing phase and after that,
+ * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
+ * through xf_setup param.
+ */
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
+
+/**
+ * @brief   SSP Polling Write in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: Buffer length
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. First, a writing operation will send
+ * the needed data. After that, a dummy reading operation is generated to clear data buffer
+ */
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   SSP Polling Read in blocking mode
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	buffer			: Buffer address
+ * @param	buffer_len		: The length of buffer
+ * @return	Actual data length has been transferred
+ * @note
+ * This function can be used in both master and slave mode. First, a dummy writing operation is generated
+ * to clear data buffer. After that, a reading operation will receive the needed data
+ */
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
+
+/**
+ * @brief   Initialize the SSP
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_SSP_Init(LPC_SSP_T *pSSP);
+
+/**
+ * @brief	Deinitialise the SSP
+ * @param	pSSP	: The base of SSP peripheral on the chip
+ * @return	Nothing
+ * @note	The SSP controller is disabled
+ */
+void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
+
+/**
+ * @brief   Set the SSP operating modes, master or slave
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	master			: 1 to set master, 0 to set slave
+ * @return	Nothing
+ */
+void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
+
+/**
+ * @brief   Set the clock frequency for SSP interface
+ * @param	pSSP			: The base SSP peripheral on the chip
+ * @param	bitRate		: The SSP bit rate
+ * @return	Nothing
+ */
+void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SSP_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/stopwatch.h b/hw/mcu/nxp/lpc_chip_40xx/inc/stopwatch.h
new file mode 100644
index 000000000..c298735fa
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/stopwatch.h
@@ -0,0 +1,137 @@
+/*
+ * @brief Common stopwatch support
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __STOPWATCH_H_
+#define __STOPWATCH_H_
+
+#include "cmsis.h"
+
+/** @defgroup Stop_Watch CHIP: Stopwatch primitives.
+ * @ingroup CHIP_Common
+ * @{
+ */
+
+/**
+ * @brief	Initialize stopwatch
+ * @return	Nothing
+ */
+void StopWatch_Init(void);
+
+/**
+ * @brief	Start a stopwatch
+ * @return	Current cycle count
+ */
+uint32_t StopWatch_Start(void);
+
+/**
+ * @brief      Returns number of ticks elapsed since stopwatch was started
+ * @param      startTime	: Time returned by StopWatch_Start().
+ * @return     Number of ticks elapsed since stopwatch was started
+ */
+STATIC INLINE uint32_t StopWatch_Elapsed(uint32_t startTime)
+{
+	return StopWatch_Start() - startTime;
+}
+
+/**
+ * @brief	Returns number of ticks per second of the stopwatch timer
+ * @return	Number of ticks per second of the stopwatch timer
+ */
+uint32_t StopWatch_TicksPerSecond(void);
+
+/**
+ * @brief	Converts from stopwatch ticks to mS.
+ * @param	ticks	: Duration in ticks to convert to mS.
+ * @return	Number of mS in given number of ticks
+ */
+uint32_t StopWatch_TicksToMs(uint32_t ticks);
+
+/**
+ * @brief	Converts from stopwatch ticks to uS.
+ * @param	ticks	: Duration in ticks to convert to uS.
+ * @return	Number of uS in given number of ticks
+ */
+uint32_t StopWatch_TicksToUs(uint32_t ticks);
+
+/**
+ * @brief	Converts from mS to stopwatch ticks.
+ * @param	mS	: Duration in mS to convert to ticks.
+ * @return	Number of ticks in given number of mS
+ */
+uint32_t StopWatch_MsToTicks(uint32_t mS);
+
+/**
+ * @brief	Converts from uS to stopwatch ticks.
+ * @param	uS	: Duration in uS to convert to ticks.
+ * @return	Number of ticks in given number of uS
+ */
+uint32_t StopWatch_UsToTicks(uint32_t uS);
+
+/**
+ * @brief	Delays the given number of ticks using stopwatch primitives
+ * @param	ticks	: Number of ticks to delay
+ * @return	Nothing
+ */
+STATIC INLINE void StopWatch_DelayTicks(uint32_t ticks)
+{
+	uint32_t startTime = StopWatch_Start();
+	while (StopWatch_Elapsed(startTime) < ticks) {}
+}
+
+/**
+ * @brief	Delays the given number of mS using stopwatch primitives
+ * @param	mS	: Number of mS to delay
+ * @return	Nothing
+ */
+STATIC INLINE void StopWatch_DelayMs(uint32_t mS)
+{
+	uint32_t ticks = StopWatch_MsToTicks(mS);
+	uint32_t startTime = StopWatch_Start();
+	while (StopWatch_Elapsed(startTime) < ticks) {}
+}
+
+/**
+ * @brief	Delays the given number of uS using stopwatch primitives
+ * @param	uS	: Number of uS to delay
+ * @return	Nothing
+ */
+STATIC INLINE void StopWatch_DelayUs(uint32_t uS)
+{
+	uint32_t ticks = StopWatch_UsToTicks(uS);
+	uint32_t startTime = StopWatch_Start();
+	while (StopWatch_Elapsed(startTime) < ticks) {}
+}
+
+/**
+ * @}
+ */
+
+#endif /* __STOPWATCH_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h b/hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h
new file mode 100644
index 000000000..bbfb9d7a7
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h
@@ -0,0 +1,42 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+/* Build for 407x/8x chip family */
+#define CHIP_LPC40XX
+
+/* For the LPC4074, the __FPU_PRESENT definition should be set to 0 */
+// #define __FPU_PRESENT 0
+
+/* Enable DMA in SDC driver */
+#define SDC_DMA_ENABLE
+
+#endif /* __SYS_CONFIG_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h
new file mode 100644
index 000000000..04b96de4e
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h
@@ -0,0 +1,360 @@
+/*
+ * @brief	LPC17xx/40xx System and Control driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef _SYSCTL_17XX_40XX_H_
+#define _SYSCTL_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup SYSCTL_17XX_40XX CHIP: LPC17xx/40xx System Control block driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief LPC17XX/40XX Clock and Power PLL register block structure
+ */
+typedef struct {
+	__IO uint32_t PLLCON;					/*!< (R/W)  PLL Control Register */
+	__IO uint32_t PLLCFG;					/*!< (R/W)  PLL Configuration Register */
+	__I  uint32_t PLLSTAT;					/*!< (R/ )  PLL Status Register */
+	__O  uint32_t PLLFEED;					/*!< ( /W)  PLL Feed Register */
+	uint32_t RESERVED1[4];
+} SYSCTL_PLL_REGS_T;
+
+/**
+ * Selectable PLLs
+ */
+typedef enum {
+	SYSCTL_MAIN_PLL,			/*!< Main PLL (PLL0) */
+	SYSCTL_USB_PLL,				/*!< USB PLL (PLL1) */
+} CHIP_SYSCTL_PLL_T;
+
+/**
+ * @brief LPC17XX/40XX Clock and Power register block structure
+ */
+typedef struct {
+	__IO uint32_t FLASHCFG;					/*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
+	uint32_t RESERVED0[15];
+	__IO uint32_t MEMMAP;					/*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
+	uint32_t RESERVED1[15];
+	SYSCTL_PLL_REGS_T PLL[SYSCTL_USB_PLL + 1];		/*!< Offset: 0x080: PLL0 and PLL1 */
+	__IO uint32_t PCON;						/*!< Offset: 0x0C0 (R/W)  Power Control Register */
+	__IO uint32_t PCONP;					/*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
+#if defined(CHIP_LPC175X_6X)
+	uint32_t RESERVED2[15];
+#elif defined(CHIP_LPC177X_8X)
+	uint32_t RESERVED2[14];
+	__IO uint32_t EMCCLKSEL;				/*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
+#else
+	__IO uint32_t PCONP1;					/*!< Offset: 0x0C8 (R/W)  Power Control 1 for Peripherals Register */
+	uint32_t RESERVED2[13];
+	__IO uint32_t EMCCLKSEL;				/*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
+#endif
+	__IO uint32_t CCLKSEL;					/*!< Offset: 0x104 (R/W)  CPU Clock Selection Register */
+	__IO uint32_t USBCLKSEL;				/*!< Offset: 0x108 (R/W)  USB Clock Selection Register */
+	__IO uint32_t CLKSRCSEL;				/*!< Offset: 0x10C (R/W)  Clock Source Select Register */
+	__IO uint32_t CANSLEEPCLR;				/*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
+	__IO uint32_t CANWAKEFLAGS;				/*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
+	uint32_t RESERVED3[10];
+	__IO uint32_t EXTINT;					/*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
+	uint32_t RESERVED4;
+	__IO uint32_t EXTMODE;					/*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
+	__IO uint32_t EXTPOLAR;					/*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
+	uint32_t RESERVED5[12];
+	__IO uint32_t RSID;						/*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
+#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC40XX)
+	uint32_t RESERVED6[7];
+#elif defined(CHIP_LPC177X_8X)
+	uint32_t RESERVED6;
+	uint32_t MATRIXARB;
+	uint32_t RESERVED6A[5];
+#endif
+	__IO uint32_t SCS;						/*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
+	__IO uint32_t RESERVED7;
+#if defined(CHIP_LPC175X_6X)
+	__IO uint32_t PCLKSEL[2];				/*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
+	uint32_t RESERVED8[4];
+#else
+	__IO uint32_t PCLKSEL;				/*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
+	uint32_t RESERVED9;
+	__IO uint32_t PBOOST;					/*!< Offset: 0x1B0 (R/W)  Power Boost control register */
+	__IO uint32_t SPIFICLKSEL;
+	__IO uint32_t LCD_CFG;					/*!< Offset: 0x1B8 (R/W)  LCD Configuration and clocking control Register */
+	uint32_t RESERVED10;
+#endif
+	__IO uint32_t USBIntSt;					/*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
+	__IO uint32_t DMAREQSEL;				/*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
+	__IO uint32_t CLKOUTCFG;				/*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
+#if defined(CHIP_LPC175X_6X)
+	uint32_t RESERVED11[6];
+#else
+	__IO uint32_t RSTCON[2];				/*!< Offset: 0x1CC (R/W)  RESET Control0/1 Registers */
+	uint32_t RESERVED11[2];
+	__IO uint32_t EMCDLYCTL;				/*!< Offset: 0x1DC (R/W) SDRAM programmable delays          */
+	__IO uint32_t EMCCAL;					/*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
+#endif
+} LPC_SYSCTL_T;
+
+/**
+ * @brief FLASH Access time definitions
+ */
+typedef enum {
+	FLASHTIM_20MHZ_CPU = 0,		/*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock */
+	FLASHTIM_40MHZ_CPU = 1,		/*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock */
+	FLASHTIM_60MHZ_CPU = 2,		/*!< Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock */
+	FLASHTIM_80MHZ_CPU = 3,		/*!< Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock */
+	FLASHTIM_100MHZ_CPU = 4,	/*!< Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock */
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	FLASHTIM_120MHZ_CPU = 3,	/*!< Flash accesses use 4 CPU clocks. Use for up to 120 MHz CPU clock with power boot on*/
+#else
+	FLASHTIM_120MHZ_CPU = 4,	/*!< Flash accesses use 5 CPU clocks. Use for up to 120 Mhz for LPC1759 and LPC1769 only.*/
+#endif
+	FLASHTIM_SAFE_SETTING = 5,	/*!< Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions */
+} FMC_FLASHTIM_T;
+
+/**
+ * @brief	Set FLASH memory access time in clocks
+ * @param	clks	: Clock cycles for FLASH access (minus 1)
+ * @return	Nothing
+ * @note	See the user manual for valid settings for this register for when
+ * power boot is enabled or off.
+ */
+STATIC INLINE void Chip_SYSCTL_SetFLASHAccess(FMC_FLASHTIM_T clks)
+{
+	uint32_t tmp = LPC_SYSCTL->FLASHCFG & 0xFFF;
+
+	/* Don't alter lower bits */
+	LPC_SYSCTL->FLASHCFG = tmp | (clks << 12);
+}
+
+/**
+ * System memory remap modes used to remap interrupt vectors
+ */
+typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
+	REMAP_BOOT_LOADER_MODE,	/*!< Interrupt vectors are re-mapped to Boot ROM */
+	REMAP_USER_FLASH_MODE	/*!< Interrupt vectors are not re-mapped and reside in Flash */
+} CHIP_SYSCTL_BOOT_MODE_REMAP_T;
+
+/**
+ * @brief	Re-map interrupt vectors
+ * @param	remap	: system memory map value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
+{
+	LPC_SYSCTL->MEMMAP = (uint32_t) remap;
+}
+
+/**
+ * System reset status
+ */
+#define SYSCTL_RST_POR    (1 << 0)	/*!< POR reset status */
+#define SYSCTL_RST_EXTRST (1 << 1)	/*!< External reset status */
+#define SYSCTL_RST_WDT    (1 << 2)	/*!< Watchdog reset status */
+#define SYSCTL_RST_BOD    (1 << 3)	/*!< Brown-out detect reset status */
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+#define SYSCTL_RST_SYSRST (1 << 4)	/*!< software system reset status */
+#define SYSCTL_RST_LOCKUP (1 << 5)	/*!< "lockup" reset status */
+#endif
+
+/**
+ * @brief	Get system reset status
+ * @return	An Or'ed value of SYSCTL_RST_*
+ * @note	This function returns the detected reset source(s).
+ */
+STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
+{
+	return LPC_SYSCTL->RSID;
+}
+
+/**
+ * @brief	Clear system reset status
+ * @param	reset	: An Or'ed value of SYSCTL_RST_* status to clear
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
+{
+	LPC_SYSCTL->RSID = reset;
+}
+
+/**
+ * @brief	Enable brown-out detection
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableBOD(void)
+{
+	LPC_SYSCTL->PCON |= (1 << 3);
+}
+
+/**
+ * @brief	Disable brown-out detection
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableBOD(void)
+{
+	LPC_SYSCTL->PCON &= ~(1 << 3);
+}
+
+/**
+ * @brief	Enable brown-out detection reset
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
+{
+	LPC_SYSCTL->PCON |= (1 << 4);
+}
+
+/**
+ * @brief	Disable brown-out detection reset
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
+{
+	LPC_SYSCTL->PCON &= ~(1 << 4);
+}
+
+/**
+ * @brief	Enable brown-out detection reduced power mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableBODRPM(void)
+{
+	LPC_SYSCTL->PCON |= (1 << 5);
+}
+
+/**
+ * @brief	Disable brown-out detection reduced power mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableBODRPM(void)
+{
+	LPC_SYSCTL->PCON &= ~(1 << 5);
+}
+
+#define SYSCTL_PD_SMFLAG (1 << 8)	/*!< Sleep Mode entry flag */
+#define SYSCTL_PD_DSFLAG (1 << 9)	/*!< Deep Sleep entry flag */
+#define SYSCTL_PD_PDFLAG (1 << 10)	/*!< Power-down entry flag */
+#define SYSCTL_PD_DPDFLAG (1 << 11)	/*!< Deep Power-down entry flag */
+
+/**
+ * @brief	Returns and clears the current sleep mode entry flags
+ * @param	flags:	One or more flags to clear, SYSCTL_PD_*
+ * @return	An Or'ed value of the sleep flags, SYSCTL_PD_*
+ * @note	These flags indicate the successful entry of one or more
+ * sleep modes.
+ */
+uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags);
+
+#if !defined(CHIP_LPC175X_6X)
+/**
+ * @brief	Enable power boost for clock operation over 100MHz
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_EnableBoost(void)
+{
+	LPC_SYSCTL->PBOOST = 0x3;
+}
+
+/**
+ * @brief	Disable power boost for clock operation under 100MHz
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_SYSCTL_DisableBoost(void)
+{
+	LPC_SYSCTL->PBOOST = 0x0;
+}
+
+#endif
+
+#if !defined(CHIP_LPC175X_6X)
+/**
+ * Peripheral reset numbers
+ * This is a list of peripherals that can be reset
+ */
+typedef enum {
+	SYSCTL_RESET_LCD,					/*!< LCD reset */
+	SYSCTL_RESET_TIMER0,			/*!< Timer 0 reset */
+	SYSCTL_RESET_TIMER1,			/*!< Timer 1 reset */
+	SYSCTL_RESET_UART0,				/*!< UART 0 reset */
+	SYSCTL_RESET_UART1,				/*!< UART 1 reset */
+	SYSCTL_RESET_PWM0,				/*!< PWM0 reset */
+	SYSCTL_RESET_PWM1,				/*!< PWM1 reset */
+	SYSCTL_RESET_I2C0,				/*!< I2C0 reset */
+	SYSCTL_RESET_UART4,				/*!< UART 4 reset */
+	SYSCTL_RESET_RTC,					/*!< RTC reset */
+	SYSCTL_RESET_SSP1,				/*!< SSP1 reset */
+	SYSCTL_RESET_EMC,					/*!< EMC reset */
+	SYSCTL_RESET_ADC,					/*!< ADC reset */
+	SYSCTL_RESET_CAN1,				/*!< CAN1 reset */
+	SYSCTL_RESET_CAN2,				/*!< CAN2 reset */
+	SYSCTL_RESET_GPIO,				/*!< GPIO reset */
+	SYSCTL_RESET_SPIFI,				/*!< SPIFI reset */
+	SYSCTL_RESET_MCPWM,				/*!< MCPWM reset */
+	SYSCTL_RESET_QEI,					/*!< QEI reset */
+	SYSCTL_RESET_I2C1,				/*!< I2C1 reset */
+	SYSCTL_RESET_SSP2,				/*!< SSP2 reset */
+	SYSCTL_RESET_SSP0,				/*!< SSP0 reset */
+	SYSCTL_RESET_TIMER2,			/*!< Timer 2 reset */
+	SYSCTL_RESET_TIMER3,			/*!< Timer 3 reset */
+	SYSCTL_RESET_UART2,				/*!< UART 2 reset */
+	SYSCTL_RESET_UART3,				/*!< UART 3 reset */
+	SYSCTL_RESET_I2C2,				/*!< I2C2 reset */
+	SYSCTL_RESET_I2S,					/*!< I2S reset */
+	SYSCTL_RESET_PCSDC,				/*!< SD Card interface reset */
+	SYSCTL_RESET_GPDMA,				/*!< GP DMA reset */
+	SYSCTL_RESET_ENET,				/*!< EMAC/Ethernet reset */
+	SYSCTL_RESET_USB,					/*!< USB reset */
+	SYSCTL_RESET_IOCON,				/*!< IOCON reset */
+	SYSCTL_RESET_DAC,					/*!< DAC reset */
+	SYSCTL_RESET_CANACC,			/*!< CAN acceptance filter reset */
+} CHIP_SYSCTL_RESET_T;
+
+/**
+ * @brief	Resets a peripheral
+ * @param	periph:	Peripheral to reset
+ * @return	Nothing
+ */
+void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph);
+
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSCTL_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/timer_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/timer_17xx_40xx.h
new file mode 100644
index 000000000..1278926bf
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/timer_17xx_40xx.h
@@ -0,0 +1,445 @@
+/*
+ * @brief LPC17xx/40xx 16/32-bit Timer/PWM driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __TIMER_17XX_40XX_H_
+#define __TIMER_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup TIMER_17XX_40XX CHIP: LPc17xx/40xx 16/32-bit Timer driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief 32-bit Standard timer register block structure
+ */
+typedef struct {					/*!< TIMERn Structure       */
+	__IO uint32_t IR;				/*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+	__IO uint32_t TCR;				/*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+	__IO uint32_t TC;				/*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+	__IO uint32_t PR;				/*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+	__IO uint32_t PC;				/*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+	__IO uint32_t MCR;				/*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+	__IO uint32_t MR[4];			/*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+	__IO uint32_t CCR;				/*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+	__IO uint32_t CR[4];			/*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
+	__IO uint32_t EMR;				/*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
+	__I  uint32_t RESERVED0[12];
+	__IO uint32_t CTCR;				/*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+} LPC_TIMER_T;
+
+/** Macro to clear interrupt pending */
+#define TIMER_IR_CLR(n)         _BIT(n)
+
+/** Macro for getting a timer match interrupt bit */
+#define TIMER_MATCH_INT(n)      (_BIT((n) & 0x0F))
+/** Macro for getting a capture event interrupt bit */
+#define TIMER_CAP_INT(n)        (_BIT((((n) & 0x0F) + 4)))
+
+/** Timer/counter enable bit */
+#define TIMER_ENABLE            ((uint32_t) (1 << 0))
+/** Timer/counter reset bit */
+#define TIMER_RESET             ((uint32_t) (1 << 1))
+
+/** Bit location for interrupt on MRx match, n = 0 to 3 */
+#define TIMER_INT_ON_MATCH(n)   (_BIT(((n) * 3)))
+/** Bit location for reset on MRx match, n = 0 to 3 */
+#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
+/** Bit location for stop on MRx match, n = 0 to 3 */
+#define TIMER_STOP_ON_MATCH(n)  (_BIT((((n) * 3) + 2)))
+
+/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
+#define TIMER_CAP_RISING(n)     (_BIT(((n) * 3)))
+/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
+#define TIMER_CAP_FALLING(n)    (_BIT((((n) * 3) + 1)))
+/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
+#define TIMER_INT_ON_CAP(n)     (_BIT((((n) * 3) + 2)))
+
+/**
+ * @brief	Initialize a timer
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
+
+/**
+ * @brief	Shutdown a timer
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
+
+/**
+ * @brief	Determine if a match interrupt is pending
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match interrupt number to check
+ * @return	false if the interrupt is not pending, otherwise true
+ * @note	Determine if the match interrupt for the passed timer and match
+ * counter is pending.
+ */
+STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
+}
+
+/**
+ * @brief	Determine if a capture interrupt is pending
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture interrupt number to check
+ * @return	false if the interrupt is not pending, otherwise true
+ * @note	Determine if the capture interrupt for the passed capture pin is
+ * pending.
+ */
+STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
+}
+
+/**
+ * @brief	Clears a (pending) match interrupt
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match interrupt number to clear
+ * @return	Nothing
+ * @note	Clears a pending timer match interrupt.
+ */
+STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->IR = TIMER_IR_CLR(matchnum);
+}
+
+/**
+ * @brief	Clears a (pending) capture interrupt
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture interrupt number to clear
+ * @return	Nothing
+ * @note	Clears a pending timer capture interrupt.
+ */
+STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->IR = (0x10 << capnum);
+}
+
+/**
+ * @brief	Enables the timer (starts count)
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ * @note	Enables the timer to start counting.
+ */
+STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
+{
+	pTMR->TCR |= TIMER_ENABLE;
+}
+
+/**
+ * @brief	Disables the timer (stops count)
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ * @note	Disables the timer to stop counting.
+ */
+STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
+{
+	pTMR->TCR &= ~TIMER_ENABLE;
+}
+
+/**
+ * @brief	Returns the current timer count
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Current timer terminal count value
+ * @note	Returns the current timer terminal count.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
+{
+	return pTMR->TC;
+}
+
+/**
+ * @brief	Returns the current prescale count
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Current timer prescale count value
+ * @note	Returns the current prescale count.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
+{
+	return pTMR->PC;
+}
+
+/**
+ * @brief	Sets the prescaler value
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	prescale	: Prescale value to set the prescale register to
+ * @return	Nothing
+ * @note	Sets the prescale count value.
+ */
+STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
+{
+	pTMR->PR = prescale;
+}
+
+/**
+ * @brief	Sets a timer match value
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer to set match count for
+ * @param	matchval	: Match value for the selected match count
+ * @return	Nothing
+ * @note	Sets one of the timer match values.
+ */
+STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
+{
+	pTMR->MR[matchnum] = matchval;
+}
+
+/**
+ * @brief	Reads a capture register
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture register to read
+ * @return	The selected capture register value
+ * @note	Returns the selected capture register value.
+ */
+STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	return pTMR->CR[capnum];
+}
+
+/**
+ * @brief	Resets the timer terminal and prescale counts to 0
+ * @param	pTMR	: Pointer to timer IP register address
+ * @return	Nothing
+ */
+void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
+
+/**
+ * @brief	Enables a match interrupt that fires when the terminal count
+ *			matches the match counter value.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Disables a match interrupt for a match counter.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	For the specific match counter, enables reset of the terminal count register when a match occurs
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	For the specific match counter, disables reset of the terminal count register when a match occurs
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Enable a match timer to stop the terminal count when a
+ *			match count equals the terminal count.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Disable stop on match for a match timer. Disables a match timer
+ *			to stop the terminal count when a match count equals the terminal count.
+ * @param	pTMR		: Pointer to timer IP register address
+ * @param	matchnum	: Match timer, 0 to 3
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
+{
+	pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
+}
+
+/**
+ * @brief	Enables capture on on rising edge of selected CAP signal for the
+ *			selected capture register, enables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a rising edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR |= TIMER_CAP_RISING(capnum);
+}
+
+/**
+ * @brief	Disables capture on on rising edge of selected CAP signal. For the
+ *			selected capture register, disables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a rising edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
+}
+
+/**
+ * @brief	Enables capture on on falling edge of selected CAP signal. For the
+ *			selected capture register, enables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a falling edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR |= TIMER_CAP_FALLING(capnum);
+}
+
+/**
+ * @brief	Disables capture on on falling edge of selected CAP signal. For the
+ *			selected capture register, disables the selected CAPn.capnum signal to load
+ *			the capture register with the terminal coount on a falling edge.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
+}
+
+/**
+ * @brief	Enables interrupt on capture of selected CAP signal. For the
+ *			selected capture register, an interrupt will be generated when the enabled
+ *			rising or falling edge on CAPn.capnum is detected.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
+}
+
+/**
+ * @brief	Disables interrupt on capture of selected CAP signal
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capnum	: Capture signal/register to use
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
+{
+	pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
+}
+
+/**
+ * @brief Standard timer initial match pin state and change state
+ */
+typedef enum IP_TIMER_PIN_MATCH_STATE {
+	TIMER_EXTMATCH_DO_NOTHING = 0,	/*!< Timer match state does nothing on match pin */
+	TIMER_EXTMATCH_CLEAR      = 1,	/*!< Timer match state sets match pin low */
+	TIMER_EXTMATCH_SET        = 2,	/*!< Timer match state sets match pin high */
+	TIMER_EXTMATCH_TOGGLE     = 3	/*!< Timer match state toggles match pin */
+} TIMER_PIN_MATCH_STATE_T;
+
+/**
+ * @brief	Sets external match control (MATn.matchnum) pin control. For the pin
+ *          selected with matchnum, sets the function of the pin that occurs on
+ *          a terminal count match for the match count.
+ * @param	pTMR			: Pointer to timer IP register address
+ * @param	initial_state	: Initial state of the pin, high(1) or low(0)
+ * @param	matchState		: Selects the match state for the pin
+ * @param	matchnum		: MATn.matchnum signal to use
+ * @return	Nothing
+ * @note	For the pin selected with matchnum, sets the function of the pin that occurs on
+ * a terminal count match for the match count.
+ */
+void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
+												 TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
+
+/**
+ * @brief Standard timer clock and edge for count source
+ */
+typedef enum IP_TIMER_CAP_SRC_STATE {
+	TIMER_CAPSRC_RISING_PCLK  = 0,	/*!< Timer ticks on PCLK rising edge */
+	TIMER_CAPSRC_RISING_CAPN  = 1,	/*!< Timer ticks on CAPn.x rising edge */
+	TIMER_CAPSRC_FALLING_CAPN = 2,	/*!< Timer ticks on CAPn.x falling edge */
+	TIMER_CAPSRC_BOTH_CAPN    = 3	/*!< Timer ticks on CAPn.x both edges */
+} TIMER_CAP_SRC_STATE_T;
+
+/**
+ * @brief	Sets timer count source and edge with the selected passed from CapSrc.
+ *          If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
+ * @param	pTMR	: Pointer to timer IP register address
+ * @param	capSrc	: timer clock source and edge
+ * @param	capnum	: CAPn.capnum pin to use (if used)
+ * @return	Nothing
+ * @note	If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
+ */
+STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
+													 TIMER_CAP_SRC_STATE_T capSrc,
+													 int8_t capnum)
+{
+	pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIMER_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h
new file mode 100644
index 000000000..f423b600c
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h
@@ -0,0 +1,814 @@
+/*
+ * @brief LPC17xx/40xx UART chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __UART_17XX_40XX_H_
+#define __UART_17XX_40XX_H_
+
+#include "ring_buffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup UART_17XX_40XX CHIP: LPC17xx/40xx UART driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief USART register block structure
+ */
+typedef struct {					/*!< USARTn Structure       */
+
+	union {
+		__IO uint32_t  DLL;			/*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+		__O  uint32_t  THR;			/*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
+		__I  uint32_t  RBR;			/*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
+	};
+
+	union {
+		__IO uint32_t IER;			/*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
+		__IO uint32_t DLM;			/*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
+	};
+
+	union {
+		__O  uint32_t FCR;			/*!< FIFO Control Register. Controls UART FIFO usage and modes. */
+		__I  uint32_t IIR;			/*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
+	};
+
+	__IO uint32_t LCR;				/*!< Line Control Register. Contains controls for frame formatting and break generation. */
+	__IO uint32_t MCR;				/*!< Modem Control Register. Only present on USART ports with full modem support. */
+	__I  uint32_t LSR;				/*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
+	__I  uint32_t MSR;				/*!< Modem Status Register. Only present on USART ports with full modem support. */
+	__IO uint32_t SCR;				/*!< Scratch Pad Register. Eight-bit temporary storage for software. */
+	__IO uint32_t ACR;				/*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
+	__IO uint32_t ICR;				/*!< IrDA control register (not all UARTS) */
+	__IO uint32_t FDR;				/*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
+	__IO uint32_t OSR;				/*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
+	__IO uint32_t TER1;				/*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+	uint32_t  RESERVED0[3];
+    __IO uint32_t HDEN;				/*!< Half-duplex enable Register- only on some UARTs */
+	__I  uint32_t RESERVED1[1];
+	__IO uint32_t SCICTRL;			/*!< Smart card interface control register- only on some UARTs */
+
+	__IO uint32_t RS485CTRL;		/*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+	__IO uint32_t RS485ADRMATCH;	/*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+	__IO uint32_t RS485DLY;			/*!< RS-485/EIA-485 direction control delay. */
+
+	union {
+		__IO uint32_t SYNCCTRL;		/*!< Synchronous mode control register. Only on USARTs. */
+		__I  uint32_t FIFOLVL;		/*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
+	};
+
+	__IO uint32_t TER2;				/*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
+} LPC_USART_T;
+
+
+/**
+ * @brief Macro defines for UART Receive Buffer register
+ */
+#define UART_RBR_MASKBIT    (0xFF)		        /*!< UART Received Buffer mask bit (8 bits) */
+
+/**
+ * @brief Macro defines for UART Divisor Latch LSB register
+ */
+#define UART_LOAD_DLL(div)  ((div) & 0xFF)		/*!< Macro for loading LSB of divisor */
+#define UART_DLL_MASKBIT    (0xFF)	            /*!< Divisor latch LSB bit mask */
+
+/**
+ * @brief Macro defines for UART Divisor Latch MSB register
+ */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)	/*!< Macro for loading MSB of divisors */
+#define UART_DLM_MASKBIT    (0xFF)		            /*!< Divisor latch MSB bit mask */
+
+/**
+ * @brief Macro defines for UART Interrupt Enable Register
+ */
+#define UART_IER_RBRINT      (1 << 0)	/*!< RBR Interrupt enable */
+#define UART_IER_THREINT     (1 << 1)	/*!< THR Interrupt enable */
+#define UART_IER_RLSINT      (1 << 2)	/*!< RX line status interrupt enable */
+#define UART_IER_MSINT       (1 << 3)	/*!< Modem status interrupt enable - valid for 11xx, 17xx/40xx UART1, 18xx/43xx UART1  only */
+#define UART_IER_CTSINT      (1 << 7)	/*!< CTS signal transition interrupt enable - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
+#define UART_IER_ABEOINT     (1 << 8)	/*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT     (1 << 9)	/*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK     (0x307)	/*!< UART interrupt enable register bit mask  - valid for 13xx, 17xx/40xx UART0/2/3, 18xx/43xx UART0/2/3 only*/
+#define UART1_IER_BITMASK    (0x30F)	/*!< UART1 interrupt enable register bit mask - valid for 11xx only */
+#define UART2_IER_BITMASK    (0x38F)	/*!< UART2 interrupt enable register bit mask - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
+
+/**
+ * @brief Macro defines for UART Interrupt Identification Register
+ */
+#define UART_IIR_INTSTAT_PEND   (1 << 0)	/*!< Interrupt pending status - Active low */
+#define UART_IIR_FIFO_EN        (3 << 6)	/*!< These bits are equivalent to FCR[0] */
+#define UART_IIR_ABEO_INT       (1 << 8)	/*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT       (1 << 9)	/*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK        (0x3CF)		/*!< UART interrupt identification register bit mask */
+
+/* Interrupt ID bit definitions */
+#define UART_IIR_INTID_MASK     (7 << 1)	/*!< Interrupt identification: Interrupt ID mask */
+#define UART_IIR_INTID_RLS      (3 << 1)	/*!< Interrupt identification: Receive line interrupt */
+#define UART_IIR_INTID_RDA      (2 << 1)	/*!< Interrupt identification: Receive data available interrupt */
+#define UART_IIR_INTID_CTI      (6 << 1)	/*!< Interrupt identification: Character time-out indicator interrupt */
+#define UART_IIR_INTID_THRE     (1 << 1)	/*!< Interrupt identification: THRE interrupt */
+#define UART_IIR_INTID_MODEM    (0 << 1)	/*!< Interrupt identification: Modem interrupt */
+
+/**
+ * @brief Macro defines for UART FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN        (1 << 0)	/*!< UART FIFO enable */
+#define UART_FCR_RX_RS          (1 << 1)	/*!< UART RX FIFO reset */
+#define UART_FCR_TX_RS          (1 << 2)	/*!< UART TX FIFO reset */
+#define UART_FCR_DMAMODE_SEL    (1 << 3)	/*!< UART DMA mode selection - valid for 17xx/40xx, 18xx/43xx only */
+#define UART_FCR_BITMASK        (0xCF)		/*!< UART FIFO control bit mask */
+
+#define UART_TX_FIFO_SIZE       (16)
+
+/* FIFO trigger level bit definitions */
+#define UART_FCR_TRG_LEV0       (0)			/*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1       (1 << 6)	/*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2       (2 << 6)	/*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3       (3 << 6)	/*!< UART FIFO trigger level 3: 14 character */
+
+/**
+ * @brief Macro defines for UART Line Control Register
+ */
+/* UART word length select bit definitions */
+#define UART_LCR_WLEN_MASK      (3 << 0)		/*!< UART word length select bit mask */
+#define UART_LCR_WLEN5          (0 << 0)		/*!< UART word length select: 5 bit data mode */
+#define UART_LCR_WLEN6          (1 << 0)		/*!< UART word length select: 6 bit data mode */
+#define UART_LCR_WLEN7          (2 << 0)		/*!< UART word length select: 7 bit data mode */
+#define UART_LCR_WLEN8          (3 << 0)		/*!< UART word length select: 8 bit data mode */
+
+/* UART Stop bit select bit definitions */
+#define UART_LCR_SBS_MASK       (1 << 2)		/*!< UART stop bit select: bit mask */
+#define UART_LCR_SBS_1BIT       (0 << 2)		/*!< UART stop bit select: 1 stop bit */
+#define UART_LCR_SBS_2BIT       (1 << 2)		/*!< UART stop bit select: 2 stop bits (in 5 bit data mode, 1.5 stop bits) */
+
+/* UART Parity enable bit definitions */
+#define UART_LCR_PARITY_EN      (1 << 3)		/*!< UART Parity Enable */
+#define UART_LCR_PARITY_DIS     (0 << 3)		/*!< UART Parity Disable */
+#define UART_LCR_PARITY_ODD     (0 << 4)		/*!< UART Parity select: Odd parity */
+#define UART_LCR_PARITY_EVEN    (1 << 4)		/*!< UART Parity select: Even parity */
+#define UART_LCR_PARITY_F_1     (2 << 4)		/*!< UART Parity select: Forced 1 stick parity */
+#define UART_LCR_PARITY_F_0     (3 << 4)		/*!< UART Parity select: Forced 0 stick parity */
+#define UART_LCR_BREAK_EN       (1 << 6)		/*!< UART Break transmission enable */
+#define UART_LCR_DLAB_EN        (1 << 7)		/*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK        (0xFF)			/*!< UART line control bit mask */
+
+/**
+ * @brief Macro defines for UART Modem Control Register
+ */
+#define UART_MCR_DTR_CTRL       (1 << 0)		/*!< Source for modem output pin DTR */
+#define UART_MCR_RTS_CTRL       (1 << 1)		/*!< Source for modem output pin RTS */
+#define UART_MCR_LOOPB_EN       (1 << 4)		/*!< Loop back mode select */
+#define UART_MCR_AUTO_RTS_EN    (1 << 6)		/*!< Enable Auto RTS flow-control */
+#define UART_MCR_AUTO_CTS_EN    (1 << 7)		/*!< Enable Auto CTS flow-control */
+#define UART_MCR_BITMASK        (0xD3)			/*!< UART bit mask value */
+
+/**
+ * @brief Macro defines for UART Line Status Register
+ */
+#define UART_LSR_RDR        (1 << 0)	/*!< Line status: Receive data ready */
+#define UART_LSR_OE         (1 << 1)	/*!< Line status: Overrun error */
+#define UART_LSR_PE         (1 << 2)	/*!< Line status: Parity error */
+#define UART_LSR_FE         (1 << 3)	/*!< Line status: Framing error */
+#define UART_LSR_BI         (1 << 4)	/*!< Line status: Break interrupt */
+#define UART_LSR_THRE       (1 << 5)	/*!< Line status: Transmit holding register empty */
+#define UART_LSR_TEMT       (1 << 6)	/*!< Line status: Transmitter empty */
+#define UART_LSR_RXFE       (1 << 7)	/*!< Line status: Error in RX FIFO */
+#define UART_LSR_TXFE       (1 << 8)	/*!< Line status: Error in RX FIFO */
+#define UART_LSR_BITMASK    (0xFF)		/*!< UART Line status bit mask */
+#define UART1_LSR_BITMASK   (0x1FF)		/*!< UART1 Line status bit mask - valid for 11xx, 18xx/43xx UART0/2/3 only */
+
+/**
+ * @brief Macro defines for UART Modem Status Register
+ */
+#define UART_MSR_DELTA_CTS      (1 << 0)	/*!< Modem status: State change of input CTS */
+#define UART_MSR_DELTA_DSR      (1 << 1)	/*!< Modem status: State change of input DSR */
+#define UART_MSR_LO2HI_RI       (1 << 2)	/*!< Modem status: Low to high transition of input RI */
+#define UART_MSR_DELTA_DCD      (1 << 3)	/*!< Modem status: State change of input DCD */
+#define UART_MSR_CTS            (1 << 4)	/*!< Modem status: Clear To Send State */
+#define UART_MSR_DSR            (1 << 5)	/*!< Modem status: Data Set Ready State */
+#define UART_MSR_RI             (1 << 6)	/*!< Modem status: Ring Indicator State */
+#define UART_MSR_DCD            (1 << 7)	/*!< Modem status: Data Carrier Detect State */
+#define UART_MSR_BITMASK        (0xFF)		/*!< Modem status: MSR register bit-mask value */
+
+/**
+ * @brief Macro defines for UART Auto baudrate control register
+ */
+#define UART_ACR_START              (1 << 0)	/*!< UART Auto-baud start */
+#define UART_ACR_MODE               (1 << 1)	/*!< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART       (1 << 2)	/*!< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR        (1 << 8)	/*!< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR        (1 << 9)	/*!< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK            (0x307)		/*!< UART Auto Baudrate register bit mask */
+
+/**
+ * Autobaud modes
+ */
+#define UART_ACR_MODE0              (0)	/*!< Auto baudrate Mode 0 */
+#define UART_ACR_MODE1              (1)	/*!< Auto baudrate Mode 1 */
+
+/**
+ * @brief Macro defines for UART RS485 Control register
+ */
+#define UART_RS485CTRL_NMM_EN       (1 << 0)	/*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
+#define UART_RS485CTRL_RX_DIS       (1 << 1)	/*!< The receiver is disabled */
+#define UART_RS485CTRL_AADEN        (1 << 2)	/*!< Auto Address Detect (AAD) is enabled */
+#define UART_RS485CTRL_SEL_DTR      (1 << 3)	/*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
+												        used for direction control */
+#define UART_RS485CTRL_DCTRL_EN     (1 << 4)	/*!< Enable Auto Direction Control */
+#define UART_RS485CTRL_OINV_1       (1 << 5)	/*!< This bit reverses the polarity of the direction
+												       control signal on the RTS (or DTR) pin. The direction control pin
+												       will be driven to logic "1" when the transmitter has data to be sent */
+#define UART_RS485CTRL_BITMASK      (0x3F)		/*!< RS485 control bit-mask value */
+
+/**
+ * @brief Macro defines for UART IrDA Control Register - valid for 11xx, 17xx/40xx UART0/2/3, 18xx/43xx UART3 only
+ */
+#define UART_ICR_IRDAEN         (1 << 0)			/*!< IrDA mode enable */
+#define UART_ICR_IRDAINV        (1 << 1)			/*!< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN    (1 << 2)			/*!< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n)    ((n & 0x07) << 3)	/*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK        (0x3F)				/*!< UART IRDA bit mask */
+
+/**
+ * @brief Macro defines for UART half duplex register - ????
+ */
+#define UART_HDEN_HDEN          ((1 << 0))			/*!< enable half-duplex mode*/
+
+/**
+ * @brief Macro defines for UART Smart card interface Control Register - valid for 11xx, 18xx/43xx UART0/2/3 only
+ */
+#define UART_SCICTRL_SCIEN        (1 << 0)			/*!< enable asynchronous half-duplex smart card interface*/
+#define UART_SCICTRL_NACKDIS      (1 << 1)			/*!< NACK response is inhibited*/
+#define UART_SCICTRL_PROTSEL_T1   (1 << 2)			/*!< ISO7816-3 protocol T1 is selected*/
+#define UART_SCICTRL_TXRETRY(n)   ((n & 0x07) << 5)	/*!< number of retransmission*/
+#define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8)	/*!< Extra guard time*/
+
+/**
+ * @brief Macro defines for UART Fractional Divider Register
+ */
+#define UART_FDR_DIVADDVAL(n)   (n & 0x0F)			/*!< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n)      ((n << 4) & 0xF0)	/*!< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK        (0xFF)				/*!< UART Fractional Divider register bit mask */
+
+/**
+ * @brief Macro defines for UART Tx Enable Register
+ */
+#define UART_TER1_TXEN      (1 << 7)		/*!< Transmit enable bit  - valid for 11xx, 13xx, 17xx/40xx only */
+#define UART_TER2_TXEN      (1 << 0)		/*!< Transmit enable bit  - valid for 18xx/43xx only */
+
+/**
+ * @brief Macro defines for UART Synchronous Control Register - 11xx, 18xx/43xx UART0/2/3 only 
+ */
+#define UART_SYNCCTRL_SYNC             (1 << 0)			/*!< enable synchronous mode*/
+#define UART_SYNCCTRL_CSRC_MASTER      (1 << 1)  		/*!< synchronous master mode*/
+#define UART_SYNCCTRL_FES              (1 << 2)			/*!< sample on falling edge*/
+#define UART_SYNCCTRL_TSBYPASS         (1 << 3)			/*!< to be defined*/
+#define UART_SYNCCTRL_CSCEN            (1 << 4)			/*!< Continuous running clock enable (master mode only)*/
+#define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5)	        /*!< Do not send start/stop bit*/
+#define UART_SYNCCTRL_CCCLR            (1 << 6)			/*!< stop continuous clock*/
+
+/**
+ * @brief	Transmit a single data byte through the UART peripheral
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	data	: Byte to transmit
+ * @return	Nothing
+ * @note	This function attempts to place a byte into the UART transmit
+ *			FIFO or transmit hold register regard regardless of UART state
+ */
+STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
+{
+	pUART->THR = (uint32_t) data;
+}
+
+/**
+ * @brief	Read a single byte data from the UART peripheral
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	A single byte of data read
+ * @note	This function reads a byte from the UART receive FIFO or
+ *			receive hold register regard regardless of UART state. The
+ *			FIFO status should be read first prior to using this function
+ */
+STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
+}
+
+/**
+ * @brief	Enable UART interrupts
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	intMask	: OR'ed Interrupts to enable in the Interrupt Enable Register (IER)
+ * @return	Nothing
+ * @note	Use an OR'ed value of UART_IER_* definitions with this function
+ *			to enable specific UART interrupts. The Divisor Latch Access Bit
+ *			(DLAB) in LCR must be cleared in order to access the IER register.
+ *			This function doesn't alter the DLAB state
+ */
+STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask)
+{
+	pUART->IER |= intMask;
+}
+
+/**
+ * @brief	Disable UART interrupts
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	intMask	: OR'ed Interrupts to disable in the Interrupt Enable Register (IER)
+ * @return	Nothing
+ * @note	Use an OR'ed value of UART_IER_* definitions with this function
+ *			to disable specific UART interrupts. The Divisor Latch Access Bit
+ *			(DLAB) in LCR must be cleared in order to access the IER register.
+ *			This function doesn't alter the DLAB state
+ */
+STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask)
+{
+	pUART->IER &= ~intMask;
+}
+
+/**
+ * @brief	Returns UART interrupts that are enabled
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Returns the enabled UART interrupts
+ * @note	Use an OR'ed value of UART_IER_* definitions with this function
+ *			to determine which interrupts are enabled. You can check
+ *			for multiple enabled bits if needed.
+ */
+STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART)
+{
+	return pUART->IER;
+}
+
+/**
+ * @brief	Read the Interrupt Identification Register (IIR)
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Current pending interrupt status per the IIR register
+ */
+STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART)
+{
+	return pUART->IIR;
+}
+
+/**
+ * @brief	Setup the UART FIFOs
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	fcr		: FIFO control register setup OR'ed flags
+ * @return	Nothing
+ * @note	Use OR'ed value of UART_FCR_* definitions with this function
+ *			to select specific options. For example, to enable the FIFOs
+ *			with a RX trip level of 8 characters, use something like
+ *			(UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2)
+ */
+STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr)
+{
+	pUART->FCR = fcr;
+}
+
+/**
+ * @brief	Configure data width, parity and stop bits
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @param	config	: UART configuration, OR'ed values of UART_LCR_* defines
+ * @return	Nothing
+ * @note	Select OR'ed config options for the UART from the UART_LCR_*
+ *			definitions. For example, a configuration of 8 data bits, 1
+ *			stop bit, and even (enabled) parity would be
+ *			(UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_EN | UART_LCR_PARITY_EVEN)
+ */
+STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config)
+{
+	pUART->LCR = config;
+}
+
+/**
+ * @brief	Enable access to Divisor Latches
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART)
+{
+	pUART->LCR |= UART_LCR_DLAB_EN;
+}
+
+/**
+ * @brief	Disable access to Divisor Latches
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART)
+{
+	pUART->LCR &= ~UART_LCR_DLAB_EN;
+}
+
+/**
+ * @brief	Set LSB and MSB divisor latch registers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	dll		: Divisor Latch LSB value
+ * @param	dlm		: Divisor Latch MSB value
+ * @return	Nothing
+ * @note	The Divisor Latch Access Bit (DLAB) in LCR must be set in
+ *			order to access the USART Divisor Latches. This function
+ *			doesn't alter the DLAB state.
+ */
+STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm)
+{
+	pUART->DLL = (uint32_t) dll;
+	pUART->DLM = (uint32_t) dlm;
+}
+
+
+/**
+ * @brief	Return modem control register/status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Modem control register (status)
+ * @note	Mask bits of the returned status value with UART_MCR_*
+ *			definitions for specific statuses.
+ */
+STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART)
+{
+	return pUART->MCR;
+}
+
+/**
+ * @brief	Set modem control register/status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	mcr		: Modem control register flags to set
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_MCR_* definitions with this
+ *			call to set specific options.
+ */
+STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr)
+{
+	pUART->MCR |= mcr;
+}
+
+/**
+ * @brief	Clear modem control register/status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	mcr		: Modem control register flags to clear
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_MCR_* definitions with this
+ *			call to clear specific options.
+ */
+STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr)
+{
+	pUART->MCR &= ~mcr;
+}
+
+/**
+ * @brief	Return Line Status register/status (LSR)
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Line Status register (status)
+ * @note	Mask bits of the returned status value with UART_LSR_*
+ *			definitions for specific statuses.
+ */
+STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART)
+{
+	return pUART->LSR;
+}
+
+/**
+ * @brief	Return Modem Status register/status (MSR)
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Modem Status register (status)
+ * @note	Mask bits of the returned status value with UART_MSR_*
+ *			definitions for specific statuses.
+ */
+STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART)
+{
+	return pUART->MSR;
+}
+
+/**
+ * @brief	Write a byte to the scratchpad register
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	data	: Byte value to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data)
+{
+	pUART->SCR = (uint32_t) data;
+}
+
+/**
+ * @brief	Returns current byte value in the scratchpad register
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Byte value read from scratchpad register
+ */
+STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->SCR & 0xFF);
+}
+
+/**
+ * @brief	Set autobaud register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	acr		: Or'ed values to set for ACR register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_ACR_* definitions with this
+ *			call to set specific options.
+ */
+STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
+{
+	pUART->ACR |= acr;
+}
+
+/**
+ * @brief	Clear autobaud register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	acr		: Or'ed values to clear for ACR register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_ACR_* definitions with this
+ *			call to clear specific options.
+ */
+STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
+{
+	pUART->ACR &= ~acr;
+}
+
+/**
+ * @brief	Set RS485 control register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	ctrl	: Or'ed values to set for RS485 control register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_RS485CTRL_* definitions with this
+ *			call to set specific options.
+ */
+STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
+{
+	pUART->RS485CTRL |= ctrl;
+}
+
+/**
+ * @brief	Clear RS485 control register options
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	ctrl	: Or'ed values to clear for RS485 control register
+ * @return	Nothing
+ * @note	Use an Or'ed value of UART_RS485CTRL_* definitions with this
+ *			call to clear specific options.
+ */
+STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
+{
+	pUART->RS485CTRL &= ~ctrl;
+}
+
+/**
+ * @brief	Set RS485 address match value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	addr	: Address match value for RS-485/EIA-485 mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr)
+{
+	pUART->RS485ADRMATCH = (uint32_t) addr;
+}
+
+/**
+ * @brief	Read RS485 address match value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	Address match value for RS-485/EIA-485 mode
+ */
+STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
+}
+
+/**
+ * @brief	Set RS485 direction control (RTS or DTR) delay value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	dly		: direction control (RTS or DTR) delay value
+ * @return	Nothing
+ * @note	This delay time is in periods of the baud clock. Any delay
+ *			time from 0 to 255 bit times may be programmed.
+ */
+STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly)
+{
+	pUART->RS485DLY = (uint32_t) dly;
+}
+
+/**
+ * @brief	Read RS485 direction control (RTS or DTR) delay value
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	direction control (RTS or DTR) delay value
+ * @note	This delay time is in periods of the baud clock. Any delay
+ *			time from 0 to 255 bit times may be programmed.
+ */
+STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART)
+{
+	return (uint8_t) (pUART->RS485DLY & 0xFF);
+}
+
+/**
+ * @brief	Initializes the pUART peripheral
+ * @param	pUART		: Pointer to selected pUART peripheral
+ * @return	Nothing
+ */
+void Chip_UART_Init(LPC_USART_T *pUART);
+
+/**
+ * @brief	De-initializes the pUART peripheral.
+ * @param	pUART		: Pointer to selected pUART peripheral
+ * @return	Nothing
+ */
+void Chip_UART_DeInit(LPC_USART_T *pUART);
+
+/**
+ * @brief	Enable transmission on UART TxD pin
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @return Nothing
+ */
+void Chip_UART_TXEnable(LPC_USART_T *pUART);
+
+/**
+ * @brief	Disable transmission on UART TxD pin
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @return Nothing
+ */
+void Chip_UART_TXDisable(LPC_USART_T *pUART);
+
+/**
+ * @brief	Check whether if UART is busy or not
+ * @param	pUART	: Pointer to selected pUART peripheral
+ * @return	RESET if UART is not busy, otherwise return SET
+ */
+FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART);
+
+/**
+ * @brief	Transmit a byte array through the UART peripheral (non-blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to bytes to transmit
+ * @param	numBytes	: Number of bytes to transmit
+ * @return	The actual number of bytes placed into the FIFO
+ * @note	This function places data into the transmit FIFO until either
+ *			all the data is in the FIFO or the FIFO is full. This function
+ *			will not block in the FIFO is full. The actual number of bytes
+ *			placed into the FIFO is returned. This function ignores errors.
+ */
+int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes);
+
+/**
+ * @brief	Read data through the UART peripheral (non-blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to bytes array to fill
+ * @param	numBytes	: Size of the passed data array
+ * @return	The actual number of bytes read
+ * @note	This function reads data from the receive FIFO until either
+ *			all the data has been read or the passed buffer is completely full.
+ *			This function will not block. This function ignores errors.
+ */
+int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes);
+
+/**
+ * @brief	Sets best dividers to get a target bit rate (without fractional divider)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	baudrate	: Target baud rate (baud rate = bit rate)
+ * @return	The actual baud rate, or 0 if no rate can be found
+ */
+uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
+
+/**
+ * @brief	Sets best dividers to get a target bit rate (with fractional divider)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	baudrate	: Target baud rate (baud rate = bit rate)
+ * @return	The actual baud rate, or 0 if no rate can be found
+ */
+uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate);
+
+/**
+ * @brief	Transmit a byte array through the UART peripheral (blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to data to transmit
+ * @param	numBytes	: Number of bytes to transmit
+ * @return	The number of bytes transmitted
+ * @note	This function will send or place all bytes into the transmit
+ *			FIFO. This function will block until the last bytes are in the FIFO.
+ */
+int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes);
+
+/**
+ * @brief	Read data through the UART peripheral (blocking)
+ * @param	pUART		: Pointer to selected UART peripheral
+ * @param	data		: Pointer to data array to fill
+ * @param	numBytes	: Size of the passed data array
+ * @return	The size of the dat array
+ * @note	This function reads data from the receive FIFO until the passed
+ *			buffer is completely full. The function will block until full.
+ *			This function ignores errors.
+ */
+int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes);
+
+/**
+ * @brief	UART receive-only interrupt handler for ring buffers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @return	Nothing
+ * @note	If ring buffer support is desired for the receive side
+ *			of data transfer, the UART interrupt should call this
+ *			function for a receive based interrupt status.
+ */
+void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
+
+/**
+ * @brief	UART transmit-only interrupt handler for ring buffers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @return	Nothing
+ * @note	If ring buffer support is desired for the transmit side
+ *			of data transfer, the UART interrupt should call this
+ *			function for a transmit based interrupt status.
+ */
+void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
+
+/**
+ * @brief	Populate a transmit ring buffer and start UART transmit
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @param	data	: Pointer to buffer to move to ring buffer
+ * @param	bytes	: Number of bytes to move
+ * @return	The number of bytes placed into the ring buffer
+ * @note	Will move the data into the TX ring buffer and start the
+ *			transfer. If the number of bytes returned is less than the
+ *			number of bytes to send, the ring buffer is considered full.
+ */
+uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes);
+
+/**
+ * @brief	Copy data from a receive ring buffer
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRB		: Pointer to ring buffer structure to use
+ * @param	data	: Pointer to buffer to fill from ring buffer
+ * @param	bytes	: Size of the passed buffer in bytes
+ * @return	The number of bytes placed into the ring buffer
+ * @note	Will move the data from the RX ring buffer up to the
+ *			the maximum passed buffer size. Returns 0 if there is
+ *			no data in the ring buffer.
+ */
+int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes);
+
+/**
+ * @brief	UART receive/transmit interrupt handler for ring buffers
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @param	pRXRB	: Pointer to transmit ring buffer
+ * @param	pTXRB	: Pointer to receive ring buffer
+ * @return	Nothing
+ * @note	This provides a basic implementation of the UART IRQ
+ *			handler for support of a ring buffer implementation for
+ *			transmit and receive.
+ */
+void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB);
+
+/**
+ * @brief	Returns the Auto Baud status
+ * @param	pUART	: Pointer to selected UART peripheral
+ * @return	RESET if autobaud not completed, SET if autobaud completed
+ */
+FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART);
+
+/**
+ * @brief	Start/stop autobaud operation
+ * @param	pUART	    : Pointer to selected UART peripheral
+ * @param	mode	    : Autobaud mode (UART_ACR_MODE0 or UART_ACR_MODE1)
+ * @param	autorestart	: Enable autorestart (true to enable or false to disable)
+ * @param	NewState	: ENABLE to start autobaud operation, DISABLE to 
+ *                          stop autobaud operation
+ * @return	Nothing
+ */
+void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart, 
+        FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h
new file mode 100644
index 000000000..d510a3aef
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h
@@ -0,0 +1,160 @@
+/*
+ * @brief LPC17xx/40xx USB driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __USB_17XX_40XX_H_
+#define __USB_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup USB_17XX_40XX CHIP: LPC17xx/40xx USB Device, Host, & OTG driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief USB register block structure
+ */
+typedef struct {
+	__I  uint32_t Revision;				/* USB Host Registers                 */
+	__IO uint32_t Control;
+	__IO uint32_t CommandStatus;
+	__IO uint32_t InterruptStatus;
+	__IO uint32_t InterruptEnable;
+	__IO uint32_t InterruptDisable;
+	__IO uint32_t HCCA;
+	__I  uint32_t PeriodCurrentED;
+	__IO uint32_t ControlHeadED;
+	__IO uint32_t ControlCurrentED;
+	__IO uint32_t BulkHeadED;
+	__IO uint32_t BulkCurrentED;
+	__I  uint32_t DoneHead;
+	__IO uint32_t FmInterval;
+	__I  uint32_t FmRemaining;
+	__I  uint32_t FmNumber;
+	__IO uint32_t PeriodicStart;
+	__IO uint32_t LSTreshold;
+	__IO uint32_t RhDescriptorA;
+	__IO uint32_t RhDescriptorB;
+	__IO uint32_t RhStatus;
+	__IO uint32_t RhPortStatus1;
+	__IO uint32_t RhPortStatus2;
+	uint32_t RESERVED0[40];
+	__I  uint32_t Module_ID;
+
+	__I  uint32_t IntSt;			/* USB On-The-Go Registers            */
+	__IO uint32_t IntEn;
+	__O  uint32_t IntSet;
+	__O  uint32_t IntClr;
+	__IO uint32_t StCtrl;
+	__IO uint32_t Tmr;
+	uint32_t RESERVED1[58];
+
+	__I  uint32_t DevIntSt;			/* USB Device Interrupt Registers     */
+	__IO uint32_t DevIntEn;
+	__O  uint32_t DevIntClr;
+	__O  uint32_t DevIntSet;
+
+	__O  uint32_t CmdCode;			/* USB Device SIE Command Registers   */
+	__I  uint32_t CmdData;
+
+	__I  uint32_t RxData;			/* USB Device Transfer Registers      */
+	__O  uint32_t TxData;
+	__I  uint32_t RxPLen;
+	__O  uint32_t TxPLen;
+	__IO uint32_t Ctrl;
+	__O  uint32_t DevIntPri;
+
+	__I  uint32_t EpIntSt;			/* USB Device Endpoint Interrupt Regs */
+	__IO uint32_t EpIntEn;
+	__O  uint32_t EpIntClr;
+	__O  uint32_t EpIntSet;
+	__O  uint32_t EpIntPri;
+
+	__IO uint32_t ReEp;				/* USB Device Endpoint Realization Reg*/
+	__O  uint32_t EpInd;
+	__IO uint32_t MaxPSize;
+
+	__I  uint32_t DMARSt;			/* USB Device DMA Registers           */
+	__O  uint32_t DMARClr;
+	__O  uint32_t DMARSet;
+	uint32_t RESERVED2[9];
+	__IO uint32_t UDCAH;
+	__I  uint32_t EpDMASt;
+	__O  uint32_t EpDMAEn;
+	__O  uint32_t EpDMADis;
+	__I  uint32_t DMAIntSt;
+	__IO uint32_t DMAIntEn;
+	uint32_t RESERVED3[2];
+	__I  uint32_t EoTIntSt;
+	__O  uint32_t EoTIntClr;
+	__O  uint32_t EoTIntSet;
+	__I  uint32_t NDDRIntSt;
+	__O  uint32_t NDDRIntClr;
+	__O  uint32_t NDDRIntSet;
+	__I  uint32_t SysErrIntSt;
+	__O  uint32_t SysErrIntClr;
+	__O  uint32_t SysErrIntSet;
+	uint32_t RESERVED4[15];
+
+	union {
+		__I  uint32_t I2C_RX;			/* USB OTG I2C Registers              */
+		__O  uint32_t I2C_TX;
+	};
+
+	__IO  uint32_t I2C_STS;
+	__IO uint32_t I2C_CTL;
+	__IO uint32_t I2C_CLKHI;
+	__O  uint32_t I2C_CLKLO;
+	uint32_t RESERVED5[824];
+
+	union {
+		__IO uint32_t USBClkCtrl;		/* USB Clock Control Registers        */
+		__IO uint32_t OTGClkCtrl;
+	};
+
+	union {
+		__I  uint32_t USBClkSt;
+		__I  uint32_t OTGClkSt;
+	};
+
+} LPC_USB_T;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_17Xx_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/inc/wwdt_17xx_40xx.h b/hw/mcu/nxp/lpc_chip_40xx/inc/wwdt_17xx_40xx.h
new file mode 100644
index 000000000..b314c9e5d
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/inc/wwdt_17xx_40xx.h
@@ -0,0 +1,276 @@
+/*
+ * @brief LPC17xx/40xx WWDT driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __WWDT_17XX_40XX_H_
+#define __WWDT_17XX_40XX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup WWDT_17XX_40XX CHIP: LPC17xx/40xx Windowed Watchdog driver
+ * @ingroup CHIP_17XX_40XX_Drivers
+ * @{
+ */
+
+#if !defined(CHIP_LPC175X_6X)
+#define WATCHDOG_WINDOW_SUPPORT
+#endif
+
+#if defined(CHIP_LPC175X_6X)
+#define WATCHDOG_CLKSEL_SUPPORT
+#endif
+
+/** WDT oscillator frequency value */
+#define WDT_OSC     (500000 / 4)		/*!< Dedicated oscillator that provides a 500 kHz clock to Watchdog timer*/
+
+/**
+ * @brief Windowed Watchdog register block structure
+ */
+typedef struct {				/*!< WWDT Structure         */
+	__IO uint32_t  MOD;			/*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+	__IO uint32_t  TC;			/*!< Watchdog timer constant register. This register determines the time-out value. */
+	__O  uint32_t  FEED;		/*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+	__I  uint32_t  TV;			/*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
+#ifdef WATCHDOG_CLKSEL_SUPPORT
+	__IO uint32_t CLKSEL;		/*!< Watchdog clock select register. */
+#else
+	__I  uint32_t  RESERVED0;
+#endif
+#ifdef WATCHDOG_WINDOW_SUPPORT
+	__IO uint32_t  WARNINT;		/*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
+	__IO uint32_t  WINDOW;		/*!< Watchdog timer window register. This register contains the Watchdog window value. */
+#endif
+} LPC_WWDT_T;
+
+/**
+ * @brief Watchdog Mode register definitions
+ */
+/** Watchdog Mode Bitmask */
+#define WWDT_WDMOD_BITMASK          ((uint32_t) 0x1F)
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDEN             ((uint32_t) (1 << 0))
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDRESET          ((uint32_t) (1 << 1))
+/** WWDT time out flag bit */
+#define WWDT_WDMOD_WDTOF            ((uint32_t) (1 << 2))
+/** WDT Time Out flag bit */
+#define WWDT_WDMOD_WDINT            ((uint32_t) (1 << 3))
+#if !defined(CHIP_LPC175X_6X)
+/** WWDT Protect flag bit */
+#define WWDT_WDMOD_WDPROTECT        ((uint32_t) (1 << 4))
+#endif
+
+/**
+ * @brief	Initialize the Watchdog timer
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ */
+void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
+
+/**
+ * @brief	Shutdown the Watchdog timer
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT) {}
+
+/**
+ * @brief	Set WDT timeout constant value used for feed
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	none
+ */
+STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)
+{
+	pWWDT->TC = timeout;
+}
+
+/**
+ * @brief	Feed watchdog timer
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ * @note	If this function isn't called, a watchdog timer warning will occur.
+ * After the warning, a timeout will occur if a feed has happened.
+ */
+STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)
+{
+	pWWDT->FEED = 0xAA;
+	pWWDT->FEED = 0x55;
+}
+
+#if defined(WATCHDOG_WINDOW_SUPPORT)
+/**
+ * @brief	Set WWDT warning interrupt
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	timeout	: WDT warning in ticks, between 0 and 1023
+ * @return	None
+ * @note	This is the number of ticks after the watchdog interrupt that the
+ * warning interrupt will be generated.
+ */
+STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)
+{
+	pWWDT->WARNINT = timeout;
+}
+
+/**
+ * @brief	Set WWDT window time
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	timeout	: WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
+ * @return	None
+ * @note	The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
+ * function and this function, with this function defining the last tick before the
+ * watchdog window interrupt occurs.
+ */
+STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)
+{
+	pWWDT->WINDOW = timeout;
+}
+
+#endif
+
+/**
+ * @brief	Enable watchdog timer options
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	options	: An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * @note	You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
+ * are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot
+ * be unset.
+ */
+STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)
+{
+	pWWDT->MOD |= options;
+}
+
+/**
+ * @brief	Disable/clear watchdog timer options
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	options	: An or'ed set of options of values
+ *						WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
+ * @return	None
+ * @note	You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
+ * WWDT_WDMOD_WDTOF).
+ */
+STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)
+{
+	pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;
+}
+
+/**
+ * @brief	Enable WWDT activity
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	None
+ */
+STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)
+{
+	Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);
+	Chip_WWDT_Feed(pWWDT);
+}
+
+/**
+ * @brief	Read WWDT status flag
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	Watchdog status, an Or'ed value of WWDT_WDMOD_*
+ */
+STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)
+{
+	return pWWDT->MOD;
+}
+
+/**
+ * @brief	Clear WWDT interrupt status flags
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @param	status	: Or'ed value of status flag(s) that you want to clear, should be:
+ *              - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
+ *              - WWDT_WDMOD_WDINT: Clear watchdog warning flag
+ * @return	None
+ */
+void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status);
+
+/**
+ * @brief	Get the current value of WDT
+ * @param	pWWDT	: The base of WatchDog Timer peripheral on the chip
+ * @return	current value of WDT
+ */
+STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)
+{
+	return pWWDT->TV;
+}
+
+#if defined(WATCHDOG_CLKSEL_SUPPORT)
+/**
+ * @brief Watchdog Timer Clock Source Selection register definitions
+ */
+/** Clock source select bitmask */
+#define WWDT_CLKSEL_BITMASK         ((uint32_t) 0x10000003)
+/** Clock source select */
+#define WWDT_CLKSEL_SOURCE(n)       ((uint32_t) (n & 0x03))
+/** Lock the clock source selection */
+#define WWDT_CLKSEL_LOCK            ((uint32_t) (1 << 31))
+
+/**
+ * @brief Watchdog Clock Source definitions
+ */
+typedef enum {
+	WWDT_CLKSRC_IRC = WWDT_CLKSEL_SOURCE(0),				/*!< Internal RC oscillator */
+#if defined(CHIP_LPC175X_6X)
+	WWDT_CLKSRC_WATCHDOG_PCLK = WWDT_CLKSEL_SOURCE(1),		/*!< APB peripheral clock (watchdog pclk) */
+	WWDT_CLKSRC_RTC_CLK = WWDT_CLKSEL_SOURCE(2),			/*!< RTC oscillator (rtc_clk) */
+#else
+	WWDT_CLKSRC_WATCHDOG_WDOSC = WWDT_CLKSEL_SOURCE(1),		/*!< Watchdog oscillator (WDOSC) */
+#endif
+} CHIP_WWDT_CLK_SRC_T;
+
+/**
+ * @brief	Get the current value of WDT
+ * @param	pWWDT		: The base of WatchDog Timer peripheral on the chip
+ * @param	wdtClkSrc	: Selected watchdog clock source
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_WWDT_SelClockSource(LPC_WWDT_T *pWWDT, CHIP_WWDT_CLK_SRC_T wdtClkSrc)
+{
+	pWWDT->CLKSEL = wdtClkSrc & WWDT_CLKSEL_BITMASK;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __WWDT_17XX_40XX_H_ */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/adc_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/adc_17xx_40xx.c
new file mode 100644
index 000000000..13a61b525
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/adc_17xx_40xx.c
@@ -0,0 +1,256 @@
+/*
+ * @brief LPC17xx/40xx A/D conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Get the number of clock for a full conversion */
+STATIC INLINE uint8_t getFullConvClk(void)
+{
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	return 31;
+#elif defined(CHIP_LPC175X_6X)
+	return 65;
+#else
+	return 0;
+#endif
+
+}
+
+/* Get divider value */
+STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
+{
+	uint32_t adcBlockFreq;
+	uint32_t fullAdcRate;
+	uint8_t div;
+
+	/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
+	   A/D converter, which should be less than or equal to 4.5MHz.
+	   A fully conversion requires (bits_accuracy+1) of these clocks.
+	   ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
+	   ADC rate = ADC clock / (the number of clocks required for each conversion);
+	 */
+#if defined(CHIP_LPC175X_6X)
+	adcBlockFreq = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_ADC);
+#else
+	adcBlockFreq = Chip_Clock_GetPeripheralClockRate();
+#endif
+#if defined(ADC_ACC_12BITS)
+	fullAdcRate = adcRate * getFullConvClk();
+#else
+	if (burstMode) {
+		fullAdcRate = adcRate * clks;
+	}
+	else {
+		fullAdcRate = adcRate * getFullConvClk();
+	}
+#endif
+	/* Get the round value by fomular: (2*A + B)/(2*B) */
+	div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
+	return div;
+}
+
+/* Set start mode for ADC */
+void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode)
+{
+	uint32_t temp;
+	temp = pADC->CR & (~ADC_CR_START_MASK);
+	pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode));
+}
+
+/* Get the ADC value */
+Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
+{
+	uint32_t temp;
+	temp = pADC->DR[channel];
+	if (!ADC_DR_DONE(temp)) {
+		return ERROR;
+	}
+	/*	if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */
+	/*	return ERROR; */
+	*data = (uint16_t) ADC_DR_RESULT(temp);
+	return SUCCESS;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the ADC peripheral and the ADC setup structure to default value */
+void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup)
+{
+	uint8_t div;
+	uint32_t cr = 0;
+	uint32_t clk;
+
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
+
+#if defined(ADC_TRIM_SUPPORT)
+	pADC->ADTRM = 0xF00;
+#endif
+	pADC->INTEN = 0;		/* Disable all interrupts */
+
+	cr |= ADC_CR_PDN;
+
+	ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE;
+	ADCSetup->bitsAccuracy = 0;	/* LPC17xx/40xx doesn't support this setting */
+	clk = 0;
+	ADCSetup->burstMode = false;
+	div = getClkDiv(pADC, false, ADCSetup->adcRate, clk);
+	cr |= ADC_CR_CLKDIV(div);
+#if !defined(ADC_ACC_12BITS)
+	cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
+#endif /*defined(ADC_ACC_12BITS)*/
+	pADC->CR = cr;
+}
+
+/* Shutdown ADC */
+void Chip_ADC_DeInit(LPC_ADC_T *pADC)
+{
+	pADC->INTEN = 0x00000100;
+	pADC->CR = 0;
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
+}
+
+/* Get the ADC value */
+Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
+{
+	return readAdcVal(pADC, channel, data);
+}
+
+/* Get ADC Channel status from ADC data register */
+FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
+{
+	switch (StatusType) {
+	case ADC_DR_DONE_STAT:
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_OVERRUN_STAT:
+		channel += 8;
+		return (pADC->STAT & (1UL << channel)) ? SET : RESET;
+
+	case ADC_DR_ADINT_STAT:
+		return pADC->STAT >> 16 ? SET : RESET;
+
+	default:
+		break;
+	}
+	return RESET;
+}
+
+/* Enable/Disable interrupt for ADC channel */
+void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->INTEN |= (1UL << channel);
+	}
+	else {
+		pADC->INTEN &= (~(1UL << channel));
+	}
+}
+
+/* Select the mode starting the AD conversion */
+void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption)
+{
+	if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
+		if (EdgeOption) {
+			pADC->CR |= ADC_CR_EDGE;
+		}
+		else {
+			pADC->CR &= ~ADC_CR_EDGE;
+		}
+	}
+	setStartMode(pADC, (uint8_t) mode);
+}
+
+/* Set the ADC Sample rate */
+void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate)
+{
+	uint8_t div;
+	uint32_t cr;
+
+	cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK);
+	ADCSetup->adcRate = rate;
+	div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy));
+	cr |= ADC_CR_CLKDIV(div);
+#if !defined(ADC_ACC_12BITS)
+	cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
+#endif /*defined(ADC_ACC_12BITS)*/
+	pADC->CR = cr;
+}
+
+/* Enable or disable the ADC channel on ADC peripheral */
+void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pADC->CR |= ADC_CR_CH_SEL(channel);
+	}
+	else {
+		pADC->CR &= ~ADC_CR_START_MASK;
+		pADC->CR &= ~ADC_CR_CH_SEL(channel);
+	}
+}
+
+/* Enable burst mode */
+void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState)
+{
+	setStartMode(pADC, ADC_NO_START);
+
+	if (NewState == DISABLE) {
+		pADC->CR &= ~ADC_CR_BURST;
+	}
+	else {
+		pADC->CR |= ADC_CR_BURST;
+	}
+}
+
+/* Read the ADC value and convert it to 8bits value */
+Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data)
+{
+	uint16_t temp;
+	Status rt;
+
+	rt = readAdcVal(pADC, channel, &temp);
+	*data = (uint8_t) temp;
+
+	return rt;
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/can_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/can_17xx_40xx.c
new file mode 100644
index 000000000..636d9df89
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/can_17xx_40xx.c
@@ -0,0 +1,1507 @@
+/*
+ * @brief LPC17xx/40xx CAN driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Set Bus Timing */
+STATIC void setBusTiming(LPC_CAN_T *pCAN, IP_CAN_BUS_TIMING_T *pBusTiming) {
+	/* Enter to Reset Mode */
+	Chip_CAN_SetMode(pCAN, CAN_RESET_MODE, ENABLE);
+
+	/* Set Bus Timing */
+	pCAN->BTR = CAN_BTR_BRP(pBusTiming->BRP)
+				| CAN_BTR_SJW(pBusTiming->SJW)
+				| CAN_BTR_TESG1(pBusTiming->TESG1)
+				| CAN_BTR_TESG2(pBusTiming->TESG2);
+
+	if (pBusTiming->SAM) {
+		pCAN->BTR |= CAN_BTR_SAM;
+	}
+
+	/* Exit from Reset Mode */
+	Chip_CAN_SetMode(pCAN, CAN_RESET_MODE, DISABLE);
+}
+
+/* Get start row, end row of the given section */
+STATIC void getSectionAddress(LPC_CANAF_T *pCANAF,
+							  CANAF_RAM_SECTION_T SectionID, uint16_t *StartAddr, uint16_t *EndAddr)
+{
+	if (SectionID == CANAF_RAM_FULLCAN_SEC) {
+		*StartAddr = 0;
+	}
+	else {
+		*StartAddr = CANAF_ENDADDR_VAL(pCANAF->ENDADDR[SectionID - 1]);
+	}
+	*EndAddr = CANAF_ENDADDR_VAL(pCANAF->ENDADDR[SectionID]);
+
+	if (*EndAddr > 0) {
+		*EndAddr -= 1;	/* Minus 1 to get the actual end row */
+	}
+	else {
+		*EndAddr = *StartAddr;
+	}
+}
+
+/* Get the total number of entries in LUT */
+STATIC INLINE uint16_t getTotalEntryNum(LPC_CANAF_T *pCANAF)
+{
+	return CANAF_ENDADDR_VAL(pCANAF->ENDADDR[CANAF_RAM_EFF_GRP_SEC]);	/* Extended ID Group section is the last section of LUT */
+}
+
+/* Set the End Address of a section. EndAddr = the number of the last row of the section + 1. */
+STATIC INLINE void setSectionEndAddress(LPC_CANAF_T *pCANAF,
+										CANAF_RAM_SECTION_T SectionID, uint16_t EndAddr)
+{
+	pCANAF->ENDADDR[SectionID] = CANAF_ENDADDR(EndAddr);
+}
+
+/* Get information of the received frame. Return ERROR means no message came.*/
+STATIC INLINE Status getReceiveFrameInfo(LPC_CAN_T *pCAN,
+										 IP_CAN_001_RX_T *pRxFrame)
+{
+	*pRxFrame = pCAN->RX;
+	return (pCAN->SR & CAN_SR_RBS(0)) ? SUCCESS : ERROR;
+}
+
+/* Set Tx Frame Information */
+STATIC INLINE void setSendFrameInfo(LPC_CAN_T *pCAN, CAN_BUFFER_ID_T TxBufID,
+									LPC_CAN_TX_T *pTxFrame)
+{
+	pCAN->TX[TxBufID] = *pTxFrame;
+}
+
+/* Create the standard ID entry */
+STATIC uint16_t createStdIDEntry(CAN_STD_ID_ENTRY_T *pEntryInfo, bool IsFullCANEntry)
+{
+	uint16_t Entry = 0;
+	Entry = (pEntryInfo->CtrlNo & CAN_STD_ENTRY_CTRL_NO_MASK) << CAN_STD_ENTRY_CTRL_NO_POS;
+	Entry |= (pEntryInfo->Disable & CAN_STD_ENTRY_DISABLE_MASK) << CAN_STD_ENTRY_DISABLE_POS;
+	Entry |= (pEntryInfo->ID_11 & CAN_STD_ENTRY_ID_MASK) << CAN_STD_ENTRY_ID_POS;
+	if (IsFullCANEntry) {
+		Entry |= 1 << CAN_STD_ENTRY_IE_POS;
+	}
+	return Entry;
+}
+
+STATIC INLINE uint16_t createUnUsedSTDEntry(uint8_t CtrlNo)
+{
+	return ((CtrlNo & CAN_STD_ENTRY_CTRL_NO_MASK) << CAN_STD_ENTRY_CTRL_NO_POS) | (1 << CAN_STD_ENTRY_DISABLE_POS);
+}
+
+/* Get information from the standard ID entry */
+STATIC void readStdIDEntry(uint16_t EntryVal, CAN_STD_ID_ENTRY_T *pEntryInfo)
+{
+	pEntryInfo->CtrlNo = (EntryVal >> CAN_STD_ENTRY_CTRL_NO_POS) & CAN_STD_ENTRY_CTRL_NO_MASK;
+	pEntryInfo->Disable = (EntryVal >> CAN_STD_ENTRY_DISABLE_POS) & CAN_STD_ENTRY_DISABLE_MASK;
+	pEntryInfo->ID_11 = (EntryVal >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK;
+}
+
+/* Setup Standard iD section */
+STATIC Status setupSTDSection(uint32_t *pCANAFRamAddr,
+							  CAN_STD_ID_ENTRY_T *pStdCANSec,
+							  uint16_t EntryNum,
+							  bool IsFullCANEntry)
+{
+	uint16_t i;
+	uint16_t CurID = 0;
+	uint16_t Entry;
+	uint16_t EntryCnt = 0;
+
+	/* Setup FullCAN section */
+	for (i = 0; i < EntryNum; i += 2) {
+		/* First Entry */
+		if (CurID > pStdCANSec[i].ID_11) {
+			return ERROR;
+		}
+		CurID = pStdCANSec[i].ID_11;
+		Entry = createStdIDEntry(&pStdCANSec[i], IsFullCANEntry);
+		pCANAFRamAddr[EntryCnt] = Entry << 16;
+
+		/* Second Entry */
+		if ((i + 1) < EntryNum) {
+			if (CurID > pStdCANSec[i + 1].ID_11) {
+				return ERROR;
+			}
+			CurID = pStdCANSec[i + 1].ID_11;
+			Entry = createStdIDEntry(&pStdCANSec[i + 1], IsFullCANEntry);
+			pCANAFRamAddr[EntryCnt] |= Entry;
+		}
+		else {
+			pCANAFRamAddr[EntryCnt] |= createUnUsedSTDEntry(pStdCANSec[0].CtrlNo);
+		}
+		EntryCnt++;
+	}
+	return SUCCESS;
+
+}
+
+/* Setup the Group Standard ID section */
+STATIC Status setupSTDRangeSection(uint32_t *pCANAFRamAddr,
+								   CAN_STD_ID_RANGE_ENTRY_T *pStdRangeCANSec,
+								   uint16_t EntryNum)
+{
+	return setupSTDSection(pCANAFRamAddr, (CAN_STD_ID_ENTRY_T *) pStdRangeCANSec, EntryNum * 2, false);
+}
+
+/* Shift a number of entries down 1 position */
+STATIC void shiftSTDEntryDown(uint32_t *arr, int32_t num)
+{
+	uint32_t i = 0;
+	uint32_t prevRow, curRow;
+
+	if (num <= 0) {
+		return;
+	}
+
+	prevRow = arr[0];
+	arr[0] = ((prevRow & 0xFFFF0000) >> 16);
+	for (i = 0; i < (num / 2); i++) {
+		curRow = arr[i + 1];
+		arr[i + 1] = ((prevRow & 0xFFFF) << 16) | ((curRow & 0xFFFF0000) >> 16);
+		prevRow = curRow;
+	}
+	if ((num % 2) == 0) {
+		uint8_t CtrlNo = (prevRow >> CAN_STD_ENTRY_CTRL_NO_POS) & CAN_STD_ENTRY_CTRL_NO_MASK;
+		arr[num / 2] = ((prevRow & 0xFFFF) << 16) | createUnUsedSTDEntry(CtrlNo);
+	}
+}
+
+/* Shift a number of entries up 1 position */
+STATIC void shiftSTDEntryUp(uint32_t *arr, int32_t num)
+{
+	int32_t i = 0;
+	uint32_t prevRow = 0, curRow = 0;
+	uint8_t CtrlNo = 0;
+
+	if (num <= 0) {
+		return;
+	}
+
+	curRow = arr[((num + 1) / 2) - 1];
+	CtrlNo = (curRow >> CAN_STD_ENTRY_CTRL_NO_POS) & CAN_STD_ENTRY_CTRL_NO_MASK;
+
+	/* If num is odd, the last row only includes one item. Therefore, there is nothing
+	   to do with it. If num is even, shift the last item to one place of the row.*/
+	if ((num % 2) == 0) {
+		arr[((num + 1) / 2) - 1] = ((curRow & 0xFFFF) << 16) | createUnUsedSTDEntry(CtrlNo);
+	}
+	/* Shift from the row before the last row */
+	for (i = ((num + 1) / 2) - 1; i > 0; i--) {
+		prevRow = arr[i - 1];
+		arr[i - 1] = ((curRow & 0xFFFF0000) >> 16) | ((prevRow & 0xFFFF) << 16);
+		curRow = prevRow;
+	}
+}
+
+/* Create an extended ID entry */
+STATIC uint32_t createExtIDEntry(CAN_EXT_ID_ENTRY_T *pEntryInfo)
+{
+	uint32_t Entry = 0;
+	Entry = (pEntryInfo->CtrlNo & CAN_EXT_ENTRY_CTRL_NO_MASK) << CAN_EXT_ENTRY_CTRL_NO_POS;
+	Entry |= (pEntryInfo->ID_29 & CAN_EXT_ENTRY_ID_MASK) << CAN_EXT_ENTRY_ID_POS;
+	return Entry;
+}
+
+/* Get information from an extended ID entry */
+STATIC void readExtIDEntry(uint32_t EntryVal, CAN_EXT_ID_ENTRY_T *pEntryInfo)
+{
+	pEntryInfo->CtrlNo = (EntryVal >> CAN_EXT_ENTRY_CTRL_NO_POS) & CAN_EXT_ENTRY_CTRL_NO_MASK;
+	pEntryInfo->ID_29 = (EntryVal >> CAN_EXT_ENTRY_ID_POS) & CAN_EXT_ENTRY_ID_MASK;
+}
+
+/* Setup the Extended ID Section */
+STATIC Status setupEXTSection(uint32_t *pCANAFRamAddr, CAN_EXT_ID_ENTRY_T *pExtCANSec, uint16_t EntryNum)
+{
+	uint16_t i;
+	uint32_t CurID = 0;
+	uint32_t Entry;
+	uint16_t EntryCnt = 0;
+
+	/* Setup FullCAN section */
+	for (i = 0; i < EntryNum; i++) {
+		if (CurID > pExtCANSec[i].ID_29) {
+			return ERROR;
+		}
+		CurID = pExtCANSec[i].ID_29;
+		Entry = createExtIDEntry(&pExtCANSec[i]);
+		pCANAFRamAddr[EntryCnt] = Entry;
+		EntryCnt++;
+	}
+	return SUCCESS;
+
+}
+
+/* Setup Group Extended ID section */
+STATIC Status setupEXTRangeSection(uint32_t *pCANAFRamAddr,
+								   CAN_EXT_ID_RANGE_ENTRY_T *pExtRangeCANSec,
+								   uint16_t EntryNum)
+{
+	return setupEXTSection(pCANAFRamAddr, (CAN_EXT_ID_ENTRY_T *) pExtRangeCANSec, EntryNum * 2);
+}
+
+/* Get entry value from the given start index of the given array. byteNum is 2 or 4 bytes */
+STATIC uint32_t getArrayVal(uint8_t *arr, uint32_t startIndex, uint8_t byteNum)
+{
+	uint8_t i = 0;
+	uint32_t retVal = 0;
+	uint32_t index;
+
+	index =  startIndex * byteNum;
+	if (byteNum == 2) {	// each entry uses 2 bytes
+		if (startIndex % 2) {
+			index -= 2;		// little endian
+		}
+		else {
+			index += 2;
+		}
+	}
+
+	for (i = 0; i < byteNum; i++) {
+		retVal |= arr[index + i] << (8 * i);
+	}
+	return retVal;
+}
+
+/* Search the index to insert the new entry */
+STATIC int32_t searchInsertIndex(uint32_t *arr, uint32_t arrNum, uint32_t val, uint32_t mask, uint8_t unitSize)
+{
+	uint32_t LowerIndex, UpperIndex, MidIndex;
+	uint32_t MidVal;
+	uint8_t *byteArray = (uint8_t *) arr;
+
+	if (arrNum == 0) {
+		return 0;		/* Insert into the first line */
+
+	}
+	LowerIndex = 0;
+	UpperIndex = arrNum - 1;
+	while (LowerIndex + 1 < UpperIndex) {
+		MidIndex = (LowerIndex + UpperIndex) / 2;
+		MidVal = getArrayVal(byteArray, MidIndex, unitSize) & mask;
+		if (MidVal == val) {
+			return -1;			/* The new value is already in the array */
+		}
+		else if (MidVal < val) {
+			LowerIndex = MidIndex + 1;
+		}
+		else {
+			UpperIndex = MidIndex - 1;
+		}
+	}
+
+	if (((getArrayVal(byteArray, LowerIndex, unitSize) & mask) == val) ||
+		((getArrayVal(byteArray, UpperIndex, unitSize) & mask) == val)) {
+		return -1;			/* The new value is already in the array */
+	}
+	if ((getArrayVal(byteArray, LowerIndex, unitSize) & mask) > val) {
+		return LowerIndex;
+	}
+	if ((getArrayVal(byteArray, UpperIndex, unitSize) & mask) < val) {
+		return UpperIndex + 1;
+	}
+
+	return UpperIndex;
+}
+
+/* Insert an entry into FullCAN Table */
+STATIC Status insertSTDEntry(LPC_CANAF_T *pCANAF,
+							 LPC_CANAF_RAM_T *pCANAFRam,
+							 CAN_STD_ID_ENTRY_T *pEntry,
+							 bool IsFullCANEntry)
+{
+	int32_t IDIndex = 0;
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+	uint16_t i = 0;
+	uint32_t tmp = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	if (getTotalEntryNum(pCANAF) >= CANAF_RAM_ENTRY_NUM) {
+		return ERROR;
+	}
+
+	/* Check if a number of entries in  section is odd or even */
+	if (IsFullCANEntry) {
+		getSectionAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, &StartRow, &EndRow);
+	}
+	else {
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_SEC, &StartRow, &EndRow);
+
+	}
+
+	if (EndRow > StartRow) {
+		EntryCnt = (EndRow - StartRow + 1) * 2;
+		if ((((pCANAFRam->MASK[EndRow] >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK) ==
+			 0) &&
+			(((pCANAFRam->MASK[EndRow] >>
+			   CAN_STD_ENTRY_DISABLE_POS) & CAN_STD_ENTRY_DISABLE_MASK) == 1)) {						/* Unsed entry */
+			EntryCnt -= 1;
+		}
+
+	}
+
+	/* Search for Index of new entry */
+	IDIndex = searchInsertIndex((uint32_t *) &pCANAFRam->MASK[StartRow],
+								EntryCnt,
+								pEntry->ID_11 & CAN_STD_ENTRY_ID_MASK,
+								CAN_STD_ENTRY_ID_MASK,
+								sizeof(uint16_t));
+	if ((IDIndex == -1) || (IDIndex > EntryCnt )) {
+		return ERROR;
+	}
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	/* Move all remaining sections one place down
+	            if new entry will increase FullCAN list */
+	if ((EntryCnt % 2) == 0) {
+		uint16_t StartAddr, EndAddr;
+
+		for (i = getTotalEntryNum(pCANAF); i > EndRow; i--) {
+			pCANAFRam->MASK[i] = pCANAFRam->MASK[i - 1];
+		}
+
+		if (IsFullCANEntry) {
+			getSectionAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, &StartAddr, &EndAddr);
+			setSectionEndAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, EndAddr + 2);
+		}
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_SEC, EndAddr + 2);
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, EndAddr + 2);
+		getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_SEC, EndAddr + 2);
+		getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EndAddr + 2);
+	}
+
+	/* Shift rows behind the row of search index. If search index  is low index of the row, shift the row of search index also. */
+	if ((IDIndex % 2) == 0) {
+		shiftSTDEntryDown((uint32_t *) &pCANAFRam->MASK[StartRow + IDIndex / 2], EntryCnt - IDIndex);
+	}
+	else {
+		shiftSTDEntryDown((uint32_t *) &pCANAFRam->MASK[StartRow + IDIndex / 2 + 1], EntryCnt - IDIndex - 1);
+	}
+
+	/* Insert new item */
+	tmp = createStdIDEntry(pEntry, IsFullCANEntry);
+	if ((IDIndex % 2) == 0) {
+		if (IDIndex == EntryCnt) {
+			/* Insert unused item if the new item is the last item*/
+			pCANAFRam->MASK[StartRow + IDIndex / 2] = (tmp << 16) | createUnUsedSTDEntry(pEntry->CtrlNo);
+		}
+		else {
+			uint32_t val;
+			val = pCANAFRam->MASK[StartRow + IDIndex / 2] & 0x0000FFFF;
+			/* Insert new item */
+			pCANAFRam->MASK[StartRow + IDIndex / 2] = val | (tmp << 16);
+		}
+	}
+	else {
+		uint32_t val, valNext;
+		val = pCANAFRam->MASK[StartRow + IDIndex / 2];
+		valNext = pCANAFRam->MASK[StartRow + IDIndex / 2 + 1];
+		/* In case the new entry is not the last item, shift the item at the found index to the next row*/
+		if (IDIndex < EntryCnt ) {
+
+			pCANAFRam->MASK[StartRow + IDIndex / 2 + 1] = (valNext & 0x0000FFFF) | ((val & 0xFFFF) << 16);
+		}
+		pCANAFRam->MASK[StartRow + IDIndex / 2] = (val & 0xFFFF0000) | tmp;
+	}
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+	return SUCCESS;
+}
+
+/* Read STD Entry */
+STATIC Status readSTDEntry(LPC_CANAF_T *pCANAF,
+						   LPC_CANAF_RAM_T *pCANAFRam,
+						   uint16_t Position,
+						   bool   IsFullCANEntry,
+						   CAN_STD_ID_ENTRY_T *pEntry)
+
+{
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+
+	/* Check if a number of entries in  section is odd or even */
+	if (IsFullCANEntry) {
+		getSectionAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, &StartRow, &EndRow);
+	}
+	else {
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_SEC, &StartRow, &EndRow);
+	}
+
+	if (EndRow > StartRow) {
+		EntryCnt = (EndRow - StartRow + 1) * 2;
+		if ((((pCANAFRam->MASK[EndRow] >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK) ==
+			 0) &&
+			(((pCANAFRam->MASK[EndRow] >>
+			   CAN_STD_ENTRY_DISABLE_POS) & CAN_STD_ENTRY_DISABLE_MASK) == 1)) {						/* Unsed entry */
+			EntryCnt -= 1;
+		}
+	}
+	if (Position >= EntryCnt) {
+		return ERROR;
+	}
+
+	if ((Position % 2) == 0) {
+		readStdIDEntry(pCANAFRam->MASK[StartRow + Position / 2] >> 16, pEntry);
+	}
+	else {
+		readStdIDEntry(pCANAFRam->MASK[StartRow + Position / 2] & 0xFFFF, pEntry);
+	}
+
+	return SUCCESS;
+}
+
+/* Remove STD Entry from given table */
+Status removeSTDEntry(LPC_CANAF_T *pCANAF,
+					  LPC_CANAF_RAM_T *pCANAFRam,
+					  int16_t IDIndex,
+					  bool IsFullCANEntry)
+{
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0, i;
+	uint32_t tmp = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	if (IDIndex < 0) {
+		return ERROR;
+	}
+
+	if (getTotalEntryNum(pCANAF) >= CANAF_RAM_ENTRY_NUM) {
+		return ERROR;
+	}
+
+	/* Check if a number of entries in  section is odd or even */
+	if (IsFullCANEntry) {
+		getSectionAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, &StartRow, &EndRow);
+	}
+	else {
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_SEC, &StartRow, &EndRow);
+	}
+
+	if (EndRow > StartRow) {
+		EntryCnt = (EndRow - StartRow + 1) * 2;
+		if ((((pCANAFRam->MASK[EndRow] >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK) ==
+			 0) &&
+			(((pCANAFRam->MASK[EndRow] >>
+			   CAN_STD_ENTRY_DISABLE_POS) & CAN_STD_ENTRY_DISABLE_MASK) == 1)) {						/* Unsed entry */
+			EntryCnt -= 1;
+		}
+
+	}
+	if (IDIndex >= EntryCnt) {
+		return ERROR;
+	}
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	/* Shift rows behind the row of remove index. If remove index  is low index of the row, shift the row of remove index also. */
+	tmp = pCANAFRam->MASK[StartRow + IDIndex / 2 + 1];
+	if ((IDIndex % 2) == 0) {
+		shiftSTDEntryUp((uint32_t *) &pCANAFRam->MASK[StartRow + IDIndex / 2], EntryCnt - IDIndex);
+	}
+	else {
+		shiftSTDEntryUp((uint32_t *) &pCANAFRam->MASK[StartRow + IDIndex / 2 + 1], EntryCnt - IDIndex - 1);
+
+		/* Set value for the entry at remove index */
+		pCANAFRam->MASK[StartRow + IDIndex / 2] &= 0xFFFF0000;
+		if (IDIndex == (EntryCnt - 1)) {
+			uint8_t CtrlNo;
+			tmp = (pCANAFRam->MASK[StartRow + IDIndex / 2]) >> 16;
+			CtrlNo = (tmp >> CAN_STD_ENTRY_CTRL_NO_POS) & CAN_STD_ENTRY_CTRL_NO_MASK;
+			pCANAFRam->MASK[StartRow + IDIndex / 2] |= createUnUsedSTDEntry(CtrlNo);
+		}
+		else {
+			pCANAFRam->MASK[StartRow + IDIndex / 2] |= (tmp >> 16) & 0xFFFF;
+		}
+	}
+	/* Move all remaining sections one place up
+	            if new entry will decrease FullCAN list */
+	if (EntryCnt % 2) {
+		uint16_t StartAddr, EndAddr;
+
+		for (i = EndRow; i < getTotalEntryNum(pCANAF); i++) {
+			pCANAFRam->MASK[i] = pCANAFRam->MASK[i + 1];
+		}
+
+		if (IsFullCANEntry) {
+			getSectionAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, &StartAddr, &EndAddr);
+			setSectionEndAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, EndAddr);
+		}
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_SEC, EndAddr);
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, EndAddr);
+		getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_SEC, EndAddr);
+		getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EndAddr);
+	}
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+	return SUCCESS;
+}
+
+/* Remove LUT Entry from given table */
+Status removeLUTEntry(LPC_CANAF_T *pCANAF,
+					  LPC_CANAF_RAM_T *pCANAFRam,
+					  CANAF_RAM_SECTION_T SectionID,
+					  int16_t Position)
+{
+	uint16_t StartRow, EndRow;
+	uint16_t StartAddr, EndAddr;
+	uint16_t EntryCnt = 0;
+	uint8_t  EntryRowNum = 1;
+	uint16_t i = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	if (Position < 0) {
+		return ERROR;
+	}
+
+	if (getTotalEntryNum(pCANAF) >= CANAF_RAM_ENTRY_NUM) {
+		return ERROR;
+	}
+
+	if (SectionID == CANAF_RAM_FULLCAN_SEC) {
+		return removeSTDEntry(pCANAF, pCANAFRam, Position, true);
+	}
+	else if (SectionID == CANAF_RAM_SFF_SEC) {
+		return removeSTDEntry(pCANAF, pCANAFRam, Position, false);
+	}
+
+	/* Get a number of rows for an entry */
+	if (SectionID == CANAF_RAM_EFF_GRP_SEC) {
+		EntryRowNum = 2;
+	}
+
+	/* Get Start Row, End Row */
+	getSectionAddress(pCANAF, SectionID, &StartRow, &EndRow);
+
+	if (EndRow > StartRow) {
+		EntryCnt = (EndRow - StartRow + 1) / EntryRowNum;
+	}
+
+	if (Position >= EntryCnt) {
+		return ERROR;
+	}
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	/* Move all remaining sections one place up
+	            if new entry will increase FullCAN list */
+	for (i = StartRow + Position * EntryRowNum; i < getTotalEntryNum(pCANAF); i++) {
+		pCANAFRam->MASK[i] = pCANAFRam->MASK[i + EntryRowNum];
+	}
+
+	/* Get Start Row, End Row */
+	switch (SectionID) {
+	case CANAF_RAM_SFF_GRP_SEC:
+		getSectionAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, EndAddr - EntryRowNum + 1);
+
+	case CANAF_RAM_EFF_SEC:
+		getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_SEC, EndAddr - EntryRowNum + 1);
+
+	case CANAF_RAM_EFF_GRP_SEC:
+		getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartAddr, &EndAddr);
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EndAddr - EntryRowNum + 1);
+		break;
+
+	default:
+		return ERROR;
+	}
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+	return SUCCESS;
+}
+
+/* Clear AF LUT */
+void clearAFLUT(LPC_CANAF_T *pCanAF, LPC_CANAF_RAM_T *pCanAFRam) {
+	uint32_t i = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCanAF);
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCanAF, CAN_AF_OFF_MODE);
+
+	/* Clear AF Ram region */
+	for (i = 0; i < CANAF_RAM_ENTRY_NUM; i++) {
+		pCanAFRam->MASK[i] = 0;
+	}
+
+	/* Reset address registers */
+	setSectionEndAddress(pCanAF, CANAF_RAM_FULLCAN_SEC, 0);
+	setSectionEndAddress(pCanAF, CANAF_RAM_SFF_SEC, 0);
+	setSectionEndAddress(pCanAF, CANAF_RAM_SFF_GRP_SEC, 0);
+	setSectionEndAddress(pCanAF, CANAF_RAM_EFF_SEC, 0);
+	setSectionEndAddress(pCanAF, CANAF_RAM_EFF_GRP_SEC, 0);
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCanAF, CurMode);
+}
+
+/* Returns clock for the peripheral block */
+STATIC CHIP_SYSCTL_CLOCK_T Chip_CAN_GetClockIndex(LPC_CAN_T *pCAN)
+{
+	CHIP_SYSCTL_CLOCK_T clkCAN;
+
+	if (pCAN == LPC_CAN1) {
+		clkCAN = SYSCTL_CLOCK_CAN1;
+	}
+	else {
+		clkCAN = SYSCTL_CLOCK_CAN2;
+	}
+
+	return clkCAN;
+}
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+/* Returns reset ID for the peripheral block */
+STATIC CHIP_SYSCTL_RESET_T Chip_CAN_GetResetIndex(LPC_CAN_T *pCAN)
+{
+	CHIP_SYSCTL_RESET_T resetCAN;
+
+	if (pCAN == LPC_CAN1) {
+		resetCAN = SYSCTL_RESET_CAN1;
+	}
+	else {
+		resetCAN = SYSCTL_RESET_CAN2;
+	}
+
+	return resetCAN;
+}
+
+#endif
+
+#if defined(CHIP_LPC175X_6X)
+/* Returns clock ID for the peripheral block */
+STATIC CHIP_SYSCTL_PCLK_T Chip_CAN_GetClkIndex(LPC_CAN_T *pCAN)
+{
+	CHIP_SYSCTL_PCLK_T clkCAN;
+
+	if (pCAN == LPC_CAN1) {
+		clkCAN = SYSCTL_PCLK_CAN1;
+	}
+	else {
+		clkCAN = SYSCTL_PCLK_CAN2;
+	}
+
+	return clkCAN;
+}
+
+#endif
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize CAN Interface */
+void Chip_CAN_Init(LPC_CAN_T *pCAN, LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam)
+{
+	volatile uint32_t i;
+
+	Chip_Clock_EnablePeriphClock(Chip_CAN_GetClockIndex(pCAN));
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	Chip_SYSCTL_PeriphReset(Chip_CAN_GetResetIndex(pCAN));
+#endif
+
+	/* Enter to Reset Mode */
+	pCAN->MOD = CAN_MOD_RM;
+
+	/* Disable all CAN Interrupts */
+	pCAN->IER &= (~CAN_IER_BITMASK) & CAN_IER_BITMASK;
+	pCAN->GSR &= (~CAN_GSR_BITMASK) & CAN_GSR_BITMASK;
+
+	/* Request command to release Rx, Tx buffer and clear data overrun */
+	pCAN->CMR = CAN_CMR_RRB | CAN_CMR_AT | CAN_CMR_CDO;
+
+	/* Read to clear interrupt pending in interrupt capture register */
+	i = pCAN->ICR;
+
+	/* Return to normal mode */
+	pCAN->MOD = CAN_MOD_OPERATION;
+
+	/* Initiialize Acceptance filter */
+	clearAFLUT(pCANAF, pCANAFRam);
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_NORMAL_MODE);
+}
+
+/* De-Initialize CAN Interface */
+void Chip_CAN_DeInit(LPC_CAN_T *pCAN)
+{
+	Chip_Clock_DisablePeriphClock(Chip_CAN_GetClockIndex(pCAN));
+}
+
+/* Set CAN Bit Rate */
+Status Chip_CAN_SetBitRate(LPC_CAN_T *pCAN, uint32_t BitRate)
+{
+	IP_CAN_BUS_TIMING_T BusTiming;
+	uint32_t result = 0;
+	uint8_t NT, TSEG1 = 0, TSEG2 = 0;
+	uint32_t CANPclk = 0;
+	uint32_t BRP = 0;
+
+#if defined(CHIP_LPC175X_6X)
+	CANPclk = Chip_Clock_GetPeripheralClockRate(Chip_CAN_GetClkIndex(pCAN));
+#else
+	CANPclk = Chip_Clock_GetPeripheralClockRate();
+#endif
+	result = CANPclk / BitRate;
+
+	/* Calculate suitable nominal time value
+	 * NT (nominal time) = (TSEG1 + TSEG2 + 3)
+	 * NT <= 24
+	 * TSEG1 >= 2*TSEG2
+	 */
+	for (NT = 24; NT > 0; NT = NT - 2) {
+		if ((result % NT) == 0) {
+			BRP = result / NT - 1;
+
+			NT--;
+
+			TSEG2 = (NT / 3) - 1;
+
+			TSEG1 = NT - (NT / 3) - 1;
+
+			break;
+		}
+	}
+	if (NT == 0) {
+		return ERROR;
+	}
+
+	BusTiming.TESG1 = TSEG1;
+	BusTiming.TESG2 = TSEG2;
+	BusTiming.BRP = BRP;
+	BusTiming.SJW = 3;
+	BusTiming.SAM = 0;
+	setBusTiming(pCAN, &BusTiming);
+	return SUCCESS;
+}
+
+/* Set CAN Mode */
+void Chip_CAN_SetMode(LPC_CAN_T *pCAN, CAN_MODE_T Mode, FunctionalState NewState)
+{
+	if ((Mode & CAN_MOD_LOM) || (Mode & CAN_MOD_STM)) {
+		/* Enter to Reset Mode */
+		pCAN->MOD |= CAN_MOD_RM;
+
+		/* Change to the given mode */
+		if (NewState) {
+			pCAN->MOD |= Mode;
+		}
+		else {
+			pCAN->MOD &= (~Mode) & CAN_MOD_BITMASK;
+		}
+
+		/* Release Reset Mode */
+		pCAN->MOD &= (~CAN_MOD_RM) & CAN_MOD_BITMASK;
+	}
+	else {
+		if (NewState) {
+			pCAN->MOD |= Mode;
+		}
+		else {
+			pCAN->MOD &= (~Mode) & CAN_MOD_BITMASK;
+		}
+	}
+
+}
+
+/* Get Free TxBuf */
+CAN_BUFFER_ID_T Chip_CAN_GetFreeTxBuf(LPC_CAN_T *pCAN)
+{
+	CAN_BUFFER_ID_T TxBufID = CAN_BUFFER_1;
+
+	/* Select a free buffer */
+	for (TxBufID = (CAN_BUFFER_ID_T) 0; TxBufID < CAN_BUFFER_LAST; TxBufID++) {
+		if (Chip_CAN_GetStatus(pCAN) & CAN_SR_TBS(TxBufID)) {
+			break;
+		}
+	}
+
+	return TxBufID;
+}
+
+/* Set AF Lookup Table */
+Status Chip_CAN_SetAFLUT(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam, CANAF_LUT_T *pAFSections) {
+	uint16_t EntryCnt = 0, FullCANEntryCnt = 0;
+	Status ret = ERROR;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	do {
+		/* Check a number of entries */
+		if ((((pAFSections->FullCANEntryNum + 1) / 2) +
+			 ((pAFSections->SffEntryNum + 1) / 2) +
+			 (pAFSections->SffGrpEntryNum) +
+			 (pAFSections->EffEntryNum) +
+			 (pAFSections->EffGrpEntryNum * 2)) > CANAF_RAM_ENTRY_NUM) {
+			ret = ERROR;
+			break;
+		}
+
+		/* Setup FullCAN section */
+		ret =
+			setupSTDSection((uint32_t *) &pCANAFRam->MASK[EntryCnt], pAFSections->FullCANSec,
+							pAFSections->FullCANEntryNum, true);
+		if (ret == ERROR) {
+			break;
+		}
+		EntryCnt = (pAFSections->FullCANEntryNum + 1) >> 1;
+		FullCANEntryCnt =  EntryCnt;
+		setSectionEndAddress(pCANAF, CANAF_RAM_FULLCAN_SEC, EntryCnt);
+
+		/* Set up Individual Standard ID section */
+		ret =
+			setupSTDSection((uint32_t *) &pCANAFRam->MASK[EntryCnt],
+							pAFSections->SffSec,
+							pAFSections->SffEntryNum,
+							false);
+		if (ret == ERROR) {
+			break;
+		}
+
+		EntryCnt += (pAFSections->SffEntryNum + 1) >> 1;
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_SEC, EntryCnt);
+
+		/* Set up Group Standard ID section */
+		ret =
+			setupSTDRangeSection((uint32_t *) &pCANAFRam->MASK[EntryCnt], pAFSections->SffGrpSec,
+								 pAFSections->SffGrpEntryNum);
+		if (ret == ERROR) {
+			break;
+		}
+
+		EntryCnt += pAFSections->SffGrpEntryNum;
+		setSectionEndAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, EntryCnt);
+
+		/* Setup Individual Extended ID section */
+		ret =
+			setupEXTSection((uint32_t *) &pCANAFRam->MASK[EntryCnt], pAFSections->EffSec, pAFSections->EffEntryNum);
+		if (ret == ERROR) {
+			break;
+		}
+
+		EntryCnt += pAFSections->EffEntryNum;
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_SEC, EntryCnt);
+
+		/* Setup Group Extended ID section */
+		ret =
+			setupEXTRangeSection((uint32_t *) &pCANAFRam->MASK[EntryCnt], pAFSections->EffGrpSec,
+								 pAFSections->EffGrpEntryNum);
+		if (ret == ERROR) {
+			break;
+		}
+
+		EntryCnt += pAFSections->EffGrpEntryNum * 2;
+		setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EntryCnt);
+
+		if ((FullCANEntryCnt > 0) && ((0x800 - 6 * FullCANEntryCnt) < EntryCnt)) {
+			ret = ERROR;
+		}
+
+	} while (0);
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+
+	return ret;
+}
+
+/* Get the number of entries of the given section */
+uint16_t Chip_CAN_GetEntriesNum(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam,
+								CANAF_RAM_SECTION_T SectionID)
+{
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+
+	getSectionAddress(pCANAF, SectionID, &StartRow, &EndRow);
+	if (EndRow <= StartRow) {
+		return 0;
+	}
+	if ((SectionID == CANAF_RAM_FULLCAN_SEC) ||
+		(SectionID == CANAF_RAM_SFF_SEC)) {
+		EntryCnt = (EndRow - StartRow + 1) * 2;
+		if ((((pCANAFRam->MASK[EndRow] >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK) ==
+			 0) &&
+			(((pCANAFRam->MASK[EndRow] >>
+			   CAN_STD_ENTRY_DISABLE_POS) & CAN_STD_ENTRY_DISABLE_MASK) == 1)) {						/* Unsed entry */
+			EntryCnt -= 1;
+		}
+	}
+	else if ((SectionID == CANAF_RAM_SFF_GRP_SEC) ||
+			 (SectionID == CANAF_RAM_EFF_SEC)) {
+		EntryCnt = EndRow - StartRow + 1;
+	}
+	else {
+		EntryCnt = (EndRow - StartRow + 1) / 2;
+	}
+	return EntryCnt;
+}
+
+/* Insert an entry into FullCAN Table */
+Status Chip_CAN_InsertFullCANEntry(LPC_CANAF_T *pCANAF,
+								   LPC_CANAF_RAM_T *pCANAFRam,
+								   CAN_STD_ID_ENTRY_T *pEntry) {
+	return insertSTDEntry(pCANAF, pCANAFRam, pEntry, true);
+}
+
+/* Insert an entry into Individual STD section */
+Status Chip_CAN_InsertSTDEntry(LPC_CANAF_T *pCANAF,
+							   LPC_CANAF_RAM_T *pCANAFRam,
+							   CAN_STD_ID_ENTRY_T *pEntry)
+{
+	return insertSTDEntry(pCANAF, pCANAFRam, pEntry, false);
+}
+
+/* Insert an entry into Individual EXT section */
+Status Chip_CAN_InsertEXTEntry(LPC_CANAF_T *pCANAF,
+							   LPC_CANAF_RAM_T *pCANAFRam,
+							   CAN_EXT_ID_ENTRY_T *pEntry) {
+	int32_t IDIndex = 0;
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+	uint16_t i = 0;
+	uint32_t tmp = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	if (getTotalEntryNum(pCANAF) >= CANAF_RAM_ENTRY_NUM) {
+		return ERROR;
+	}
+
+	/* Check if a number of entries in  section is odd or even */
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartRow, &EndRow);
+
+	if (EndRow > StartRow) {
+		EntryCnt = EndRow - StartRow + 1;
+	}
+
+	/* Search for Index of new entry */
+	IDIndex = searchInsertIndex((uint32_t *) &pCANAFRam->MASK[StartRow],
+								EntryCnt,
+								pEntry->ID_29 & CAN_EXT_ENTRY_ID_MASK,
+								CAN_EXT_ENTRY_ID_MASK,
+								sizeof(uint32_t));
+	if ((IDIndex == -1) || (IDIndex > EntryCnt )) {
+		return ERROR;
+	}
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	/* Move all remaining sections one place down
+	            if new entry will increase FullCAN list */
+
+	for (i = getTotalEntryNum(pCANAF); i > (StartRow + IDIndex); i--) {
+		pCANAFRam->MASK[i] = pCANAFRam->MASK[i - 1];
+	}
+
+	/* Insert new item */
+	tmp = createExtIDEntry(pEntry);
+	pCANAFRam->MASK[StartRow + IDIndex] = tmp;
+
+	/* Update address table */
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartRow, &EndRow);
+	setSectionEndAddress(pCANAF, CANAF_RAM_EFF_SEC, EndRow + 2);
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartRow, &EndRow);
+	setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EndRow + 2);
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+	return SUCCESS;
+}
+
+Status Chip_CAN_InsertGroupSTDEntry(LPC_CANAF_T *pCANAF,
+									LPC_CANAF_RAM_T *pCANAFRam,
+									CAN_STD_ID_RANGE_ENTRY_T *pEntry)
+{
+	uint16_t InsertIndex = 0;
+	uint16_t StartRow, EndRow;
+	uint16_t LowerID = 0, UpperID = 0;
+	uint16_t i = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	if (getTotalEntryNum(pCANAF) >= CANAF_RAM_ENTRY_NUM) {
+		return ERROR;
+	}
+
+	getSectionAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, &StartRow, &EndRow);
+
+	/* Search for Index of the entry which upper the new item */
+	for (InsertIndex = StartRow; InsertIndex <= EndRow; InsertIndex++) {
+		LowerID = (pCANAFRam->MASK[InsertIndex] >> (16 + CAN_STD_ENTRY_ID_POS)) & CAN_STD_ENTRY_ID_MASK;
+		UpperID = (pCANAFRam->MASK[InsertIndex] >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK;
+		if (LowerID >= pEntry->LowerID.ID_11) {
+			break;
+		}
+	}
+
+	/* Compare to the previous row (if any)*/
+	if (InsertIndex > 0) {
+		uint16_t PrevUpperID;
+		PrevUpperID = (pCANAFRam->MASK[InsertIndex - 1] >> CAN_STD_ENTRY_ID_POS) & CAN_STD_ENTRY_ID_MASK;
+
+		if (PrevUpperID >= pEntry->UpperID.ID_11) {
+			return SUCCESS;
+		}
+
+		if (pEntry->UpperID.ID_11 < LowerID) {
+			if (pEntry->LowerID.ID_11 < PrevUpperID) {	/* The new range is merged to the range of the previous row */
+				uint32_t val = pCANAFRam->MASK[InsertIndex - 1] & 0xFFFF0000;
+				pCANAFRam->MASK[InsertIndex - 1] = val | createStdIDEntry(&pEntry->UpperID, false);
+				return SUCCESS;
+			}
+			else {
+				goto insert_grp_entry;
+			}
+		}
+	}
+
+	/* Compare to the next row  (if any)*/
+	if ((EndRow) && (InsertIndex <= EndRow)) {
+		if (pEntry->UpperID.ID_11 >= UpperID) {	/* The new range is merged to the range of the next row */
+			uint32_t val;
+			val = createStdIDEntry(&pEntry->LowerID, false) << 16;
+			val |= createStdIDEntry(&pEntry->UpperID, false);
+			pCANAFRam->MASK[InsertIndex] = val;
+			return SUCCESS;
+		}
+		else if (pEntry->UpperID.ID_11 < UpperID) {
+			if (pEntry->UpperID.ID_11 > LowerID) {	/* The new range is merged to the range of the next row */
+				uint32_t val = pCANAFRam->MASK[InsertIndex] & 0x0000FFFF;
+				pCANAFRam->MASK[InsertIndex] = val | (createStdIDEntry(&pEntry->LowerID, false) << 16);
+				return SUCCESS;
+			}
+		}
+	}
+
+insert_grp_entry:
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	/* Move all remaining sections one place down
+	            if new entry will increase FullCAN list */
+
+	for (i = getTotalEntryNum(pCANAF); i > InsertIndex; i--) {
+		pCANAFRam->MASK[i] = pCANAFRam->MASK[i - 1];
+	}
+
+	/* Insert new item */
+	pCANAFRam->MASK[InsertIndex] = createStdIDEntry(&pEntry->LowerID, false) << 16;
+	pCANAFRam->MASK[InsertIndex] |= createStdIDEntry(&pEntry->UpperID, false);
+
+	getSectionAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, &StartRow, &EndRow);
+	setSectionEndAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, EndRow + 2);
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartRow, &EndRow);
+	setSectionEndAddress(pCANAF, CANAF_RAM_EFF_SEC, EndRow + 2);
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartRow, &EndRow);
+	setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EndRow + 2);
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+	return SUCCESS;
+}
+
+Status Chip_CAN_InsertGroupEXTEntry(LPC_CANAF_T *pCANAF,
+									LPC_CANAF_RAM_T *pCANAFRam,
+									CAN_EXT_ID_RANGE_ENTRY_T *pEntry)
+{
+	uint32_t InsertIndex = 0;
+	uint16_t StartRow, EndRow;
+	uint32_t LowerID = 0, UpperID = 0;
+	uint16_t i = 0;
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	if (getTotalEntryNum(pCANAF) >= CANAF_RAM_ENTRY_NUM) {
+		return ERROR;
+	}
+
+	/* Check if a number of entries in  section is odd or even */
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartRow, &EndRow);
+
+	/* Search for Index of new entry */
+	for (InsertIndex = StartRow; InsertIndex <= EndRow; InsertIndex += 2) {
+		LowerID = (pCANAFRam->MASK[InsertIndex] >> CAN_EXT_ENTRY_ID_POS) & CAN_EXT_ENTRY_ID_MASK;
+		UpperID = (pCANAFRam->MASK[InsertIndex + 1] >> CAN_EXT_ENTRY_ID_POS) & CAN_EXT_ENTRY_ID_MASK;
+		if (LowerID >= pEntry->LowerID.ID_29) {
+			break;
+		}
+	}
+
+	/* Compare to the previous row (if any)*/
+	if (InsertIndex > 0) {
+		uint32_t PrevUpperID;
+		PrevUpperID = (pCANAFRam->MASK[(InsertIndex - 2) + 1] >> CAN_EXT_ENTRY_ID_POS) & CAN_EXT_ENTRY_ID_MASK;
+
+		if (PrevUpperID >= pEntry->UpperID.ID_29) {
+			return SUCCESS;
+		}
+
+		if (pEntry->UpperID.ID_29 < LowerID) {
+			if (pEntry->LowerID.ID_29 < PrevUpperID) {
+				pCANAFRam->MASK[(InsertIndex - 2) + 1] = createExtIDEntry(&pEntry->UpperID);
+				return SUCCESS;
+			}
+			else {
+				goto insert_grp_entry;
+			}
+		}
+	}
+
+	if ((EndRow) && (InsertIndex < EndRow)) {
+		if (pEntry->UpperID.ID_29 >= UpperID) {
+			pCANAFRam->MASK[InsertIndex] = createExtIDEntry(&pEntry->LowerID);
+			pCANAFRam->MASK[InsertIndex + 1] = createExtIDEntry(&pEntry->UpperID);
+			return SUCCESS;
+		}
+		else if (pEntry->UpperID.ID_29 < UpperID) {
+			if (pEntry->UpperID.ID_29 > LowerID) {
+				pCANAFRam->MASK[InsertIndex] = createExtIDEntry(&pEntry->LowerID);
+				return SUCCESS;
+			}
+		}
+	}
+
+insert_grp_entry:
+
+	/*  AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	/* Move all remaining sections two places down
+	            if new entry will increase FullCAN list */
+
+	for (i = getTotalEntryNum(pCANAF) + 1; i > InsertIndex; i--) {
+		pCANAFRam->MASK[i] = pCANAFRam->MASK[i - 2];
+	}
+
+	/* Insert new item */
+	pCANAFRam->MASK[InsertIndex] = createExtIDEntry(&pEntry->LowerID);
+	pCANAFRam->MASK[InsertIndex + 1] = createExtIDEntry(&pEntry->UpperID);
+
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartRow, &EndRow);
+	setSectionEndAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, EndRow + 3);
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+	return SUCCESS;
+}
+
+/* Remove an entry into FullCAN Table */
+Status Chip_CAN_RemoveFullCANEntry(LPC_CANAF_T *pCANAF,
+								   LPC_CANAF_RAM_T *pCANAFRam,
+								   int16_t Position) {
+	return removeLUTEntry(pCANAF, pCANAFRam, CANAF_RAM_FULLCAN_SEC, Position);
+}
+
+/* Remove an entry into Individual STD section */
+Status Chip_CAN_RemoveSTDEntry(LPC_CANAF_T *pCANAF,
+							   LPC_CANAF_RAM_T *pCANAFRam,
+							   int16_t Position)
+{
+	return removeLUTEntry(pCANAF, pCANAFRam, CANAF_RAM_SFF_SEC, Position);
+}
+
+/* Remove an entry into Group STD section */
+Status Chip_CAN_RemoveGroupSTDEntry(LPC_CANAF_T *pCANAF,
+									LPC_CANAF_RAM_T *pCANAFRam,
+									int16_t Position)
+{
+	return removeLUTEntry(pCANAF, pCANAFRam, CANAF_RAM_SFF_GRP_SEC, Position);
+}
+
+/* Remove an entry into Individual EXT section */
+Status Chip_CAN_RemoveEXTEntry(LPC_CANAF_T *pCANAF,
+							   LPC_CANAF_RAM_T *pCANAFRam,
+							   int16_t Position) {
+	return removeLUTEntry(pCANAF, pCANAFRam, CANAF_RAM_EFF_SEC, Position);
+}
+
+/* Remove an entry into Group EXT section */
+Status Chip_CAN_RemoveGroupEXTEntry(LPC_CANAF_T *pCANAF,
+									LPC_CANAF_RAM_T *pCANAFRam,
+									int16_t Position)
+{
+	return removeLUTEntry(pCANAF, pCANAFRam, CANAF_RAM_EFF_GRP_SEC, Position);
+}
+
+Status Chip_CAN_ReadFullCANEntry(LPC_CANAF_T *pCANAF,
+								 LPC_CANAF_RAM_T *pCANAFRam,
+								 uint16_t Position,
+								 CAN_STD_ID_ENTRY_T *pEntry)
+{
+	return readSTDEntry(pCANAF, pCANAFRam, Position, true, pEntry);
+}
+
+Status Chip_CAN_ReadSTDEntry(LPC_CANAF_T *pCANAF,
+							 LPC_CANAF_RAM_T *pCANAFRam,
+							 uint16_t Position,
+							 CAN_STD_ID_ENTRY_T *pEntry)
+{
+	return readSTDEntry(pCANAF, pCANAFRam, Position, false, pEntry);
+}
+
+Status Chip_CAN_ReadGroupSTDEntry(LPC_CANAF_T *pCANAF,
+								  LPC_CANAF_RAM_T *pCANAFRam,
+								  uint16_t Position,
+								  CAN_STD_ID_RANGE_ENTRY_T *pEntry)
+{
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+
+	getSectionAddress(pCANAF, CANAF_RAM_SFF_GRP_SEC, &StartRow, &EndRow);
+
+	if (EndRow > StartRow) {
+		EntryCnt = EndRow - StartRow + 1;
+	}
+	if (Position >= EntryCnt) {
+		return ERROR;
+	}
+
+	readStdIDEntry(pCANAFRam->MASK[StartRow + Position] >> 16, &pEntry->LowerID);
+	readStdIDEntry(pCANAFRam->MASK[StartRow + Position] & 0xFFFF, &pEntry->UpperID);
+	return SUCCESS;
+}
+
+Status Chip_CAN_ReadEXTEntry(LPC_CANAF_T *pCANAF,
+							 LPC_CANAF_RAM_T *pCANAFRam,
+							 uint16_t Position,
+							 CAN_EXT_ID_ENTRY_T *pEntry)
+{
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_SEC, &StartRow, &EndRow);
+
+	if (EndRow > StartRow) {
+		EntryCnt = EndRow - StartRow + 1;
+	}
+	if (Position >= EntryCnt) {
+		return ERROR;
+	}
+
+	readExtIDEntry(pCANAFRam->MASK[StartRow + Position], pEntry);
+	return SUCCESS;
+}
+
+Status Chip_CAN_ReadGroupEXTEntry(LPC_CANAF_T *pCANAF,
+								  LPC_CANAF_RAM_T *pCANAFRam,
+								  uint16_t Position,
+								  CAN_EXT_ID_RANGE_ENTRY_T *pEntry)
+
+{
+	uint16_t StartRow, EndRow;
+	uint16_t EntryCnt = 0;
+
+	getSectionAddress(pCANAF, CANAF_RAM_EFF_GRP_SEC, &StartRow, &EndRow);
+
+	if (EndRow > StartRow) {
+		EntryCnt = (EndRow - StartRow + 1) / 2;
+	}
+	if (Position >= EntryCnt) {
+		return ERROR;
+	}
+
+	readExtIDEntry(pCANAFRam->MASK[StartRow + Position * 2], &pEntry->LowerID);
+	readExtIDEntry(pCANAFRam->MASK[StartRow + Position * 2 + 1], &pEntry->UpperID);
+	return SUCCESS;
+}
+
+/* Send CAN Message */
+Status Chip_CAN_Send(LPC_CAN_T *pCAN, CAN_BUFFER_ID_T TxBufID, CAN_MSG_T *pMsg)
+{
+	uint8_t i = 0;
+	LPC_CAN_TX_T TxFrame;
+
+	/* Write Frame Information */
+	TxFrame.TFI = 0;
+	if (pMsg->Type & CAN_REMOTE_MSG) {
+		TxFrame.TFI |= CAN_TFI_RTR;
+	}
+	else {
+		TxFrame.TFI |= CAN_TFI_DLC(pMsg->DLC);
+		for (i = 0; i < (CAN_MSG_MAX_DATA_LEN + 3) / 4; i++) {
+			TxFrame.TD[i] =
+				pMsg->Data[4 *
+						   i] |
+				(pMsg->Data[4 * i +
+							1] << 8) | (pMsg->Data[4 * i + 2] << 16) | (pMsg->Data[4 * i + 3] << 24);
+		}
+	}
+
+	if (pMsg->ID & CAN_EXTEND_ID_USAGE) {
+		TxFrame.TFI |= CAN_TFI_FF;
+		TxFrame.TID = CAN_TID_ID29(pMsg->ID);
+	}
+	else {
+		TxFrame.TID = CAN_TID_ID11(pMsg->ID);
+	}
+
+	/* Set message information */
+	setSendFrameInfo(pCAN, TxBufID, &TxFrame);
+
+	/* Select buffer and Write Transmission Request */
+	if (Chip_CAN_GetMode(pCAN) == CAN_SELFTEST_MODE) {
+		Chip_CAN_SetCmd(pCAN, CAN_CMR_STB(TxBufID) | CAN_CMR_SRR);
+	}
+	else {
+		Chip_CAN_SetCmd(pCAN, CAN_CMR_STB(TxBufID) | CAN_CMR_TR);
+	}
+
+	return SUCCESS;
+}
+
+/* Receive CAN Message */
+Status Chip_CAN_Receive(LPC_CAN_T *pCAN, CAN_MSG_T *pMsg) {
+	int8_t i;
+	IP_CAN_001_RX_T RxFrame;
+	if (getReceiveFrameInfo(pCAN, &RxFrame) == SUCCESS) {
+
+		/* Read Message Identifier */
+		if (RxFrame.RFS & CAN_RFS_FF) {
+			pMsg->ID = CAN_EXTEND_ID_USAGE | CAN_RID_ID_29(RxFrame.RID);
+		}
+		else {
+			pMsg->ID = CAN_RID_ID_11(RxFrame.RID);
+		}
+
+		/* Read Data Length */
+		pMsg->DLC = CAN_RFS_DLC(RxFrame.RFS);
+
+		/* Read Message Type */
+		pMsg->Type = 0;
+		if (RxFrame.RFS & CAN_RFS_RTR) {
+			pMsg->Type |= CAN_REMOTE_MSG;
+		}
+		else {
+			/* Read data only if the received message is not Remote message */
+			for (i = 0; i < CAN_MSG_MAX_DATA_LEN; i++) {
+				pMsg->Data[i] = (RxFrame.RD[i / 4] >> (8 * (i % 4))) & 0xFF;
+			}
+		}
+
+		/* Release received message */
+		Chip_CAN_SetCmd(pCAN, CAN_CMR_RRB);
+
+		return SUCCESS;
+	}
+	return ERROR;
+}
+
+/* Enable/Disable FullCAN interrupt */
+void Chip_CAN_ConfigFullCANInt(LPC_CANAF_T *pCANAF, FunctionalState NewState)
+{
+	CAN_AF_MODE_T CurMode = Chip_CAN_GetAFMode(pCANAF);
+
+	/* AF Off */
+	Chip_CAN_SetAFMode(pCANAF, CAN_AF_OFF_MODE);
+
+	if (NewState == ENABLE) {
+		pCANAF->FCANIE |= CANAF_FCANIE;
+	}
+	else {
+		pCANAF->FCANIE &= (~CANAF_FCANIE) & CANAF_FCANIE_BITMASK;
+	}
+
+	/* Return to previous mode */
+	Chip_CAN_SetAFMode(pCANAF, CurMode);
+}
+
+/* Get interrupt status of the given object */
+uint32_t Chip_CAN_GetFullCANIntStatus(LPC_CANAF_T *pCANAF, uint8_t ObjID)
+{
+	if (ObjID < 64) {
+		return (pCANAF->FCANIC[ObjID / 32] & (1 << (ObjID % 32))) ? SET : RESET;
+	}
+	return RESET;
+}
+
+/* Read FullCAN message received */
+Status Chip_CAN_FullCANReceive(LPC_CANAF_T *pCANAF, LPC_CANAF_RAM_T *pCANAFRam
+							   , uint8_t ObjID, CAN_MSG_T *pMsg, uint8_t *pSCC) {
+	uint32_t    *pSrc;
+	uint16_t    FullCANEntryCnt;
+	pSrc = (uint32_t *) pCANAFRam;
+
+	FullCANEntryCnt = getTotalEntryNum(pCANAF);
+	pSrc += FullCANEntryCnt + ObjID * 3;
+	/* If the AF hasn't finished updating msg info */
+	if (((pSrc[0] >> CANAF_FULLCAN_MSG_SEM_POS) & CANAF_FULLCAN_MSG_SEM_BITMASK) !=
+		CANAF_FULCAN_MSG_AF_FINISHED) {
+		return ERROR;
+	}
+
+	/* Mark that CPU is handling message */
+	pSrc[0] = CANAF_FULCAN_MSG_CPU_READING << CANAF_FULLCAN_MSG_SEM_POS;
+
+	/* Read Message */
+	*pSCC = (pSrc[0] >> CANAF_FULLCAN_MSG_SCC_POS) & CANAF_FULLCAN_MSG_SCC_BITMASK;
+	pMsg->ID = (pSrc[0] >> CANAF_FULLCAN_MSG_ID11_POS) & CANAF_FULLCAN_MSG_ID11_BITMASK;
+	pMsg->Type = 0;
+	if (pSrc[0] & (1 << CANAF_FULLCAN_MSG_RTR_POS)) {
+		pMsg->Type = CAN_REMOTE_MSG;
+	}
+	pMsg->DLC = (pSrc[0] >> CANAF_FULLCAN_MSG_DLC_POS) & CANAF_FULLCAN_MSG_DLC_BITMASK;
+	((uint32_t *) pMsg->Data)[0] = pSrc[1];
+	((uint32_t *) pMsg->Data)[1] = pSrc[2];
+
+	/* Recheck message status to make sure data is not be updated while CPU is reading */
+	if (((pSrc[0] >> CANAF_FULLCAN_MSG_SEM_POS) & CANAF_FULLCAN_MSG_SEM_BITMASK) !=
+		CANAF_FULCAN_MSG_CPU_READING) {
+		return ERROR;
+	}
+
+	return SUCCESS;
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c
new file mode 100644
index 000000000..0936096cd
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c
@@ -0,0 +1,110 @@
+/*
+ * @brief LPC17xx/40xx Miscellaneous chip specific functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/* System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetSystemClockRate();
+}
+
+/* Sets up USB PLL, all needed clocks and enables USB PHY on the chip. USB pins which are
+	muxed to different pads are not initialized here. This routine assumes that the XTAL 
+	OSC is enabled and running prior to this call. */
+void Chip_USB_Init(void)
+{
+
+#if defined(CHIP_LPC175X_6X)
+	/* Setup USB PLL1 for a 48MHz clock
+	   Input clock rate (FIN) is main oscillator = 12MHz
+	   PLL1 Output = USBCLK = 48MHz = FIN * MSEL, so MSEL = 4.
+	   FCCO = USBCLK = USBCLK * 2 * P. It must be between 156 MHz to 320 MHz.
+	   so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
+	Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1);	/* Multiply by 4, Divide by 2 */
+
+	/* Use PLL1 output as USB Clock Source */
+	/* Enable PLL1 */
+	Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
+
+	/* Wait for PLL1 to lock */
+	while (!Chip_Clock_IsUSBPLLLocked()) {}
+
+	/* Connect PLL1 */
+	Chip_Clock_EnablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT);
+
+	/* Wait for PLL1 to be connected */
+	while (!Chip_Clock_IsUSBPLLConnected()) {}
+
+#else
+
+	/* Select XTAL as clock source for USB block and divider as 1 */
+	LPC_SYSCTL->USBCLKSEL = 0x1;
+	/* Setup USB PLL1 for a 48MHz clock
+	   Input clock rate (FIN) is main oscillator = 12MHz
+	   PLL output = 48MHz = FIN * MSEL, so MSEL = 4
+	   FCCO must be between 156 MHz to 320 MHz, where FCCO = PLL output * 2 * P,
+	   so P = 2 and FCCO = 48MHz * 2 * 2 = 192MHz */
+	Chip_Clock_SetupPLL(SYSCTL_USB_PLL, 3, 1);  
+
+	/* Wait for USB PLL to lock */
+	while ((Chip_Clock_GetPLLStatus(SYSCTL_USB_PLL) & SYSCTL_PLLSTS_LOCKED) == 0) {}
+
+	/* Select PLL1/USBPLL as clock source for USB block and divider as 1 */
+	LPC_SYSCTL->USBCLKSEL = (SYSCTL_USBCLKSRC_USBPLL << 8) | 0x01;
+
+#endif /* defined(CHIP_LPC175X_6X) */
+
+	/* Enable AHB clock to the USB block and USB RAM. */
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
+
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c
new file mode 100644
index 000000000..42e4d7cc8
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c
@@ -0,0 +1,516 @@
+/*
+ * @brief	LPC17xx/40xx System and Control driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Enables or connects a PLL */
+void Chip_Clock_EnablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags) {
+	uint32_t temp;
+
+	temp = LPC_SYSCTL->PLL[PLLNum].PLLCON;
+	temp |= flags;
+	LPC_SYSCTL->PLL[PLLNum].PLLCON = temp;
+	Chip_Clock_FeedPLL(PLLNum);
+}
+
+/* Disables or disconnects a PLL */
+void Chip_Clock_DisablePLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t flags) {
+	uint32_t temp;
+
+	temp = LPC_SYSCTL->PLL[PLLNum].PLLCON;
+	temp &= ~flags;
+	LPC_SYSCTL->PLL[PLLNum].PLLCON = temp;
+	Chip_Clock_FeedPLL(PLLNum);
+}
+
+/* Sets up a PLL */
+void Chip_Clock_SetupPLL(CHIP_SYSCTL_PLL_T PLLNum, uint32_t msel, uint32_t psel) {
+	uint32_t PLLcfg;
+
+#if defined(CHIP_LPC175X_6X)
+	/* PLL0 and PLL1 are slightly different */
+	if (PLLNum == SYSCTL_MAIN_PLL) {
+		PLLcfg = (msel) | (psel << 16);
+	}
+	else {
+		PLLcfg = (msel) | (psel << 5);
+	}
+
+#else
+	PLLcfg = (msel) | (psel << 5);
+#endif
+
+	LPC_SYSCTL->PLL[PLLNum].PLLCFG = PLLcfg;
+	LPC_SYSCTL->PLL[PLLNum].PLLCON = 0x1;
+	Chip_Clock_FeedPLL(PLLNum);
+}
+
+/* Enables power and clocking for a peripheral */
+void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk) {
+	uint32_t bs = (uint32_t) clk;
+
+#if defined(CHIP_LPC40XX)
+	if (bs >= 32) {
+		LPC_SYSCTL->PCONP1 |= (1 << (bs - 32));
+	}
+	else {
+		LPC_SYSCTL->PCONP |= (1 << bs);
+	}
+#else
+	LPC_SYSCTL->PCONP |= (1 << bs);
+#endif
+}
+
+/* Disables power and clocking for a peripheral */
+void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk) {
+	uint32_t bs = (uint32_t) clk;
+
+#if defined(CHIP_LPC40XX)
+	if (bs >= 32) {
+		LPC_SYSCTL->PCONP1 &= ~(1 << (bs - 32));
+	}
+	else {
+		LPC_SYSCTL->PCONP |= ~(1 << bs);
+	}
+#else
+	LPC_SYSCTL->PCONP |= ~(1 << bs);
+#endif
+}
+
+/* Returns power enables state for a peripheral */
+bool Chip_Clock_IsPeripheralClockEnabled(CHIP_SYSCTL_CLOCK_T clk)
+{
+	uint32_t bs = (uint32_t) clk;
+
+#if defined(CHIP_LPC40XX)
+	if (bs >= 32) {
+		bs = LPC_SYSCTL->PCONP1 & (1 << (bs - 32));
+	}
+	else {
+		bs = LPC_SYSCTL->PCONP & (1 << bs);
+	}
+#else
+	bs = LPC_SYSCTL->PCONP & (1 << bs);
+#endif
+
+	return (bool) (bs != 0);
+}
+
+/* Sets the current CPU clock source */
+void Chip_Clock_SetCPUClockSource(CHIP_SYSCTL_CCLKSRC_T src)
+{
+#if defined(CHIP_LPC175X_6X)
+	/* LPC175x/6x CPU clock source is based on PLL connect status */
+	if (src == SYSCTL_CCLKSRC_MAINPLL) {
+		/* Connect PLL0 */
+		Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
+	}
+	else {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
+	}
+#else
+	/* LPC177x/8x and 407x/8x CPU clock source is based on CCLKSEL */
+	if (src == SYSCTL_CCLKSRC_MAINPLL) {
+		/* Connect PLL0 */
+		LPC_SYSCTL->CCLKSEL |= (1 << 8);
+	}
+	else {
+		LPC_SYSCTL->CCLKSEL &= ~(1 << 8);
+	}
+#endif
+}
+
+/* Returns the current CPU clock source */
+CHIP_SYSCTL_CCLKSRC_T Chip_Clock_GetCPUClockSource(void)
+{
+	CHIP_SYSCTL_CCLKSRC_T src;
+#if defined(CHIP_LPC175X_6X)
+	/* LPC175x/6x CPU clock source is based on PLL connect status */
+	if (Chip_Clock_IsMainPLLConnected()) {
+		src = SYSCTL_CCLKSRC_MAINPLL;
+	}
+	else {
+		src = SYSCTL_CCLKSRC_SYSCLK;
+	}
+#else
+	/* LPC177x/8x and 407x/8x CPU clock source is based on CCLKSEL */
+	if (LPC_SYSCTL->CCLKSEL & (1 << 8)) {
+		src = SYSCTL_CCLKSRC_MAINPLL;
+	}
+	else {
+		src = SYSCTL_CCLKSRC_SYSCLK;
+	}
+#endif
+
+	return src;
+}
+
+/* Selects the CPU clock divider */
+void Chip_Clock_SetCPUClockDiv(uint32_t div)
+{
+#if defined(CHIP_LPC175X_6X)
+	LPC_SYSCTL->CCLKSEL = div;
+#else
+	uint32_t temp;
+
+	/* Save state of CPU clock source bit */
+	temp = LPC_SYSCTL->CCLKSEL & (1 << 8);
+	LPC_SYSCTL->CCLKSEL = temp | div;
+#endif
+}
+
+/* Gets the CPU clock divider */
+uint32_t Chip_Clock_GetCPUClockDiv(void)
+{
+#if defined(CHIP_LPC175X_6X)
+	return (LPC_SYSCTL->CCLKSEL & 0xFF) + 1;
+#else
+	return LPC_SYSCTL->CCLKSEL & 0x1F;
+#endif
+}
+
+#if !defined(CHIP_LPC175X_6X)
+/* Selects the USB clock divider source */
+void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src)
+{
+	uint32_t temp;
+
+	/* Mask out current source, but keep divider */
+	temp = LPC_SYSCTL->USBCLKSEL & ~(0x3 << 8);
+	LPC_SYSCTL->USBCLKSEL = temp | (((uint32_t) src) << 8);
+}
+
+#endif
+
+/* Sets the USB clock divider */
+void Chip_Clock_SetUSBClockDiv(uint32_t div)
+{
+	uint32_t temp;
+
+	/* Mask out current divider */
+#if defined(CHIP_LPC175X_6X)
+	temp = LPC_SYSCTL->USBCLKSEL & ~(0xF);
+#else
+	temp = LPC_SYSCTL->USBCLKSEL & ~(0x1F);
+#endif
+	LPC_SYSCTL->USBCLKSEL = temp | div;
+}
+
+/* Gets the USB clock divider */
+uint32_t Chip_Clock_GetUSBClockDiv(void)
+{
+#if defined(CHIP_LPC175X_6X)
+	return (LPC_SYSCTL->USBCLKSEL & 0xF) + 1;
+#else
+	return (LPC_SYSCTL->USBCLKSEL & 0x1F) + 1;
+#endif
+}
+
+#if defined(CHIP_LPC175X_6X)
+/* Selects a clock divider for a peripheral */
+void Chip_Clock_SetPCLKDiv(CHIP_SYSCTL_PCLK_T clk, CHIP_SYSCTL_CLKDIV_T div)
+{
+	uint32_t temp, bitIndex, regIndex = (uint32_t) clk;
+
+	/* Get register array index and clock index into the register */
+	bitIndex = ((regIndex % 16) * 2);
+	regIndex = regIndex / 16;
+
+	/* Mask and update register */
+	temp = LPC_SYSCTL->PCLKSEL[regIndex] & ~(0x3 << bitIndex);
+	temp |= (((uint32_t) div) << bitIndex);
+	LPC_SYSCTL->PCLKSEL[regIndex] = temp;
+}
+
+/* Gets a clock divider for a peripheral */
+uint32_t Chip_Clock_GetPCLKDiv(CHIP_SYSCTL_PCLK_T clk)
+{
+	uint32_t div = 1, bitIndex, regIndex = ((uint32_t) clk) * 2;
+
+	/* Get register array index and clock index into the register */
+	bitIndex = regIndex % 32;
+	regIndex = regIndex / 32;
+
+	/* Mask and update register */
+	div = LPC_SYSCTL->PCLKSEL[regIndex];
+	div = (div >> bitIndex) & 0x3;
+	if (div == SYSCTL_CLKDIV_4) {
+		div = 4;
+	}
+	else if (div == SYSCTL_CLKDIV_1) {
+		div = 1;
+	}
+	else if (div == SYSCTL_CLKDIV_2) {
+		div = 2;
+	}
+	else {
+		/* Special case for CAN clock divider */
+		if ((clk == SYSCTL_PCLK_CAN1) || (clk == SYSCTL_PCLK_CAN2) || (clk == SYSCTL_PCLK_ACF)) {
+			div = 6;
+		}
+		else {
+			div = 8;
+		}
+	}
+
+	return div;
+}
+
+#endif
+
+/* Selects a source clock and divider rate for the CLKOUT pin */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src,
+								uint32_t div)
+{
+	uint32_t temp;
+
+	temp = LPC_SYSCTL->CLKOUTCFG & ~0x1FF;
+	temp |= ((uint32_t) src) | ((div - 1) << 4);
+	LPC_SYSCTL->CLKOUTCFG = temp;
+}
+
+/* Returns the current SYSCLK clock rate */
+uint32_t Chip_Clock_GetSYSCLKRate(void)
+{
+	/* Determine clock input rate to SYSCLK based on input selection */
+	switch (Chip_Clock_GetMainPLLSource()) {
+	case (uint32_t) SYSCTL_PLLCLKSRC_IRC:
+		return Chip_Clock_GetIntOscRate();
+
+	case (uint32_t) SYSCTL_PLLCLKSRC_MAINOSC:
+		return Chip_Clock_GetMainOscRate();
+
+#if defined(CHIP_LPC175X_6X)
+	case (uint32_t) SYSCTL_PLLCLKSRC_RTC:
+		return Chip_Clock_GetRTCOscRate();
+#endif
+	}
+	return 0;
+}
+
+/* Returns the main PLL output clock rate */
+uint32_t Chip_Clock_GetMainPLLOutClockRate(void)
+{
+	uint32_t clkhr = 0;
+
+#if defined(CHIP_LPC175X_6X)
+	/* Only valid if enabled */
+	if (Chip_Clock_IsMainPLLEnabled()) {
+		uint32_t msel, nsel;
+
+		/* PLL0 rate is (FIN * 2 * MSEL) / NSEL, get MSEL and NSEL */
+		msel = 1 + (LPC_SYSCTL->PLL[SYSCTL_MAIN_PLL].PLLCFG & 0x7FFF);
+		nsel = 1 + ((LPC_SYSCTL->PLL[SYSCTL_MAIN_PLL].PLLCFG >> 16) & 0xFF);
+		clkhr = (Chip_Clock_GetMainPLLInClockRate() * 2 * msel) / nsel;
+	}
+#else
+	if (Chip_Clock_IsMainPLLEnabled()) {
+		uint32_t msel;
+
+		/* PLL0 rate is (FIN * MSEL) */
+		msel = 1 + (LPC_SYSCTL->PLL[SYSCTL_MAIN_PLL].PLLCFG & 0x1F);
+		clkhr = (Chip_Clock_GetMainPLLInClockRate() * msel);
+	}
+#endif
+
+	return (uint32_t) clkhr;
+}
+
+/* Get USB output clock rate */
+uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
+{
+	uint32_t clkhr = 0;
+
+	/* Only valid if enabled */
+	if (Chip_Clock_IsUSBPLLEnabled()) {
+		uint32_t msel;
+
+		/* PLL1 input clock (FIN) is always main oscillator */
+		/* PLL1 rate is (FIN * MSEL) */
+		msel = 1 + (LPC_SYSCTL->PLL[SYSCTL_USB_PLL].PLLCFG & 0x1F);
+		clkhr = (Chip_Clock_GetUSBPLLInClockRate() * msel);
+	}
+
+	return (uint32_t) clkhr;
+}
+
+/* Get the main clock rate */
+/* On 175x/6x devices, this is the input clock to the CPU divider.
+   Additionally, on 177x/8x and 407x/8x devices, this is also the
+   input clock to the peripheral divider. */
+uint32_t Chip_Clock_GetMainClockRate(void)
+{
+	switch (Chip_Clock_GetCPUClockSource()) {
+	case SYSCTL_CCLKSRC_MAINPLL:
+		return Chip_Clock_GetMainPLLOutClockRate();
+
+	case SYSCTL_CCLKSRC_SYSCLK:
+		return Chip_Clock_GetSYSCLKRate();
+
+	default:
+		return 0;
+	}
+}
+
+/* Get CCLK rate */
+uint32_t Chip_Clock_GetSystemClockRate(void)
+{
+	return Chip_Clock_GetMainClockRate() / Chip_Clock_GetCPUClockDiv();
+}
+
+/* Returns the USB clock (USB_CLK) rate */
+uint32_t Chip_Clock_GetUSBClockRate(void)
+{
+	uint32_t div, clkrate;
+#if defined(CHIP_LPC175X_6X)
+	/* The USB clock rate is derived from PLL1 or PLL0 */
+	if (Chip_Clock_IsUSBPLLConnected()) {
+		/* Use PLL1 clock for USB source with divider of 1 */
+		clkrate = Chip_Clock_GetUSBPLLOutClockRate();
+		div = 1;
+	}
+	else {
+		clkrate = Chip_Clock_GetMainClockRate();
+		div = Chip_Clock_GetUSBClockDiv();
+	}
+
+#else
+	/* Get clock from source drving USB */
+	switch (Chip_Clock_GetUSBClockSource()) {
+	case SYSCTL_USBCLKSRC_SYSCLK:
+	default:
+		clkrate = Chip_Clock_GetSYSCLKRate();
+		break;
+
+	case SYSCTL_USBCLKSRC_MAINPLL:
+		clkrate = Chip_Clock_GetMainPLLOutClockRate();
+		break;
+
+	case SYSCTL_USBCLKSRC_USBPLL:
+		clkrate = Chip_Clock_GetUSBPLLOutClockRate();
+		break;
+	}
+
+	div = Chip_Clock_GetUSBClockDiv();
+#endif
+
+	return clkrate / div;
+}
+
+#if !defined(CHIP_LPC175X_6X)
+/* Selects the SPIFI clock divider source */
+void Chip_Clock_SetSPIFIClockSource(CHIP_SYSCTL_SPIFICLKSRC_T src)
+{
+	uint32_t temp;
+
+	/* Mask out current source, but keep divider */
+	temp = LPC_SYSCTL->SPIFICLKSEL & ~(0x3 << 8);
+	LPC_SYSCTL->SPIFICLKSEL = temp | (((uint32_t) src) << 8);
+}
+
+/* Sets the SPIFI clock divider */
+void Chip_Clock_SetSPIFIClockDiv(uint32_t div)
+{
+	uint32_t temp;
+
+	/* Mask out current divider */
+	temp = LPC_SYSCTL->SPIFICLKSEL & ~(0x1F);
+	LPC_SYSCTL->SPIFICLKSEL = temp | div;
+}
+
+/* Returns the SPIFI clock rate */
+uint32_t Chip_Clock_GetSPIFIClockRate(void)
+{
+	uint32_t div, clkrate;
+
+	/* Get clock from source drving USB */
+	switch (Chip_Clock_GetSPIFIClockSource()) {
+	case SYSCTL_SPIFICLKSRC_SYSCLK:
+	default:
+		clkrate = Chip_Clock_GetSYSCLKRate();
+		break;
+
+	case SYSCTL_SPIFICLKSRC_MAINPLL:
+		clkrate = Chip_Clock_GetMainPLLOutClockRate();
+		break;
+
+	case SYSCTL_SPIFICLKSRC_USBPLL:
+		clkrate = Chip_Clock_GetUSBPLLOutClockRate();
+		break;
+	}
+
+	div = Chip_Clock_GetSPIFIClockDiv();
+
+	return clkrate / div;
+}
+
+#endif
+
+#if defined(CHIP_LPC175X_6X)
+/* Returns the clock rate for a peripheral */
+uint32_t Chip_Clock_GetPeripheralClockRate(CHIP_SYSCTL_PCLK_T clk) {
+	/* 175x/6x clock is derived from CPU clock with CPU divider */
+	return Chip_Clock_GetSystemClockRate() / Chip_Clock_GetPCLKDiv(clk);
+}
+
+#else
+/* Returns the clock rate for all peripherals */
+uint32_t Chip_Clock_GetPeripheralClockRate(void)
+{
+	uint32_t clkrate = 0, div;
+
+	/* Get divider, a divider of 0 means the clock is disabled */
+	div = Chip_Clock_GetPCLKDiv();
+	if (div != 0) {
+		/* Derived from periperhal clock input and peripheral clock divider */
+		clkrate = Chip_Clock_GetMainClockRate() / div;
+	}
+
+	return clkrate;
+}
+
+#endif
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/cmp_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/cmp_17xx_40xx.c
new file mode 100644
index 000000000..cee9e43ee
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/cmp_17xx_40xx.c
@@ -0,0 +1,64 @@
+/*
+ * @brief LPC17xx/40xx Comparator driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the CMP */
+void Chip_CMP_Init(void)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_CMP);
+}
+
+/* De-initializes the CMP */
+void Chip_CMP_DeInit(void)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_CMP);
+}
+
+#endif /* defined(CHIP_LPC40XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/crc_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/crc_17xx_40xx.c
new file mode 100644
index 000000000..4a44969a7
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/crc_17xx_40xx.c
@@ -0,0 +1,110 @@
+/*
+ * @brief LPC17xx/40xx Cyclic Redundancy Check (CRC) Engine driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Sets up the CRC engine with defaults based on the polynomial to be used */
+void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly)
+{
+	switch (poly) {
+	case CRC_POLY_CRC16:
+		LPC_CRC->MODE = MODE_CFG_CRC16;
+		LPC_CRC->SEED = CRC_SEED_CRC16;
+		break;
+
+	case CRC_POLY_CRC32:
+		LPC_CRC->MODE = MODE_CFG_CRC32;
+		LPC_CRC->SEED = CRC_SEED_CRC32;
+		break;
+
+	case CRC_POLY_CCITT:
+	default:
+		LPC_CRC->MODE = MODE_CFG_CCITT;
+		LPC_CRC->SEED = CRC_SEED_CCITT;
+		break;
+	}
+}
+
+/* configure CRC engine and compute CCITT checksum from 8-bit data */
+uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes)
+{
+	Chip_CRC_UseDefaultConfig(CRC_POLY_CCITT);
+	while (bytes > 0) {
+		Chip_CRC_Write8(*data);
+		data++;
+		bytes--;
+	}
+	return Chip_CRC_Sum();
+}
+
+/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */
+uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords)
+{
+	Chip_CRC_UseDefaultConfig(CRC_POLY_CRC16);
+	while (hwords > 0) {
+		Chip_CRC_Write16(*data);
+		data++;
+		hwords--;
+	}
+	return Chip_CRC_Sum();
+}
+
+/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */
+uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words)
+{
+	Chip_CRC_UseDefaultConfig(CRC_POLY_CRC32);
+	while (words > 0) {
+		Chip_CRC_Write32(*data);
+		data++;
+		words--;
+	}
+	return Chip_CRC_Sum();
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/dac_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/dac_17xx_40xx.c
new file mode 100644
index 000000000..4387b0234
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/dac_17xx_40xx.c
@@ -0,0 +1,84 @@
+/*
+ * @brief LPC17xx/40xx D/A conversion driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the DAC peripheral */
+void Chip_DAC_Init(LPC_DAC_T *pDAC)
+{
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	Chip_SYSCTL_PeriphReset(SYSCTL_RESET_DAC);
+#endif
+
+	/* Set maximum update rate 1MHz */
+	Chip_DAC_SetBias(pDAC, DAC_MAX_UPDATE_RATE_1MHz);
+}
+
+/* Shutdown DAC peripheral */
+void Chip_DAC_DeInit(LPC_DAC_T *pDAC)
+{}
+
+/* Update value to DAC buffer*/
+void Chip_DAC_UpdateValue(LPC_DAC_T *pDAC, uint32_t dac_value)
+{
+	uint32_t tmp;
+
+	tmp = pDAC->CR & DAC_BIAS_EN;
+	tmp |= DAC_VALUE(dac_value);
+	/* Update value */
+	pDAC->CR = tmp;
+}
+
+/* Set Maximum update rate for DAC */
+void Chip_DAC_SetBias(LPC_DAC_T *pDAC, uint32_t bias)
+{
+	pDAC->CR &= ~DAC_BIAS_EN;
+
+	if (bias  == DAC_MAX_UPDATE_RATE_400kHz) {
+		pDAC->CR |= DAC_BIAS_EN;
+	}
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/eeprom_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/eeprom_17xx_40xx.c
new file mode 100644
index 000000000..abad37880
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/eeprom_17xx_40xx.c
@@ -0,0 +1,258 @@
+/*
+ * @brief LPC17xx/40xx EEPROM driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+/* Setup EEPROM clock */
+STATIC void setClkDiv(LPC_EEPROM_T *pEEPROM)
+{
+	uint32_t clk;
+
+	/* Setup EEPROM timing to 375KHz based on PCLK rate */
+	clk = Chip_Clock_GetSystemClockRate();
+
+	/* Set EEPROM clock divide value*/
+	pEEPROM->CLKDIV = clk / 375000 - 1;
+}
+
+/* Setup EEPROM clock */
+STATIC void setWaitState(LPC_EEPROM_T *pEEPROM)
+{
+	uint32_t val, clk;
+
+	/* Setup EEPROM timing to 375KHz based on PCLK rate */
+	clk = Chip_Clock_GetSystemClockRate();
+
+	/* Setup EEPROM wait states to 15, 35, 35nS */
+	val  = ((((clk / 1000000) * 15) / 1000) + 1);
+	val |= (((((clk / 1000000) * 55) / 1000) + 1) << 8);
+	val |= (((((clk / 1000000) * 35) / 1000) + 1) << 16);
+	Chip_EEPROM_SetWaitState(pEEPROM, val);
+
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the EEPROM peripheral with specified parameter */
+void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM)
+{
+	Chip_EEPROM_DisablePowerDown(pEEPROM);
+	setClkDiv(pEEPROM);
+	setWaitState(pEEPROM);
+}
+
+/* Wait for interrupt */
+void Chip_EEPROM_WaitForIntStatus(LPC_EEPROM_T *pEEPROM, uint32_t mask)
+{
+	uint32_t status;
+
+	while (1) {
+		status = Chip_EEPROM_GetIntStatus(pEEPROM);
+		if ((status & mask) == mask) {
+			break;
+		}
+	}
+
+	Chip_EEPROM_ClearIntStatus(pEEPROM, mask);
+}
+
+/* Erase data in page register */
+void Chip_EEPROM_ErasePageRegister(LPC_EEPROM_T *pEEPROM)
+{
+	uint32_t i = 0;
+
+	Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
+
+	Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_32BITS_WRITE);
+
+	Chip_EEPROM_SetAddr(pEEPROM, 0, 0);
+
+	for (i = 0; i < EEPROM_PAGE_SIZE; i += 4) {
+		Chip_EEPROM_WriteData(pEEPROM, 0);
+		Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
+	}
+
+}
+
+/* Write data to page register */
+uint32_t Chip_EEPROM_WritePageRegister(LPC_EEPROM_T *pEEPROM, uint16_t pageOffset,
+									   uint8_t *pData, uint8_t wsize, uint32_t byteNum)
+{
+	uint32_t i = 0;
+	uint32_t mask = (1 << (8 * wsize)) - 1;
+
+	Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
+
+	if (wsize == 1) {
+		Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_8BITS_WRITE);
+	}
+	else if (wsize == 2) {
+		Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_16BITS_WRITE);
+	}
+	else {
+		Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_32BITS_WRITE);
+	}
+
+	Chip_EEPROM_SetAddr(pEEPROM, 0, pageOffset);
+
+	for (i = 0; i < byteNum; i += wsize) {
+		Chip_EEPROM_WriteData(pEEPROM, (*(uint32_t *) (&pData[i])) & mask);
+		Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
+	}
+
+	return i;
+}
+
+/* Write data from page register to non-volatile memory */
+void Chip_EEPROM_EraseProgramPage(LPC_EEPROM_T *pEEPROM, uint16_t pageAddr)
+{
+	Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_CMD_ERASE_PRG_PAGE);
+	Chip_EEPROM_SetAddr(pEEPROM, pageAddr, 0);
+	Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_ERASE_PRG_PAGE);
+	Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFPROG);
+}
+
+/* Read data from non-volatile memory */
+uint32_t Chip_EEPROM_ReadPage(LPC_EEPROM_T *pEEPROM,
+							  uint16_t pageOffset,
+							  uint16_t pageAddr,
+							  uint8_t *pData,
+							  uint8_t rsize,
+							  uint32_t byteNum)
+{
+	uint32_t i;
+	uint32_t mask = (1 << (8 * rsize)) - 1;
+
+	Chip_EEPROM_ClearIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
+	Chip_EEPROM_SetAddr(pEEPROM, pageAddr, pageOffset);
+
+	if (rsize == 1) {
+		Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_8BITS_READ | EEPROM_CMD_RDPREFETCH);
+	}
+	else if (rsize == 2) {
+		Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_16BITS_READ | EEPROM_CMD_RDPREFETCH);
+	}
+	else {
+		Chip_EEPROM_SetCmd(pEEPROM, EEPROM_CMD_32BITS_READ | EEPROM_CMD_RDPREFETCH);
+	}
+
+	/* read and store data in buffer */
+	for (i = 0; i < byteNum; i += rsize) {
+		(*(uint32_t *) (&pData[i]) ) &= ~mask;
+		(*(uint32_t *) (&pData[i]) ) |= (Chip_EEPROM_ReadData(pEEPROM) & mask);
+		Chip_EEPROM_WaitForIntStatus(pEEPROM, EEPROM_INT_ENDOFRW);
+	}
+	return i;
+}
+
+/* Write data to EEPROM at specific address */
+Status Chip_EEPROM_Write(LPC_EEPROM_T *pEEPROM,
+						 uint16_t pageOffset,
+						 uint16_t pageAddr,
+						 void *pData,
+						 EEPROM_RWSIZE_T wsize,
+						 uint32_t byteNum)
+{
+	uint32_t wTotalByteNum = 0;
+	uint32_t wOffset = (pageOffset & (EEPROM_PAGE_SIZE - 1));
+	uint32_t wByteNum = EEPROM_PAGE_SIZE - wOffset;
+	while (byteNum) {
+		if (wByteNum > byteNum) {
+			wByteNum = byteNum;
+		}
+		/* update data to page register */
+		Chip_EEPROM_WritePageRegister(pEEPROM, wOffset,
+									  &((uint8_t *) pData)[wTotalByteNum], (uint8_t) wsize, wByteNum);
+		Chip_EEPROM_EraseProgramPage(pEEPROM, pageAddr);
+		wTotalByteNum += wByteNum;
+		byteNum -= wByteNum;
+
+		/* Change to next page */
+		pageAddr++;
+		wOffset = 0;
+		wByteNum = EEPROM_PAGE_SIZE;
+	}
+	return SUCCESS;
+}
+
+/* Read data to EEPROM at specific address */
+void Chip_EEPROM_Read(LPC_EEPROM_T *pEEPROM,
+					  uint16_t pageOffset,
+					  uint16_t pageAddr,
+					  void *pData,
+					  EEPROM_RWSIZE_T rsize,
+					  uint32_t byteNum)
+{
+	uint32_t rTotalByteNum = 0;
+	uint32_t rOffset = (pageOffset & (EEPROM_PAGE_SIZE - 1));
+	uint32_t rByteNum = EEPROM_PAGE_SIZE - rOffset;
+	/* read and store data in buffer */
+	while (byteNum) {
+		if (rByteNum > byteNum) {
+			rByteNum = byteNum;
+		}
+		/* update data to page register */
+		Chip_EEPROM_ReadPage(pEEPROM, rOffset, pageAddr,
+							 &((uint8_t *) pData)[rTotalByteNum], (uint8_t) rsize, rByteNum);
+		rTotalByteNum += rByteNum;
+		byteNum -= rByteNum;
+
+		/* Change to next page */
+		pageAddr++;
+		rOffset = 0;
+		rByteNum = EEPROM_PAGE_SIZE;
+	}
+}
+
+/* Erase a page at the specific address */
+void Chip_EEPROM_Erase(LPC_EEPROM_T *pEEPROM, uint16_t pageAddr)
+{
+	Chip_EEPROM_ErasePageRegister(pEEPROM);
+
+	Chip_EEPROM_EraseProgramPage(pEEPROM, pageAddr);
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/emc_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/emc_17xx_40xx.c
new file mode 100644
index 000000000..9a4969101
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/emc_17xx_40xx.c
@@ -0,0 +1,282 @@
+/*
+ * @brief LPC17xx/40xx EMC driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+/* DIV function with result rounded up */
+#define EMC_DIV_ROUND_UP(x, y)  ((x + y - 1) / y)
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+#ifndef EMC_SUPPORT_ONLY_PL172
+/* Get ARM External Memory Controller Version */
+STATIC uint32_t getARMPeripheralID(void)
+{
+	uint32_t *RegAdd;
+	RegAdd = (uint32_t *) ((uint32_t) LPC_EMC + 0xFE0);
+	return (RegAdd[0] & 0xFF) | ((RegAdd[1] & 0xFF) << 8) |
+		   ((RegAdd[2] & 0xFF) << 16) | (RegAdd[3] << 24);
+}
+
+#endif
+
+/* Calculate Clock Count from Timing Unit(nanoseconds) */
+STATIC uint32_t convertTimmingParam(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust)
+{
+	uint32_t temp;
+	if (input_ns < 0) {
+		return (-input_ns) >> 8;
+	}
+	temp = EMC_Clock / 1000000;		/* MHz calculation */
+	temp = temp * input_ns / 1000;
+
+	/* round up */
+	temp += 0xFF;
+
+	/* convert to simple integer number format */
+	temp >>= 8;
+	if (temp > adjust) {
+		return temp - adjust;
+	}
+
+	return 0;
+}
+
+/* Get Dynamic Memory Device Colum len */
+STATIC uint32_t getColsLen(uint32_t DynConfig)
+{
+	uint32_t DevBusWidth;
+	DevBusWidth = (DynConfig >> EMC_DYN_CONFIG_DEV_BUS_BIT) & 0x03;
+	if (DevBusWidth == 2) {
+		return 8;
+	}
+	else if (DevBusWidth == 1) {
+		return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 8;
+	}
+	else if (DevBusWidth == 0) {
+		return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 9;
+	}
+
+	return 0;
+}
+
+/* Initializes the Dynamic Controller according to the specified parameters
+   in the IP_EMC_DYN_CONFIG_T */
+void initDynMem(LPC_EMC_T *pEMC, IP_EMC_DYN_CONFIG_T *Dynamic_Config, uint32_t EMC_Clock)
+{
+	uint32_t ChipSelect, tmpclk;
+	int i;
+
+	for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
+		LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + (ChipSelect << 5));
+
+		EMC_Reg_add->DYNAMICRASCAS0    = Dynamic_Config->DevConfig[ChipSelect].RAS |
+										 ((Dynamic_Config->DevConfig[ChipSelect].ModeRegister <<
+										   (8 - EMC_DYN_MODE_CAS_BIT)) & 0xF00);
+		EMC_Reg_add->DYNAMICCONFIG0    = Dynamic_Config->DevConfig[ChipSelect].DynConfig;
+	}
+	pEMC->DYNAMICREADCONFIG = Dynamic_Config->ReadConfig;	/* Read strategy */
+
+	pEMC->DYNAMICRP         = convertTimmingParam(EMC_Clock, Dynamic_Config->tRP, 1);
+	pEMC->DYNAMICRAS        = convertTimmingParam(EMC_Clock, Dynamic_Config->tRAS, 1);
+	pEMC->DYNAMICSREX       = convertTimmingParam(EMC_Clock, Dynamic_Config->tSREX, 1);
+	pEMC->DYNAMICAPR        = convertTimmingParam(EMC_Clock, Dynamic_Config->tAPR, 1);
+	pEMC->DYNAMICDAL        = convertTimmingParam(EMC_Clock, Dynamic_Config->tDAL, 0);
+	pEMC->DYNAMICWR         = convertTimmingParam(EMC_Clock, Dynamic_Config->tWR, 1);
+	pEMC->DYNAMICRC         = convertTimmingParam(EMC_Clock, Dynamic_Config->tRC, 1);
+	pEMC->DYNAMICRFC        = convertTimmingParam(EMC_Clock, Dynamic_Config->tRFC, 1);
+	pEMC->DYNAMICXSR        = convertTimmingParam(EMC_Clock, Dynamic_Config->tXSR, 1);
+	pEMC->DYNAMICRRD        = convertTimmingParam(EMC_Clock, Dynamic_Config->tRRD, 1);
+	pEMC->DYNAMICMRD        = convertTimmingParam(EMC_Clock, Dynamic_Config->tMRD, 1);
+
+	/* TIM_Waitus(100); */
+	/*FIXME: if Timer driver is ready, it should replace below "for" delay technic */
+	for (i = 0; i < 1000; i++) {	/* wait 100us */
+	}
+	pEMC->DYNAMICCONTROL    = 0x00000183;	/* Issue NOP command */
+
+	/* TIM_Waitus(200); */						   /* wait 200us */
+	/*FIXME: if Timer driver is ready, it should replace below "for" delay technic */
+	for (i = 0; i < 1000; i++) {}
+	pEMC->DYNAMICCONTROL    = 0x00000103;	/* Issue PALL command */
+
+	pEMC->DYNAMICREFRESH = 2;	/* ( 2 * 16 ) -> 32 clock cycles */
+
+	/* FIXME: TIM_Waitus(200); */						   /* wait 200us */
+	for (i = 0; i < 80; i++) {}
+
+	tmpclk = EMC_DIV_ROUND_UP(convertTimmingParam(EMC_Clock, Dynamic_Config->RefreshPeriod, 0), 16);
+	pEMC->DYNAMICREFRESH    = tmpclk;
+
+	pEMC->DYNAMICCONTROL    = 0x00000083;	/* Issue MODE command */
+
+	for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) {
+		/*uint32_t burst_length;*/
+		uint32_t DynAddr;
+		uint8_t Col_len;
+
+		Col_len = getColsLen(Dynamic_Config->DevConfig[ChipSelect].DynConfig);
+		/* get bus wide: if 32bit, len is 4 else if 16bit len is 2 */
+		/* burst_length = 1 << ((((Dynamic_Config->DynConfig[ChipSelect] >> 14) & 1)^1) +1); */
+		if (Dynamic_Config->DevConfig[ChipSelect].DynConfig & (1 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)) {
+			/*32bit bus */
+			/*burst_length = 2;*/
+			Col_len += 2;
+		}
+		else {
+			/*burst_length = 4;*/
+			Col_len += 1;
+		}
+		DynAddr = Dynamic_Config->DevConfig[ChipSelect].BaseAddr;
+
+		if (DynAddr != 0) {
+			uint32_t temp;
+			uint32_t ModeRegister;
+			ModeRegister = Dynamic_Config->DevConfig[ChipSelect].ModeRegister;
+			temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len)));
+			temp = temp;
+		}
+	}
+	pEMC->DYNAMICCONTROL    = 0x00000000;	/* Issue NORMAL command */
+
+	/* enable buffers */
+	pEMC->DYNAMICCONFIG0    |= 1 << 19;
+	pEMC->DYNAMICCONFIG1    |= 1 << 19;
+	pEMC->DYNAMICCONFIG2    |= 1 << 19;
+	pEMC->DYNAMICCONFIG3    |= 1 << 19;
+}
+
+/* Initializes the Static Controller according to the specified parameters
+ * in the IP_EMC_STATIC_CONFIG_T
+ */
+void initStaticMem(LPC_EMC_T *pEMC, IP_EMC_STATIC_CONFIG_T *Static_Config, uint32_t EMC_Clock)
+{
+	LPC_EMC_T *EMC_Reg_add = (LPC_EMC_T *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5));
+	EMC_Reg_add->STATICCONFIG0      = Static_Config->Config;
+	EMC_Reg_add->STATICWAITWEN0     = convertTimmingParam(EMC_Clock, Static_Config->WaitWen, 1);
+	EMC_Reg_add->STATICWAITOEN0     = convertTimmingParam(EMC_Clock, Static_Config->WaitOen, 0);
+	EMC_Reg_add->STATICWAITRD0      = convertTimmingParam(EMC_Clock, Static_Config->WaitRd, 1);
+	EMC_Reg_add->STATICWAITPAG0     = convertTimmingParam(EMC_Clock, Static_Config->WaitPage, 1);
+	EMC_Reg_add->STATICWAITWR0      = convertTimmingParam(EMC_Clock, Static_Config->WaitWr, 2);
+	EMC_Reg_add->STATICWAITTURN0    = convertTimmingParam(EMC_Clock, Static_Config->WaitTurn, 1);
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Dyanmic memory setup */
+void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config)
+{
+	uint32_t ClkFreq;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetEMCClockRate();
+
+	initDynMem(LPC_EMC, Dynamic_Config, ClkFreq);
+}
+
+/* Enable Dynamic Memory Controller */
+void Chip_EMC_Dynamic_Enable(uint8_t Enable)
+{
+	if (Enable) {
+		LPC_EMC->DYNAMICCONTROL |= EMC_DYN_CONTROL_ENABLE;
+	}
+	else {
+		LPC_EMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE;
+	}
+}
+
+/* Static memory setup */
+void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config)
+{
+	uint32_t ClkFreq;
+
+	/* Note clocks must be enabled prior to this call */
+	ClkFreq = Chip_Clock_GetEMCClockRate();
+
+	initStaticMem(LPC_EMC, Static_Config, ClkFreq);
+}
+
+/* Mirror CS1 to CS0 and DYCS0 */
+void Chip_EMC_Mirror(uint8_t Enable)
+{
+	if (Enable) {
+		LPC_EMC->CONTROL |= 1 << 1;
+	}
+	else {
+		LPC_EMC->CONTROL &= ~(1 << 1);
+	}
+}
+
+/* Enable EMC */
+void Chip_EMC_Enable(uint8_t Enable)
+{
+	if (Enable) {
+		LPC_EMC->CONTROL |= 1;
+	}
+	else {
+		LPC_EMC->CONTROL &= ~(1);
+	}
+}
+
+/* Set EMC LowPower Mode */
+void Chip_EMC_LowPowerMode(uint8_t Enable)
+{
+	if (Enable) {
+		LPC_EMC->CONTROL |= 1 << 2;
+	}
+	else {
+		LPC_EMC->CONTROL &= ~(1 << 2);
+	}
+}
+
+/* Initialize EMC */
+void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
+{
+	LPC_EMC->CONFIG    = (EndianMode ? 1 : 0) | ((ClockRatio ? 1 : 0) << 8);
+
+	/* Enable EMC 001 Normal Memory Map, No low power mode */
+	LPC_EMC->CONTROL     = (Enable ? 1 : 0);
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/enet_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/enet_17xx_40xx.c
new file mode 100644
index 000000000..363a133da
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/enet_17xx_40xx.c
@@ -0,0 +1,289 @@
+/*
+ * @brief LPC17xx/40xx ethernet driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Saved address for PHY and clock divider */
+STATIC uint32_t phyAddr;
+
+/* Divider index values for the MII PHY clock */
+STATIC const uint8_t EnetClkDiv[] = {4, 6, 8, 10, 14, 20, 28, 36, 40, 44,
+									 48, 52, 56, 60, 64};
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+STATIC INLINE void resetENET(LPC_ENET_T *pENET)
+{
+	volatile uint32_t i;
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	Chip_SYSCTL_PeriphReset(SYSCTL_RESET_ENET);
+#endif
+
+	/* Reset ethernet peripheral */
+	Chip_ENET_Reset(pENET);
+	for (i = 0; i < 100; i++) {}
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Basic Ethernet interface initialization */
+void Chip_ENET_Init(LPC_ENET_T *pENET, bool useRMII)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ENET);
+	resetENET(pENET);
+
+	/* Initial MAC configuration for  full duplex,
+	   100Mbps, inter-frame gap use default values */
+	pENET->MAC.MAC1 = ENET_MAC1_PARF;
+	pENET->MAC.MAC2 = ENET_MAC2_FULLDUPLEX | ENET_MAC2_CRCEN | ENET_MAC2_PADCRCEN;
+
+	if (useRMII) {
+		pENET->CONTROL.COMMAND = ENET_COMMAND_FULLDUPLEX | ENET_COMMAND_PASSRUNTFRAME | ENET_COMMAND_RMII;
+	}
+	else {
+		pENET->CONTROL.COMMAND = ENET_COMMAND_FULLDUPLEX | ENET_COMMAND_PASSRUNTFRAME;
+	}
+
+	pENET->MAC.IPGT = ENET_IPGT_FULLDUPLEX;
+	pENET->MAC.IPGR = ENET_IPGR_P2_DEF;
+	pENET->MAC.SUPP = ENET_SUPP_100Mbps_SPEED;
+	pENET->MAC.MAXF = ENET_ETH_MAX_FLEN;
+	pENET->MAC.CLRT = ENET_CLRT_DEF;
+
+	/* Setup default filter */
+	pENET->CONTROL.COMMAND |= ENET_COMMAND_PASSRXFILTER;
+
+	/* Clear all MAC interrupts */
+	pENET->MODULE_CONTROL.INTCLEAR = 0xFFFF;
+
+	/* Disable MAC interrupts */
+	pENET->MODULE_CONTROL.INTENABLE = 0;
+}
+
+/* Ethernet interface shutdown */
+void Chip_ENET_DeInit(LPC_ENET_T *pENET)
+{
+	/* Disable packet reception */
+	pENET->MAC.MAC1 &= ~ENET_MAC1_RXENABLE;
+	pENET->CONTROL.COMMAND = 0;
+
+	/* Clear all MAC interrupts */
+	pENET->MODULE_CONTROL.INTCLEAR = 0xFFFF;
+
+	/* Disable MAC interrupts */
+	pENET->MODULE_CONTROL.INTENABLE = 0;
+
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ENET);
+}
+
+/* Sets up the PHY link clock divider and PHY address */
+void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
+{
+	/* Save clock divider and PHY address in MII address register */
+	phyAddr = ENET_MADR_PHYADDR(addr);
+
+	/*  Write to MII configuration register and reset */
+	pENET->MAC.MCFG = ENET_MCFG_CLOCKSEL(div) | ENET_MCFG_RES_MII;
+
+	/* release reset */
+	pENET->MAC.MCFG &= ~(ENET_MCFG_RES_MII);
+}
+
+/* Find the divider index for a desired MII clock rate */
+uint32_t Chip_ENET_FindMIIDiv(LPC_ENET_T *pENET, uint32_t clockRate)
+{
+	uint32_t tmp, divIdx = 0;
+
+	/* Find desired divider value */
+	tmp = Chip_Clock_GetENETClockRate() / clockRate;
+
+	/* Determine divider index from desired divider */
+	for (divIdx = 0; divIdx < (sizeof(EnetClkDiv) / sizeof(EnetClkDiv[0])); divIdx++) {
+		/* Closest index, but not higher than desired rate */
+		if (EnetClkDiv[divIdx] >= tmp) {
+			return divIdx;
+		}
+	}
+
+	/* Use maximum divider index */
+	return (sizeof(EnetClkDiv) / sizeof(EnetClkDiv[0])) - 1;
+}
+
+/* Starts a PHY write via the MII */
+void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
+{
+	/* Write value at PHY address and register */
+	pENET->MAC.MCMD = 0;
+	pENET->MAC.MADR = phyAddr | ENET_MADR_REGADDR(reg);
+	pENET->MAC.MWTD = data;
+}
+
+/*Starts a PHY read via the MII */
+void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg)
+{
+	/* Read value at PHY address and register */
+	pENET->MAC.MADR = phyAddr | ENET_MADR_REGADDR(reg);
+	pENET->MAC.MCMD = ENET_MCMD_READ;
+}
+
+/* Read MII data */
+uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET)
+{
+	pENET->MAC.MCMD = 0;
+	return pENET->MAC.MRDD;
+}
+
+/* Sets full duplex for the ENET interface */
+void Chip_ENET_SetFullDuplex(LPC_ENET_T *pENET)
+{
+	pENET->MAC.MAC2 |= ENET_MAC2_FULLDUPLEX;
+	pENET->CONTROL.COMMAND |= ENET_COMMAND_FULLDUPLEX;
+	pENET->MAC.IPGT = ENET_IPGT_FULLDUPLEX;
+}
+
+/* Sets half duplex for the ENET interface */
+void Chip_ENET_SetHalfDuplex(LPC_ENET_T *pENET)
+{
+	pENET->MAC.MAC2 &= ~ENET_MAC2_FULLDUPLEX;
+	pENET->CONTROL.COMMAND &= ~ENET_COMMAND_FULLDUPLEX;
+	pENET->MAC.IPGT = ENET_IPGT_HALFDUPLEX;
+}
+
+/* Configures the initial ethernet transmit descriptors */
+void Chip_ENET_InitTxDescriptors(LPC_ENET_T *pENET,
+								 ENET_TXDESC_T *pDescs,
+								 ENET_TXSTAT_T *pStatus,
+								 uint32_t descNum)
+{
+	/* Setup descriptor list base addresses */
+	pENET->CONTROL.TX.DESCRIPTOR = (uint32_t) pDescs;
+	pENET->CONTROL.TX.DESCRIPTORNUMBER = descNum - 1;
+	pENET->CONTROL.TX.STATUS = (uint32_t) pStatus;
+	pENET->CONTROL.TX.PRODUCEINDEX = 0;
+}
+
+/* Configures the initial ethernet receive descriptors */
+void Chip_ENET_InitRxDescriptors(LPC_ENET_T *pENET,
+								 ENET_RXDESC_T *pDescs,
+								 ENET_RXSTAT_T *pStatus,
+								 uint32_t descNum)
+{
+	/* Setup descriptor list base addresses */
+	pENET->CONTROL.RX.DESCRIPTOR = (uint32_t) pDescs;
+	pENET->CONTROL.RX.DESCRIPTORNUMBER = descNum - 1;
+	pENET->CONTROL.RX.STATUS = (uint32_t) pStatus;
+	pENET->CONTROL.RX.CONSUMEINDEX = 0;
+}
+
+/* Get status for the descriptor list */
+ENET_BUFF_STATUS_T Chip_ENET_GetBufferStatus(LPC_ENET_T *pENET,
+											 uint16_t produceIndex,
+											 uint16_t consumeIndex,
+											 uint16_t buffSize)
+{
+	/* Empty descriptor list */
+	if (consumeIndex == produceIndex) {
+		return ENET_BUFF_EMPTY;
+	}
+
+	/* Full descriptor list */
+	if ((consumeIndex == 0) &&
+		(produceIndex == (buffSize - 1))) {
+		return ENET_BUFF_FULL;
+	}
+
+	/* Wrap-around, full descriptor list */
+	if (consumeIndex == (produceIndex + 1)) {
+		return ENET_BUFF_FULL;
+	}
+
+	return ENET_BUFF_PARTIAL_FULL;
+}
+
+/* Get the number of descriptor filled */
+uint32_t Chip_ENET_GetFillDescNum(LPC_ENET_T *pENET, uint16_t produceIndex, uint16_t consumeIndex, uint16_t buffSize)
+{
+	/* Empty descriptor list */
+	if (consumeIndex == produceIndex) {
+		return 0;
+	}
+
+	if (consumeIndex > produceIndex) {
+		return (buffSize - consumeIndex) + produceIndex;
+	}
+
+	return produceIndex - consumeIndex;
+}
+
+/* Increase the current Tx Produce Descriptor Index */
+uint16_t Chip_ENET_IncTXProduceIndex(LPC_ENET_T *pENET)
+{
+	/* Get current TX produce index */
+	uint32_t idx = pENET->CONTROL.TX.PRODUCEINDEX;
+
+	/* Start frame transmission by incrementing descriptor */
+	idx++;
+	if (idx > pENET->CONTROL.TX.DESCRIPTORNUMBER) {
+		idx = 0;
+	}
+	pENET->CONTROL.TX.PRODUCEINDEX = idx;
+
+	return idx;
+}
+
+/* Increase the current Rx Consume Descriptor Index */
+uint16_t Chip_ENET_IncRXConsumeIndex(LPC_ENET_T *pENET)
+{
+	/* Get current RX consume index */
+	uint32_t idx = pENET->CONTROL.RX.CONSUMEINDEX;
+
+	/* Consume descriptor */
+	idx++;
+	if (idx > pENET->CONTROL.RX.DESCRIPTORNUMBER) {
+		idx = 0;
+	}
+	pENET->CONTROL.RX.CONSUMEINDEX = idx;
+
+	return idx;
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/fpu_init.c b/hw/mcu/nxp/lpc_chip_40xx/src/fpu_init.c
new file mode 100644
index 000000000..88125dda5
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/fpu_init.c
@@ -0,0 +1,97 @@
+/*
+ * @brief FPU init code
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#if defined(CORE_M4)
+
+#include "sys_config.h"
+#include "cmsis.h"
+#include "stdint.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define LPC_CPACR           0xE000ED88
+
+#define SCB_MVFR0           0xE000EF40
+#define SCB_MVFR0_RESET     0x10110021
+
+#define SCB_MVFR1           0xE000EF44
+#define SCB_MVFR1_RESET     0x11000011
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Early initialization of the FPU */
+void fpuInit(void)
+{
+#if __FPU_PRESENT != 0
+	// from arm trm manual:
+	//                ; CPACR is located at address 0xE000ED88
+	//                LDR.W R0, =0xE000ED88
+	//                ; Read CPACR
+	//                LDR R1, [R0]
+	//                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+	//                ORR R1, R1, #(0xF << 20)
+	//                ; Write back the modified value to the CPACR
+	//                STR R1, [R0]
+
+	volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
+	volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
+	volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
+	volatile uint32_t Cpacr;
+	volatile uint32_t Mvfr0;
+	volatile uint32_t Mvfr1;
+	char vfpPresent = 0;
+
+	Mvfr0 = *regMvfr0;
+	Mvfr1 = *regMvfr1;
+
+	vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
+
+	if (vfpPresent) {
+		Cpacr = *regCpacr;
+		Cpacr |= (0xF << 20);
+		*regCpacr = Cpacr;	// enable CP10 and CP11 for full access
+	}
+#endif /* __FPU_PRESENT != 0 */
+}
+
+#endif /* defined(CORE_M4 */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/gpdma_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/gpdma_17xx_40xx.c
new file mode 100644
index 000000000..b19dc0ea8
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/gpdma_17xx_40xx.c
@@ -0,0 +1,704 @@
+/*
+ * @brief LPC17xx/40xx GPDMA driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Channel array to monitor free channel */
+static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS];
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+/* Optimized Peripheral Source and Destination burst size (177x_8x,407x_8x) */
+static const uint8_t GPDMA_LUTPerBurst[] = {
+	0,								/* Reserved */
+	GPDMA_BSIZE_8,					/* SD Card */
+	GPDMA_BSIZE_4,					/* SSP0 Tx */
+	GPDMA_BSIZE_4,					/* SSP0 Rx */
+	GPDMA_BSIZE_4,					/* SSP1 Tx */
+	GPDMA_BSIZE_4,					/* SSP1 Rx */
+	GPDMA_BSIZE_4,					/* SSP2 Tx */
+	GPDMA_BSIZE_4,					/* SSP2 Rx */
+	GPDMA_BSIZE_1,					/* ADC */
+	GPDMA_BSIZE_1,					/* DAC */
+	GPDMA_BSIZE_1,					/* UART0 Tx */
+	GPDMA_BSIZE_1,					/* UART0 Rx */
+	GPDMA_BSIZE_1,					/* UART1 Tx */
+	GPDMA_BSIZE_1,					/* UART1 Rx */
+	GPDMA_BSIZE_1,					/* UART2 Tx */
+	GPDMA_BSIZE_1,					/* UART2 Rx */
+	GPDMA_BSIZE_1,					/* MAT0.0 */
+	GPDMA_BSIZE_1,					/* MAT0.1 */
+	GPDMA_BSIZE_1,					/* MAT1.0 */
+	GPDMA_BSIZE_1,					/* MAT1.1 */
+	GPDMA_BSIZE_1,					/* MAT2.0 */
+	GPDMA_BSIZE_1,					/* MAT2.1 */
+	GPDMA_BSIZE_32,					/* I2S channel 0 */
+	GPDMA_BSIZE_32,					/* I2S channel 1 */
+	0,								/* Reserved */
+	0,								/* Reserved */
+	GPDMA_BSIZE_1,					/* UART3 Tx */
+	GPDMA_BSIZE_1,					/* UART3 Rx */
+	GPDMA_BSIZE_1,					/* UART4 Tx */
+	GPDMA_BSIZE_1,					/* UART4 Rx */
+	GPDMA_BSIZE_1,					/* MAT3.0 */
+	GPDMA_BSIZE_1,					/* MAT3.1 */
+};
+
+/* Optimized Peripheral Source and Destination transfer width (177x_8x,407x_8x) */
+static const uint8_t GPDMA_LUTPerWid[] =  {
+	0,									/* Reserved */
+	GPDMA_WIDTH_WORD,					/* SD Card */
+	GPDMA_WIDTH_BYTE,					/* SSP0 Tx */
+	GPDMA_WIDTH_BYTE,					/* SSP0 Rx */
+	GPDMA_WIDTH_BYTE,					/* SSP1 Tx */
+	GPDMA_WIDTH_BYTE,					/* SSP1 Rx */
+	GPDMA_WIDTH_BYTE,					/* SSP2 Tx */
+	GPDMA_WIDTH_BYTE,					/* SSP2 Rx */
+	GPDMA_WIDTH_WORD,					/* ADC */
+	GPDMA_WIDTH_HALFWORD,				/* DAC */
+	GPDMA_WIDTH_BYTE,					/* UART0 Tx */
+	GPDMA_WIDTH_BYTE,					/* UART0 Rx */
+	GPDMA_WIDTH_BYTE,					/* UART1 Tx */
+	GPDMA_WIDTH_BYTE,					/* UART1 Rx */
+	GPDMA_WIDTH_BYTE,					/* UART2 Tx */
+	GPDMA_WIDTH_BYTE,					/* UART2 Rx */
+	GPDMA_WIDTH_WORD,					/* MAT0.0 */
+	GPDMA_WIDTH_WORD,					/* MAT0.1 */
+	GPDMA_WIDTH_WORD,					/* MAT1.0 */
+	GPDMA_WIDTH_WORD,					/* MAT1.1 */
+	GPDMA_WIDTH_WORD,					/* MAT2.0 */
+	GPDMA_WIDTH_WORD,					/* MAT2.1 */
+	GPDMA_WIDTH_WORD,					/* I2S channel 0 */
+	GPDMA_WIDTH_WORD,					/* I2S channel 1 */
+	0,									/* Reserved */
+	0,									/* Reserved */
+	GPDMA_WIDTH_BYTE,					/* UART3 Tx */
+	GPDMA_WIDTH_BYTE,					/* UART3 Rx */
+	GPDMA_WIDTH_BYTE,					/* UART4 Tx */
+	GPDMA_WIDTH_BYTE,					/* UART4 Rx */
+	GPDMA_WIDTH_WORD,					/* MAT3.0 */
+	GPDMA_WIDTH_WORD,					/* MAT3.1 */
+};
+
+/* Lookup Table of Connection Type matched with (177x_8x,407x_8x) Peripheral Data (FIFO) register base address */
+volatile static const void *GPDMA_LUTPerAddr[] = {
+	0,									/* Reserved */
+	(&LPC_SDC->FIFO),					/* SD Card */
+	(&LPC_SSP0->DR),					/* SSP0 Tx */
+	(&LPC_SSP0->DR),					/* SSP0 Rx */
+	(&LPC_SSP1->DR),					/* SSP1 Tx */
+	(&LPC_SSP1->DR),					/* SSP1 Rx */
+	(&LPC_SSP2->DR),					/* SSP2 Tx */
+	(&LPC_SSP2->DR),					/* SSP2 Rx */
+	(&LPC_ADC->GDR),					/* ADC */
+	(&LPC_DAC->CR),						/* DAC */
+	(&LPC_UART0-> /*RBTHDLR.*/ THR),	/* UART0 Tx */
+	(&LPC_UART0-> /*RBTHDLR.*/ RBR),	/* UART0 Rx */
+	(&LPC_UART1-> /*RBTHDLR.*/ THR),	/* UART1 Tx */
+	(&LPC_UART1-> /*RBTHDLR.*/ RBR),	/* UART1 Rx */
+	(&LPC_UART2-> /*RBTHDLR.*/ THR),	/* UART2 Tx */
+	(&LPC_UART2-> /*RBTHDLR.*/ RBR),	/* UART2 Rx */
+	(&LPC_TIMER0->MR[0]),				/* MAT0.0 */
+	(&LPC_TIMER0->MR[1]),				/* MAT0.1 */
+	(&LPC_TIMER1->MR[0]),				/* MAT1.0 */
+	(&LPC_TIMER1->MR[1]),				/* MAT1.1 */
+	(&LPC_TIMER2->MR[0]),				/* MAT2.0 */
+	(&LPC_TIMER2->MR[1]),				/* MAT2.1 */
+	(&LPC_I2S->TXFIFO),					/* I2S Tx */
+	(&LPC_I2S->RXFIFO),					/* I2S Rx */
+	0,									/* Reverse */
+	0,									/* Reverse */
+	(&LPC_UART3-> /*RBTHDLR.*/ THR),	/* UART3 Tx */
+	(&LPC_UART3-> /*RBTHDLR.*/ RBR),	/* UART3 Rx */
+	(&LPC_UART4-> /*RBTHDLR.*/ THR),	/* UART4 Tx */
+	(&LPC_UART4-> /*RBTHDLR.*/ RBR),	/* UART4 Rx */
+	(&LPC_TIMER3->MR[0]),				/* MAT3.0 */
+	(&LPC_TIMER3->MR[1])				/* MAT3.1 */
+};
+
+#elif defined(CHIP_LPC175X_6X)
+const uint8_t GPDMA_LUTPerBurst[] = {
+	GPDMA_BSIZE_4,					// SSP0 Tx
+	GPDMA_BSIZE_4,					// SSP0 Rx
+	GPDMA_BSIZE_4,					// SSP1 Tx
+	GPDMA_BSIZE_4,					// SSP1 Rx
+	GPDMA_BSIZE_1,					// ADC
+	GPDMA_BSIZE_32,					// I2S channel 0
+	GPDMA_BSIZE_32,					// I2S channel 1
+	GPDMA_BSIZE_1,					// DAC
+	GPDMA_BSIZE_1,					// UART0 Tx
+	GPDMA_BSIZE_1,					// UART0 Rx
+	GPDMA_BSIZE_1,					// UART1 Tx
+	GPDMA_BSIZE_1,					// UART1 Rx
+	GPDMA_BSIZE_1,					// UART2 Tx
+	GPDMA_BSIZE_1,					// UART2 Rx
+	GPDMA_BSIZE_1,					// UART3 Tx
+	GPDMA_BSIZE_1,					// UART3 Rx
+	GPDMA_BSIZE_1,					// MAT0.0
+	GPDMA_BSIZE_1,					// MAT0.1
+	GPDMA_BSIZE_1,					// MAT1.0
+	GPDMA_BSIZE_1,					// MAT1.1
+	GPDMA_BSIZE_1,					// MAT2.0
+	GPDMA_BSIZE_1,					// MAT2.1
+	GPDMA_BSIZE_1,					// MAT3.0
+	GPDMA_BSIZE_1					// MAT3.1
+};
+
+/**
+ * @brief Optimized Peripheral Source and Destination transfer width
+ */
+const uint8_t GPDMA_LUTPerWid[] = {
+	GPDMA_WIDTH_BYTE,					// SSP0 Tx
+	GPDMA_WIDTH_BYTE,					// SSP0 Rx
+	GPDMA_WIDTH_BYTE,					// SSP1 Tx
+	GPDMA_WIDTH_BYTE,					// SSP1 Rx
+	GPDMA_WIDTH_WORD,					// ADC
+	GPDMA_WIDTH_WORD,					// I2S channel 0
+	GPDMA_WIDTH_WORD,					// I2S channel 1
+	GPDMA_WIDTH_HALFWORD,				// DAC
+	GPDMA_WIDTH_BYTE,					// UART0 Tx
+	GPDMA_WIDTH_BYTE,					// UART0 Rx
+	GPDMA_WIDTH_BYTE,					// UART1 Tx
+	GPDMA_WIDTH_BYTE,					// UART1 Rx
+	GPDMA_WIDTH_BYTE,					// UART2 Tx
+	GPDMA_WIDTH_BYTE,					// UART2 Rx
+	GPDMA_WIDTH_BYTE,					// UART3 Tx
+	GPDMA_WIDTH_BYTE,					// UART3 Rx
+	GPDMA_WIDTH_WORD,					// MAT0.0
+	GPDMA_WIDTH_WORD,					// MAT0.1
+	GPDMA_WIDTH_WORD,					// MAT1.0
+	GPDMA_WIDTH_WORD,					// MAT1.1
+	GPDMA_WIDTH_WORD,					// MAT2.0
+	GPDMA_WIDTH_WORD,					// MAT2.1
+	GPDMA_WIDTH_WORD,					// MAT3.0
+	GPDMA_WIDTH_WORD					// MAT3.1
+};
+
+/**
+ * @brief Peripheral Source and Destination address
+ */
+volatile const void *GPDMA_LUTPerAddr[] = {
+	(&LPC_SSP0->DR),					// SSP0 Tx
+	(&LPC_SSP0->DR),					// SSP0 Rx
+	(&LPC_SSP1->DR),					// SSP1 Tx
+	(&LPC_SSP1->DR),					// SSP1 Rx
+	(&LPC_ADC->GDR),				// ADC
+	(&LPC_I2S->TXFIFO),				// I2S Tx
+	(&LPC_I2S->RXFIFO),				// I2S Rx
+	(&LPC_DAC->CR),					// DAC
+	(&LPC_UART0-> /*RBTHDLR.*/ THR),	// UART0 Tx
+	(&LPC_UART0-> /*RBTHDLR.*/ RBR),	// UART0 Rx
+	(&LPC_UART1-> /*RBTHDLR.*/ THR),	// UART1 Tx
+	(&LPC_UART1-> /*RBTHDLR.*/ RBR),	// UART1 Rx
+	(&LPC_UART2-> /*RBTHDLR.*/ THR),	// UART2 Tx
+	(&LPC_UART2-> /*RBTHDLR.*/ RBR),	// UART2 Rx
+	(&LPC_UART3-> /*RBTHDLR.*/ THR),	// UART3 Tx
+	(&LPC_UART3-> /*RBTHDLR.*/ RBR),	// UART3 Rx
+	(&LPC_TIMER0->MR[0]),					// MAT0.0
+	(&LPC_TIMER0->MR[1]),					// MAT0.1
+	(&LPC_TIMER1->MR[0]),					// MAT1.0
+	(&LPC_TIMER1->MR[1]),					// MAT1.1
+	(&LPC_TIMER2->MR[0]),					// MAT2.0
+	(&LPC_TIMER2->MR[1]),					// MAT2.1
+	(&LPC_TIMER3->MR[0]),					// MAT3.0
+	(&LPC_TIMER3->MR[1])					// MAT3.1
+
+};
+#endif
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Control which set of peripherals is connected to the DMA controller */
+STATIC uint8_t configDMAMux(uint32_t gpdma_peripheral_connection_number)
+{
+#if defined(CHIP_LPC175X_6X)
+	if (gpdma_peripheral_connection_number > 15) {
+		LPC_SYSCTL->DMAREQSEL |= (1 << (gpdma_peripheral_connection_number - 16));
+		return gpdma_peripheral_connection_number - 8;
+	}
+	else {
+		if (gpdma_peripheral_connection_number > 7) {
+			LPC_SYSCTL->DMAREQSEL &= ~(1 << (gpdma_peripheral_connection_number - 8));
+		}
+		return gpdma_peripheral_connection_number;
+	}
+#elif defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	if (gpdma_peripheral_connection_number > 15) {
+		LPC_SYSCTL->DMAREQSEL |= (1 << (gpdma_peripheral_connection_number - 16));
+		return gpdma_peripheral_connection_number - 16;
+	}
+	else {
+		LPC_SYSCTL->DMAREQSEL &= ~(1 << (gpdma_peripheral_connection_number));
+		return gpdma_peripheral_connection_number;
+	}
+#endif
+}
+
+uint32_t makeCtrlWord(const GPDMA_CH_CFG_T *GPDMAChannelConfig,
+					  uint32_t GPDMA_LUTPerBurstSrcConn,
+					  uint32_t GPDMA_LUTPerBurstDstConn,
+					  uint32_t GPDMA_LUTPerWidSrcConn,
+					  uint32_t GPDMA_LUTPerWidDstConn)
+{
+	uint32_t ctrl_word = 0;
+
+	switch (GPDMAChannelConfig->TransferType) {
+	/* Memory to memory */
+	case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
+		ctrl_word = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize)
+					| GPDMA_DMACCxControl_SBSize((4UL))				/**< Burst size = 32 */
+					| GPDMA_DMACCxControl_DBSize((4UL))				/**< Burst size = 32 */
+					| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth)
+					| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth)
+					| GPDMA_DMACCxControl_SI
+					| GPDMA_DMACCxControl_DI
+					| GPDMA_DMACCxControl_I;
+		break;
+
+	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
+		ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
+					| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn)
+					| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
+					| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn)
+					| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
+					| GPDMA_DMACCxControl_DestTransUseAHBMaster1
+					| GPDMA_DMACCxControl_SI
+					| GPDMA_DMACCxControl_I;
+		break;
+
+	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
+		ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
+					| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
+					| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn)
+					| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
+					| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn)
+					| GPDMA_DMACCxControl_SrcTransUseAHBMaster1
+					| GPDMA_DMACCxControl_DI
+					| GPDMA_DMACCxControl_I;
+		break;
+
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
+		ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
+					| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
+					| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
+					| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
+					| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
+					| GPDMA_DMACCxControl_SrcTransUseAHBMaster1
+					| GPDMA_DMACCxControl_DestTransUseAHBMaster1
+					| GPDMA_DMACCxControl_I;
+
+		break;
+
+	/* Do not support any more transfer type, return ERROR */
+	default:
+		return ERROR;
+	}
+	return ctrl_word;
+}
+
+/* Set up the DPDMA according to the specification configuration details */
+Status setupChannel(LPC_GPDMA_T *pGPDMA,
+					GPDMA_CH_CFG_T *GPDMAChannelConfig,
+					uint32_t CtrlWord,
+					uint32_t LinkListItem,
+					uint8_t SrcPeripheral,
+					uint8_t DstPeripheral)
+{
+	GPDMA_CH_T *pDMAch;
+
+	if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) {
+		/* This channel is enabled, return ERROR, need to release this channel first */
+		return ERROR;
+	}
+
+	/* Get Channel pointer */
+	pDMAch = (GPDMA_CH_T *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]);
+
+	/* Reset the Interrupt status */
+	pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
+	pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
+
+	/* Assign Linker List Item value */
+	pDMAch->LLI = LinkListItem;
+
+	/* Enable DMA channels, little endian */
+	pGPDMA->CONFIG = GPDMA_DMACConfig_E;
+	while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {}
+
+	pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr;
+	pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr;
+
+	/* Configure DMA Channel, enable Error Counter and Terminate counter */
+	pDMAch->CONFIG = GPDMA_DMACCxConfig_IE
+					 | GPDMA_DMACCxConfig_ITC		/*| GPDMA_DMACCxConfig_E*/
+					 | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType)
+					 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
+					 | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);
+
+	pDMAch->CONTROL = CtrlWord;
+
+	return SUCCESS;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the GPDMA */
+void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA)
+{
+	uint8_t i;
+
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPDMA);
+
+	/* Reset all channel configuration register */
+	for (i = 8; i > 0; i--) {
+		pGPDMA->CH[i - 1].CONFIG = 0;
+	}
+
+	/* Clear all DMA interrupt and error flag */
+	pGPDMA->INTTCCLEAR = 0xFF;
+	pGPDMA->INTERRCLR = 0xFF;
+
+	/* Reset all channels are free */
+	for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++) {
+		ChannelHandlerArray[i].ChannelStatus = DISABLE;
+	}
+}
+
+/* Shutdown the GPDMA */
+void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPDMA);
+}
+
+/* Stop a stream DMA transfer */
+void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA,
+					 uint8_t ChannelNum)
+{
+	Chip_GPDMA_ChannelCmd(pGPDMA, (ChannelNum), DISABLE);
+	if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTTC, ChannelNum)) {
+		/* Clear terminate counter Interrupt pending */
+		Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTTC, ChannelNum);
+	}
+	if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTERR, ChannelNum)) {
+		/* Clear terminate counter Interrupt pending */
+		Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTERR, ChannelNum);
+	}
+	ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE;
+}
+
+/* The GPDMA stream interrupt status checking */
+Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA,
+							uint8_t ChannelNum)
+{
+
+	if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INT, ChannelNum)) {
+		/* Check counter terminal status */
+		if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTTC, ChannelNum)) {
+			/* Clear terminate counter Interrupt pending */
+			Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTTC, ChannelNum);
+			return SUCCESS;
+		}
+		/* Check error terminal status */
+		if (Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_INTERR, ChannelNum)) {
+			/* Clear error counter Interrupt pending */
+
+			Chip_GPDMA_ClearIntPending(pGPDMA, GPDMA_STATCLR_INTERR, ChannelNum);
+			return ERROR;
+		}
+	}
+	return ERROR;
+}
+
+int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
+							  GPDMA_CH_CFG_T *GPDMACfg,
+							  uint8_t  ChannelNum,
+							  uint32_t src,
+							  uint32_t dst,
+							  uint32_t Size,
+							  GPDMA_FLOW_CONTROL_T TransferType)
+{
+	int rval = -1;
+	GPDMACfg->ChannelNum = ChannelNum;
+	GPDMACfg->TransferType = TransferType;
+	GPDMACfg->TransferSize = Size;
+
+	switch (TransferType) {
+	case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
+		GPDMACfg->SrcAddr = (uint32_t) src;
+		GPDMACfg->DstAddr = (uint32_t) dst;
+		rval = 3;
+		GPDMACfg->TransferWidth = GPDMA_WIDTH_WORD;
+		GPDMACfg->TransferSize = Size / 4;
+		break;
+
+	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
+		GPDMACfg->SrcAddr = (uint32_t) src;
+		rval = 1;
+		GPDMACfg->DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
+		break;
+
+	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
+		GPDMACfg->SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
+		GPDMACfg->DstAddr = (uint32_t) dst;
+		rval = 2;
+		break;
+
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
+	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
+		GPDMACfg->SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src];
+		GPDMACfg->DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst];
+		rval = 0;
+		break;
+
+	default:
+		break;
+	}
+	return rval;
+}
+
+/* Read the status from different registers according to the type */
+IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel)
+{
+	/**
+	 * TODO check the channel <=8 type is exited
+	 */
+	switch (type) {
+	case GPDMA_STAT_INT:/* check status of DMA channel interrupts */
+		return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF)));
+
+	case GPDMA_STAT_INTTC:	/* check terminal count interrupt request status for DMA */
+		return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF)));
+
+	case GPDMA_STAT_INTERR:	/* check interrupt status for DMA channels */
+		return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF)));
+
+	case GPDMA_STAT_RAWINTTC:	/* check status of the terminal count interrupt for DMA channels */
+		return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF)));
+
+	case GPDMA_STAT_RAWINTERR:	/* check status of the error interrupt for DMA channels */
+		return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF)));
+
+	default:/* check enable status for DMA channels */
+		return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF)));
+	}
+}
+
+/* Clear the Interrupt Flag from different registers according to the type */
+void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel)
+{
+	if (type == GPDMA_STATCLR_INTTC) {
+		/* clears the terminal count interrupt request on DMA channel */
+		pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF));
+	}
+	else {
+		/* clear the error interrupt request */
+		pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF));
+	}
+}
+
+/* Enable or Disable the GPDMA Channel */
+void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
+{
+	GPDMA_CH_T *pDMAch;
+
+	/* Get Channel pointer */
+	pDMAch = (GPDMA_CH_T *) &(pGPDMA->CH[channelNum]);
+
+	if (NewState == ENABLE) {
+		pDMAch->CONFIG |= GPDMA_DMACCxConfig_E;
+	}
+	else {
+		pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E;
+	}
+}
+
+/* Do a DMA transfer M2M, M2P,P2M or P2P */
+Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA,
+						   uint8_t ChannelNum,
+						   uint32_t src,
+						   uint32_t dst,
+						   GPDMA_FLOW_CONTROL_T TransferType,
+						   uint32_t Size)
+{
+	GPDMA_CH_CFG_T GPDMACfg;
+	uint8_t SrcPeripheral = 0, DstPeripheral = 0;
+	uint32_t cwrd;
+	int ret;
+
+	ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, Size, TransferType);
+	if (ret < 0) {
+		return ERROR;
+	}
+
+	/* Adjust src/dst index if they are memory */
+	if (ret & 1) {
+		src = 0;
+	}
+	else {
+		SrcPeripheral = configDMAMux(src);
+	}
+
+	if (ret & 2) {
+		dst = 0;
+	}
+	else {
+		DstPeripheral = configDMAMux(dst);
+	}
+
+	cwrd = makeCtrlWord(&GPDMACfg,
+						(uint32_t) GPDMA_LUTPerBurst[src],
+						(uint32_t) GPDMA_LUTPerBurst[dst],
+						(uint32_t) GPDMA_LUTPerWid[src],
+						(uint32_t) GPDMA_LUTPerWid[dst]);
+	if (setupChannel(pGPDMA, &GPDMACfg, cwrd, 0, SrcPeripheral, DstPeripheral) == ERROR) {
+		return ERROR;
+	}
+
+	/* Start the Channel */
+	Chip_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE);
+	return SUCCESS;
+}
+
+Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
+									DMA_TransferDescriptor_t *DMADescriptor,
+									uint32_t src,
+									uint32_t dst,
+									uint32_t Size,
+									GPDMA_FLOW_CONTROL_T TransferType,
+									const DMA_TransferDescriptor_t *NextDescriptor)
+{
+	int ret;
+	GPDMA_CH_CFG_T GPDMACfg;
+
+	ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, 0, src, dst, Size, TransferType);
+	if (ret < 0) {
+		return ERROR;
+	}
+
+	/* Adjust src/dst index if they are memory */
+	if (ret & 1) {
+		src = 0;
+	}
+
+	if (ret & 2) {
+		dst = 0;
+	}
+
+	DMADescriptor->src  = GPDMACfg.SrcAddr;
+	DMADescriptor->dst  = GPDMACfg.DstAddr;
+	DMADescriptor->lli  = (uint32_t) NextDescriptor;
+	DMADescriptor->ctrl = makeCtrlWord(&GPDMACfg,
+									   (uint32_t) GPDMA_LUTPerBurst[src],
+									   (uint32_t) GPDMA_LUTPerBurst[dst],
+									   (uint32_t) GPDMA_LUTPerWid[src],
+									   (uint32_t) GPDMA_LUTPerWid[dst]);
+
+	/* By default set interrupt only for last transfer */
+	if (NextDescriptor) {
+		DMADescriptor->ctrl &= ~GPDMA_DMACCxControl_I;
+	}
+
+	return SUCCESS;
+}
+
+/* Do a DMA scatter-gather transfer M2M, M2P,P2M or P2P using DMA descriptors */
+Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
+							 uint8_t ChannelNum,
+							 const DMA_TransferDescriptor_t *DMADescriptor,
+							 GPDMA_FLOW_CONTROL_T TransferType)
+{
+	const DMA_TransferDescriptor_t *dsc = DMADescriptor;
+	GPDMA_CH_CFG_T GPDMACfg;
+	uint8_t SrcPeripheral = 0, DstPeripheral = 0;
+	uint32_t src = DMADescriptor->src, dst = DMADescriptor->dst;
+	int ret;
+
+	ret = Chip_GPDMA_InitChannelCfg(pGPDMA, &GPDMACfg, ChannelNum, src, dst, 0, TransferType);
+	if (ret < 0) {
+		return ERROR;
+	}
+
+	/* Adjust src/dst index if they are memory */
+	if (ret & 1) {
+		src = 0;
+	}
+	else {
+		SrcPeripheral = configDMAMux(src);
+	}
+
+	if (ret & 2) {
+		dst = 0;
+	}
+	else {
+		DstPeripheral = configDMAMux(dst);
+	}
+
+	if (setupChannel(pGPDMA, &GPDMACfg, dsc->ctrl, dsc->lli, SrcPeripheral, DstPeripheral) == ERROR) {
+		return ERROR;
+	}
+
+	/* Start the Channel */
+	Chip_GPDMA_ChannelCmd(pGPDMA, ChannelNum, ENABLE);
+	return SUCCESS;
+}
+
+/* Get a free GPDMA channel for one DMA connection */
+uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA,
+								  uint32_t PeripheralConnection_ID)
+{
+	uint8_t temp = 0;
+	for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++) {
+		if (!Chip_GPDMA_IntGetStatus(pGPDMA, GPDMA_STAT_ENABLED_CH,
+									 temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) {
+			ChannelHandlerArray[temp].ChannelStatus = ENABLE;
+			return temp;
+		}
+	}
+	return 0;
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c
new file mode 100644
index 000000000..a029d057b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c
@@ -0,0 +1,46 @@
+/*
+ * @brief LPC17xx/40xx GPIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/gpioint_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/gpioint_17xx_40xx.c
new file mode 100644
index 000000000..58b7ccf32
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/gpioint_17xx_40xx.c
@@ -0,0 +1,46 @@
+/*
+ * @brief LPC17xx/40xx GPIO Interrupt driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/i2c_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/i2c_17xx_40xx.c
new file mode 100644
index 000000000..f1711b533
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/i2c_17xx_40xx.c
@@ -0,0 +1,561 @@
+/*
+ * @brief LPC17xx/40xx I2C driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+/* Control flags */
+#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
+#define LPC_I2Cx(id)      ((i2c[id].ip))
+#define SLAVE_ACTIVE(iic) (((iic)->flags & 0xFF00) != 0)
+
+#ifdef CHIP_LPC175X_6X
+static const CHIP_SYSCTL_PCLK_T I2C_PeriphClk[I2C_NUM_INTERFACE] = {
+	SYSCTL_PCLK_I2C0,
+	SYSCTL_PCLK_I2C1,
+	SYSCTL_PCLK_I2C2
+};
+#endif
+
+/* I2C common interface structure */
+struct i2c_interface {
+	LPC_I2C_T *ip;		/* IP base address of the I2C device */
+	CHIP_SYSCTL_CLOCK_T clk;	/* Clock used by I2C */
+	I2C_EVENTHANDLER_T mEvent;	/* Current active Master event handler */
+	I2C_EVENTHANDLER_T sEvent;	/* Slave transfer events */
+	I2C_XFER_T *mXfer;	/* Current active xfer pointer */
+	I2C_XFER_T *sXfer;	/* Pointer to store xfer when bus is busy */
+	uint32_t flags;		/* Flags used by I2C master and slave */
+};
+
+/* Slave interface structure */
+struct i2c_slave_interface {
+	I2C_XFER_T *xfer;
+	I2C_EVENTHANDLER_T event;
+};
+
+/* I2C interfaces */
+static struct i2c_interface i2c[I2C_NUM_INTERFACE] = {
+	{LPC_I2C0, SYSCTL_CLOCK_I2C0, Chip_I2C_EventHandler, NULL, NULL, NULL, 0},
+	{LPC_I2C1, SYSCTL_CLOCK_I2C1, Chip_I2C_EventHandler, NULL, NULL, NULL, 0},
+	{LPC_I2C2, SYSCTL_CLOCK_I2C2, Chip_I2C_EventHandler, NULL, NULL, NULL, 0}
+};
+
+static struct i2c_slave_interface i2c_slave[I2C_NUM_INTERFACE][I2C_SLAVE_NUM_INTERFACE];
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+STATIC INLINE void enableClk(I2C_ID_T id)
+{
+	Chip_Clock_EnablePeriphClock(i2c[id].clk);
+}
+
+STATIC INLINE void disableClk(I2C_ID_T id)
+{
+	Chip_Clock_DisablePeriphClock(i2c[id].clk);
+}
+
+/* Get the ADC Clock Rate */
+STATIC INLINE uint32_t getClkRate(I2C_ID_T id)
+{
+#if defined(CHIP_LPC175X_6X)
+	return Chip_Clock_GetPeripheralClockRate(I2C_PeriphClk[id]);
+#else
+	return Chip_Clock_GetPeripheralClockRate();
+#endif
+}
+
+/* Enable I2C and start master transfer */
+STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C)
+{
+	/* Reset STA, STO, SI */
+	pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
+
+	/* Enter to Master Transmitter mode */
+	pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
+}
+
+/* Enable I2C and enable slave transfers */
+STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C)
+{
+	/* Reset STA, STO, SI */
+	pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
+
+	/* Enter to Master Transmitter mode */
+	pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
+}
+
+/* Check if I2C bus is free */
+STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C)
+{
+	return !(pI2C->CONSET & I2C_CON_STO);
+}
+
+/* Get current state of the I2C peripheral */
+STATIC INLINE int getCurState(LPC_I2C_T *pI2C)
+{
+	return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
+}
+
+/* Check if the active state belongs to master mode*/
+STATIC INLINE int isMasterState(LPC_I2C_T *pI2C)
+{
+	return getCurState(pI2C) < 0x60;
+}
+
+/* Set OWN slave address for specific slave ID */
+STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
+{
+	uint32_t index = (uint32_t) sid - 1;
+	pI2C->MASK[index] = mask;
+	if (sid == I2C_SLAVE_0) {
+		pI2C->ADR0 = addr;
+	}
+	else {
+		volatile uint32_t *abase = &pI2C->ADR1;
+		abase[index - 1] = addr;
+	}
+}
+
+/* Match the slave address */
+STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask)
+{
+	mask |= 1;
+	return (addr1 & ~mask) == (addr2 & ~mask);
+}
+
+/* Get the index of the active slave */
+STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr)
+{
+	if (!(slaveAddr >> 1)) {
+		return I2C_SLAVE_GENERAL;					/* General call address */
+	}
+	if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) {
+		return I2C_SLAVE_0;
+	}
+	if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) {
+		return I2C_SLAVE_1;
+	}
+	if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) {
+		return I2C_SLAVE_2;
+	}
+	if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) {
+		return I2C_SLAVE_3;
+	}
+
+	/* If everything is fine the code should never come here */
+	return I2C_SLAVE_GENERAL;
+}
+
+/* Master transfer state change handler handler */
+int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T  *xfer)
+{
+	uint32_t cclr = I2C_CON_FLAGS;
+
+	switch (getCurState(pI2C)) {
+	case 0x08:		/* Start condition on bus */
+	case 0x10:		/* Repeated start condition */
+		pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
+		break;
+
+	/* Tx handling */
+	case 0x18:		/* SLA+W sent and ACK received */
+	case 0x28:		/* DATA sent and ACK received */
+		if (!xfer->txSz) {
+			cclr &= ~(xfer->rxSz ? I2C_CON_STA : I2C_CON_STO);
+		}
+		else {
+			pI2C->DAT = *xfer->txBuff++;
+			xfer->txSz--;
+		}
+		break;
+
+	/* Rx handling */
+	case 0x58:		/* Data Received and NACK sent */
+		cclr &= ~I2C_CON_STO;
+
+	case 0x50:		/* Data Received and ACK sent */
+		*xfer->rxBuff++ = pI2C->DAT;
+		xfer->rxSz--;
+
+	case 0x40:		/* SLA+R sent and ACK received */
+		if (xfer->rxSz > 1) {
+			cclr &= ~I2C_CON_AA;
+		}
+		break;
+
+	/* NAK Handling */
+	case 0x20:		/* SLA+W sent NAK received */
+	case 0x30:		/* DATA sent NAK received */
+	case 0x48:		/* SLA+R sent NAK received */
+		xfer->status = I2C_STATUS_NAK;
+		cclr &= ~I2C_CON_STO;
+		break;
+
+	case 0x38:		/* Arbitration lost */
+		xfer->status = I2C_STATUS_ARBLOST;
+		break;
+
+	/* Bus Error */
+	case 0x00:
+		xfer->status = I2C_STATUS_BUSERR;
+		cclr &= ~I2C_CON_STO;
+	}
+
+	/* Set clear control flags */
+	pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
+	pI2C->CONCLR = cclr;
+
+	/* If stopped return 0 */
+	if (!(cclr & I2C_CON_STO) || (xfer->status == I2C_STATUS_ARBLOST)) {
+		if (xfer->status == I2C_STATUS_BUSY) {
+			xfer->status = I2C_STATUS_DONE;
+		}
+		return 0;
+	}
+	return 1;
+}
+
+/* Find the slave address of SLA+W or SLA+R */
+I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C)
+{
+	switch (getCurState(pI2C)) {
+	case 0x60:
+	case 0x68:
+	case 0x70:
+	case 0x78:
+	case 0xA8:
+	case 0xB0:
+		return lookupSlaveIndex(pI2C, pI2C->DAT);
+	}
+
+	/* If everything is fine code should never come here */
+	return I2C_SLAVE_GENERAL;
+}
+
+/* Slave state machine handler */
+int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
+{
+	uint32_t cclr = I2C_CON_FLAGS;
+	int ret = RET_SLAVE_BUSY;
+
+	xfer->status = I2C_STATUS_BUSY;
+	switch (getCurState(pI2C)) {
+	case 0x80:		/* SLA: Data received + ACK sent */
+	case 0x90:		/* GC: Data received + ACK sent */
+		*xfer->rxBuff++ = pI2C->DAT;
+		xfer->rxSz--;
+		ret = RET_SLAVE_RX;
+		if (xfer->rxSz > 1) {
+			cclr &= ~I2C_CON_AA;
+		}
+		break;
+
+	case 0x60:		/* Own SLA+W received */
+	case 0x68:		/* Own SLA+W received after losing arbitration */
+	case 0x70:		/* GC+W received */
+	case 0x78:		/* GC+W received after losing arbitration */
+		xfer->slaveAddr = pI2C->DAT & ~1;
+		if (xfer->rxSz > 1) {
+			cclr &= ~I2C_CON_AA;
+		}
+		break;
+
+	case 0xA8:		/* SLA+R received */
+	case 0xB0:		/* SLA+R received after losing arbitration */
+		xfer->slaveAddr = pI2C->DAT & ~1;
+
+	case 0xB8:		/* DATA sent and ACK received */
+		pI2C->DAT = *xfer->txBuff++;
+		xfer->txSz--;
+		if (xfer->txSz > 0) {
+			cclr &= ~I2C_CON_AA;
+		}
+		ret = RET_SLAVE_TX;
+		break;
+
+	case 0xC0:		/* Data transmitted and NAK received */
+	case 0xC8:		/* Last data transmitted and ACK received */
+	case 0x88:		/* SLA: Data received + NAK sent */
+	case 0x98:		/* GC: Data received + NAK sent */
+	case 0xA0:		/* STOP/Repeated START condition received */
+		ret = RET_SLAVE_IDLE;
+		cclr &= ~I2C_CON_AA;
+		xfer->status = I2C_STATUS_DONE;
+		if (xfer->slaveAddr & 1) {
+			cclr &= ~I2C_CON_STA;
+		}
+		break;
+	}
+
+	/* Set clear control flags */
+	pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
+	pI2C->CONCLR = cclr;
+
+	return ret;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+/* Chip event handler interrupt based */
+void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event)
+{
+	struct i2c_interface *iic = &i2c[id];
+	volatile I2C_STATUS_T *stat;
+
+	/* Only WAIT event needs to be handled */
+	if (event != I2C_EVENT_WAIT) {
+		return;
+	}
+
+	stat = &iic->mXfer->status;
+	/* Wait for the status to change */
+	while (*stat == I2C_STATUS_BUSY) {}
+}
+
+/* Chip polling event handler */
+void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event)
+{
+	struct i2c_interface *iic = &i2c[id];
+	volatile I2C_STATUS_T *stat;
+
+	/* Only WAIT event needs to be handled */
+	if (event != I2C_EVENT_WAIT) {
+		return;
+	}
+
+	stat = &iic->mXfer->status;
+	/* Call the state change handler till xfer is done */
+	while (*stat == I2C_STATUS_BUSY) {
+		if (Chip_I2C_IsStateChanged(id)) {
+			Chip_I2C_MasterStateHandler(id);
+		}
+	}
+}
+
+/* Initializes the LPC_I2C peripheral with specified parameter */
+void Chip_I2C_Init(I2C_ID_T id)
+{
+	enableClk(id);
+
+	/* Set I2C operation to default */
+	LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
+}
+
+/* De-initializes the I2C peripheral registers to their default reset values */
+void Chip_I2C_DeInit(I2C_ID_T id)
+{
+	/* Disable I2C control */
+	LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
+
+	disableClk(id);
+}
+
+/* Set up clock rate for LPC_I2C peripheral */
+void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate)
+{
+	uint32_t SCLValue;
+
+	SCLValue = (getClkRate(id) / clockrate);
+	LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1);
+	LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH);
+}
+
+/* Get current clock rate for LPC_I2C peripheral */
+uint32_t Chip_I2C_GetClockRate(I2C_ID_T id)
+{
+	return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL);
+}
+
+/* Set the master event handler */
+int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event)
+{
+	struct i2c_interface *iic = &i2c[id];
+	if (!iic->mXfer) {
+		iic->mEvent = event;
+	}
+	return iic->mEvent == event;
+}
+
+/* Get the master event handler */
+I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id)
+{
+	return i2c[id].mEvent;
+}
+
+/* Transmit and Receive data in master mode */
+int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer)
+{
+	struct i2c_interface *iic = &i2c[id];
+
+	iic->mEvent(id, I2C_EVENT_LOCK);
+	xfer->status = I2C_STATUS_BUSY;
+	iic->mXfer = xfer;
+
+	/* If slave xfer not in progress */
+	if (!iic->sXfer) {
+		startMasterXfer(iic->ip);
+	}
+	iic->mEvent(id, I2C_EVENT_WAIT);
+	iic->mXfer = 0;
+
+	/* Wait for stop condition to appear on bus */
+	while (!isI2CBusFree(iic->ip)) {}
+
+	/* Start slave if one is active */
+	if (SLAVE_ACTIVE(iic)) {
+		startSlaverXfer(iic->ip);
+	}
+
+	iic->mEvent(id, I2C_EVENT_UNLOCK);
+	return (int) xfer->status;
+}
+
+/* Master tx only */
+int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len)
+{
+	I2C_XFER_T xfer = {0};
+	xfer.slaveAddr = slaveAddr;
+	xfer.txBuff = buff;
+	xfer.txSz = len;
+	while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
+	return len - xfer.txSz;
+}
+
+/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
+ * This function is useful for communicating with the I2C slave registers
+ */
+int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len)
+{
+	I2C_XFER_T xfer = {0};
+	xfer.slaveAddr = slaveAddr;
+	xfer.txBuff = &cmd;
+	xfer.txSz = 1;
+	xfer.rxBuff = buff;
+	xfer.rxSz = len;
+	while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
+	return len - xfer.rxSz;
+}
+
+/* Sequential master read */
+int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len)
+{
+	I2C_XFER_T xfer = {0};
+	xfer.slaveAddr = slaveAddr;
+	xfer.rxBuff = buff;
+	xfer.rxSz = len;
+	while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
+	return len - xfer.rxSz;
+}
+
+/* Check if master state is active */
+int Chip_I2C_IsMasterActive(I2C_ID_T id)
+{
+	return isMasterState(i2c[id].ip);
+}
+
+/* State change handler for master transfer */
+void Chip_I2C_MasterStateHandler(I2C_ID_T id)
+{
+	if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) {
+		i2c[id].mEvent(id, I2C_EVENT_DONE);
+	}
+}
+
+/* Setup slave function */
+void Chip_I2C_SlaveSetup(I2C_ID_T id,
+						 I2C_SLAVE_ID sid,
+						 I2C_XFER_T *xfer,
+						 I2C_EVENTHANDLER_T event,
+						 uint8_t addrMask)
+{
+	struct i2c_interface *iic = &i2c[id];
+	struct i2c_slave_interface *si2c = &i2c_slave[id][sid];
+	si2c->xfer = xfer;
+	si2c->event = event;
+
+	/* Set up the slave address */
+	if (sid != I2C_SLAVE_GENERAL) {
+		setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask);
+	}
+
+	if (!SLAVE_ACTIVE(iic) && !iic->mXfer) {
+		startSlaverXfer(iic->ip);
+	}
+	iic->flags |= 1 << (sid + 8);
+}
+
+/* I2C Slave event handler */
+void Chip_I2C_SlaveStateHandler(I2C_ID_T id)
+{
+	int ret;
+	struct i2c_interface *iic = &i2c[id];
+
+	/* Get the currently addressed slave */
+	if (!iic->sXfer) {
+		struct i2c_slave_interface *si2c;
+
+		I2C_SLAVE_ID sid = getSlaveIndex(iic->ip);
+		si2c = &i2c_slave[id][sid];
+		iic->sXfer = si2c->xfer;
+		iic->sEvent = si2c->event;
+	}
+
+	iic->sXfer->slaveAddr |= iic->mXfer != 0;
+	ret = handleSlaveXferState(iic->ip, iic->sXfer);
+	if (ret) {
+		if (iic->sXfer->status == I2C_STATUS_DONE) {
+			iic->sXfer = 0;
+		}
+		iic->sEvent(id, (I2C_EVENT_T) ret);
+	}
+}
+
+/* Disable I2C device */
+void Chip_I2C_Disable(I2C_ID_T id)
+{
+	LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC;
+}
+
+/* State change checking */
+int Chip_I2C_IsStateChanged(I2C_ID_T id)
+{
+	return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0;
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/i2s_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/i2s_17xx_40xx.c
new file mode 100644
index 000000000..6cdd43676
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/i2s_17xx_40xx.c
@@ -0,0 +1,260 @@
+/*
+ * @brief LPC17xx/40xx I2S driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Get divider value */
+STATIC Status getClkDiv(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format, uint16_t *pxDiv, uint16_t *pyDiv, uint32_t *pN)
+{
+	uint32_t pClk;
+	uint32_t x, y;
+	uint64_t divider;
+	uint16_t dif;
+	uint16_t xDiv = 0, yDiv = 0;
+	uint32_t N;
+	uint16_t err, ErrorOptimal = 0xFFFF;
+
+#if defined(CHIP_LPC175X_6X)
+	pClk = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_I2S);
+#else
+	pClk = Chip_Clock_GetPeripheralClockRate();
+#endif
+
+	/* divider is a fixed point number with 16 fractional bits */
+	divider = (((uint64_t) (format->SampleRate) * 2 * (format->WordWidth) * 2) << 16) / pClk;
+	/* find N that make x/y <= 1 -> divider <= 2^16 */
+	for (N = 64; N > 0; N--) {
+		if ((divider * N) < (1 << 16)) {
+			break;
+		}
+	}
+	if (N == 0) {
+		return ERROR;
+	}
+	divider *= N;
+	for (y = 255; y > 0; y--) {
+		x = y * divider;
+		if (x & (0xFF000000)) {
+			continue;
+		}
+		dif = x & 0xFFFF;
+		if (dif > 0x8000) {
+			err = 0x10000 - dif;
+		}
+		else {
+			err = dif;
+		}
+		if (err == 0) {
+			yDiv = y;
+			break;
+		}
+		else if (err < ErrorOptimal) {
+			ErrorOptimal = err;
+			yDiv = y;
+		}
+	}
+	xDiv = ((uint64_t) yDiv * (format->SampleRate) * 2 * (format->WordWidth) * N * 2) / pClk;
+	if (xDiv >= 256) {
+		xDiv = 0xFF;
+	}
+	if (xDiv == 0) {
+		xDiv = 1;
+	}
+
+	*pxDiv = xDiv;
+	*pyDiv = yDiv;
+	*pN = N;
+	return SUCCESS;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the I2S interface */
+void Chip_I2S_Init(LPC_I2S_T *pI2S)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2S);
+}
+
+/* Shutdown I2S */
+void Chip_I2S_DeInit(LPC_I2S_T *pI2S)
+{
+	pI2S->DAI = 0x07E1;
+	pI2S->DAO = 0x87E1;
+	pI2S->IRQ = 0;
+	pI2S->TXMODE = 0;
+	pI2S->RXMODE = 0;
+	pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] = 0;
+	pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] = 0;
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_I2S);
+}
+
+/* Configure I2S for Audio Format input */
+Status Chip_I2S_TxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format)
+{
+	uint32_t temp;
+	uint16_t xDiv, yDiv;
+	uint32_t N;
+
+	if (getClkDiv(pI2S, format, &xDiv, &yDiv, &N) == ERROR) {
+		return ERROR;
+	}
+
+	temp = pI2S->DAO & (~(I2S_DAO_WORDWIDTH_MASK | I2S_DAO_MONO | I2S_DAO_SLAVE | I2S_DAO_WS_HALFPERIOD_MASK));
+	if (format->WordWidth <= 8) {
+		temp |= I2S_WORDWIDTH_8;
+	}
+	else if (format->WordWidth <= 16) {
+		temp |= I2S_WORDWIDTH_16;
+	}
+	else {
+		temp |= I2S_WORDWIDTH_32;
+	}
+
+	temp |= (format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO;
+	temp |= I2S_MASTER_MODE;
+	temp |= I2S_DAO_WS_HALFPERIOD(format->WordWidth - 1);
+	pI2S->DAO = temp;
+	pI2S->TXMODE = I2S_TXMODE_CLKSEL(0);
+	pI2S->TXBITRATE = N - 1;
+	pI2S->TXRATE = yDiv | (xDiv << 8);
+	return SUCCESS;
+}
+
+/* Configure I2S for Audio Format input */
+Status Chip_I2S_RxConfig(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format)
+{
+	uint32_t temp;
+	uint16_t xDiv, yDiv;
+	uint32_t N;
+
+	if (getClkDiv(pI2S, format, &xDiv, &yDiv, &N) == ERROR) {
+		return ERROR;
+	}
+	temp = pI2S->DAI & (~(I2S_DAI_WORDWIDTH_MASK | I2S_DAI_MONO | I2S_DAI_SLAVE | I2S_DAI_WS_HALFPERIOD_MASK));
+	if (format->WordWidth <= 8) {
+		temp |= I2S_WORDWIDTH_8;
+	}
+	else if (format->WordWidth <= 16) {
+		temp |= I2S_WORDWIDTH_16;
+	}
+	else {
+		temp |= I2S_WORDWIDTH_32;
+	}
+
+	temp |= (format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO;
+	temp |= I2S_MASTER_MODE;
+	temp |= I2S_DAI_WS_HALFPERIOD(format->WordWidth - 1);
+	pI2S->DAI = temp;
+	pI2S->RXMODE = I2S_RXMODE_CLKSEL(0);
+	pI2S->RXBITRATE = N - 1;
+	pI2S->RXRATE = yDiv | (xDiv << 8);
+	return SUCCESS;
+}
+
+/* Enable/Disable Interrupt with a specific FIFO depth */
+void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth)
+{
+	uint32_t temp;
+	depth &= 0x0F;
+	if (newState == ENABLE) {
+		pI2S->IRQ |= 0x02;
+	}
+	else {
+		pI2S->IRQ &= (~0x02);
+	}
+	temp = pI2S->IRQ & (~I2S_IRQ_TX_DEPTH_MASK);
+	pI2S->IRQ = temp | (I2S_IRQ_TX_DEPTH(depth));
+}
+
+/* Enable/Disable Interrupt with a specific FIFO depth */
+void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth)
+{
+	uint32_t temp;
+	depth &= 0x0F;
+	if (newState == ENABLE) {
+		pI2S->IRQ |= 0x01;
+	}
+	else {
+		pI2S->IRQ &= (~0x01);
+	}
+	temp = pI2S->IRQ & (~I2S_IRQ_RX_DEPTH_MASK);
+	pI2S->IRQ = temp | (I2S_IRQ_RX_DEPTH(depth));
+}
+
+/* Enable/Disable DMA with a specific FIFO depth */
+void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S,
+						I2S_DMA_CHANNEL_T dmaNum,
+						FunctionalState newState,
+						uint8_t depth)
+{
+	/* Set FIFO Level */
+	pI2S->DMA[dmaNum] &= ~(0x0F << 16);
+	pI2S->DMA[dmaNum] |= depth << 16;
+	/* Enable/Disable I2S transmit*/
+	if (newState == ENABLE) {
+		pI2S->DMA[dmaNum] |= 0x02;
+	}
+	else {
+		pI2S->DMA[dmaNum] &= ~0x02;
+	}
+}
+
+/* Enable/Disable DMA with a specific FIFO depth */
+void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S,
+						I2S_DMA_CHANNEL_T dmaNum,
+						FunctionalState newState,
+						uint8_t depth)
+{
+	/* Set FIFO Level */
+	pI2S->DMA[dmaNum] &= ~(0x0F << 8);
+	pI2S->DMA[dmaNum] |= depth << 8;
+	/* Enable/Disable I2S Receive */
+	if (newState == ENABLE) {
+		pI2S->DMA[dmaNum] |= 0x01;
+	}
+	else {
+		pI2S->DMA[dmaNum] &= ~0x01;
+	}
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/iap.c b/hw/mcu/nxp/lpc_chip_40xx/src/iap.c
new file mode 100644
index 000000000..76f72a2f5
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/iap.c
@@ -0,0 +1,175 @@
+/*
+ * @brief Common FLASH support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Prepare sector for write operation */
+uint8_t Chip_IAP_PreSectorForReadWrite(uint32_t strSector, uint32_t endSector)
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_PREWRRITE_CMD;
+	command[1] = strSector;
+	command[2] = endSector;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* Copy RAM to flash */
+uint8_t Chip_IAP_CopyRamToFlash(uint32_t dstAdd, uint32_t *srcAdd, uint32_t byteswrt)
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_WRISECTOR_CMD;
+	command[1] = dstAdd;
+	command[2] = (uint32_t) srcAdd;
+	command[3] = byteswrt;
+	command[4] = SystemCoreClock / 1000;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* Erase sector */
+uint8_t Chip_IAP_EraseSector(uint32_t strSector, uint32_t endSector)
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_ERSSECTOR_CMD;
+	command[1] = strSector;
+	command[2] = endSector;
+	command[3] = SystemCoreClock / 1000;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* Blank check sector */
+uint8_t Chip_IAP_BlankCheckSector(uint32_t strSector, uint32_t endSector)
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_BLANK_CHECK_SECTOR_CMD;
+	command[1] = strSector;
+	command[2] = endSector;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* Read part identification number */
+uint32_t Chip_IAP_ReadPID()
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_REPID_CMD;
+	iap_entry(command, result);
+
+	return result[1];
+}
+
+/* Read boot code version number */
+uint8_t Chip_IAP_ReadBootCode()
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_READ_BOOT_CODE_CMD;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* IAP compare */
+uint8_t Chip_IAP_Compare(uint32_t dstAdd, uint32_t srcAdd, uint32_t bytescmp)
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_COMPARE_CMD;
+	command[1] = dstAdd;
+	command[2] = srcAdd;
+	command[3] = bytescmp;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* Reinvoke ISP */
+uint8_t Chip_IAP_ReinvokeISP()
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_REINVOKE_ISP_CMD;
+	iap_entry(command, result);
+
+	return result[0];
+}
+
+/* Read the unique ID */
+uint32_t Chip_IAP_ReadUID()
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_READ_UID_CMD;
+	iap_entry(command, result);
+
+	return result[1];
+}
+
+/* Erase page */
+uint8_t Chip_IAP_ErasePage(uint32_t strPage, uint32_t endPage)
+{
+	uint32_t command[5], result[4];
+
+	command[0] = IAP_ERASE_PAGE_CMD;
+	command[1] = strPage;
+	command[2] = endPage;
+	command[3] = SystemCoreClock / 1000;
+	iap_entry(command, result);
+
+	return result[0];
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c
new file mode 100644
index 000000000..0e00a5b8e
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c
@@ -0,0 +1,83 @@
+/*
+ * @brief LPC17xx/40xx IOCON driver
+ *
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+#if defined(CHIP_LPC175X_6X)
+/* Sets I/O Control pin mux */
+void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+	Chip_IOCON_PinMux(pIOCON, port, pin, 
+					  /* mode is in bits 3:2 */
+					  modefunc >> 2, 
+					  /* func is in bits 1:0 */
+					  modefunc & 3 );
+}
+
+/* Setup pin modes and function */
+void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t mode, uint8_t func)
+{
+	uint8_t reg, bitPos;
+	uint32_t temp;
+
+	bitPos =  IOCON_BIT_INDEX(pin);
+	reg = IOCON_REG_INDEX(port,pin);
+	
+	temp = pIOCON->PINSEL[reg] & ~(0x03UL << bitPos);
+	pIOCON->PINSEL[reg] = temp | (func << bitPos);
+
+	temp = pIOCON->PINMODE[reg] & ~(0x03UL << bitPos);
+	pIOCON->PINMODE[reg] = temp | (mode << bitPos);
+}
+#endif /* defined(CHIP_LPC175X_6X) */
+
+/* Set all I/O Control pin muxing */
+void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T* pinArray, uint32_t arrayLength)
+{
+	uint32_t ix;
+
+	for (ix = 0; ix < arrayLength; ix++ ) {
+		Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].pingrp, pinArray[ix].pinnum, pinArray[ix].modefunc);
+	}
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/lcd_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/lcd_17xx_40xx.c
new file mode 100644
index 000000000..c89ead222
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/lcd_17xx_40xx.c
@@ -0,0 +1,210 @@
+/*
+ * @brief LCD chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+static LCD_CURSOR_SIZE_OPT_T LCD_Cursor_Size = LCD_CURSOR_64x64;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the LCD controller */
+void Chip_LCD_Init(LPC_LCD_T *pLCD, LCD_CONFIG_T *LCD_ConfigStruct)
+{
+	uint32_t i, regValue, *pPal;
+	uint32_t pcd;
+
+	/* Enable LCD Clock */
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_LCD);
+
+	/* disable the display */
+	pLCD->CTRL &= ~CLCDC_LCDCTRL_ENABLE;
+
+	/* Setting LCD_TIMH register */
+	regValue = ( ((((LCD_ConfigStruct->PPL / 16) - 1) & 0x3F) << 2)
+				 |         (( (LCD_ConfigStruct->HSW - 1)    & 0xFF) << 8)
+				 |         (( (LCD_ConfigStruct->HFP - 1)    & 0xFF) << 16)
+				 |         (( (LCD_ConfigStruct->HBP - 1)    & 0xFF) << 24) );
+	pLCD->TIMH = regValue;
+
+	/* Setting LCD_TIMV register */
+	regValue = ((((LCD_ConfigStruct->LPP - 1) & 0x3FF) << 0)
+				|        (((LCD_ConfigStruct->VSW - 1) & 0x03F) << 10)
+				|        (((LCD_ConfigStruct->VFP - 1) & 0x0FF) << 16)
+				|        (((LCD_ConfigStruct->VBP - 1) & 0x0FF) << 24) );
+	pLCD->TIMV = regValue;
+
+	/* Generate the clock and signal polarity control word */
+	regValue = 0;
+	regValue = (((LCD_ConfigStruct->ACB - 1) & 0x1F) << 6);
+	regValue |= (LCD_ConfigStruct->IOE & 1) << 14;
+	regValue |= (LCD_ConfigStruct->IPC & 1) << 13;
+	regValue |= (LCD_ConfigStruct->IHS & 1) << 12;
+	regValue |= (LCD_ConfigStruct->IVS & 1) << 11;
+
+	/* Compute clocks per line based on panel type */
+	switch (LCD_ConfigStruct->LCD) {
+	case LCD_MONO_4:
+		regValue |= ((((LCD_ConfigStruct->PPL / 4) - 1) & 0x3FF) << 16);
+		break;
+
+	case LCD_MONO_8:
+		regValue |= ((((LCD_ConfigStruct->PPL / 8) - 1) & 0x3FF) << 16);
+		break;
+
+	case LCD_CSTN:
+		regValue |= (((((LCD_ConfigStruct->PPL * 3) / 8) - 1) & 0x3FF) << 16);
+		break;
+
+	case LCD_TFT:
+	default:
+		regValue |=	 /*1<<26 |*/ (((LCD_ConfigStruct->PPL - 1) & 0x3FF) << 16);
+	}
+
+	/* panel clock divisor */
+	pcd = 5;// LCD_ConfigStruct->pcd;   /* TODO: should be calculated from LCDDCLK */
+	pcd &= 0x3FF;
+	regValue |=  ((pcd >> 5) << 27) | ((pcd) & 0x1F);
+	pLCD->POL = regValue;
+
+	/* disable interrupts */
+	pLCD->INTMSK = 0;
+
+	/* set bits per pixel */
+	regValue = LCD_ConfigStruct->BPP << 1;
+
+	/* set color format RGB */
+	regValue |= LCD_ConfigStruct->color_format << 8;
+	regValue |= LCD_ConfigStruct->LCD << 4;
+	if (LCD_ConfigStruct->Dual == 1) {
+		regValue |= 1 << 7;
+	}
+	pLCD->CTRL = regValue;
+
+	/* clear palette */
+	pPal = (uint32_t *) (&(pLCD->PAL));
+	for (i = 0; i < 128; i++) {
+		*pPal = 0;
+		pPal++;
+	}
+}
+
+/* Shutdown the LCD controller */
+void Chip_LCD_DeInit(LPC_LCD_T *pLCD)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_LCD);
+}
+
+/* Configure Cursor */
+void Chip_LCD_Cursor_Config(LPC_LCD_T *pLCD, LCD_CURSOR_SIZE_OPT_T cursor_size, bool sync)
+{
+	LCD_Cursor_Size = cursor_size;
+	pLCD->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size;
+}
+
+/* Write Cursor Image into Internal Cursor Image Buffer */
+void Chip_LCD_Cursor_WriteImage(LPC_LCD_T *pLCD, uint8_t cursor_num, void *Image)
+{
+	int i, j;
+	uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image;
+
+	/* Check if Cursor Size was configured as 32x32 or 64x64*/
+	if (LCD_Cursor_Size == LCD_CURSOR_32x32) {
+		i = cursor_num * 64;
+		j = i + 64;
+	}
+	else {
+		i = 0;
+		j = 256;
+	}
+	fifoptr = (void *) &(pLCD->CRSR_IMG[0]);
+
+	/* Copy Cursor Image content to FIFO */
+	for (; i < j; i++) {
+
+		*fifoptr = *crsr_ptr;
+		crsr_ptr++;
+		fifoptr++;
+	}
+}
+
+/* Load LCD Palette */
+void Chip_LCD_LoadPalette(LPC_LCD_T *pLCD, void *palette)
+{
+	LCD_PALETTE_ENTRY_T pal_entry, *ptr_pal_entry;
+	uint8_t i, *pal_ptr;
+	/* This function supports loading of the color palette from
+	   the C file generated by the bmp2c utility. It expects the
+	   palette to be passed as an array of 32-bit BGR entries having
+	   the following format:
+	   2:0 - Not used
+	   7:3 - Blue
+	   10:8 - Not used
+	   15:11 - Green
+	   18:16 - Not used
+	   23:19 - Red
+	   31:24 - Not used
+	   arg = pointer to input palette table address */
+	ptr_pal_entry = &pal_entry;
+	pal_ptr = (uint8_t *) palette;
+
+	/* 256 entry in the palette table */
+	for (i = 0; i < 256 / 2; i++) {
+		pal_entry.Bl = (*pal_ptr++) >> 3;	/* blue first */
+		pal_entry.Gl = (*pal_ptr++) >> 3;	/* get green */
+		pal_entry.Rl = (*pal_ptr++) >> 3;	/* get red */
+		pal_ptr++;	/* skip over the unused byte */
+		/* do the most significant halfword of the palette */
+		pal_entry.Bu = (*pal_ptr++) >> 3;	/* blue first */
+		pal_entry.Gu = (*pal_ptr++) >> 3;	/* get green */
+		pal_entry.Ru = (*pal_ptr++) >> 3;	/* get red */
+		pal_ptr++;	/* skip over the unused byte */
+
+		pLCD->PAL[i] = *((uint32_t *) ptr_pal_entry);
+	}
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/pmu_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/pmu_17xx_40xx.c
new file mode 100644
index 000000000..8b5a841ad
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/pmu_17xx_40xx.c
@@ -0,0 +1,118 @@
+/*
+ * @brief LPC15xx PMU chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Enter MCU Sleep mode */
+void Chip_PMU_SleepState(LPC_PMU_T *pPMU)
+{
+	/* Select Sleep/Deep Sleep mode */
+	pPMU->PCON &= ~(PMU_PCON_PM1_FLAG | PMU_PCON_PM0_FLAG);
+
+	/* Clearing SLEEPDEEP bit in SCR makes it Sleep mode */
+	SCB->SCR &= ~(1UL << SCB_SCR_SLEEPDEEP_Pos);
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Enter MCU Deep Sleep mode */
+void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU)
+{
+	/* Select Sleep/Deep Sleep mode */
+	pPMU->PCON &= ~(PMU_PCON_PM1_FLAG | PMU_PCON_PM0_FLAG);
+
+	/* Setting SLEEPDEEP bit in SCR makes it Deep Sleep mode */
+	SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Enter MCU Power down mode */
+void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU)
+{
+	/* Select power down mode */
+	pPMU->PCON = (pPMU->PCON & ~PMU_PCON_PM1_FLAG) | PMU_PCON_PM0_FLAG;
+
+	/* Setting SLEEPDEEP bit in SCR makes it power down mode */
+	SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Enter MCU Deep Power down mode */
+void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU)
+{
+	/* Select deep power down mode */
+	pPMU->PCON |= PMU_PCON_PM1_FLAG | PMU_PCON_PM0_FLAG;
+
+	/* Setting SLEEPDEEP bit in SCR makes it deep power down mode */
+	SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
+
+	/* Enter sleep mode */
+	__WFI();
+}
+
+/* Put some of the peripheral in sleep mode */
+void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode)
+{
+	if (SleepMode == PMU_MCU_DEEP_SLEEP) {
+		Chip_PMU_DeepSleepState(pPMU);
+	}
+	else if (SleepMode == PMU_MCU_POWER_DOWN) {
+		Chip_PMU_PowerDownState(pPMU);
+	}
+	else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
+		Chip_PMU_DeepPowerDownState(pPMU);
+	}
+	else {
+		/* PMU_MCU_SLEEP */
+		Chip_PMU_SleepState(pPMU);
+	}
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/ring_buffer.c b/hw/mcu/nxp/lpc_chip_40xx/src/ring_buffer.c
new file mode 100644
index 000000000..47a0c34f9
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/ring_buffer.c
@@ -0,0 +1,167 @@
+/*
+ * @brief Common ring buffer support functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include <string.h>
+#include "ring_buffer.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define RB_INDH(rb)                ((rb)->head & ((rb)->count - 1))
+#define RB_INDT(rb)                ((rb)->tail & ((rb)->count - 1))
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize ring buffer */
+int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
+{
+	RingBuff->data = buffer;
+	RingBuff->count = count;
+	RingBuff->itemSz = itemSize;
+	RingBuff->head = RingBuff->tail = 0;
+
+	return 1;
+}
+
+/* Insert a single item into Ring Buffer */
+int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
+{
+	uint8_t *ptr = RingBuff->data;
+
+	/* We cannot insert when queue is full */
+	if (RingBuffer_IsFull(RingBuff))
+		return 0;
+
+	ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
+	memcpy(ptr, data, RingBuff->itemSz);
+	RingBuff->head++;
+
+	return 1;
+}
+
+/* Insert multiple items into Ring Buffer */
+int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num)
+{
+	uint8_t *ptr = RingBuff->data;
+	int cnt1, cnt2;
+
+	/* We cannot insert when queue is full */
+	if (RingBuffer_IsFull(RingBuff))
+		return 0;
+
+	/* Calculate the segment lengths */
+	cnt1 = cnt2 = RingBuffer_GetFree(RingBuff);
+	if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count)
+		cnt1 = RingBuff->count - RB_INDH(RingBuff);
+	cnt2 -= cnt1;
+
+	cnt1 = MIN(cnt1, num);
+	num -= cnt1;
+
+	cnt2 = MIN(cnt2, num);
+	num -= cnt2;
+
+	/* Write segment 1 */
+	ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
+	memcpy(ptr, data, cnt1 * RingBuff->itemSz);
+	RingBuff->head += cnt1;
+
+	/* Write segment 2 */
+	ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz;
+	data = (const uint8_t *) data + cnt1 * RingBuff->itemSz;
+	memcpy(ptr, data, cnt2 * RingBuff->itemSz);
+	RingBuff->head += cnt2;
+
+	return cnt1 + cnt2;
+}
+
+/* Pop single item from Ring Buffer */
+int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
+{
+	uint8_t *ptr = RingBuff->data;
+
+	/* We cannot pop when queue is empty */
+	if (RingBuffer_IsEmpty(RingBuff))
+		return 0;
+
+	ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
+	memcpy(data, ptr, RingBuff->itemSz);
+	RingBuff->tail++;
+
+	return 1;
+}
+
+/* Pop multiple items from Ring buffer */
+int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num)
+{
+	uint8_t *ptr = RingBuff->data;
+	int cnt1, cnt2;
+
+	/* We cannot insert when queue is empty */
+	if (RingBuffer_IsEmpty(RingBuff))
+		return 0;
+
+	/* Calculate the segment lengths */
+	cnt1 = cnt2 = RingBuffer_GetCount(RingBuff);
+	if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count)
+		cnt1 = RingBuff->count - RB_INDT(RingBuff);
+	cnt2 -= cnt1;
+
+	cnt1 = MIN(cnt1, num);
+	num -= cnt1;
+
+	cnt2 = MIN(cnt2, num);
+	num -= cnt2;
+
+	/* Write segment 1 */
+	ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
+	memcpy(data, ptr, cnt1 * RingBuff->itemSz);
+	RingBuff->tail += cnt1;
+
+	/* Write segment 2 */
+	ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz;
+	data = (uint8_t *) data + cnt1 * RingBuff->itemSz;
+	memcpy(data, ptr, cnt2 * RingBuff->itemSz);
+	RingBuff->tail += cnt2;
+
+	return cnt1 + cnt2;
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/ritimer_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/ritimer_17xx_40xx.c
new file mode 100644
index 000000000..a94e6175c
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/ritimer_17xx_40xx.c
@@ -0,0 +1,100 @@
+/*
+ * @brief LPC17xx/40xx RITimer driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC175X_6X)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the RIT */
+void Chip_RIT_Init(LPC_RITIMER_T *pRITimer)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RIT);
+	pRITimer->COMPVAL = 0xFFFFFFFF;
+	pRITimer->MASK  = 0x00000000;
+	pRITimer->CTRL  = 0x0C;
+	pRITimer->COUNTER   = 0x00000000;
+}
+
+/* DeInitialize the RIT */
+void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer)
+{
+	Chip_RIT_Init(pRITimer);
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_RIT);
+}
+
+/* Set timer interval value */
+void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval)
+{
+	uint32_t cmp_value;
+
+	/* Determine aapproximate compare value based on clock rate and passed interval */
+	cmp_value = (Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_RIT) / 1000) * time_interval;
+
+	/* Set timer compare value */
+	Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
+
+	/* Set timer enable clear bit to clear timer to 0 whenever
+	   counter value equals the contents of RICOMPVAL */
+	Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR);
+}
+
+/* Check whether interrupt is pending */
+IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)
+{
+	uint8_t result;
+
+	if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) {
+		result = SET;
+	}
+	else {
+		return RESET;
+	}
+
+	return (IntStatus) result;
+}
+
+#endif /* defined(CHIP_LPC175X_6X) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/rtc_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/rtc_17xx_40xx.c
new file mode 100644
index 000000000..3ad88c28d
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/rtc_17xx_40xx.c
@@ -0,0 +1,221 @@
+/*
+ * @brief LPC17xx/40xx RTC chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the RTC peripheral */
+void Chip_RTC_Init(LPC_RTC_T *pRTC)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RTC);
+
+	/* Disable RTC */
+	Chip_RTC_Enable(pRTC, DISABLE);
+
+	/* Disable Calibration */
+	Chip_RTC_CalibCounterCmd(pRTC, DISABLE);
+
+	/* Reset RTC Clock */
+	Chip_RTC_ResetClockTickCounter(pRTC);
+
+	/* Clear counter increment and alarm interrupt */
+	pRTC->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF;
+	while (pRTC->ILR != 0) {}
+
+	/* Clear all register to be default */
+	pRTC->CIIR = 0x00;
+	pRTC->AMR = 0xFF;
+	pRTC->CALIBRATION = 0x00;
+}
+
+/*De-initialize the RTC peripheral */
+void Chip_RTC_DeInit(LPC_RTC_T *pRTC)
+{
+	pRTC->CCR = 0x00;
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_RTC);
+}
+
+/* Reset clock tick counter in the RTC peripheral */
+void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC)
+{
+	do {
+		/* Reset RTC clock*/
+		pRTC->CCR |= RTC_CCR_CTCRST;
+	} while ((pRTC->CCR & RTC_CCR_CTCRST) != RTC_CCR_CTCRST);
+
+	do {
+		/* Finish resetting RTC clock */
+		pRTC->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;
+	} while (pRTC->CCR & RTC_CCR_CTCRST);
+}
+
+/* Start/Stop RTC peripheral */
+void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		do {
+			pRTC->CCR |= RTC_CCR_CLKEN;
+		} while ((pRTC->CCR & RTC_CCR_CLKEN) == 0);
+	}
+	else {
+		pRTC->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
+	}
+}
+
+/* Enable/Disable Counter increment interrupt for a time type in the RTC peripheral */
+void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pRTC->CIIR |= cntrMask;
+	}
+
+	else {
+		pRTC->CIIR &= (~cntrMask) & RTC_AMR_CIIR_BITMASK;
+		while (pRTC->CIIR & cntrMask) {}
+	}
+}
+
+/* Enable/Disable Alarm interrupt for a time type in the RTC peripheral */
+void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		pRTC->AMR &= (~alarmMask) & RTC_AMR_CIIR_BITMASK;
+	}
+	else {
+		pRTC->AMR |= (alarmMask);
+		while ((pRTC->AMR & alarmMask) == 0) {}
+	}
+}
+
+/* Set full time in the RTC peripheral */
+void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
+{
+	RTC_TIMEINDEX_T i;
+	uint32_t ccr_val = pRTC->CCR;
+
+	/* Temporarily disable */
+	if (ccr_val & RTC_CCR_CLKEN) {
+		pRTC->CCR = ccr_val & (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
+	}
+
+	/* Date time setting */
+	for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
+		pRTC->TIME[i] = pFullTime->time[i];
+	}
+
+	/* Restore to old setting */
+	pRTC->CCR = ccr_val;
+}
+
+/* Get full time from the RTC peripheral */
+void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
+{
+	RTC_TIMEINDEX_T i;
+	uint32_t secs = 0xFF;
+
+	/* Read full time, but verify second tick didn't change during the read. If
+	   it did, re-read the time again so it will be consistent across all fields. */
+	while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) {
+		secs = pFullTime->time[RTC_TIMETYPE_SECOND] = pRTC->TIME[RTC_TIMETYPE_SECOND];
+		for (i = RTC_TIMETYPE_MINUTE; i < RTC_TIMETYPE_LAST; i++) {
+			pFullTime->time[i] = pRTC->TIME[i];
+		}
+	}
+}
+
+/* Set full alarm time in the RTC peripheral */
+void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
+{
+	RTC_TIMEINDEX_T i;
+
+	for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
+		pRTC->ALRM[i] = pFullTime->time[i];
+	}
+}
+
+/* Get full alarm time in the RTC peripheral */
+void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime)
+{
+	RTC_TIMEINDEX_T i;
+
+	for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) {
+		pFullTime->time[i] = pRTC->ALRM[i];
+	}
+}
+
+/* Enable/Disable calibration counter in the RTC peripheral */
+void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState)
+{
+	if (NewState == ENABLE) {
+		do {
+			pRTC->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;
+		} while (pRTC->CCR & RTC_CCR_CCALEN);
+	}
+	else {
+		pRTC->CCR |= RTC_CCR_CCALEN;
+	}
+}
+
+#if RTC_EV_SUPPORT
+/* Get first timestamp value */
+void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp)
+{
+	pTimeStamp->sec = RTC_ER_TIMESTAMP_SEC(pRTC->ERFIRSTSTAMP[ch]);
+	pTimeStamp->min = RTC_ER_TIMESTAMP_MIN(pRTC->ERFIRSTSTAMP[ch]);
+	pTimeStamp->hour = RTC_ER_TIMESTAMP_HOUR(pRTC->ERFIRSTSTAMP[ch]);
+	pTimeStamp->dayofyear = RTC_ER_TIMESTAMP_DOY(pRTC->ERFIRSTSTAMP[ch]);
+}
+
+/* Get last timestamp value */
+void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp)
+{
+	pTimeStamp->sec = RTC_ER_TIMESTAMP_SEC(pRTC->ERLASTSTAMP[ch]);
+	pTimeStamp->min = RTC_ER_TIMESTAMP_MIN(pRTC->ERLASTSTAMP[ch]);
+	pTimeStamp->hour = RTC_ER_TIMESTAMP_HOUR(pRTC->ERLASTSTAMP[ch]);
+	pTimeStamp->dayofyear = RTC_ER_TIMESTAMP_DOY(pRTC->ERLASTSTAMP[ch]);
+}
+
+#endif /*RTC_EV_SUPPORT*/
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/sdc_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/sdc_17xx_40xx.c
new file mode 100644
index 000000000..61ca5be39
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/sdc_17xx_40xx.c
@@ -0,0 +1,247 @@
+/*
+ * @brief	SD Card Interface registers and control functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+static void writeDelay(void)
+{
+	volatile uint8_t i;
+	for ( i = 0; i < 0x10; i++ ) {	/* delay 3MCLK + 2PCLK  */
+	}
+}
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set power state of SDC peripheral */
+void Chip_SDC_PowerControl(LPC_SDC_T *pSDC, SDC_PWR_CTRL_T pwrMode, uint32_t flag)
+{
+	pSDC->POWER = SDC_PWR_CTRL(pwrMode) | flag;
+	writeDelay();
+}
+
+/* Set clock divider for SDC peripheral */
+void Chip_SDC_SetClockDiv(LPC_SDC_T *pSDC, uint8_t div)
+{
+	uint32_t temp;
+	temp = (pSDC->CLOCK & (~SDC_CLOCK_CLKDIV_BITMASK));
+	pSDC->CLOCK = temp | (SDC_CLOCK_CLKDIV(div));
+	writeDelay();
+}
+
+/* Clock control for SDC peripheral*/
+void Chip_SDC_ClockControl(LPC_SDC_T *pSDC, SDC_CLOCK_CTRL_T ctrlType,
+						   FunctionalState NewState)
+{
+	if (NewState) {
+		pSDC->CLOCK |= (1 << ctrlType);
+	}
+	else {
+		pSDC->CLOCK &= (~(1 << ctrlType));
+	}
+	writeDelay();
+}
+
+/* Initialize SDC peripheral */
+static void SDC_Init(LPC_SDC_T *pSDC)
+{
+	/* Disable SD_CLK */
+	Chip_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, DISABLE);
+
+	/* Power-off */
+	Chip_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
+	writeDelay();
+
+	/* Disable all interrupts */
+	pSDC->MASK0 = 0;
+
+	/*Setting for timeout problem */
+	pSDC->DATATIMER = 0x1FFFFFFF;
+
+	pSDC->COMMAND = 0;
+	writeDelay();
+
+	pSDC->DATACTRL = 0;
+	writeDelay();
+
+	/* clear all pending interrupts */
+	pSDC->CLEAR = SDC_CLEAR_ALL;
+}
+
+/* Initializes the SDC card controller */
+void Chip_SDC_Init(LPC_SDC_T *pSDC)
+{
+	uint32_t i = 0;
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SDC);
+	Chip_SYSCTL_PeriphReset(SYSCTL_RESET_PCSDC);
+
+	/* Initialize GPDMA controller */
+	Chip_GPDMA_Init(LPC_GPDMA);
+
+	/* Initialize SDC peripheral */
+	SDC_Init(pSDC);
+
+	/* Power-up SDC Peripheral */
+	Chip_SDC_PowerControl(pSDC, SDC_POWER_UP, 0);
+
+	/* delays for the supply output is stable*/
+	for ( i = 0; i < 0x80000; i++ ) {}
+
+	Chip_SDC_SetClock(pSDC, SDC_IDENT_CLOCK_RATE);
+	Chip_SDC_ClockControl(pSDC, SDC_CLOCK_ENABLE, ENABLE);
+
+	/* Power-on SDC Interface */
+	Chip_SDC_PowerControl(pSDC, SDC_POWER_ON, 0);
+
+}
+
+/* Set Command Info */
+void Chip_SDC_SetCommand(LPC_SDC_T *pSDC, uint32_t Cmd, uint32_t Arg)
+{
+	/* Clear status register */
+	pSDC->CLEAR = SDC_CLEAR_ALL;
+
+	/* Set the argument first, finally command */
+	pSDC->ARGUMENT = Arg;
+
+	/* Write command value, enable the command */
+	pSDC->COMMAND = Cmd | SDC_COMMAND_ENABLE;
+
+	writeDelay();
+}
+
+/* Reset Command Info */
+void Chip_SDC_ResetCommand(LPC_SDC_T *pSDC)
+{
+	pSDC->CLEAR = SDC_CLEAR_ALL;
+
+	pSDC->ARGUMENT = 0xFFFFFFFF;
+
+	pSDC->COMMAND = 0;
+
+	writeDelay();
+}
+
+/* Get Command response */
+void Chip_SDC_GetResp(LPC_SDC_T *pSDC, SDC_RESP_T *pResp)
+{
+	uint8_t i;
+	pResp->CmdIndex = SDC_RESPCOMMAND_VAL(pSDC->RESPCMD);
+	for (i = 0; i < SDC_CARDSTATUS_BYTENUM; i++) {
+		pResp->Data[i] = pSDC->RESPONSE[i];
+	}
+}
+
+/* Setup Data Transfer Information */
+void Chip_SDC_SetDataTransfer(LPC_SDC_T *pSDC, SDC_DATA_TRANSFER_T *pTransfer)
+{
+	uint32_t DataCtrl = 0;
+	pSDC->DATATIMER = pTransfer->Timeout;
+	pSDC->DATALENGTH = pTransfer->BlockNum * SDC_DATACTRL_BLOCKSIZE_VAL(pTransfer->BlockSize);
+	DataCtrl = SDC_DATACTRL_ENABLE;
+	DataCtrl |= ((uint32_t) pTransfer->Dir) | ((uint32_t) pTransfer->Mode) | SDC_DATACTRL_BLOCKSIZE(
+		pTransfer->BlockSize);
+	if (pTransfer->DMAUsed) {
+		DataCtrl |= SDC_DATACTRL_DMA_ENABLE;
+	}
+	pSDC->DATACTRL = DataCtrl;
+	writeDelay();
+}
+
+/* Write data to FIFO */
+void Chip_SDC_WriteFIFO(LPC_SDC_T *pSDC, uint32_t *pSrc, bool bFirstHalf)
+{
+	uint8_t start = 0, end = 7;
+	if (!bFirstHalf) {
+		start += 8;
+		end += 8;
+	}
+	for (; start <= end; start++) {
+		pSDC->FIFO[start] = *pSrc;
+		pSrc++;
+	}
+}
+
+/* Read data from FIFO */
+void Chip_SDC_ReadFIFO(LPC_SDC_T *pSDC, uint32_t *pDst, bool bFirstHalf)
+{
+	uint8_t start = 0, end = 7;
+
+	if (!bFirstHalf) {
+		start += 8;
+		end += 8;
+	}
+	for (; start <= end; start++) {
+		*pDst = pSDC->FIFO[start];
+		pDst++;
+	}
+}
+
+/* Set SD_CLK Clock */
+void Chip_SDC_SetClock(LPC_SDC_T *pSDC, uint32_t freq)
+{
+	uint32_t PClk;
+	uint32_t ClkValue = 0;
+
+	PClk = Chip_Clock_GetPeripheralClockRate();
+
+	ClkValue = (PClk + 2 * freq - 1) / (2 * freq);
+	if (ClkValue > 0) {
+		ClkValue -= 1;
+	}
+	Chip_SDC_SetClockDiv(pSDC, ClkValue);
+}
+
+/* Shutdown the SDC card controller */
+void Chip_SDC_DeInit(LPC_SDC_T *pSDC)
+{
+	/* Power-off */
+	Chip_SDC_PowerControl(pSDC, SDC_POWER_OFF, 0);
+
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SDC);
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC4XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/sdmmc_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/sdmmc_17xx_40xx.c
new file mode 100644
index 000000000..93b2b820f
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/sdmmc_17xx_40xx.c
@@ -0,0 +1,1196 @@
+/*
+ * @brief LPC17xx/40xx SDMMC card driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+#define CMD_TIMEOUT                  (0x10000)
+#define DATA_TIMEOUT                 (0x1000000)
+#define DATA_TIMER_VALUE_R           (SDC_TRAN_CLOCK_RATE / 4)		// 250ms
+#define DATA_TIMER_VALUE_W           (SDC_TRAN_CLOCK_RATE)		// 1000ms
+#define MS_ACQUIRE_DELAY             (100)			/*!< inter-command acquire oper condition delay in msec*/
+
+/* SD Card HW has a data length regsiter of 16-bits.
+ * This supports max of 0xFFFF bytes of data transfer at a time.
+ * We will use transfers of 127 blocks of 512 bytes at a time
+ */
+ #define SDMMC_MAX_BLK               (127)
+ #define SDMMC_MAX_TFR_SIZE          (SDMMC_MAX_BLK * MMC_SECTOR_SIZE)
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+/* Send a command to card */
+STATIC int32_t sendCmd(LPC_SDC_T *pSDC, uint32_t Command, uint32_t Arg, uint32_t timeout)
+{
+	int32_t ret = SDC_RET_TIMEOUT;
+	uint32_t Status;
+
+	/* Set Command Info */
+	Chip_SDC_SetCommand(pSDC, Command, Arg);
+
+	while (timeout) {
+
+		Status = Chip_SDC_GetStatus(pSDC);
+
+		/* check if command was sent */
+		if (((Command & SDC_COMMAND_RSP_BITMASK) == SDC_COMMAND_NO_RSP) && (Status & SDC_STATUS_CMDSENT)) {
+			ret =  SDC_RET_OK;
+			break;
+		}
+		/* check if response was received */
+		if (Status & SDC_STATUS_CMDRESPEND) {
+			ret = SDC_RET_OK;
+			break;
+		}
+
+		/* check command sending status */
+		if (Status & SDC_STATUS_CMDERR) {
+			if (Status & SDC_STATUS_CMDCRCFAIL) {
+				if ((SDC_COMMAND_INDEX(Command) == MMC_SEND_OP_COND) ||
+					(SDC_COMMAND_INDEX(Command) == SD_APP_OP_COND) ||
+					(SDC_COMMAND_INDEX(Command) == MMC_STOP_TRANSMISSION)) {
+					ret = SDC_RET_OK;	/* ignore CRC error if it's a resp for SEND_OP_COND  or STOP_TRANSMISSION. */
+					break;
+				}
+			}
+			ret = SDC_RET_CMD_FAILED;
+			break;
+		}
+
+		timeout--;
+	}
+
+	Chip_SDC_ResetCommand(pSDC);
+
+	return ret;
+}
+
+/* Function to send a command to card and get its response (if any)*/
+STATIC int32_t executeCmd(LPC_SDC_T *pSDC, uint32_t Command, uint32_t Arg, SDC_RESP_T *pResp)
+{
+	int32_t Ret = SDC_RET_FAILED;
+
+	/* Send Command to card */
+	Ret = sendCmd(pSDC, Command, Arg, CMD_TIMEOUT);
+	if (Ret != SDC_RET_OK) {
+		return Ret;
+	}
+
+	/* Get response (if any) */
+	if ((Command & SDC_COMMAND_RSP_BITMASK) != SDC_COMMAND_NO_RSP) {
+
+		Chip_SDC_GetResp(pSDC, pResp);
+
+		/* If the response is not R1, in the response field, the Expected Cmd data
+		        won't be the same as the CMD data in SendCmd(). Below four cmds have
+		        R2 or R3 response. We don't need to check if MCI_RESP_CMD is the same
+		        as the Expected or not. */
+		if ((SDC_COMMAND_INDEX(Command) != MMC_SEND_OP_COND) &&
+			(SDC_COMMAND_INDEX(Command) != SD_APP_OP_COND) &&
+			(SDC_COMMAND_INDEX(Command) != MMC_ALL_SEND_CID) &&
+			(SDC_COMMAND_INDEX(Command) != MMC_SEND_CSD) &&
+			(pResp->CmdIndex != SDC_COMMAND_INDEX(Command))) {
+			return SDC_RET_CMD_FAILED;
+		}
+	}
+
+	return SDC_RET_OK;
+}
+
+/* Check R1 response, the result is stored in pCheckResult parameter. */
+/* This function return 1 to exit the command execution, 0 to retry sending command */
+STATIC int32_t checkR1Response(uint32_t resp, int32_t *pCheckResult)
+{
+	int32_t Ret = 1;
+
+	if (!(resp & R1_READY_FOR_DATA)) {
+		*pCheckResult = SDC_RET_NOT_READY;
+		Ret = 0;
+	}
+	else if (R1_STATUS(resp)) {
+		*pCheckResult =  SDC_RET_FAILED;
+	}
+	else {
+		*pCheckResult =  SDC_RET_OK;
+	}
+	return Ret;
+}
+
+/* Send APP_CMD to card*/
+STATIC int32_t sendAppCmd(LPC_SDC_T *pSDC, uint16_t rca)
+
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD55_APP_CMD, CMD55_RCA(rca), &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				if (Ret != SDC_RET_OK) {
+					return Ret;
+				}
+				if (Response.Data[0] & R1_APP_CMD) {
+					return SDC_RET_OK;
+				}
+				else {
+					Ret = SDC_RET_FAILED;
+				}
+			}
+		}
+		RetryCnt--;
+	}
+	return SDC_RET_FAILED;
+}
+
+/* Send Reset command to card*/
+STATIC INLINE int32_t cardReset(LPC_SDC_T *pSDC)
+{
+	return executeCmd(pSDC, SD_GO_IDLE_STATE, 0, NULL);
+}
+
+/* Send Interface condition to card*/
+STATIC int32_t sendIfCond(LPC_SDC_T *pSDC)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD8_SEND_IF_COND, (CMD8_VOLTAGESUPPLIED_27_36 | CMD8_CHECKPATTERN(
+														  CMD8_DEF_PATTERN)), &Response);
+		if (Ret == SDC_RET_OK) {
+			if ((Response.Data[0] & CMDRESP_R7_VOLTAGE_ACCEPTED) &&
+				(CMDRESP_R7_CHECK_PATTERN(Response.Data[0]) == CMD8_DEF_PATTERN)) {
+				return SDC_RET_OK;
+			}
+			return SDC_RET_BAD_PARAMETERS;
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+/* Send Operation condition to card */
+STATIC int32_t sendOpCond(LPC_SDC_T *pSDC, uint32_t *pOCR)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  0x200;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD1_SEND_OP_COND, SDC_OCR_27_36, &Response);
+		if (Ret == SDC_RET_OK) {
+			*pOCR = Response.Data[0];
+			if (*pOCR & SDC_OCR_IDLE) {
+				if ((Response.Data[0] & SDC_OCR_27_36) != SDC_OCR_27_36) {
+					return SDC_RET_BAD_PARAMETERS;
+				}
+				return SDC_RET_OK;
+			}
+		}
+		RetryCnt--;
+	}
+	return SDC_RET_FAILED;
+}
+
+/* Send ACMD41 command to card.If *Ocr = 0, it gets OCR. Otherwise, it starts initialization card.  */
+/* Open Drain bit must be cleared before calling this function */
+STATIC int32_t sendAppOpCond(LPC_SDC_T *pSDC, uint16_t rca, bool hcs, uint32_t *pOcr, bool *pCCS)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t Argument;
+	uint32_t RetryCnt =  0x2000;	/* The host repeatedly issues ACMD41 for at least 1 second or
+									       until the busy bit are set to 1 */
+
+	Argument = ACMD41_OCR(*pOcr);
+	if (hcs) {
+		Argument |= ACMD41_HCS;
+	}
+
+	while (RetryCnt > 0) {
+		Ret = sendAppCmd(pSDC, rca);
+		if (Ret == SDC_RET_OK) {
+			Ret = executeCmd(pSDC, SD_ACMD41_SD_SEND_OP_COND, Argument, &Response);
+			if (Ret == SDC_RET_OK) {
+				if (Response.Data[0] & CMDRESP_R3_INIT_COMPLETE) {
+					if (*pOcr == 0) {
+						*pOcr = CMDRESP_R3_OCR_VAL(Response.Data[0]);
+						return SDC_RET_OK;
+					}
+					if ((CMDRESP_R3_OCR_VAL(Response.Data[0]) & *pOcr) != *pOcr) {
+						return SDC_RET_BAD_PARAMETERS;
+					}
+					*pCCS = (Response.Data[0] & CMDRESP_R3_HC_CCS) ? true : false;
+					return SDC_RET_OK;
+				}
+			}
+		}
+		else {
+			return Ret;
+		}
+		RetryCnt--;
+	}
+	return SDC_RET_FAILED;
+}
+
+/* Get CID */
+STATIC int32_t getCID(LPC_SDC_T *pSDC, uint32_t *pCID)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD2_ALL_SEND_CID, 0, &Response);
+		if (Ret == SDC_RET_OK) {
+			pCID[3] = Response.Data[0];
+			pCID[2] = Response.Data[1];
+			pCID[1] = Response.Data[2];
+			pCID[0] = Response.Data[3];
+			return SDC_RET_OK;
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+/* Set Addr */
+STATIC int32_t setAddr(LPC_SDC_T *pSDC, uint16_t addr)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD3_SET_RELATIVE_ADDR, CMD3_RCA(addr), &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				return Ret;
+			}
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+STATIC int32_t getAddr(LPC_SDC_T *pSDC, uint16_t *pRCA)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	*pRCA = 0;
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD3_SEND_RELATIVE_ADDR, 0, &Response);
+		if (Ret == SDC_RET_OK) {
+			if (!(CMDRESP_R6_CARD_STATUS(Response.Data[0]) & R1_READY_FOR_DATA)) {
+				Ret = SDC_RET_NOT_READY;
+			}
+			else if (R1_CURRENT_STATE(CMDRESP_R6_CARD_STATUS(Response.Data[0])) != SDMMC_STBY_ST) {
+				Ret = SDC_RET_ERR_STATE;
+			}
+			else {
+				*pRCA = CMDRESP_R6_RCA_VAL(Response.Data[0]);
+				return SDC_RET_OK;
+			}
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+STATIC int32_t getCSD(LPC_SDC_T *pSDC, uint16_t rca, uint32_t *pCSD)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD9_SEND_CSD, CMD9_RCA(rca), &Response);
+		if (Ret == SDC_RET_OK) {
+			pCSD[3] = Response.Data[0];
+			pCSD[2] = Response.Data[1];
+			pCSD[1] = Response.Data[2];
+			pCSD[0] = Response.Data[3];
+			return Ret;
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+/* Select card*/
+STATIC int32_t selectCard(LPC_SDC_T *pSDC, uint16_t addr)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD7_SELECT_CARD, CMD7_RCA(addr), &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				return Ret;
+			}
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+/* Get card status */
+STATIC int32_t getStatus(LPC_SDC_T *pSDC, uint16_t rca, uint32_t *pStatus)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	*pStatus = (uint32_t) -1;
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD13_SEND_STATUS, CMD13_RCA(rca), &Response);
+		if (Ret == SDC_RET_OK) {
+			checkR1Response(Response.Data[0], &Ret);
+			*pStatus = Response.Data[0];
+			return Ret;
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+/* Set bus width.  */
+STATIC int32_t getAppStatus(LPC_SDC_T *pSDC, uint16_t rca, uint32_t *pStatus)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint8_t RetryCnt =  0x20;
+
+	while (RetryCnt > 0) {
+		Ret = sendAppCmd(pSDC, rca);
+		if (Ret == SDC_RET_OK) {
+			Ret = executeCmd(pSDC, SD_ACMD13_SEND_SD_STATUS, 0, &Response);
+			if (Ret == SDC_RET_OK) {
+				if (checkR1Response(Response.Data[0], &Ret)) {
+					return Ret;
+				}
+			}
+		}
+		RetryCnt--;
+	}
+	return SDC_RET_FAILED;
+}
+
+/* Helper function to get a bit field withing multi-word  buffer. Used to get
+   fields with-in CSD & EXT-CSD */
+STATIC uint32_t getBits(LPC_SDC_T *pSDC, int32_t start, int32_t end, uint32_t *data)
+{
+	uint32_t v;
+	uint32_t i = end >> 5;
+	uint32_t j = start & 0x1f;
+
+	if (i == (start >> 5)) {
+		v = (data[i] >> j);
+	}
+	else {
+		v = ((data[i] << (32 - j)) | (data[start >> 5] >> j));
+	}
+
+	return v & ((1 << (end - start + 1)) - 1);
+}
+
+/* Function to process the CSD & EXT-CSD of the card */
+STATIC void processCSD(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo)
+{
+	int32_t CSize = 0;
+	int32_t CSizeMult = 0;
+	int32_t Mult = 0;
+
+	/* compute block length based on CSD response */
+	pCardInfo->block_len = 1 << getBits(pSDC, 80, 83, pCardInfo->csd);
+
+	if ((pCardInfo->card_type & CARD_TYPE_HC) && (pCardInfo->card_type & CARD_TYPE_SD)) {
+		/* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec  an explanation for the calculation of these values */
+		CSize = getBits(pSDC, 48, 63, (uint32_t *) pCardInfo->csd) + 1;
+		pCardInfo->blocknr = CSize << 10;	/* 512 byte blocks */
+	}
+	else {
+		/* See section 5.3 of the 4.1 revision of the MMC specs for  an explanation for the calculation of these values */
+		CSize = getBits(pSDC, 62, 73, (uint32_t *) pCardInfo->csd);
+		CSizeMult = getBits(pSDC, 47, 49, (uint32_t *) pCardInfo->csd);
+		Mult = 1 << (CSizeMult + 2);
+		pCardInfo->blocknr = (CSize + 1) * Mult;
+
+		/* adjust blocknr to 512/block */
+		if (pCardInfo->block_len > MMC_SECTOR_SIZE) {
+			pCardInfo->blocknr = pCardInfo->blocknr * (pCardInfo->block_len >> 9);
+		}
+	}
+
+	pCardInfo->device_size = pCardInfo->blocknr << 9;	/* blocknr * 512 */
+}
+
+/* Set bus width.  */
+STATIC int32_t setBusWidth(LPC_SDC_T *pSDC, uint16_t rca, uint8_t width)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint8_t RetryCnt =  0x20;
+
+	while (RetryCnt > 0) {
+		Ret = sendAppCmd(pSDC, rca);
+		if (Ret == SDC_RET_OK) {
+			Ret = executeCmd(pSDC, SD_ACMD6_SET_BUS_WIDTH, ACMD6_BUS_WIDTH(width), &Response);
+			if (Ret == SDC_RET_OK) {
+				if (checkR1Response(Response.Data[0], &Ret)) {
+					return Ret;
+				}
+			}
+		}
+		RetryCnt--;
+	}
+	return SDC_RET_FAILED;
+}
+
+/* Puts current selected card in trans state */
+STATIC int32_t setTranState(LPC_SDC_T *pSDC, uint16_t rca)
+{
+	int32_t Ret = 0;
+	uint32_t status = 0;
+	SDMMC_STATE_T state;
+
+	/* get current state of the card */
+	Ret = getStatus(pSDC, rca, &status);
+	if (Ret != SDC_RET_OK) {
+		/* unable to get the card state. So return immediatly. */
+		return Ret;
+	}
+
+	/* check card state in response */
+	state = (SDMMC_STATE_T) R1_CURRENT_STATE(status);
+	switch (state) {
+	case SDMMC_STBY_ST:
+		/* put card in 'Trans' state */
+		Ret = selectCard(pSDC, rca);
+		if (Ret != SDC_RET_OK) {
+			/* unable to put the card in Trans state. So return immediatly. */
+			return Ret;
+		}
+		getStatus(pSDC, rca, &status);
+		if (((SDMMC_STATE_T) R1_CURRENT_STATE(status)) != SDMMC_TRAN_ST) {
+			return SDC_RET_ERR_STATE;
+		}
+		break;
+
+	case SDMMC_TRAN_ST:
+		/*do nothing */
+		break;
+
+	default:
+		/* card shouldn't be in other states so return */
+		return SDC_RET_ERR_STATE;
+	}
+
+	return SDC_RET_OK;
+}
+
+/* Set bus width.  */
+STATIC int32_t setblock_length(LPC_SDC_T *pSDC, uint32_t rca, uint32_t block_len)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint8_t RetryCnt =  0x20;
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD16_SET_BLOCKLEN, block_len, &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				return Ret;
+			}
+		}
+		RetryCnt--;
+	}
+	return SDC_RET_FAILED;
+}
+
+/* Sets card data width and block size */
+STATIC int32_t setCardParams(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo)
+{
+	int32_t Ret;
+
+	Chip_SDC_SetClock(pSDC, SDC_TRAN_CLOCK_RATE);
+	if (pCardInfo->card_type & CARD_TYPE_SD) {
+		Chip_SDC_ClockControl(pSDC, SDC_CLOCK_WIDEBUS_MODE, ENABLE);
+		Ret = setBusWidth(pSDC, pCardInfo->rca, ACMD6_BUS_WIDTH_4);
+		if (Ret != SDC_RET_OK) {
+			return Ret;
+		}
+	}
+	else {
+		Chip_SDC_ClockControl(pSDC, SDC_CLOCK_WIDEBUS_MODE, DISABLE);
+	}
+
+	/* set block length */
+	Ret = setblock_length(pSDC, pCardInfo->rca, MMC_SECTOR_SIZE);
+	return Ret;
+}
+
+STATIC int32_t readBlocks(LPC_SDC_T *pSDC, uint32_t card_type, uint32_t startBlock, uint32_t blockNum)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t Command, Argument;
+	uint8_t RetryCnt =  0x20;
+
+	if (blockNum == 1) {
+		Command = SD_CMD17_READ_SINGLE_BLOCK;
+	}
+	else {
+		Command = SD_CMD18_READ_MULTIPLE_BLOCK;
+	}
+
+	/* Select single or multiple read based on number of blocks */
+	/* if high capacity card use block indexing */
+	if (card_type & CARD_TYPE_HC) {
+		Argument = startBlock;
+	}
+	else {	/*fix at 512 bytes*/
+		Argument = startBlock << 9;
+	}
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, Command, Argument, &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				return Ret;
+			}
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+STATIC int32_t writeBlocks(LPC_SDC_T *pSDC, uint32_t card_type, uint32_t startBlock, uint32_t blockNum)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t Command, Argument;
+	uint8_t RetryCnt =  0x20;
+
+	if (blockNum == 1) {
+		Command = SD_CMD24_WRITE_BLOCK;
+	}
+	else {
+		Command = SD_CMD25_WRITE_MULTIPLE_BLOCK;
+	}
+
+	/* if high capacity card use block indexing */
+	if (card_type & CARD_TYPE_HC) {
+		Argument = startBlock;
+	}
+	else {	/*fix at 512 bytes*/
+		Argument = startBlock << 9;
+
+	}
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, Command, Argument, &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				return Ret;
+			}
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+STATIC int32_t stopTranmission(LPC_SDC_T *pSDC, uint32_t rca)
+{
+	uint32_t Status;
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_RESP_T Response;
+	uint32_t RetryCnt =  20;
+
+	Ret = getStatus(pSDC, rca, &Status);
+	if (Ret != SDC_RET_OK) {
+		return SDC_RET_ERR_STATE;
+	}
+
+	if (R1_CURRENT_STATE(Status) == SDMMC_TRAN_ST) {
+		return SDC_RET_OK;
+	}
+
+	if ((R1_CURRENT_STATE(Status) != SDMMC_DATA_ST) &&
+		(R1_CURRENT_STATE(Status) != SDMMC_RCV_ST)) {
+		return SDC_RET_ERR_STATE;
+	}
+
+	while (RetryCnt > 0) {
+		Ret = executeCmd(pSDC, SD_CMD12_STOP_TRANSMISSION, 0, &Response);
+		if (Ret == SDC_RET_OK) {
+			if (checkR1Response(Response.Data[0], &Ret)) {
+				if (Ret != SDC_RET_OK) {
+					return Ret;
+				}
+				Ret = getStatus(pSDC, rca, &Status);
+				if ((R1_CURRENT_STATE(Status) == SDMMC_TRAN_ST) || (R1_CURRENT_STATE(Status) == SDMMC_PRG_ST)) {
+					return SDC_RET_OK;
+				}
+				return SDC_RET_ERR_STATE;
+			}
+		}
+		RetryCnt--;
+	}
+	return Ret;
+}
+
+STATIC int32_t Chip_SDMMC_FIFOIRQHandler(LPC_SDC_T *pSDC, uint8_t *txBuf, uint32_t *txCnt,
+										 uint8_t *rxBuf, uint32_t *rxCnt)
+{
+	uint32_t Status;
+	Status = Chip_SDC_GetStatus(pSDC);
+
+	if (txBuf ) {
+		if (Status & SDC_STATUS_TXFIFOHALFEMPTY) {
+			if (*txCnt % 64) {
+				Chip_SDC_WriteFIFO(pSDC, (uint32_t *) &txBuf[*txCnt], false);
+			}
+			else {
+				Chip_SDC_WriteFIFO(pSDC, (uint32_t *) &txBuf[*txCnt], true);
+			}
+			*txCnt += 32;
+		}
+	}
+
+	if (rxBuf ) {
+		if (Status & SDC_STATUS_RXFIFOHALFFULL) {
+			if (*rxCnt % 64) {
+				Chip_SDC_ReadFIFO(pSDC, (uint32_t *) &rxBuf[*rxCnt], false);
+			}
+			else {
+				Chip_SDC_ReadFIFO(pSDC, (uint32_t *) &rxBuf[*rxCnt], true);
+			}
+			*rxCnt += 32;
+		}
+	}
+
+	Chip_SDC_ClearStatus(pSDC, SDC_STATUS_FIFO);
+
+	return 1;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* SDMMC IRQ handler function */
+int32_t Chip_SDMMC_IRQHandler(LPC_SDC_T *pSDC, uint8_t *txBuf, uint32_t *txCnt,
+							  uint8_t *rxBuf, uint32_t *rxCnt)
+{
+	uint32_t Status;
+
+	Status = Chip_SDC_GetStatus(pSDC);
+
+	if ( Status & SDC_STATUS_DATAERR) {
+		Chip_SDC_ClearStatus(pSDC, SDC_STATUS_DATAERR);
+		return -1;	/* Data transfer error */
+	}
+
+	if ( Status & SDC_STATUS_DATAEND) {
+		Chip_SDC_ClearStatus(pSDC, SDC_STATUS_DATAEND);
+		Chip_SDC_SetIntMask(pSDC, 0);
+		return 0;
+	}
+
+	if ( Status & SDC_STATUS_DATABLOCKEND) {
+		Chip_SDC_ClearStatus(pSDC, SDC_STATUS_DATABLOCKEND);
+		return 1;
+	}
+
+	if (Status & SDC_STATUS_FIFO) {
+		return Chip_SDMMC_FIFOIRQHandler(pSDC, txBuf, txCnt, rxBuf, rxCnt);
+	}
+
+	return 1;
+}
+
+/* Get card's current state (idle, transfer, program, etc.) */
+SDMMC_STATE_T Chip_SDMMC_GetCardState(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo)
+{
+	uint32_t Status;
+
+	/* get current state of the card */
+	getStatus(pSDC, pCardInfo->rca, &Status);
+
+	/* check card state in response */
+	return (SDMMC_STATE_T) R1_CURRENT_STATE(Status);
+}
+
+/* Get current card status */
+uint32_t Chip_SDMMC_GetCardStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo)
+{
+	uint32_t Status;
+	getStatus(pSDC, pCardInfo->rca, &Status);
+	return Status;
+}
+
+/* Get current sd status */
+int32_t Chip_SDMMC_GetSDStatus(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo, uint32_t *pStatus)
+{
+	int32_t Ret;
+	uint16_t ByteNum = 64;
+	SDMMC_EVENT_T  Event;
+	SDC_DATA_TRANSFER_T Transfer;
+
+	/* Put to tran state */
+	if (setTranState(pSDC, pCardInfo->rca) != SDC_RET_OK) {
+		return 0;
+	}
+
+#ifdef SDC_DMA_ENABLE
+	Chip_SDC_SetIntMask(pSDC, SDC_MASK0_DATA | SDC_MASK0_RXDATAERR);
+	Event.DmaChannel = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, GPDMA_CONN_SDC);
+
+	/* DMA Setup */
+	Chip_GPDMA_Transfer(LPC_GPDMA, Event.DmaChannel,
+						GPDMA_CONN_SDC,
+						(uint32_t) pStatus,
+						GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL,
+						ByteNum);
+#else
+	Chip_SDC_SetIntMask(pSDC, SDC_MASK0_DATA | SDC_MASK0_RXDATAERR | SDC_MASK0_RXFIFO);
+
+	Event.Buffer = pStatus;
+	Event.Size = ByteNum;
+	Event.Index = 0;
+	Event.Dir = 1;
+#endif
+	pCardInfo->evsetup_cb((void *) &Event);
+
+	/* set transfer information */
+	Transfer.BlockNum = 1;
+	Transfer.BlockSize = SDC_BLOCK_SIZE_64;	/* 512 bit */
+	Transfer.Dir = SDC_TRANSFER_DIR_FROMCARD;
+#ifdef SDC_DMA_ENABLE
+	Transfer.DMAUsed = true;
+#else
+	Transfer.DMAUsed = false;
+#endif
+	Transfer.Mode = SDC_TRANSFER_MODE_BLOCK;
+	Transfer.Timeout = DATA_TIMER_VALUE_R;
+	Chip_SDC_SetDataTransfer(pSDC, &Transfer);
+
+	/* Send ACMD13 command */
+	Ret = getAppStatus(pSDC, pCardInfo->rca, pStatus);
+	if (Ret != SDC_RET_OK) {
+		ByteNum = 0;
+		goto send_end;
+	}
+
+	/* Wait for transfer Finish */
+	if ((pCardInfo->waitfunc_cb()) != 0) {
+		ByteNum = 0;
+	}
+
+send_end:
+#ifdef SDC_DMA_ENABLE
+	Chip_GPDMA_Stop(LPC_GPDMA, Event.DmaChannel);
+#endif
+	if (Chip_SDMMC_GetCardState(pSDC, pCardInfo) == SDMMC_DATA_ST) {
+		/* Send Stop transmission command */
+		stopTranmission(pSDC, pCardInfo->rca);
+	}
+
+	/*Wait for card enters to tran state*/
+	while ((Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_TRAN_ST)) {}
+
+	return ByteNum;
+}
+
+/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */
+int32_t Chip_SDMMC_Acquire(LPC_SDC_T *pSDC, SDMMC_CARD_T *pCardInfo)
+{
+	int32_t Ret;
+
+	/* Initialize card info */
+	pCardInfo->speed = SDC_TRAN_CLOCK_RATE;
+	pCardInfo->card_type = 0;
+
+	/* During identification phase, the clock should be less than
+	   400Khz. Once we pass this phase, the normal clock can be set up
+	   to 25Mhz on SD card and 20Mhz on MMC card. */
+	Chip_SDC_SetClock(pSDC, SDC_IDENT_CLOCK_RATE);
+
+	/* Clear Open Drain output control for SD */
+	Chip_SDC_PowerControl(pSDC, SDC_POWER_ON, 0);
+
+	/* Card Reset */
+	Ret = cardReset(pSDC);
+	if (Ret != 0) {
+		return Ret;
+	}
+
+	pCardInfo->msdelay_func(MS_ACQUIRE_DELAY);
+
+	/* Send interface operation condiftion */
+	Ret = sendIfCond(pSDC);
+	if (Ret == SDC_RET_BAD_PARAMETERS) {
+		return Ret;		/* Non-compatible voltage range or check pattern is not correct */
+
+	}
+	/* Get Card Type */
+	if (Ret == SDC_RET_OK) {/* Ver2.00 or later SD Memory Card*/
+		bool CCS;
+		uint32_t OCR = SDC_OCR_27_36;
+		pCardInfo->card_type |= CARD_TYPE_SD;
+		Ret = sendAppOpCond(pSDC, 0, true, &OCR, &CCS);
+		if (CCS) {	/* High Capacity or Extended Capacity SD Memory Card */
+			pCardInfo->card_type |= CARD_TYPE_HC;
+		}
+	}
+	else {	/*Ver2.00 or later SD Memory Card(voltage mismatch) or Ver1.X SD Memory Card
+			   or not SD Memory Card*/
+		bool CCS;
+		uint32_t OCR = SDC_OCR_27_36;
+		Ret = sendAppOpCond(pSDC, 0, false, &OCR, &CCS);
+		if (Ret == SDC_RET_OK) {
+			pCardInfo->card_type |= CARD_TYPE_SD;
+		}
+		else if (Ret == SDC_RET_BAD_PARAMETERS) {
+			return Ret;
+		}
+		else {	/* MMC Card setup */
+			uint32_t OCR;
+			/* Enter to Open Drain mode */
+			Chip_SDC_PowerControl(pSDC, SDC_POWER_ON, SDC_PWR_OPENDRAIN);
+			pCardInfo->msdelay_func(MS_ACQUIRE_DELAY);
+			Ret = sendOpCond(pSDC, &OCR);
+			if (Ret != SDC_RET_OK) {
+				return Ret;
+			}
+
+		}
+	}
+
+	/* Read CID */
+	getCID(pSDC, pCardInfo->cid);
+
+	/* RCA send, for SD get RCA */
+	if (pCardInfo->card_type & CARD_TYPE_SD) {
+		getAddr(pSDC, &pCardInfo->rca);
+	}
+	else {
+		pCardInfo->rca = 1;
+		setAddr(pSDC, pCardInfo->rca);
+		Chip_SDC_PowerControl(pSDC, SDC_POWER_ON, 0);	/* enter to push-pull mode */
+	}
+
+	/* Get CSD */
+	getCSD(pSDC, pCardInfo->rca, pCardInfo->csd);
+
+	/* Compute card size, block size and no. of blocks  based on CSD response recived. */
+	if (pCardInfo->cid[0]) {
+		processCSD(pSDC, pCardInfo);
+
+		if (setTranState(pSDC, pCardInfo->rca) != SDC_RET_OK) {
+			return 0;
+		}
+
+		if (Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_TRAN_ST) {
+			return 0;
+		}
+
+		if (setCardParams(pSDC, pCardInfo) != 0) {
+			return 0;
+		}
+	}
+
+	return (pCardInfo->cid[0]) ? 1 : 0;
+}
+
+/* Performs the read of data from the SD/MMC card */
+int32_t Chip_SDMMC_ReadBlocks(LPC_SDC_T *pSDC,
+							  SDMMC_CARD_T *pCardInfo,
+							  void *buffer,
+							  int32_t startBlock,
+							  int32_t blockNum)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_DATA_TRANSFER_T Transfer;
+	SDMMC_EVENT_T  Event;
+	int32_t tfr_blk_cnt, start_blk = startBlock, block_cnt = blockNum;
+	int32_t ByteNum = blockNum *  MMC_SECTOR_SIZE;
+	uint32_t buf_ptr = (uint32_t) buffer;
+
+	/* if card is not acquired return immediately */
+	if (( startBlock < 0) || ( (startBlock + blockNum) > pCardInfo->blocknr) ) {
+		return 0;
+	}
+
+	/* Put to tran state */
+	if (setTranState(pSDC, pCardInfo->rca) != SDC_RET_OK) {
+		return 0;
+	}
+
+	/* Do data transfers in a loop */
+	Transfer.BlockSize = SDC_BLOCK_SIZE_512;
+	Transfer.Dir = SDC_TRANSFER_DIR_FROMCARD;
+#ifdef SDC_DMA_ENABLE
+	Transfer.DMAUsed = true;
+#else
+	Transfer.DMAUsed = false;
+#endif
+	Transfer.Mode = SDC_TRANSFER_MODE_BLOCK;
+	Transfer.Timeout = DATA_TIMER_VALUE_R;
+
+	while (block_cnt > 0) {
+		if (block_cnt > SDMMC_MAX_BLK) {
+			tfr_blk_cnt = SDMMC_MAX_BLK;
+		}
+		else {
+			tfr_blk_cnt = block_cnt;
+		}
+
+#ifdef SDC_DMA_ENABLE
+		/* Enable Receive interrupts */
+		Chip_SDC_SetIntMask(pSDC, SDC_MASK0_DATA | SDC_MASK0_RXDATAERR);
+
+		/* Get DMA channel */
+		Event.DmaChannel = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, GPDMA_CONN_SDC);
+
+		/* Start the DMA transfer */
+		Chip_GPDMA_Transfer(LPC_GPDMA, Event.DmaChannel,
+							GPDMA_CONN_SDC,
+							buf_ptr,
+							GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL,
+							(tfr_blk_cnt * MMC_SECTOR_SIZE));
+#else
+		/* Enable Receive interrupts */
+		Chip_SDC_SetIntMask(SDC_MASK0_DATA | SDC_MASK0_RXDATAERR | SDC_MASK0_RXFIFO);
+
+		Event.Buffer = buf_ptr;
+		Event.Size = (tfr_blk_cnt * MMC_SECTOR_SIZE);
+		Event.Index = 0;
+		Event.Dir = 1;
+#endif
+		/* Call Event Setup function */
+		pCardInfo->evsetup_cb((void *) &Event);
+
+		/* Set transfer information */
+		Transfer.BlockNum = tfr_blk_cnt;
+		Chip_SDC_SetDataTransfer(pSDC, &Transfer);
+
+		/* Send command for reading data */
+		Ret = readBlocks(pSDC, pCardInfo->card_type, start_blk, tfr_blk_cnt);
+		if (Ret != SDC_RET_OK) {
+			ByteNum = 0;
+			goto send_end;
+		}
+
+		/* Wait for transfer Finish */
+		if ((pCardInfo->waitfunc_cb()) != 0) {
+			ByteNum = 0;
+			goto send_end;
+		}
+
+#ifdef SDC_DMA_ENABLE
+		Chip_GPDMA_Stop(LPC_GPDMA, Event.DmaChannel);
+#endif
+
+		/* Send stop transmission */
+		if ((tfr_blk_cnt > 1) || (Chip_SDMMC_GetCardState(pSDC, pCardInfo) == SDMMC_DATA_ST)) {
+			/* Send Stop transmission command */
+			stopTranmission(pSDC, pCardInfo->rca);
+		}
+
+		/* Wait for card enter to tran state */
+		while (Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_TRAN_ST) {}
+
+		/* Update block counter, buffer address */
+		block_cnt -= tfr_blk_cnt;
+		buf_ptr += (tfr_blk_cnt * MMC_SECTOR_SIZE);
+		start_blk += tfr_blk_cnt;
+	}
+
+send_end:
+	/* Stop the DMA in case of error */
+	if (ByteNum == 0) {
+#ifdef SDC_DMA_ENABLE
+		Chip_GPDMA_Stop(LPC_GPDMA, Event.DmaChannel);
+#endif
+
+		if ((blockNum > 1) || (Chip_SDMMC_GetCardState(pSDC, pCardInfo) == SDMMC_DATA_ST)) {
+			/* Send Stop transmission command */
+			stopTranmission(pSDC, pCardInfo->rca);
+		}
+
+		/* Wait for card enter to tran state */
+		while (Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_TRAN_ST) {}
+	}
+
+	return ByteNum;
+}
+
+/* Performs write of data to the SD/MMC card */
+int32_t Chip_SDMMC_WriteBlocks(LPC_SDC_T *pSDC,
+							   SDMMC_CARD_T *pCardInfo,
+							   void *buffer,
+							   int32_t startBlock,
+							   int32_t blockNum)
+{
+	int32_t Ret = SDC_RET_FAILED;
+	SDC_DATA_TRANSFER_T Transfer;
+	SDMMC_EVENT_T  Event;
+	int32_t tfr_blk_cnt, start_blk = startBlock, block_cnt = blockNum;
+	int32_t ByteNum = blockNum *  MMC_SECTOR_SIZE;
+	uint32_t buf_ptr = (uint32_t) buffer;
+
+	/* if card is not acquired return immediately */
+	if (( startBlock < 0) || ( (startBlock + blockNum) > pCardInfo->blocknr) ) {
+		return 0;
+	}
+
+	/* Put to tran state */
+	if (setTranState(pSDC, pCardInfo->rca) != SDC_RET_OK) {
+		return 0;
+	}
+
+	/* Do the trnasfers */
+	Transfer.BlockSize = SDC_BLOCK_SIZE_512;
+	Transfer.Dir = SDC_TRANSFER_DIR_TOCARD;
+#ifdef SDC_DMA_ENABLE
+	Transfer.DMAUsed = true;
+#else
+	Transfer.DMAUsed = false;
+#endif
+	Transfer.Mode = SDC_TRANSFER_MODE_BLOCK;
+	Transfer.Timeout = DATA_TIMER_VALUE_W;
+	while (block_cnt > 0) {
+		if (block_cnt > SDMMC_MAX_BLK) {
+			tfr_blk_cnt = SDMMC_MAX_BLK;
+		}
+		else {
+			tfr_blk_cnt = block_cnt;
+		}
+
+		/* Send Write block(s) command */
+		Ret = writeBlocks(pSDC, pCardInfo->card_type, start_blk, tfr_blk_cnt);
+		if (Ret != SDC_RET_OK) {
+			return 0;
+		}
+
+		/* Wait for card enter to rcv state */
+		while (Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_RCV_ST) {}
+
+#ifdef SDC_DMA_ENABLE
+		/* Enable Transmit interrupts */
+		Chip_SDC_SetIntMask(pSDC, SDC_MASK0_DATA | SDC_MASK0_TXDATAERR);
+
+		/* Get DMA channel */
+		Event.DmaChannel = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, GPDMA_CONN_SDC);
+
+		/* Start the DMA transfer */
+		Chip_GPDMA_Transfer(LPC_GPDMA, Event.DmaChannel,
+							buf_ptr,
+							GPDMA_CONN_SDC,
+							GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL,
+							(tfr_blk_cnt * MMC_SECTOR_SIZE));
+#else
+		/* Enable Transmit interrupts */
+		Chip_SDC_SetIntMask(SDC_MASK0_DATA | SDC_MASK0_TXDATAERR | SDC_MASK0_TXFIFO);
+
+		Event.Buffer = buf_ptr;
+		Event.Size = (tfr_blk_cnt * MMC_SECTOR_SIZE);
+		Event.Index = 0;
+		Event.Dir = 0;
+#endif
+		/* Call Event Setup function */
+		pCardInfo->evsetup_cb((void *) &Event);
+
+		/* Set transfer information */
+		Transfer.BlockNum = tfr_blk_cnt;
+		Chip_SDC_SetDataTransfer(pSDC, &Transfer);
+
+		/* Wait for transfer done */
+		if ((pCardInfo->waitfunc_cb()) != 0) {
+			ByteNum = 0;
+			goto end_send;
+		}
+
+#ifdef SDC_DMA_ENABLE
+		Chip_GPDMA_Stop(LPC_GPDMA, Event.DmaChannel);
+#endif
+
+		if ((tfr_blk_cnt > 1) || (Chip_SDMMC_GetCardState(pSDC, pCardInfo) == SDMMC_RCV_ST)) {
+			/* Send Stop transmission command */
+			stopTranmission(pSDC, pCardInfo->rca);
+		}
+
+		/*Wait for card enter to tran state*/
+		while (Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_TRAN_ST) {}
+
+		/* Update cnt */
+		block_cnt -= tfr_blk_cnt;
+		buf_ptr += (tfr_blk_cnt * MMC_SECTOR_SIZE);
+		start_blk += tfr_blk_cnt;
+	}
+
+end_send:
+	if (ByteNum == 0) {
+#ifdef SDC_DMA_ENABLE
+		Chip_GPDMA_Stop(LPC_GPDMA, Event.DmaChannel);
+#endif
+
+		if ((blockNum > 1) || (Chip_SDMMC_GetCardState(pSDC, pCardInfo) == SDMMC_RCV_ST)) {
+			/* Send Stop transmission command */
+			stopTranmission(pSDC, pCardInfo->rca);
+		}
+
+		/* Wait for card enter to tran state */
+		while (Chip_SDMMC_GetCardState(pSDC, pCardInfo) != SDMMC_TRAN_ST) {}
+	}
+
+	return ByteNum;
+}
+
+#endif /* defined(CHIP_LPC177X_8X) || defined(CHIP_LPC4XX) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/spi_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/spi_17xx_40xx.c
new file mode 100644
index 000000000..ac3ebe78a
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/spi_17xx_40xx.c
@@ -0,0 +1,227 @@
+/*
+ * @brief LPC17xx/40xx SPI driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+#if defined(CHIP_LPC175X_6X)
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Execute callback function */
+STATIC void executeCallback(LPC_SPI_T *pSPI, SPI_CALLBACK_T pfunc)
+{
+	if (pfunc) {
+		(pfunc) ();
+	}
+}
+
+/* Write byte(s) to FIFO buffer */
+STATIC void writeData(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint32_t num_bytes)
+{
+	uint16_t data2write = 0xFFFF;
+
+	if ( pXfSetup->pTxData) {
+		data2write =  pXfSetup->pTxData[pXfSetup->cnt];
+		if (num_bytes == 2) {
+			data2write |= pXfSetup->pTxData[pXfSetup->cnt + 1] << 8;
+		}
+	}
+
+	Chip_SPI_SendFrame(pSPI, data2write);
+
+}
+
+/* Read byte(s) from FIFO buffer */
+STATIC void readData(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint16_t rDat, uint32_t num_bytes)
+{
+	rDat = Chip_SPI_ReceiveFrame(pSPI);
+	if (pXfSetup->pRxData) {
+		pXfSetup->pRxData[pXfSetup->cnt] = rDat;
+		if (num_bytes == 2) {
+			pXfSetup->pRxData[pXfSetup->cnt + 1] = rDat >> 8;
+		}
+	}
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* SPI Polling Read/Write in blocking mode */
+uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
+{
+	uint32_t status;
+	uint16_t rDat = 0x0000;
+	uint8_t bytes = 1;
+
+	/* Clear status */
+	Chip_SPI_Int_FlushData(pSPI);
+
+	if (Chip_SPI_GetDataSize(pSPI) != SPI_BITS_8) {
+		bytes = 2;
+	}
+
+	executeCallback(pSPI, pXfSetup->fnBefTransfer);
+
+	while (pXfSetup->cnt < pXfSetup->length) {
+
+		executeCallback(pSPI, pXfSetup->fnBefFrame);
+
+		/* write data to buffer */
+		writeData(pSPI, pXfSetup, bytes);
+
+		/* Wait for transfer completes */
+		while (1) {
+			status = Chip_SPI_GetStatus(pSPI);
+			/* Check error */
+			if (status & SPI_SR_ERROR) {
+				goto rw_end;
+			}
+			if (status & SPI_SR_SPIF) {
+				break;
+			}
+		}
+
+		executeCallback(pSPI, pXfSetup->fnAftFrame);
+
+		/* Read data*/
+		readData(pSPI, pXfSetup, rDat, bytes);
+		pXfSetup->cnt += bytes;
+	}
+
+rw_end:
+	executeCallback(pSPI, pXfSetup->fnAftTransfer);
+	return pXfSetup->cnt;
+}
+
+/* Clean all data in RX FIFO of SPI */
+void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI)
+{
+	volatile uint32_t tmp;
+	Chip_SPI_GetStatus(pSPI);
+	tmp = Chip_SPI_ReceiveFrame(pSPI);
+	Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF);
+}
+
+/* SPI Interrupt Read/Write with 8-bit frame width */
+Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup, uint8_t bytes)
+{
+	uint32_t status;
+	uint16_t rDat = 0x0000;
+
+	status = Chip_SPI_GetStatus(pSPI);
+	/* Check error status */
+	if (status & SPI_SR_ERROR) {
+		return ERROR;
+	}
+
+	Chip_SPI_Int_ClearStatus(pSPI, SPI_INT_SPIF);
+	if (status & SPI_SR_SPIF) {
+		executeCallback(pSPI, pXfSetup->fnAftFrame);
+		if (pXfSetup->cnt < pXfSetup->length) {
+			/* read data */
+			readData(pSPI, pXfSetup, rDat, bytes);
+			pXfSetup->cnt += bytes;
+		}
+	}
+
+	if (pXfSetup->cnt < pXfSetup->length) {
+
+		executeCallback(pSPI, pXfSetup->fnBefFrame);
+
+		/* Write data  */
+		writeData(pSPI, pXfSetup, bytes);
+	}
+	else {
+		executeCallback(pSPI, pXfSetup->fnAftTransfer);
+	}
+	return SUCCESS;
+}
+
+/* SPI Interrupt Read/Write with 8-bit frame width */
+Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
+{
+	return Chip_SPI_Int_RWFrames(pSPI, pXfSetup, 1);
+}
+
+/* SPI Interrupt Read/Write with 16-bit frame width */
+Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup)
+{
+	return Chip_SPI_Int_RWFrames(pSPI, pXfSetup, 2);
+}
+
+/* Set the clock frequency for SPI interface */
+void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate)
+{
+	uint32_t spiClk, counter;
+	/* Get SPI clock rate */
+	spiClk = Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_SPI);
+
+	counter = spiClk / bitRate;
+	if (counter < 8) {
+		counter = 8;
+	}
+	counter = ((counter + 1) / 2) * 2;
+
+	if (counter > 254) {
+		counter = 254;
+	}
+
+	Chip_SPI_SetClockCounter(pSPI, counter);
+}
+
+/* Initialize the SPI */
+void Chip_SPI_Init(LPC_SPI_T *pSPI)
+{
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SPI);
+
+	Chip_SPI_SetMode(pSPI, SPI_MODE_MASTER);
+	pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | SPI_BITS_8 | SPI_CLOCK_CPHA0_CPOL0 | SPI_DATA_MSB_FIRST;
+	Chip_SPI_SetBitRate(pSPI, 400000);
+}
+
+/* De-initializes the SPI peripheral */
+void Chip_SPI_DeInit(LPC_SPI_T *pSPI)
+{
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SPI);
+}
+
+#endif /* defined(CHIP_LPC175X_6X) */
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/ssp_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/ssp_17xx_40xx.c
new file mode 100644
index 000000000..112618e9b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/ssp_17xx_40xx.c
@@ -0,0 +1,478 @@
+/*
+ * @brief LPC17xx/40xx SSP driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	if (xf_setup->tx_data) {
+		Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data +
+												 xf_setup->tx_cnt)));
+	}
+	else {
+		Chip_SSP_SendFrame(pSSP, 0xFFFF);
+	}
+
+	xf_setup->tx_cnt += 2;
+}
+
+/** SSP macro: write 1 bytes to FIFO buffer */
+STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	if (xf_setup->tx_data) {
+		Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
+	}
+	else {
+		Chip_SSP_SendFrame(pSSP, 0xFF);
+	}
+
+	xf_setup->tx_cnt++;
+}
+
+/** SSP macro: read 1 bytes from FIFO buffer */
+STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	uint16_t rDat;
+
+	while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
+		   (xf_setup->rx_cnt < xf_setup->length)) {
+		rDat = Chip_SSP_ReceiveFrame(pSSP);
+		if (xf_setup->rx_data) {
+			*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
+		}
+
+		xf_setup->rx_cnt += 2;
+	}
+}
+
+/** SSP macro: read 2 bytes from FIFO buffer */
+STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	uint16_t rDat;
+
+	while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
+		   (xf_setup->rx_cnt < xf_setup->length)) {
+		rDat = Chip_SSP_ReceiveFrame(pSSP);
+		if (xf_setup->rx_data) {
+			*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
+		}
+
+		xf_setup->rx_cnt++;
+	}
+}
+
+/* Returns clock for the peripheral block */
+STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
+{
+	CHIP_SYSCTL_CLOCK_T clkSSP;
+
+	if (pSSP == LPC_SSP1) {
+		clkSSP = SYSCTL_CLOCK_SSP1;
+	}
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	else if (pSSP == LPC_SSP2) {
+		clkSSP = SYSCTL_CLOCK_SSP2;
+	}
+#endif
+	else {
+		clkSSP = SYSCTL_CLOCK_SSP0;
+	}
+
+	return clkSSP;
+}
+
+#if defined(CHIP_LPC175X_6X)
+/* Returns clock ID for the peripheral block */
+STATIC CHIP_SYSCTL_PCLK_T Chip_SSP_GetClkIndex(LPC_SSP_T *pSSP)
+{
+	CHIP_SYSCTL_PCLK_T clkSSP;
+
+	if (pSSP == LPC_SSP0) {
+		clkSSP = SYSCTL_PCLK_SSP0;
+	}
+	else {
+		clkSSP = SYSCTL_PCLK_SSP1;
+	}
+
+	return clkSSP;
+}
+
+#endif
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/*Set up output clocks per bit for SSP bus*/
+void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
+{
+	uint32_t temp;
+	temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
+	pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
+	pSSP->CPSR = prescale;
+}
+
+/* SSP Polling Read/Write in blocking mode */
+uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
+			/* write data to buffer */
+			if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
+				SSP_Write2BFifo(pSSP, xf_setup);
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			SSP_Read2BFifo(pSSP, xf_setup);
+		}
+	}
+	else {
+		while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
+			/* write data to buffer */
+			if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
+				SSP_Write1BFifo(pSSP, xf_setup);
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			SSP_Read1BFifo(pSSP, xf_setup);
+		}
+	}
+	if (xf_setup->tx_data) {
+		return xf_setup->tx_cnt;
+	}
+	else if (xf_setup->rx_data) {
+		return xf_setup->rx_cnt;
+	}
+
+	return 0;
+}
+
+/* SSP Polling Write in blocking mode */
+uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
+{
+	uint32_t tx_cnt = 0, rx_cnt = 0;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		uint16_t *wdata16;
+
+		wdata16 = (uint16_t *) buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, *wdata16);
+				wdata16++;
+				tx_cnt += 2;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
+				Chip_SSP_ReceiveFrame(pSSP);	/* read dummy data */
+				rx_cnt += 2;
+			}
+		}
+	}
+	else {
+		uint8_t *wdata8;
+
+		wdata8 = buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, *wdata8);
+				wdata8++;
+				tx_cnt++;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				Chip_SSP_ReceiveFrame(pSSP);	/* read dummy data */
+				rx_cnt++;
+			}
+		}
+	}
+
+	return tx_cnt;
+
+}
+
+/* SSP Polling Read in blocking mode */
+uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
+{
+	uint32_t rx_cnt = 0, tx_cnt = 0;
+
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+
+	if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
+		uint16_t *rdata16;
+
+		rdata16 = (uint16_t *) buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, 0xFFFF);	/* just send dummy data */
+				tx_cnt += 2;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
+				rdata16++;
+				rx_cnt += 2;
+			}
+		}
+	}
+	else {
+		uint8_t *rdata8;
+
+		rdata8 = buffer;
+
+		while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
+			/* write data to buffer */
+			if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
+				Chip_SSP_SendFrame(pSSP, 0xFF);	/* just send dummy data		 */
+				tx_cnt++;
+			}
+
+			/* Check overrun error */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/* Check for any data available in RX FIFO */
+			while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
+				*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
+				rdata8++;
+				rx_cnt++;
+			}
+		}
+	}
+
+	return rx_cnt;
+
+}
+
+/* Clean all data in RX FIFO of SSP */
+void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
+{
+	if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
+		while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
+	}
+
+	/* Clear all remaining frames in RX FIFO */
+	while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
+		Chip_SSP_ReceiveFrame(pSSP);
+	}
+
+	/* Clear status */
+	Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
+}
+
+/* SSP Interrupt Read/Write with 8-bit frame width */
+Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	/* Check overrun error in RIS register */
+	if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+		return ERROR;
+	}
+
+	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
+		/* check if RX FIFO contains data */
+		SSP_Read1BFifo(pSSP, xf_setup);
+
+		while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
+			/* Write data to buffer */
+			SSP_Write1BFifo(pSSP, xf_setup);
+
+			/* Check overrun error in RIS register */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/*  Check for any data available in RX FIFO */
+			SSP_Read1BFifo(pSSP, xf_setup);
+		}
+
+		return SUCCESS;
+	}
+
+	return ERROR;
+}
+
+/* SSP Interrupt Read/Write with 16-bit frame width */
+Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
+{
+	/* Check overrun error in RIS register */
+	if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+		return ERROR;
+	}
+
+	if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
+		/* check if RX FIFO contains data */
+		SSP_Read2BFifo(pSSP, xf_setup);
+
+		while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
+			/* Write data to buffer */
+			SSP_Write2BFifo(pSSP, xf_setup);
+
+			/* Check overrun error in RIS register */
+			if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
+				return ERROR;
+			}
+
+			/*  Check for any data available in RX FIFO			 */
+			SSP_Read2BFifo(pSSP, xf_setup);
+		}
+
+		return SUCCESS;
+	}
+
+	return ERROR;
+}
+
+/* Set the SSP operating modes, master or slave */
+void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
+{
+	if (master) {
+		Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
+	}
+	else {
+		Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
+	}
+}
+
+/* Set the clock frequency for SSP interface */
+void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
+{
+	uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
+
+#if defined(CHIP_LPC175X_6X)
+	ssp_clk = Chip_Clock_GetPeripheralClockRate(Chip_SSP_GetClkIndex(pSSP));
+#else
+	ssp_clk = Chip_Clock_GetPeripheralClockRate();
+#endif
+
+	cr0_div = 0;
+	cmp_clk = 0xFFFFFFFF;
+	prescale = 2;
+
+	while (cmp_clk > bitRate) {
+		cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
+		if (cmp_clk > bitRate) {
+			cr0_div++;
+			if (cr0_div > 0xFF) {
+				cr0_div = 0;
+				prescale += 2;
+			}
+		}
+	}
+
+	Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
+}
+
+/* Initialize the SSP */
+void Chip_SSP_Init(LPC_SSP_T *pSSP)
+{
+	Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
+
+	Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
+	Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
+	Chip_SSP_SetBitRate(pSSP, 100000);
+}
+
+/* De-initializes the SSP peripheral */
+void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
+{
+	Chip_SSP_Disable(pSSP);
+
+	Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/stopwatch_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/stopwatch_17xx_40xx.c
new file mode 100644
index 000000000..856409440
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/stopwatch_17xx_40xx.c
@@ -0,0 +1,110 @@
+/*
+ * @brief LPC17xx_40xx specific stopwatch implementation
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+#include "stopwatch.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Precompute these to optimize runtime */
+static uint32_t ticksPerSecond;
+static uint32_t ticksPerMs;
+static uint32_t ticksPerUs;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize stopwatch */
+void StopWatch_Init(void)
+{
+	/* Use timer 1. Set prescaler to divide by 8, should give ticks at 3.75 MHz.
+	   That gives a useable stopwatch measurement range of about 19 minutes
+	   (if system clock is running at 120 MHz). */
+	const uint32_t prescaleDivisor = 8;
+	Chip_TIMER_Init(LPC_TIMER1);
+	Chip_TIMER_PrescaleSet(LPC_TIMER1, prescaleDivisor - 1);
+	Chip_TIMER_Enable(LPC_TIMER1);
+
+	/* Pre-compute tick rate. Note that peripheral clock supplied to the
+	   timer includes a fixed divide by 4. */
+	ticksPerSecond = Chip_Clock_GetSystemClockRate() / prescaleDivisor / 4;
+	ticksPerMs = ticksPerSecond / 1000;
+	ticksPerUs = ticksPerSecond / 1000000;
+}
+
+/* Start a stopwatch */
+uint32_t StopWatch_Start(void)
+{
+	/* Return the current timer count. */
+	return Chip_TIMER_ReadCount(LPC_TIMER1);
+}
+
+/* Returns number of ticks per second of the stopwatch timer */
+uint32_t StopWatch_TicksPerSecond(void)
+{
+	return ticksPerSecond;
+}
+
+/* Converts from stopwatch ticks to mS. */
+uint32_t StopWatch_TicksToMs(uint32_t ticks)
+{
+	return ticks / ticksPerMs;
+}
+
+/* Converts from stopwatch ticks to uS. */
+uint32_t StopWatch_TicksToUs(uint32_t ticks)
+{
+	return ticks / ticksPerUs;
+}
+
+/* Converts from mS to stopwatch ticks. */
+uint32_t StopWatch_MsToTicks(uint32_t mS)
+{
+	return mS * ticksPerMs;
+}
+
+/* Converts from uS to stopwatch ticks. */
+uint32_t StopWatch_UsToTicks(uint32_t uS)
+{
+	return uS * ticksPerUs;
+}
+
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c
new file mode 100644
index 000000000..ec5a3eb39
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c
@@ -0,0 +1,70 @@
+/*
+ * @brief	LPC17xx/40xx System and Control driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+/* Returns and clears the current sleep mode entry flags */
+uint32_t Chip_SYSCTL_GetClrSleepFlags(uint32_t flags) {
+	uint32_t savedFlags = LPC_SYSCTL->PCON;
+
+	LPC_SYSCTL->PCON = flags;
+
+	return savedFlags & (SYSCTL_PD_SMFLAG | SYSCTL_PD_DSFLAG |
+						 SYSCTL_PD_PDFLAG | SYSCTL_PD_DPDFLAG);
+}
+
+#if !defined(CHIP_LPC175X_6X)
+/* Resets a peripheral */
+void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_RESET_T periph)
+{
+	uint32_t bitIndex, regIndex = (uint32_t) periph;
+
+	/* Get register array index and clock index into the register */
+	bitIndex = (regIndex % 32);
+	regIndex = regIndex / 32;
+
+	/* Reset peripheral */
+	LPC_SYSCTL->RSTCON[regIndex] = (1 << bitIndex);
+	LPC_SYSCTL->RSTCON[regIndex] &= ~(1 << bitIndex);
+}
+
+#endif /*!defined(CHIP_LPC175X_6X)*/
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c
new file mode 100644
index 000000000..2cfb9b318
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c
@@ -0,0 +1,178 @@
+/*
+ * @brief LPC17xx/40xx Chip specific SystemInit
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+#if defined(CHIP_LPC175X_6X)
+void Chip_SetupIrcClocking(void)
+{
+	/* Disconnect the Main PLL if it is connected already */
+	if (Chip_Clock_IsMainPLLConnected()) {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
+	}
+
+	/* Disable the PLL if it is enabled */
+	if (Chip_Clock_IsMainPLLEnabled()) {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+	}
+
+	Chip_Clock_SetCPUClockDiv(0);
+	Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_IRC);
+
+	/* FCCO = ((44+1) * 2 * 4MHz) / (0+1) = 360MHz */
+	Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 44, 0);
+
+	Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+
+	Chip_Clock_SetCPUClockDiv(2);
+	while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
+
+	Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
+}
+
+void Chip_SetupXtalClocking(void)
+{
+	/* Disconnect the Main PLL if it is connected already */
+	if (Chip_Clock_IsMainPLLConnected()) {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
+	}
+
+	/* Disable the PLL if it is enabled */
+	if (Chip_Clock_IsMainPLLEnabled()) {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+	}
+
+	/* Enable the crystal */
+	if (!Chip_Clock_IsCrystalEnabled())
+		Chip_Clock_EnableCrystal();
+	while(!Chip_Clock_IsCrystalEnabled()) {}
+
+	/* Set PLL0 Source to Crystal Oscillator */
+	Chip_Clock_SetCPUClockDiv(0);
+	Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
+
+	/* FCCO = ((15+1) * 2 * 12MHz) / (0+1) = 384MHz */
+	Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 15, 0);
+
+	Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+
+	/* 384MHz / (3+1) = 96MHz */
+	Chip_Clock_SetCPUClockDiv(3);
+	while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
+
+	Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
+}
+#endif
+
+#if (defined(CHIP_LPC177X_8X) | defined(CHIP_LPC40XX))
+/* Clock and PLL initialization based on the internal oscillator */
+void Chip_SetupIrcClocking(void)
+{
+	/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
+	Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
+
+	/* Disable the PLL if it is enabled */
+	if (Chip_Clock_IsMainPLLEnabled()) {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+	}
+
+	/* It is safe to switch the PLL Source to IRC */
+	Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_IRC);
+
+	/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
+	/* Fout = FCCO / ((0+1) * 2) = 120MHz */
+	Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
+
+	Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+	Chip_Clock_SetCPUClockDiv(1);
+	while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
+	Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
+
+	/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
+	Chip_Clock_SetPCLKDiv(2);
+}
+
+/* Clock and PLL initialization based on the external oscillator */
+void Chip_SetupXtalClocking(void)
+{
+	/* Enable the crystal */
+	if (!Chip_Clock_IsCrystalEnabled())
+		Chip_Clock_EnableCrystal();
+
+	while(!Chip_Clock_IsCrystalEnabled()) {}
+
+	/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
+	Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
+
+	/* Disable the PLL if it is enabled */
+	if (Chip_Clock_IsMainPLLEnabled()) {
+		Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+	}
+
+	/* It is safe to switch the PLL Source to Crystal Oscillator */
+	Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
+
+	/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
+	/* Fout = FCCO / ((0+1) * 2) = 120MHz */
+	Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
+
+	Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
+	Chip_Clock_SetCPUClockDiv(1);
+
+	while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
+	Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
+
+	/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
+	Chip_Clock_SetPCLKDiv(2);
+}
+#endif
+
+/* Set up and initialize hardware prior to call to main */
+void Chip_SystemInit(void)
+{
+	/* Setup Chip clocking */
+	Chip_SetupIrcClocking();
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/timer_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/timer_17xx_40xx.c
new file mode 100644
index 000000000..224adc33c
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/timer_17xx_40xx.c
@@ -0,0 +1,116 @@
+/*
+ * @brief LPC17xx/40xx 16/32-bit Timer/PWM driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Returns clock for the peripheral block */
+STATIC CHIP_SYSCTL_CLOCK_T Chip_Timer_GetClockIndex(LPC_TIMER_T *pTMR)
+{
+	CHIP_SYSCTL_CLOCK_T clkTMR;
+
+	if (pTMR == LPC_TIMER1) {
+		clkTMR = SYSCTL_CLOCK_TIMER1;
+	}
+	else if (pTMR == LPC_TIMER2) {
+		clkTMR = SYSCTL_CLOCK_TIMER2;
+	}
+	else if (pTMR == LPC_TIMER3) {
+		clkTMR = SYSCTL_CLOCK_TIMER3;
+	}
+	else {
+		clkTMR = SYSCTL_CLOCK_TIMER0;
+	}
+
+	return clkTMR;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize a timer */
+void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
+{
+	Chip_Clock_EnablePeriphClock(Chip_Timer_GetClockIndex(pTMR));
+}
+
+/*	Shutdown a timer */
+void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
+{
+	Chip_Clock_DisablePeriphClock(Chip_Timer_GetClockIndex(pTMR));
+}
+
+/* Resets the timer terminal and prescale counts to 0 */
+void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
+{
+	uint32_t reg;
+
+	/* Disable timer, set terminal count to non-0 */
+	reg = pTMR->TCR;
+	pTMR->TCR = 0;
+	pTMR->TC = 1;
+
+	/* Reset timer counter */
+	pTMR->TCR = TIMER_RESET;
+
+	/* Wait for terminal count to clear */
+	while (pTMR->TC != 0) {}
+
+	/* Restore timer state */
+	pTMR->TCR = reg;
+}
+
+/* Sets external match control (MATn.matchnum) pin control */
+void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
+								   TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
+{
+	uint32_t mask, reg;
+
+	/* Clear bits corresponding to selected match register */
+	mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2)));
+	reg = pTMR->EMR &= ~mask;
+
+	/* Set new configuration for selected match register */
+	pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) |
+				(((uint32_t) matchState) << (4 + (matchnum * 2)));
+}
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c
new file mode 100644
index 000000000..88555bdf3
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c
@@ -0,0 +1,533 @@
+/*
+ * @brief LPC11xx UART chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Autobaud status flag */
+STATIC volatile FlagStatus ABsyncSts = RESET;
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Returns clock for the peripheral block */
+STATIC CHIP_SYSCTL_CLOCK_T Chip_UART_GetClockIndex(LPC_USART_T *pUART)
+{
+	CHIP_SYSCTL_CLOCK_T clkUART;
+
+	if (pUART == LPC_UART1) {
+		clkUART = SYSCTL_CLOCK_UART1;
+	}
+	else if (pUART == LPC_UART2) {
+		clkUART = SYSCTL_CLOCK_UART2;
+	}
+	else if (pUART == LPC_UART3) {
+		clkUART = SYSCTL_CLOCK_UART3;
+	}
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+	else if (pUART == LPC_UART4) {
+		clkUART = SYSCTL_CLOCK_UART4;
+	}
+#endif
+	else {
+		clkUART = SYSCTL_CLOCK_UART0;
+	}
+
+	return clkUART;
+}
+
+/* UART Autobaud command interrupt handler */
+STATIC void Chip_UART_ABIntHandler(LPC_USART_T *pUART)
+{
+	/* Handle End Of Autobaud interrupt */
+	if((Chip_UART_ReadIntIDReg(pUART) & UART_IIR_ABEO_INT) != 0) {
+        Chip_UART_SetAutoBaudReg(pUART, UART_ACR_ABEOINT_CLR); 
+		Chip_UART_IntDisable(pUART, UART_IER_ABEOINT);
+	    if (ABsyncSts == RESET) {
+	        ABsyncSts = SET;
+        }
+	}
+	
+    /* Handle Autobaud Timeout interrupt */
+	if((Chip_UART_ReadIntIDReg(pUART) & UART_IIR_ABTO_INT) != 0) {
+        Chip_UART_SetAutoBaudReg(pUART, UART_ACR_ABTOINT_CLR); 
+		Chip_UART_IntDisable(pUART, UART_IER_ABTOINT);
+	}
+}
+
+#if defined(CHIP_LPC175X_6X)
+/* Returns clock ID for the peripheral block */
+STATIC CHIP_SYSCTL_PCLK_T Chip_UART_GetClkIndex(LPC_USART_T *pUART)
+{
+	CHIP_SYSCTL_PCLK_T clkUART;
+
+	if (pUART == LPC_UART1) {
+		clkUART = SYSCTL_PCLK_UART1;
+	}
+	else if (pUART == LPC_UART2) {
+		clkUART = SYSCTL_PCLK_UART2;
+	}
+	else if (pUART == LPC_UART3) {
+		clkUART = SYSCTL_PCLK_UART3;
+	}
+	else {
+		clkUART = SYSCTL_PCLK_UART0;
+	}
+
+	return clkUART;
+}
+#endif
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the pUART peripheral */
+void Chip_UART_Init(LPC_USART_T *pUART)
+{
+    uint32_t tmp;
+
+	(void) tmp;
+	
+	/* Enable UART clocking. UART base clock(s) must already be enabled */
+	Chip_Clock_EnablePeriphClock(Chip_UART_GetClockIndex(pUART));
+
+	/* Enable FIFOs by default, reset them */
+	Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS));
+    
+    /* Disable Tx */
+    Chip_UART_TXDisable(pUART);
+	
+    /* Disable interrupts */
+	pUART->IER = 0;
+	/* Set LCR to default state */
+	pUART->LCR = 0;
+	/* Set ACR to default state */
+	pUART->ACR = 0;
+    /* Set RS485 control to default state */
+	pUART->RS485CTRL = 0;
+	/* Set RS485 delay timer to default state */
+	pUART->RS485DLY = 0;
+	/* Set RS485 addr match to default state */
+	pUART->RS485ADRMATCH = 0;
+	
+    /* Clear MCR */
+    if (pUART == LPC_UART1) {
+		/* Set Modem Control to default state */
+		pUART->MCR = 0;
+		/*Dummy Reading to Clear Status */
+		tmp = pUART->MSR;
+	}
+
+	/* Default 8N1, with DLAB disabled */
+	Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS));
+
+	/* Disable fractional divider */
+	pUART->FDR = 0x10;
+}
+
+/* De-initializes the pUART peripheral */
+void Chip_UART_DeInit(LPC_USART_T *pUART)
+{
+    /* Disable Tx */
+    Chip_UART_TXDisable(pUART);
+
+    /* Disable clock */
+	Chip_Clock_DisablePeriphClock(Chip_UART_GetClockIndex(pUART));
+}
+
+/* Enable transmission on UART TxD pin */
+void Chip_UART_TXEnable(LPC_USART_T *pUART)
+{
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+    if(pUART == LPC_UART4) {
+        pUART->TER2 = UART_TER2_TXEN;
+    }
+    else {
+#endif
+        pUART->TER1 = UART_TER1_TXEN;
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+    }
+#endif
+}
+
+/* Disable transmission on UART TxD pin */
+void Chip_UART_TXDisable(LPC_USART_T *pUART)
+{
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+    if(pUART == LPC_UART4) {
+        pUART->TER2 = 0;
+    }
+    else {
+#endif
+        pUART->TER1 = 0;
+#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC40XX)
+    }
+#endif
+}
+
+/* Transmit a byte array through the UART peripheral (non-blocking) */
+int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
+{
+	int sent = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	/* Send until the transmit FIFO is full or out of bytes */
+	while ((sent < numBytes) &&
+		   ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) {
+		Chip_UART_SendByte(pUART, *p8);
+		p8++;
+		sent++;
+	}
+
+	return sent;
+}
+
+/* Check whether if UART is busy or not */
+FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART)
+{
+	if (pUART->LSR & UART_LSR_TEMT) {
+		return RESET;
+	}
+	else {
+		return SET;
+	}
+}
+
+/* Transmit a byte array through the UART peripheral (blocking) */
+int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes)
+{
+	int pass, sent = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	while (numBytes > 0) {
+		pass = Chip_UART_Send(pUART, p8, numBytes);
+		numBytes -= pass;
+		sent += pass;
+		p8 += pass;
+	}
+
+	return sent;
+}
+
+/* Read data through the UART peripheral (non-blocking) */
+int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
+{
+	int readBytes = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	/* Send until the transmit FIFO is full or out of bytes */
+	while ((readBytes < numBytes) &&
+		   ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) {
+		*p8 = Chip_UART_ReadByte(pUART);
+		p8++;
+		readBytes++;
+	}
+
+	return readBytes;
+}
+
+/* Read data through the UART peripheral (blocking) */
+int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes)
+{
+	int pass, readBytes = 0;
+	uint8_t *p8 = (uint8_t *) data;
+
+	while (readBytes < numBytes) {
+		pass = Chip_UART_Read(pUART, p8, numBytes);
+		numBytes -= pass;
+		readBytes += pass;
+		p8 += pass;
+	}
+
+	return readBytes;
+}
+
+/* Determines and sets best dividers to get a target bit rate */
+uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
+{
+	uint32_t div, divh, divl, clkin;
+
+	/* Determine UART clock in rate without FDR */
+#if defined(CHIP_LPC175X_6X)
+	clkin = Chip_Clock_GetPeripheralClockRate(Chip_UART_GetClkIndex(pUART));
+#else
+	clkin = Chip_Clock_GetPeripheralClockRate();
+#endif
+	div = clkin / (baudrate * 16);
+
+	/* High and low halves of the divider */
+	divh = div / 256;
+	divl = div - (divh * 256);
+
+	Chip_UART_EnableDivisorAccess(pUART);
+	Chip_UART_SetDivisorLatches(pUART, divl, divh);
+	Chip_UART_DisableDivisorAccess(pUART);
+
+	/* Fractional FDR already setup for 1 in UART init */
+
+	return clkin / div;
+}
+
+/* UART receive-only interrupt handler for ring buffers */
+void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
+{
+	/* New data will be ignored if data not popped in time */
+	while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) {
+		uint8_t ch = Chip_UART_ReadByte(pUART);
+		RingBuffer_Insert(pRB, &ch);
+	}
+}
+
+/* UART transmit-only interrupt handler for ring buffers */
+void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
+{
+	uint8_t ch;
+
+	/* Fill FIFO until full or until TX ring buffer is empty */
+	while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 &&
+		   RingBuffer_Pop(pRB, &ch)) {
+		Chip_UART_SendByte(pUART, ch);
+	}
+}
+
+/* Populate a transmit ring buffer and start UART transmit */
+uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
+{
+	uint32_t ret;
+	uint8_t *p8 = (uint8_t *) data;
+
+	/* Don't let UART transmit ring buffer change in the UART IRQ handler */
+	Chip_UART_IntDisable(pUART, UART_IER_THREINT);
+
+	/* Move as much data as possible into transmit ring buffer */
+	ret = RingBuffer_InsertMult(pRB, p8, bytes);
+	Chip_UART_TXIntHandlerRB(pUART, pRB);
+
+	/* Add additional data to transmit ring buffer if possible */
+	ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
+
+	/* Enable UART transmit interrupt */
+	Chip_UART_IntEnable(pUART, UART_IER_THREINT);
+
+	return ret;
+}
+
+/* Copy data from a receive ring buffer */
+int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes)
+{
+	(void) pUART;
+
+	return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes);
+}
+
+/* UART receive/transmit interrupt handler for ring buffers */
+void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
+{
+	/* Handle transmit interrupt if enabled */
+	if (pUART->IER & UART_IER_THREINT) {
+		Chip_UART_TXIntHandlerRB(pUART, pTXRB);
+
+		/* Disable transmit interrupt if the ring buffer is empty */
+		if (RingBuffer_IsEmpty(pTXRB)) {
+			Chip_UART_IntDisable(pUART, UART_IER_THREINT);
+		}
+	}
+
+	/* Handle receive interrupt */
+	Chip_UART_RXIntHandlerRB(pUART, pRXRB);
+
+    /* Handle Autobaud interrupts */
+    Chip_UART_ABIntHandler(pUART);
+}
+
+/* Determines and sets best dividers to get a target baud rate */
+uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate)
+
+{
+	uint32_t uClk;
+	uint32_t actualRate = 0, d, m, bestd, bestm, tmp;
+	uint32_t current_error, best_error;
+	uint64_t best_divisor, divisor;
+	uint32_t recalcbaud;
+
+	/* Get Clock rate */
+#if defined(CHIP_LPC175X_6X)
+	uClk = Chip_Clock_GetPeripheralClockRate(Chip_UART_GetClkIndex(pUART));
+#else
+	uClk = Chip_Clock_GetPeripheralClockRate();
+#endif
+    
+	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
+	 * The formula is :
+	 * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
+	 * It involves floating point calculations. That's the reason the formulae are adjusted with
+	 * Multiply and divide method.*/
+	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
+	 * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
+	best_error = 0xFFFFFFFF;/* Worst case */
+	bestd = 0;
+	bestm = 0;
+	best_divisor = 0;
+	for (m = 1; m <= 15; m++) {
+		for (d = 0; d < m; d++) {
+
+			/*   The result here is a fixed point number.  The integer portion is in the upper 32 bits.
+			 * The fractional portion is in the lower 32 bits.
+			 */
+			divisor = ((uint64_t) uClk << 28) * m / (baudrate * (m + d));
+
+			/*   The fractional portion is the error. */
+			current_error = divisor & 0xFFFFFFFF;
+
+			/*   Snag the integer portion of the divisor. */
+			tmp = divisor >> 32;
+
+			/*   If closer to the next divisor... */
+			if (current_error > ((uint32_t) 1 << 31)) {
+
+				/* Increment to the next divisor... */
+				tmp++;
+
+				/* Now the error is the distance to the next divisor... */
+				current_error = -current_error;
+			}
+
+			/*   Can't use a divisor that's less than 1 or more than 65535. */
+			if ((tmp < 1) || (tmp > 65535)) {
+				/* Out of range */
+				continue;
+			}
+
+			/*   Also, if fractional divider is enabled can't use a divisor that is less than 3. */
+			if ((d != 0) && (tmp < 3)) {
+				/* Out of range */
+				continue;
+			}
+
+			/*   Do we have a new best? */
+			if (current_error < best_error) {
+				best_error = current_error;
+				best_divisor = tmp;
+				bestd = d;
+				bestm = m;
+
+				/*   If error is 0, that's perfect.  We're done. */
+				if (best_error == 0) {
+					break;
+				}
+			}
+		}	/* for (d) */
+
+		/*   If error is 0, that's perfect.  We're done. */
+		if (best_error == 0) {
+			break;
+		}
+	}	/* for (m) */
+
+	if (best_divisor == 0) {
+		/* can not find best match */
+		return 0;
+	}
+
+	recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
+
+	/* reuse best_error to evaluate baud error */
+	if (baudrate > recalcbaud) {
+		best_error = baudrate - recalcbaud;
+	}
+	else {
+		best_error = recalcbaud - baudrate;
+	}
+
+	best_error = (best_error * 100) / baudrate;
+
+    /* Update UART registers */
+	Chip_UART_EnableDivisorAccess(pUART);
+	Chip_UART_SetDivisorLatches(pUART, UART_LOAD_DLL(best_divisor), UART_LOAD_DLM(best_divisor));
+	Chip_UART_DisableDivisorAccess(pUART);
+
+	/* Set best fractional divider */
+	pUART->FDR = (UART_FDR_MULVAL(bestm) | UART_FDR_DIVADDVAL(bestd));
+
+	/* Return actual baud rate */
+	actualRate = recalcbaud;
+
+	return actualRate;
+}
+
+/* UART interrupt service routine */
+FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART)
+{
+	(void) pUART;
+	return ABsyncSts;
+}
+
+/* Start/Stop Auto Baudrate activity */
+void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart, FunctionalState NewState)
+{
+    uint32_t tmp = 0;
+
+	if (NewState == ENABLE) {
+		/* Clear DLL and DLM value */
+		pUART->LCR |= UART_LCR_DLAB_EN;
+		pUART->DLL = 0;
+		pUART->DLM = 0;
+		pUART->LCR &= ~UART_LCR_DLAB_EN;
+
+		/* FDR value must be reset to default value */
+		pUART->FDR = 0x10;
+
+		if (mode == UART_ACR_MODE1) {
+			tmp = UART_ACR_START | UART_ACR_MODE;
+		}
+		else {
+			tmp = UART_ACR_START;
+		}
+
+		if (autorestart == true) {
+			tmp |= UART_ACR_AUTO_RESTART;
+		}
+		pUART->ACR = tmp;
+	}
+	else {
+		pUART->ACR = 0;
+	}
+}
+
diff --git a/hw/mcu/nxp/lpc_chip_40xx/src/wwdt_17xx_40xx.c b/hw/mcu/nxp/lpc_chip_40xx/src/wwdt_17xx_40xx.c
new file mode 100644
index 000000000..ad3121e5b
--- /dev/null
+++ b/hw/mcu/nxp/lpc_chip_40xx/src/wwdt_17xx_40xx.c
@@ -0,0 +1,72 @@
+/*
+ * @brief LPC17xx/40xx WWDT chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize the Watchdog timer */
+void Chip_WWDT_Init(LPC_WWDT_T *pWWDT)
+{
+	/* Disable watchdog */
+	pWWDT->MOD       = 0;
+	pWWDT->TC        = 0xFF;
+#if defined(WATCHDOG_WINDOW_SUPPORT)
+	pWWDT->WARNINT   = 0xFFFF;
+	pWWDT->WINDOW    = 0xFFFFFF;
+#endif
+}
+
+/* Clear WWDT interrupt status flags */
+void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
+{
+	if (status & WWDT_WDMOD_WDTOF) {
+		pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK;
+	}
+
+	if (status & WWDT_WDMOD_WDINT) {
+		pWWDT->MOD |= WWDT_WDMOD_WDINT;
+	}
+}
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
new file mode 100644
index 000000000..549420f22
--- /dev/null
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -0,0 +1,590 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc175x_6x.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
+
+#include "device/dcd.h"
+#include "dcd_lpc175x_6x.h"
+#include "chip.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+#define DCD_ENDPOINT_MAX 32
+
+typedef struct ATTR_ALIGNED(4)
+{
+  //------------- Word 0 -------------//
+  uint32_t next;
+
+  //------------- Word 1 -------------//
+  uint16_t atle_mode       : 2; // 00: normal, 01: ATLE (auto length extraction)
+  uint16_t next_valid      : 1;
+  uint16_t                 : 1; ///< reserved
+  uint16_t isochronous     : 1; // is an iso endpoint
+  uint16_t max_packet_size : 11;
+
+  volatile uint16_t buflen; // bytes for non-iso, number of packets for iso endpoint
+
+  //------------- Word 2 -------------//
+  volatile uint32_t buffer;
+
+  //------------- Word 3 -------------//
+  volatile uint16_t retired                : 1; // initialized to zero
+  volatile uint16_t status                 : 4;
+  volatile uint16_t iso_last_packet_valid  : 1;
+  volatile uint16_t atle_lsb_extracted     : 1;	// used in ATLE mode
+  volatile uint16_t atle_msb_extracted     : 1;	// used in ATLE mode
+  volatile uint16_t atle_mess_len_position : 6; // used in ATLE mode
+  uint16_t                                 : 2;
+
+  volatile uint16_t present_count;  // For non-iso : The number of bytes transferred by the DMA engine
+                                    // For iso : number of packets
+
+  //------------- Word 4 -------------//
+  //	uint32_t iso_packet_size_addr;		// iso only, can be omitted for non-iso
+}dma_desc_t;
+
+TU_VERIFY_STATIC( sizeof(dma_desc_t) == 16, "size is not correct"); // TODO not support ISO for now
+
+typedef struct
+{
+  // must be 128 byte aligned
+  volatile dma_desc_t* udca[DCD_ENDPOINT_MAX];
+
+  // TODO DMA does not support control transfer (0-1 are not used, offset to reduce memory)
+  dma_desc_t dd[DCD_ENDPOINT_MAX];
+
+  struct
+  {
+    uint8_t* out_buffer;
+    uint8_t  out_bytes;
+    volatile bool out_received; // indicate if data is already received in endpoint
+
+    uint8_t  in_bytes;
+  } control;
+
+} dcd_data_t;
+
+ATTR_ALIGNED(128) static dcd_data_t _dcd;
+
+
+//--------------------------------------------------------------------+
+// SIE Command
+//--------------------------------------------------------------------+
+static void sie_cmd_code (sie_cmdphase_t phase, uint8_t code_data)
+{
+  LPC_USB->DevIntClr = (DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK);
+  LPC_USB->CmdCode   = (phase << 8) | (code_data << 16);
+
+  uint32_t const wait_flag = (phase == SIE_CMDPHASE_READ) ? DEV_INT_COMMAND_DATA_FULL_MASK : DEV_INT_COMMAND_CODE_EMPTY_MASK;
+  while ((LPC_USB->DevIntSt & wait_flag) == 0) {}
+
+  LPC_USB->DevIntClr = wait_flag;
+}
+
+static void sie_write (uint8_t cmd_code, uint8_t data_len, uint8_t data)
+{
+  sie_cmd_code(SIE_CMDPHASE_COMMAND, cmd_code);
+
+  if (data_len)
+  {
+    sie_cmd_code(SIE_CMDPHASE_WRITE, data);
+  }
+}
+
+static uint8_t sie_read (uint8_t cmd_code)
+{
+  sie_cmd_code(SIE_CMDPHASE_COMMAND , cmd_code);
+  sie_cmd_code(SIE_CMDPHASE_READ    , cmd_code);
+  return (uint8_t) LPC_USB->CmdData;
+}
+
+//--------------------------------------------------------------------+
+// PIPE HELPER
+//--------------------------------------------------------------------+
+static inline uint8_t ep_addr2idx(uint8_t ep_addr)
+{
+  return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
+}
+
+static void set_ep_size(uint8_t ep_id, uint16_t max_packet_size)
+{
+  // follows example in 11.10.4.2
+  LPC_USB->ReEp    |= BIT_(ep_id);
+  LPC_USB->EpInd    = ep_id; // select index before setting packet size
+  LPC_USB->MaxPSize = max_packet_size;
+
+  while ((LPC_USB->DevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {}
+  LPC_USB->DevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
+}
+
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+static void bus_reset(void)
+{
+  // step 7 : slave mode set up
+  LPC_USB->EpIntClr     = 0xFFFFFFFF; // clear all pending interrupt
+  LPC_USB->DevIntClr    = 0xFFFFFFFF; // clear all pending interrupt
+  LPC_USB->EpIntEn      = 0x03UL;     // control endpoint cannot use DMA, non-control all use DMA
+  LPC_USB->EpIntPri     = 0x03UL;     // fast for control endpoint
+
+  // step 8 : DMA set up
+  LPC_USB->EpDMADis     = 0xFFFFFFFF; // firstly disable all dma
+  LPC_USB->DMARClr      = 0xFFFFFFFF; // clear all pending interrupt
+  LPC_USB->EoTIntClr    = 0xFFFFFFFF;
+  LPC_USB->NDDRIntClr   = 0xFFFFFFFF;
+  LPC_USB->SysErrIntClr = 0xFFFFFFFF;
+
+  tu_memclr(&_dcd, sizeof(dcd_data_t));
+}
+
+bool dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  //------------- user manual 11.13 usb device controller initialization -------------//
+  // step 6 : set up control endpoint
+  set_ep_size(0, CFG_TUD_ENDOINT0_SIZE);
+  set_ep_size(1, CFG_TUD_ENDOINT0_SIZE);
+
+  bus_reset();
+
+  LPC_USB->DevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_FAST_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
+  LPC_USB->UDCAH = (uint32_t) _dcd.udca;
+  LPC_USB->DMAIntEn = (DMA_INT_END_OF_XFER_MASK /*| DMA_INT_NEW_DD_REQUEST_MASK*/ | DMA_INT_ERROR_MASK);
+
+  sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);    // connect
+
+  // USB IRQ priority should be set by application previously
+  NVIC_ClearPendingIRQ(USB_IRQn);
+  NVIC_EnableIRQ(USB_IRQn);
+
+  return TUSB_ERROR_NONE;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  sie_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+  (void) rhport;
+  (void) config_num;
+  sie_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
+}
+
+//--------------------------------------------------------------------+
+// CONTROL HELPER
+//--------------------------------------------------------------------+
+static inline uint8_t byte2dword(uint8_t bytes)
+{
+  return (bytes + 3) / 4; // length in dwords
+}
+
+static void control_ep_write(void const * buffer, uint8_t len)
+{
+  uint32_t const * buf32 = (uint32_t const *) buffer;
+
+  LPC_USB->Ctrl   = USBCTRL_WRITE_ENABLE_MASK; // logical endpoint = 0
+  LPC_USB->TxPLen = (uint32_t) len;
+
+  for (uint8_t count = 0; count < byte2dword(len); count++)
+  {
+    LPC_USB->TxData = *buf32; // NOTE: cortex M3 have no problem with alignment
+    buf32++;
+  }
+
+  LPC_USB->Ctrl = 0;
+
+  // select control IN & validate the endpoint
+  sie_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0);
+  sie_write(SIE_CMDCODE_BUFFER_VALIDATE  , 0, 0);
+}
+
+static uint8_t control_ep_read(void * buffer, uint8_t len)
+{
+  LPC_USB->Ctrl = USBCTRL_READ_ENABLE_MASK; // logical endpoint = 0
+  while ((LPC_USB->RxPLen & USBRXPLEN_PACKET_READY_MASK) == 0) {} // TODO blocking, should have timeout
+
+  len = tu_min8(len, (uint8_t) (LPC_USB->RxPLen & USBRXPLEN_PACKET_LENGTH_MASK) );
+  uint32_t *buf32 = (uint32_t*) buffer;
+
+  for (uint8_t count=0; count < byte2dword(len); count++)
+  {
+    *buf32 = LPC_USB->RxData;
+    buf32++;
+  }
+
+  LPC_USB->Ctrl = 0;
+
+  // select control OUT & clear the endpoint
+  sie_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
+  sie_write(SIE_CMDCODE_BUFFER_CLEAR     , 0, 0);
+
+  return len;
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void) rhport;
+
+  uint8_t const epnum = edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_id = ep_addr2idx(p_endpoint_desc->bEndpointAddress);
+
+  // Endpoint type is fixed to endpoint number
+  // 1: interrupt, 2: Bulk, 3: Iso and so on
+  switch ( p_endpoint_desc->bmAttributes.xfer )
+  {
+    case TUSB_XFER_INTERRUPT:
+      TU_ASSERT((epnum % 3) == 1);
+      break;
+
+    case TUSB_XFER_BULK:
+      TU_ASSERT((epnum % 3) == 2 || (epnum == 15));
+      break;
+
+    case TUSB_XFER_ISOCHRONOUS:
+      TU_ASSERT((epnum % 3) == 3 && (epnum != 15));
+      break;
+
+    default:
+      break;
+  }
+
+  //------------- Realize Endpoint with Max Packet Size -------------//
+  set_ep_size(ep_id, p_endpoint_desc->wMaxPacketSize.size);
+
+  //------------- first DD prepare -------------//
+  dma_desc_t* const dd = &_dcd.dd[ep_id];
+  tu_memclr(dd, sizeof(dma_desc_t));
+
+  dd->isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
+  dd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size;
+  dd->retired = 1; // invalid at first
+
+  sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, 0);    // clear all endpoint status
+
+  return true;
+}
+
+bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t ep_id = ep_addr2idx( ep_addr );
+  return (_dcd.udca[ep_id] != NULL && !_dcd.udca[ep_id]->retired);
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  if ( edpt_number(ep_addr) == 0 )
+  {
+    sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
+  }else
+  {
+    uint8_t ep_id = ep_addr2idx( ep_addr );
+    sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, SIE_SET_ENDPOINT_STALLED_MASK);
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  uint8_t ep_id = ep_addr2idx(ep_addr);
+
+  sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, 0);
+}
+
+bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  uint8_t const ep_state = sie_read(SIE_CMDCODE_ENDPOINT_SELECT +  ep_addr2idx(ep_addr));
+  return (ep_state & SIE_SELECT_ENDPOINT_STALL_MASK) ? true : false;
+}
+
+static bool control_xact(uint8_t rhport, uint8_t dir, uint8_t * buffer, uint8_t len)
+{
+  (void) rhport;
+
+  if ( dir )
+  {
+    _dcd.control.in_bytes = len;
+    control_ep_write(buffer, len);
+  }else
+  {
+    if ( _dcd.control.out_received )
+    {
+      // Already received the DATA OUT packet
+      _dcd.control.out_received = false;
+      _dcd.control.out_buffer = NULL;
+      _dcd.control.out_bytes  = 0;
+
+      uint8_t received = control_ep_read(buffer, len);
+      dcd_event_xfer_complete(0, 0, received, XFER_RESULT_SUCCESS, true);
+    }else
+    {
+      _dcd.control.out_buffer = buffer;
+      _dcd.control.out_bytes  = len;
+    }
+  }
+
+  return true;
+}
+
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  // Control transfer is not DMA support, and must be done in slave mode
+  if ( edpt_number(ep_addr) == 0 )
+  {
+    return control_xact(rhport, edpt_dir(ep_addr), buffer, (uint8_t) total_bytes);
+  }
+  else
+  {
+    uint8_t ep_id = ep_addr2idx(ep_addr);
+    dma_desc_t* dd = &_dcd.dd[ep_id];
+
+    // Prepare DMA descriptor
+    // Isochronous & max packet size must be preserved, Other fields of dd should be clear
+    uint16_t const ep_size = dd->max_packet_size;
+    uint8_t  is_iso = dd->isochronous;
+
+    tu_memclr(dd, sizeof(dma_desc_t));
+    dd->isochronous = is_iso;
+    dd->max_packet_size = ep_size;
+    dd->buffer = (uint32_t) buffer;
+    dd->buflen = total_bytes;
+
+    _dcd.udca[ep_id] = dd;
+
+    if ( ep_id % 2 )
+    {
+      // Clear EP interrupt before Enable DMA
+      LPC_USB->EpIntEn &= ~BIT_(ep_id);
+      LPC_USB->EpDMAEn = BIT_(ep_id);
+
+      // endpoint IN need to actively raise DMA request
+      LPC_USB->DMARSet = BIT_(ep_id);
+    }else
+    {
+      // Enable DMA
+      LPC_USB->EpDMAEn = BIT_(ep_id);
+    }
+
+    return true;
+  }
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+
+// handle control xfer (slave mode)
+static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
+{
+  // Control out complete
+  if ( ep_int_status & BIT_(0) )
+  {
+    bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
+
+    LPC_USB->EpIntClr = BIT_(0);
+
+    if (is_setup)
+    {
+      uint8_t setup_packet[8];
+      control_ep_read(setup_packet, 8); // TODO read before clear setup above
+
+      dcd_event_setup_received(rhport, setup_packet, true);
+    }
+    else if ( _dcd.control.out_buffer )
+    {
+      // software queued transfer previously
+      uint8_t received = control_ep_read(_dcd.control.out_buffer, _dcd.control.out_bytes);
+
+      _dcd.control.out_buffer = NULL;
+      _dcd.control.out_bytes = 0;
+
+      dcd_event_xfer_complete(rhport, 0, received, XFER_RESULT_SUCCESS, true);
+    }else
+    {
+      // hardware auto ack packet -> mark as received
+      _dcd.control.out_received = true;
+    }
+  }
+
+  // Control In complete
+  if ( ep_int_status & BIT_(1) )
+  {
+    LPC_USB->EpIntClr = BIT_(1);
+    dcd_event_xfer_complete(rhport, TUSB_DIR_IN_MASK, _dcd.control.in_bytes, XFER_RESULT_SUCCESS, true);
+  }
+}
+
+// handle bus event signal
+static void bus_event_isr(uint8_t rhport)
+{
+  uint8_t const dev_status = sie_read(SIE_CMDCODE_DEVICE_STATUS);
+  if (dev_status & SIE_DEV_STATUS_RESET_MASK)
+  {
+    bus_reset();
+    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
+  }
+
+  if (dev_status & SIE_DEV_STATUS_CONNECT_CHANGE_MASK)
+  {
+    // device is disconnected, require using VBUS (P1_30)
+    dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+  }
+
+  if (dev_status & SIE_DEV_STATUS_SUSPEND_CHANGE_MASK)
+  {
+    if (dev_status & SIE_DEV_STATUS_SUSPEND_MASK)
+    {
+      dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
+    }
+    else
+    {
+      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+    }
+  }
+}
+
+// Helper to complete a DMA descriptor for non-control transfer
+static void dd_complete_isr(uint8_t rhport, uint8_t ep_id)
+{
+  dma_desc_t* const dd = &_dcd.dd[ep_id];
+  uint8_t result = (dd->status == DD_STATUS_NORMAL || dd->status == DD_STATUS_DATA_UNDERUN) ? XFER_RESULT_SUCCESS : XFER_RESULT_FAILED;
+  uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
+
+  dcd_event_xfer_complete(rhport, ep_addr, dd->present_count, result, true);
+}
+
+// main USB IRQ handler
+void hal_dcd_isr(uint8_t rhport)
+{
+  uint32_t const dev_int_status = LPC_USB->DevIntSt & LPC_USB->DevIntEn;
+  LPC_USB->DevIntClr = dev_int_status;// Acknowledge handled interrupt
+
+  // Bus event
+  if (dev_int_status & DEV_INT_DEVICE_STATUS_MASK)
+  {
+    bus_event_isr(rhport);
+  }
+
+  // Endpoint interrupt
+  uint32_t const ep_int_status = LPC_USB->EpIntSt & LPC_USB->EpIntEn;
+
+  // Control Endpoint are fast
+  if (dev_int_status & DEV_INT_ENDPOINT_FAST_MASK)
+  {
+    // Note clear USBEpIntClr will also clear the setup received bit --> clear after handle setup packet
+    // Only clear USBEpIntClr 1 endpoint each, and should wait for CDFULL bit set
+    control_xfer_isr(rhport, ep_int_status);
+  }
+
+  // non-control IN are slow
+  if (dev_int_status & DEV_INT_ENDPOINT_SLOW_MASK)
+  {
+    for ( uint8_t ep_id = 3; ep_id < DCD_ENDPOINT_MAX; ep_id += 2 )
+    {
+      if ( BIT_TEST_(ep_int_status, ep_id) )
+      {
+        LPC_USB->EpIntClr = BIT_(ep_id);
+
+        // Clear Ep interrupt for next DMA
+        LPC_USB->EpIntEn &= ~BIT_(ep_id);
+
+        dd_complete_isr(rhport, ep_id);
+      }
+    }
+  }
+
+  // DMA transfer complete (RAM <-> EP) for Non-Control
+  // OUT: USB transfer is fully complete
+  // IN : UBS transfer is still on-going -> enable EpIntEn to know when it is complete
+  uint32_t const dma_int_status = LPC_USB->DMAIntSt & LPC_USB->DMAIntEn;
+  if (dma_int_status & DMA_INT_END_OF_XFER_MASK)
+  {
+    uint32_t const eot = LPC_USB->EoTIntSt;
+    LPC_USB->EoTIntClr = eot; // acknowledge interrupt source
+
+    for ( uint8_t ep_id = 2; ep_id < DCD_ENDPOINT_MAX; ep_id++ )
+    {
+      if ( BIT_TEST_(eot, ep_id) )
+      {
+        if ( ep_id & 0x01 )
+        {
+          // IN enable EpInt for end of usb transfer
+          LPC_USB->EpIntEn |= BIT_(ep_id);
+        }else
+        {
+          // OUT
+          dd_complete_isr(rhport, ep_id);
+        }
+      }
+    }
+  }
+
+  // Errors
+  if ( (dev_int_status & DEV_INT_ERROR_MASK) || (dma_int_status & DMA_INT_ERROR_MASK) )
+  {
+    uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS);
+    (void) error_status;
+    TU_BREAKPOINT();
+  }
+}
+
+#endif
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
new file mode 100644
index 000000000..d6b76fcd1
--- /dev/null
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
@@ -0,0 +1,164 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc175x_6x.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#ifndef _TUSB_DCD_LPC175X_6X_H_
+#define _TUSB_DCD_LPC175X_6X_H_
+
+#include "common/tusb_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Register Interface
+//--------------------------------------------------------------------+
+
+//------------- USB Interrupt USBIntSt -------------//
+//enum {
+//  DCD_USB_REQ_LOW_PRIO_MASK   = BIT_(0),
+//  DCD_USB_REQ_HIGH_PRIO_MASK  = BIT_(1),
+//  DCD_USB_REQ_DMA_MASK        = BIT_(2),
+//  DCD_USB_REQ_NEED_CLOCK_MASK = BIT_(8),
+//  DCD_USB_REQ_ENABLE_MASK     = BIT_(31)
+//};
+
+//------------- Device Interrupt USBDevInt -------------//
+enum {
+  DEV_INT_FRAME_MASK              = BIT_(0),
+  DEV_INT_ENDPOINT_FAST_MASK      = BIT_(1),
+  DEV_INT_ENDPOINT_SLOW_MASK      = BIT_(2),
+  DEV_INT_DEVICE_STATUS_MASK      = BIT_(3),
+  DEV_INT_COMMAND_CODE_EMPTY_MASK = BIT_(4),
+  DEV_INT_COMMAND_DATA_FULL_MASK  = BIT_(5),
+  DEV_INT_RX_ENDPOINT_PACKET_MASK = BIT_(6),
+  DEV_INT_TX_ENDPOINT_PACKET_MASK = BIT_(7),
+  DEV_INT_ENDPOINT_REALIZED_MASK  = BIT_(8),
+  DEV_INT_ERROR_MASK              = BIT_(9)
+};
+
+//------------- DMA Interrupt USBDMAInt-------------//
+enum {
+  DMA_INT_END_OF_XFER_MASK    = BIT_(0),
+  DMA_INT_NEW_DD_REQUEST_MASK = BIT_(1),
+  DMA_INT_ERROR_MASK          = BIT_(2)
+};
+
+//------------- USBCtrl -------------//
+enum {
+  USBCTRL_READ_ENABLE_MASK  = BIT_(0),
+  USBCTRL_WRITE_ENABLE_MASK = BIT_(1),
+};
+
+//------------- USBRxPLen -------------//
+enum {
+  USBRXPLEN_PACKET_LENGTH_MASK = (BIT_(10)-1),
+  USBRXPLEN_DATA_VALID_MASK    = BIT_(10),
+  USBRXPLEN_PACKET_READY_MASK  = BIT_(11),
+};
+
+//------------- SIE Command Code -------------//
+typedef enum
+{
+  SIE_CMDPHASE_WRITE   = 1,
+  SIE_CMDPHASE_READ    = 2,
+  SIE_CMDPHASE_COMMAND = 5
+} sie_cmdphase_t;
+
+enum {
+  // device commands
+  SIE_CMDCODE_SET_ADDRESS                     = 0xd0,
+  SIE_CMDCODE_CONFIGURE_DEVICE                = 0xd8,
+  SIE_CMDCODE_SET_MODE                        = 0xf3,
+  SIE_CMDCODE_READ_FRAME_NUMBER               = 0xf5,
+  SIE_CMDCODE_READ_TEST_REGISTER              = 0xfd,
+  SIE_CMDCODE_DEVICE_STATUS                   = 0xfe,
+  SIE_CMDCODE_GET_ERROR                       = 0xff,
+  SIE_CMDCODE_READ_ERROR_STATUS               = 0xfb,
+
+  // endpoint commands
+  SIE_CMDCODE_ENDPOINT_SELECT                 = 0x00, // + endpoint index
+  SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT = 0x40, // + endpoint index, should use USBEpIntClr instead
+  SIE_CMDCODE_ENDPOINT_SET_STATUS             = 0x40, // + endpoint index
+  SIE_CMDCODE_BUFFER_CLEAR                    = 0xf2,
+  SIE_CMDCODE_BUFFER_VALIDATE                 = 0xfa
+};
+
+//------------- SIE Device Status (get/set from SIE_CMDCODE_DEVICE_STATUS) -------------//
+enum {
+  SIE_DEV_STATUS_CONNECT_STATUS_MASK = BIT_(0),
+  SIE_DEV_STATUS_CONNECT_CHANGE_MASK = BIT_(1),
+  SIE_DEV_STATUS_SUSPEND_MASK        = BIT_(2),
+  SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = BIT_(3),
+  SIE_DEV_STATUS_RESET_MASK          = BIT_(4)
+};
+
+//------------- SIE Select Endpoint Command -------------//
+enum {
+  SIE_SELECT_ENDPOINT_FULL_EMPTY_MASK         = BIT_(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full
+  SIE_SELECT_ENDPOINT_STALL_MASK              = BIT_(1),
+  SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK     = BIT_(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT
+  SIE_SELECT_ENDPOINT_PACKET_OVERWRITTEN_MASK = BIT_(3), // previous packet is overwritten by a SETUP packet
+  SIE_SELECT_ENDPOINT_NAK_MASK                = BIT_(4), // last packet response is NAK (auto clear by an ACK)
+  SIE_SELECT_ENDPOINT_BUFFER1_FULL_MASK       = BIT_(5),
+  SIE_SELECT_ENDPOINT_BUFFER2_FULL_MASK       = BIT_(6)
+};
+
+typedef enum
+{
+  SIE_SET_ENDPOINT_STALLED_MASK           = BIT_(0),
+  SIE_SET_ENDPOINT_DISABLED_MASK          = BIT_(5),
+  SIE_SET_ENDPOINT_RATE_FEEDBACK_MASK     = BIT_(6),
+  SIE_SET_ENDPOINT_CONDITION_STALLED_MASK = BIT_(7),
+}sie_endpoint_set_status_mask_t;
+
+//------------- DMA Descriptor Status -------------//
+enum {
+  DD_STATUS_NOT_SERVICED = 0,
+  DD_STATUS_BEING_SERVICED,
+  DD_STATUS_NORMAL,
+  DD_STATUS_DATA_UNDERUN, // short packet
+  DD_STATUS_DATA_OVERRUN,
+  DD_STATUS_SYSTEM_ERROR
+};
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_DCD_LPC175X_6X_H_ */
diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
new file mode 100644
index 000000000..668cabd80
--- /dev/null
+++ b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
@@ -0,0 +1,108 @@
+/**************************************************************************/
+/*!
+    @file     hal_lpc175x_6x.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "common/tusb_common.h"
+
+#if (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
+
+#include "chip.h"
+
+void tusb_hal_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+void tusb_hal_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_IRQn);
+}
+
+//--------------------------------------------------------------------+
+// IMPLEMENTATION
+//--------------------------------------------------------------------+
+bool tusb_hal_init(void)
+{
+  enum {
+    USBCLK_DEVCIE = 0x12,     // AHB + Device
+    USBCLK_HOST   = 0x19,     // AHB + Host + OTG (!)
+  };
+
+  Chip_USB_Init();
+
+  /* Configure P0.29 as D+, P0.30 as D- */
+  Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1);
+  Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
+
+#if MODE_HOST_SUPPORTED
+  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 22, .Funcnum = 2} ); // P1.22 as USB_PWRD
+  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 19, .Funcnum = 2} ); // P1.19 as USB_PPWR
+
+  // Enable host
+  LPC_USB->USBClkCtrl = USBCLK_HOST;
+  while ((LPC_USB->USBClkSt & USBCLK_HOST) != USBCLK_HOST);
+  LPC_USB->OTGStCtrl = 0x3;
+#endif
+
+#if TUSB_OPT_DEVICE_ENABLED
+  // P2_9 as USB Connect
+  Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1);
+
+  // Enable Device
+  LPC_USB->USBClkCtrl = USBCLK_DEVCIE;
+  while ((LPC_USB->USBClkSt & USBCLK_DEVCIE) != USBCLK_DEVCIE);
+#endif
+
+  return true;
+}
+
+void USB_IRQHandler(void)
+{
+  extern void hal_dcd_isr(uint8_t rhport);
+
+  #if MODE_HOST_SUPPORTED
+    hal_hcd_isr(0);
+  #endif
+
+  #if TUSB_OPT_DEVICE_ENABLED
+    hal_dcd_isr(0);
+  #endif
+}
+
+#endif
diff --git a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
deleted file mode 100644
index e94670a92..000000000
--- a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc175x_6x.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
-
-#include "device/dcd.h"
-#include "dcd_lpc175x_6x.h"
-#include "chip.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-#define DCD_ENDPOINT_MAX 32
-
-typedef struct ATTR_ALIGNED(4)
-{
-  //------------- Word 0 -------------//
-  uint32_t next;
-
-  //------------- Word 1 -------------//
-  uint16_t atle_mode       : 2; // 00: normal, 01: ATLE (auto length extraction)
-  uint16_t next_valid      : 1;
-  uint16_t                 : 1; ///< reserved
-  uint16_t isochronous     : 1; // is an iso endpoint
-  uint16_t max_packet_size : 11;
-
-  volatile uint16_t buflen; // bytes for non-iso, number of packets for iso endpoint
-
-  //------------- Word 2 -------------//
-  volatile uint32_t buffer;
-
-  //------------- Word 3 -------------//
-  volatile uint16_t retired                : 1; // initialized to zero
-  volatile uint16_t status                 : 4;
-  volatile uint16_t iso_last_packet_valid  : 1;
-  volatile uint16_t atle_lsb_extracted     : 1;	// used in ATLE mode
-  volatile uint16_t atle_msb_extracted     : 1;	// used in ATLE mode
-  volatile uint16_t atle_mess_len_position : 6; // used in ATLE mode
-  uint16_t                                 : 2;
-
-  volatile uint16_t present_count;  // For non-iso : The number of bytes transferred by the DMA engine
-                                    // For iso : number of packets
-
-  //------------- Word 4 -------------//
-  //	uint32_t iso_packet_size_addr;		// iso only, can be omitted for non-iso
-}dma_desc_t;
-
-TU_VERIFY_STATIC( sizeof(dma_desc_t) == 16, "size is not correct"); // TODO not support ISO for now
-
-typedef struct
-{
-  // must be 128 byte aligned
-  volatile dma_desc_t* udca[DCD_ENDPOINT_MAX];
-
-  // TODO DMA does not support control transfer (0-1 are not used, offset to reduce memory)
-  dma_desc_t dd[DCD_ENDPOINT_MAX];
-
-  struct
-  {
-    uint8_t* out_buffer;
-    uint8_t  out_bytes;
-    volatile bool out_received; // indicate if data is already received in endpoint
-
-    uint8_t  in_bytes;
-  } control;
-
-} dcd_data_t;
-
-ATTR_ALIGNED(128) static dcd_data_t _dcd;
-
-
-//--------------------------------------------------------------------+
-// SIE Command
-//--------------------------------------------------------------------+
-static void sie_cmd_code (sie_cmdphase_t phase, uint8_t code_data)
-{
-  LPC_USB->DevIntClr = (DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK);
-  LPC_USB->CmdCode   = (phase << 8) | (code_data << 16);
-
-  uint32_t const wait_flag = (phase == SIE_CMDPHASE_READ) ? DEV_INT_COMMAND_DATA_FULL_MASK : DEV_INT_COMMAND_CODE_EMPTY_MASK;
-  while ((LPC_USB->DevIntSt & wait_flag) == 0) {}
-
-  LPC_USB->DevIntClr = wait_flag;
-}
-
-static void sie_write (uint8_t cmd_code, uint8_t data_len, uint8_t data)
-{
-  sie_cmd_code(SIE_CMDPHASE_COMMAND, cmd_code);
-
-  if (data_len)
-  {
-    sie_cmd_code(SIE_CMDPHASE_WRITE, data);
-  }
-}
-
-static uint8_t sie_read (uint8_t cmd_code)
-{
-  sie_cmd_code(SIE_CMDPHASE_COMMAND , cmd_code);
-  sie_cmd_code(SIE_CMDPHASE_READ    , cmd_code);
-  return (uint8_t) LPC_USB->CmdData;
-}
-
-//--------------------------------------------------------------------+
-// PIPE HELPER
-//--------------------------------------------------------------------+
-static inline uint8_t ep_addr2idx(uint8_t ep_addr)
-{
-  return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
-}
-
-static void set_ep_size(uint8_t ep_id, uint16_t max_packet_size)
-{
-  // follows example in 11.10.4.2
-  LPC_USB->ReEp    |= BIT_(ep_id);
-  LPC_USB->EpInd    = ep_id; // select index before setting packet size
-  LPC_USB->MaxPSize = max_packet_size;
-
-  while ((LPC_USB->DevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) {}
-  LPC_USB->DevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK;
-}
-
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-static void bus_reset(void)
-{
-  // step 7 : slave mode set up
-  LPC_USB->EpIntClr     = 0xFFFFFFFF; // clear all pending interrupt
-  LPC_USB->DevIntClr    = 0xFFFFFFFF; // clear all pending interrupt
-  LPC_USB->EpIntEn      = 0x03UL;     // control endpoint cannot use DMA, non-control all use DMA
-  LPC_USB->EpIntPri     = 0x03UL;     // fast for control endpoint
-
-  // step 8 : DMA set up
-  LPC_USB->EpDMADis     = 0xFFFFFFFF; // firstly disable all dma
-  LPC_USB->DMARClr      = 0xFFFFFFFF; // clear all pending interrupt
-  LPC_USB->EoTIntClr    = 0xFFFFFFFF;
-  LPC_USB->NDDRIntClr   = 0xFFFFFFFF;
-  LPC_USB->SysErrIntClr = 0xFFFFFFFF;
-
-  tu_memclr(&_dcd, sizeof(dcd_data_t));
-}
-
-bool dcd_init(uint8_t rhport)
-{
-  (void) rhport;
-
-  //------------- user manual 11.13 usb device controller initialization -------------//
-  // step 6 : set up control endpoint
-  set_ep_size(0, CFG_TUD_ENDOINT0_SIZE);
-  set_ep_size(1, CFG_TUD_ENDOINT0_SIZE);
-
-  bus_reset();
-
-  LPC_USB->DevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_FAST_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK);
-  LPC_USB->UDCAH = (uint32_t) _dcd.udca;
-  LPC_USB->DMAIntEn = (DMA_INT_END_OF_XFER_MASK /*| DMA_INT_NEW_DD_REQUEST_MASK*/ | DMA_INT_ERROR_MASK);
-
-  sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);    // connect
-
-  // USB IRQ priority should be set by application previously
-  NVIC_ClearPendingIRQ(USB_IRQn);
-  NVIC_EnableIRQ(USB_IRQn);
-
-  return TUSB_ERROR_NONE;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-  sie_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-  (void) rhport;
-  (void) config_num;
-  sie_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1);
-}
-
-//--------------------------------------------------------------------+
-// CONTROL HELPER
-//--------------------------------------------------------------------+
-static inline uint8_t byte2dword(uint8_t bytes)
-{
-  return (bytes + 3) / 4; // length in dwords
-}
-
-static void control_ep_write(void const * buffer, uint8_t len)
-{
-  uint32_t const * buf32 = (uint32_t const *) buffer;
-
-  LPC_USB->Ctrl   = USBCTRL_WRITE_ENABLE_MASK; // logical endpoint = 0
-  LPC_USB->TxPLen = (uint32_t) len;
-
-  for (uint8_t count = 0; count < byte2dword(len); count++)
-  {
-    LPC_USB->TxData = *buf32; // NOTE: cortex M3 have no problem with alignment
-    buf32++;
-  }
-
-  LPC_USB->Ctrl = 0;
-
-  // select control IN & validate the endpoint
-  sie_write(SIE_CMDCODE_ENDPOINT_SELECT+1, 0, 0);
-  sie_write(SIE_CMDCODE_BUFFER_VALIDATE  , 0, 0);
-}
-
-static uint8_t control_ep_read(void * buffer, uint8_t len)
-{
-  LPC_USB->Ctrl = USBCTRL_READ_ENABLE_MASK; // logical endpoint = 0
-  while ((LPC_USB->RxPLen & USBRXPLEN_PACKET_READY_MASK) == 0) {} // TODO blocking, should have timeout
-
-  len = tu_min8(len, (uint8_t) (LPC_USB->RxPLen & USBRXPLEN_PACKET_LENGTH_MASK) );
-  uint32_t *buf32 = (uint32_t*) buffer;
-
-  for (uint8_t count=0; count < byte2dword(len); count++)
-  {
-    *buf32 = LPC_USB->RxData;
-    buf32++;
-  }
-
-  LPC_USB->Ctrl = 0;
-
-  // select control OUT & clear the endpoint
-  sie_write(SIE_CMDCODE_ENDPOINT_SELECT+0, 0, 0);
-  sie_write(SIE_CMDCODE_BUFFER_CLEAR     , 0, 0);
-
-  return len;
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  (void) rhport;
-
-  uint8_t const epnum = edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const ep_id = ep_addr2idx(p_endpoint_desc->bEndpointAddress);
-
-  // Endpoint type is fixed to endpoint number
-  // 1: interrupt, 2: Bulk, 3: Iso and so on
-  switch ( p_endpoint_desc->bmAttributes.xfer )
-  {
-    case TUSB_XFER_INTERRUPT:
-      TU_ASSERT((epnum % 3) == 1);
-      break;
-
-    case TUSB_XFER_BULK:
-      TU_ASSERT((epnum % 3) == 2 || (epnum == 15));
-      break;
-
-    case TUSB_XFER_ISOCHRONOUS:
-      TU_ASSERT((epnum % 3) == 3 && (epnum != 15));
-      break;
-
-    default:
-      break;
-  }
-
-  //------------- Realize Endpoint with Max Packet Size -------------//
-  set_ep_size(ep_id, p_endpoint_desc->wMaxPacketSize.size);
-
-  //------------- first DD prepare -------------//
-  dma_desc_t* const dd = &_dcd.dd[ep_id];
-  tu_memclr(dd, sizeof(dma_desc_t));
-
-  dd->isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
-  dd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size;
-  dd->retired = 1; // invalid at first
-
-  sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, 0);    // clear all endpoint status
-
-  return true;
-}
-
-bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  uint8_t ep_id = ep_addr2idx( ep_addr );
-  return (_dcd.udca[ep_id] != NULL && !_dcd.udca[ep_id]->retired);
-}
-
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  if ( edpt_number(ep_addr) == 0 )
-  {
-    sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK);
-  }else
-  {
-    uint8_t ep_id = ep_addr2idx( ep_addr );
-    sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, SIE_SET_ENDPOINT_STALLED_MASK);
-  }
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-  uint8_t ep_id = ep_addr2idx(ep_addr);
-
-  sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS+ep_id, 1, 0);
-}
-
-bool dcd_edpt_stalled (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  uint8_t const ep_state = sie_read(SIE_CMDCODE_ENDPOINT_SELECT +  ep_addr2idx(ep_addr));
-  return (ep_state & SIE_SELECT_ENDPOINT_STALL_MASK) ? true : false;
-}
-
-static bool control_xact(uint8_t rhport, uint8_t dir, uint8_t * buffer, uint8_t len)
-{
-  (void) rhport;
-
-  if ( dir )
-  {
-    _dcd.control.in_bytes = len;
-    control_ep_write(buffer, len);
-  }else
-  {
-    if ( _dcd.control.out_received )
-    {
-      // Already received the DATA OUT packet
-      _dcd.control.out_received = false;
-      _dcd.control.out_buffer = NULL;
-      _dcd.control.out_bytes  = 0;
-
-      uint8_t received = control_ep_read(buffer, len);
-      dcd_event_xfer_complete(0, 0, received, XFER_RESULT_SUCCESS, true);
-    }else
-    {
-      _dcd.control.out_buffer = buffer;
-      _dcd.control.out_bytes  = len;
-    }
-  }
-
-  return true;
-}
-
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
-  // Control transfer is not DMA support, and must be done in slave mode
-  if ( edpt_number(ep_addr) == 0 )
-  {
-    return control_xact(rhport, edpt_dir(ep_addr), buffer, (uint8_t) total_bytes);
-  }
-  else
-  {
-    uint8_t ep_id = ep_addr2idx(ep_addr);
-    dma_desc_t* dd = &_dcd.dd[ep_id];
-
-    // Prepare DMA descriptor
-    // Isochronous & max packet size must be preserved, Other fields of dd should be clear
-    uint16_t const ep_size = dd->max_packet_size;
-    uint8_t  is_iso = dd->isochronous;
-
-    tu_memclr(dd, sizeof(dma_desc_t));
-    dd->isochronous = is_iso;
-    dd->max_packet_size = ep_size;
-    dd->buffer = (uint32_t) buffer;
-    dd->buflen = total_bytes;
-
-    _dcd.udca[ep_id] = dd;
-
-    if ( ep_id % 2 )
-    {
-      // Clear EP interrupt before Enable DMA
-      LPC_USB->EpIntEn &= ~BIT_(ep_id);
-      LPC_USB->EpDMAEn = BIT_(ep_id);
-
-      // endpoint IN need to actively raise DMA request
-      LPC_USB->DMARSet = BIT_(ep_id);
-    }else
-    {
-      // Enable DMA
-      LPC_USB->EpDMAEn = BIT_(ep_id);
-    }
-
-    return true;
-  }
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-
-// handle control xfer (slave mode)
-static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status)
-{
-  // Control out complete
-  if ( ep_int_status & BIT_(0) )
-  {
-    bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT+0) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK;
-
-    LPC_USB->EpIntClr = BIT_(0);
-
-    if (is_setup)
-    {
-      uint8_t setup_packet[8];
-      control_ep_read(setup_packet, 8); // TODO read before clear setup above
-
-      dcd_event_setup_received(rhport, setup_packet, true);
-    }
-    else if ( _dcd.control.out_buffer )
-    {
-      // software queued transfer previously
-      uint8_t received = control_ep_read(_dcd.control.out_buffer, _dcd.control.out_bytes);
-
-      _dcd.control.out_buffer = NULL;
-      _dcd.control.out_bytes = 0;
-
-      dcd_event_xfer_complete(rhport, 0, received, XFER_RESULT_SUCCESS, true);
-    }else
-    {
-      // hardware auto ack packet -> mark as received
-      _dcd.control.out_received = true;
-    }
-  }
-
-  // Control In complete
-  if ( ep_int_status & BIT_(1) )
-  {
-    LPC_USB->EpIntClr = BIT_(1);
-    dcd_event_xfer_complete(rhport, TUSB_DIR_IN_MASK, _dcd.control.in_bytes, XFER_RESULT_SUCCESS, true);
-  }
-}
-
-// handle bus event signal
-static void bus_event_isr(uint8_t rhport)
-{
-  uint8_t const dev_status = sie_read(SIE_CMDCODE_DEVICE_STATUS);
-  if (dev_status & SIE_DEV_STATUS_RESET_MASK)
-  {
-    bus_reset();
-    dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true);
-  }
-
-  if (dev_status & SIE_DEV_STATUS_CONNECT_CHANGE_MASK)
-  {
-    // device is disconnected, require using VBUS (P1_30)
-    dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-  }
-
-  if (dev_status & SIE_DEV_STATUS_SUSPEND_CHANGE_MASK)
-  {
-    if (dev_status & SIE_DEV_STATUS_SUSPEND_MASK)
-    {
-      dcd_event_bus_signal(rhport, DCD_EVENT_SUSPENDED, true);
-    }
-    else
-    {
-      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-    }
-  }
-}
-
-// Helper to complete a DMA descriptor for non-control transfer
-static void dd_complete_isr(uint8_t rhport, uint8_t ep_id)
-{
-  dma_desc_t* const dd = &_dcd.dd[ep_id];
-  uint8_t result = (dd->status == DD_STATUS_NORMAL || dd->status == DD_STATUS_DATA_UNDERUN) ? XFER_RESULT_SUCCESS : XFER_RESULT_FAILED;
-  uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
-
-  dcd_event_xfer_complete(rhport, ep_addr, dd->present_count, result, true);
-}
-
-// main USB IRQ handler
-void hal_dcd_isr(uint8_t rhport)
-{
-  uint32_t const dev_int_status = LPC_USB->DevIntSt & LPC_USB->DevIntEn;
-  LPC_USB->DevIntClr = dev_int_status;// Acknowledge handled interrupt
-
-  // Bus event
-  if (dev_int_status & DEV_INT_DEVICE_STATUS_MASK)
-  {
-    bus_event_isr(rhport);
-  }
-
-  // Endpoint interrupt
-  uint32_t const ep_int_status = LPC_USB->EpIntSt & LPC_USB->EpIntEn;
-
-  // Control Endpoint are fast
-  if (dev_int_status & DEV_INT_ENDPOINT_FAST_MASK)
-  {
-    // Note clear USBEpIntClr will also clear the setup received bit --> clear after handle setup packet
-    // Only clear USBEpIntClr 1 endpoint each, and should wait for CDFULL bit set
-    control_xfer_isr(rhport, ep_int_status);
-  }
-
-  // non-control IN are slow
-  if (dev_int_status & DEV_INT_ENDPOINT_SLOW_MASK)
-  {
-    for ( uint8_t ep_id = 3; ep_id < DCD_ENDPOINT_MAX; ep_id += 2 )
-    {
-      if ( BIT_TEST_(ep_int_status, ep_id) )
-      {
-        LPC_USB->EpIntClr = BIT_(ep_id);
-
-        // Clear Ep interrupt for next DMA
-        LPC_USB->EpIntEn &= ~BIT_(ep_id);
-
-        dd_complete_isr(rhport, ep_id);
-      }
-    }
-  }
-
-  // DMA transfer complete (RAM <-> EP) for Non-Control
-  // OUT: USB transfer is fully complete
-  // IN : UBS transfer is still on-going -> enable EpIntEn to know when it is complete
-  uint32_t const dma_int_status = LPC_USB->DMAIntSt & LPC_USB->DMAIntEn;
-  if (dma_int_status & DMA_INT_END_OF_XFER_MASK)
-  {
-    uint32_t const eot = LPC_USB->EoTIntSt;
-    LPC_USB->EoTIntClr = eot; // acknowledge interrupt source
-
-    for ( uint8_t ep_id = 2; ep_id < DCD_ENDPOINT_MAX; ep_id++ )
-    {
-      if ( BIT_TEST_(eot, ep_id) )
-      {
-        if ( ep_id & 0x01 )
-        {
-          // IN enable EpInt for end of usb transfer
-          LPC_USB->EpIntEn |= BIT_(ep_id);
-        }else
-        {
-          // OUT
-          dd_complete_isr(rhport, ep_id);
-        }
-      }
-    }
-  }
-
-  // Errors
-  if ( (dev_int_status & DEV_INT_ERROR_MASK) || (dma_int_status & DMA_INT_ERROR_MASK) )
-  {
-    uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS);
-    (void) error_status;
-    TU_BREAKPOINT();
-  }
-}
-
-#endif
diff --git a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.h b/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.h
deleted file mode 100644
index d6b76fcd1..000000000
--- a/src/portable/nxp/lpc17xx/dcd_lpc175x_6x.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc175x_6x.h
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#ifndef _TUSB_DCD_LPC175X_6X_H_
-#define _TUSB_DCD_LPC175X_6X_H_
-
-#include "common/tusb_common.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// Register Interface
-//--------------------------------------------------------------------+
-
-//------------- USB Interrupt USBIntSt -------------//
-//enum {
-//  DCD_USB_REQ_LOW_PRIO_MASK   = BIT_(0),
-//  DCD_USB_REQ_HIGH_PRIO_MASK  = BIT_(1),
-//  DCD_USB_REQ_DMA_MASK        = BIT_(2),
-//  DCD_USB_REQ_NEED_CLOCK_MASK = BIT_(8),
-//  DCD_USB_REQ_ENABLE_MASK     = BIT_(31)
-//};
-
-//------------- Device Interrupt USBDevInt -------------//
-enum {
-  DEV_INT_FRAME_MASK              = BIT_(0),
-  DEV_INT_ENDPOINT_FAST_MASK      = BIT_(1),
-  DEV_INT_ENDPOINT_SLOW_MASK      = BIT_(2),
-  DEV_INT_DEVICE_STATUS_MASK      = BIT_(3),
-  DEV_INT_COMMAND_CODE_EMPTY_MASK = BIT_(4),
-  DEV_INT_COMMAND_DATA_FULL_MASK  = BIT_(5),
-  DEV_INT_RX_ENDPOINT_PACKET_MASK = BIT_(6),
-  DEV_INT_TX_ENDPOINT_PACKET_MASK = BIT_(7),
-  DEV_INT_ENDPOINT_REALIZED_MASK  = BIT_(8),
-  DEV_INT_ERROR_MASK              = BIT_(9)
-};
-
-//------------- DMA Interrupt USBDMAInt-------------//
-enum {
-  DMA_INT_END_OF_XFER_MASK    = BIT_(0),
-  DMA_INT_NEW_DD_REQUEST_MASK = BIT_(1),
-  DMA_INT_ERROR_MASK          = BIT_(2)
-};
-
-//------------- USBCtrl -------------//
-enum {
-  USBCTRL_READ_ENABLE_MASK  = BIT_(0),
-  USBCTRL_WRITE_ENABLE_MASK = BIT_(1),
-};
-
-//------------- USBRxPLen -------------//
-enum {
-  USBRXPLEN_PACKET_LENGTH_MASK = (BIT_(10)-1),
-  USBRXPLEN_DATA_VALID_MASK    = BIT_(10),
-  USBRXPLEN_PACKET_READY_MASK  = BIT_(11),
-};
-
-//------------- SIE Command Code -------------//
-typedef enum
-{
-  SIE_CMDPHASE_WRITE   = 1,
-  SIE_CMDPHASE_READ    = 2,
-  SIE_CMDPHASE_COMMAND = 5
-} sie_cmdphase_t;
-
-enum {
-  // device commands
-  SIE_CMDCODE_SET_ADDRESS                     = 0xd0,
-  SIE_CMDCODE_CONFIGURE_DEVICE                = 0xd8,
-  SIE_CMDCODE_SET_MODE                        = 0xf3,
-  SIE_CMDCODE_READ_FRAME_NUMBER               = 0xf5,
-  SIE_CMDCODE_READ_TEST_REGISTER              = 0xfd,
-  SIE_CMDCODE_DEVICE_STATUS                   = 0xfe,
-  SIE_CMDCODE_GET_ERROR                       = 0xff,
-  SIE_CMDCODE_READ_ERROR_STATUS               = 0xfb,
-
-  // endpoint commands
-  SIE_CMDCODE_ENDPOINT_SELECT                 = 0x00, // + endpoint index
-  SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT = 0x40, // + endpoint index, should use USBEpIntClr instead
-  SIE_CMDCODE_ENDPOINT_SET_STATUS             = 0x40, // + endpoint index
-  SIE_CMDCODE_BUFFER_CLEAR                    = 0xf2,
-  SIE_CMDCODE_BUFFER_VALIDATE                 = 0xfa
-};
-
-//------------- SIE Device Status (get/set from SIE_CMDCODE_DEVICE_STATUS) -------------//
-enum {
-  SIE_DEV_STATUS_CONNECT_STATUS_MASK = BIT_(0),
-  SIE_DEV_STATUS_CONNECT_CHANGE_MASK = BIT_(1),
-  SIE_DEV_STATUS_SUSPEND_MASK        = BIT_(2),
-  SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = BIT_(3),
-  SIE_DEV_STATUS_RESET_MASK          = BIT_(4)
-};
-
-//------------- SIE Select Endpoint Command -------------//
-enum {
-  SIE_SELECT_ENDPOINT_FULL_EMPTY_MASK         = BIT_(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full
-  SIE_SELECT_ENDPOINT_STALL_MASK              = BIT_(1),
-  SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK     = BIT_(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT
-  SIE_SELECT_ENDPOINT_PACKET_OVERWRITTEN_MASK = BIT_(3), // previous packet is overwritten by a SETUP packet
-  SIE_SELECT_ENDPOINT_NAK_MASK                = BIT_(4), // last packet response is NAK (auto clear by an ACK)
-  SIE_SELECT_ENDPOINT_BUFFER1_FULL_MASK       = BIT_(5),
-  SIE_SELECT_ENDPOINT_BUFFER2_FULL_MASK       = BIT_(6)
-};
-
-typedef enum
-{
-  SIE_SET_ENDPOINT_STALLED_MASK           = BIT_(0),
-  SIE_SET_ENDPOINT_DISABLED_MASK          = BIT_(5),
-  SIE_SET_ENDPOINT_RATE_FEEDBACK_MASK     = BIT_(6),
-  SIE_SET_ENDPOINT_CONDITION_STALLED_MASK = BIT_(7),
-}sie_endpoint_set_status_mask_t;
-
-//------------- DMA Descriptor Status -------------//
-enum {
-  DD_STATUS_NOT_SERVICED = 0,
-  DD_STATUS_BEING_SERVICED,
-  DD_STATUS_NORMAL,
-  DD_STATUS_DATA_UNDERUN, // short packet
-  DD_STATUS_DATA_OVERRUN,
-  DD_STATUS_SYSTEM_ERROR
-};
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_DCD_LPC175X_6X_H_ */
diff --git a/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c b/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
deleted file mode 100644
index bc61178d8..000000000
--- a/src/portable/nxp/lpc17xx/hal_lpc175x_6x.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_lpc175x_6x.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "common/tusb_common.h"
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X
-
-#include "chip.h"
-
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USB_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_IRQn);
-}
-
-//--------------------------------------------------------------------+
-// IMPLEMENTATION
-//--------------------------------------------------------------------+
-bool tusb_hal_init(void)
-{
-  enum {
-    USBCLK_DEVCIE = 0x12,     // AHB + Device
-    USBCLK_HOST   = 0x19,     // AHB + Host + OTG (!)
-  };
-
-  Chip_USB_Init();
-
-  /* Configure P0.29 as D+, P0.30 as D- */
-  Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1);
-  Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
-
-#if MODE_HOST_SUPPORTED
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 22, .Funcnum = 2} ); // P1.22 as USB_PWRD
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 19, .Funcnum = 2} ); // P1.19 as USB_PPWR
-
-  // Enable host
-  LPC_USB->USBClkCtrl = USBCLK_HOST;
-  while ((LPC_USB->USBClkSt & USBCLK_HOST) != USBCLK_HOST);
-  LPC_USB->OTGStCtrl = 0x3;
-#endif
-
-#if TUSB_OPT_DEVICE_ENABLED
-  // P2_9 as USB Connect
-  Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1);
-
-  // Enable Device
-  LPC_USB->USBClkCtrl = USBCLK_DEVCIE;
-  while ((LPC_USB->USBClkSt & USBCLK_DEVCIE) != USBCLK_DEVCIE);
-#endif
-
-  return true;
-}
-
-void USB_IRQHandler(void)
-{
-  extern void hal_dcd_isr(uint8_t rhport);
-
-  #if MODE_HOST_SUPPORTED
-    hal_hcd_isr(0);
-  #endif
-
-  #if TUSB_OPT_DEVICE_ENABLED
-    hal_dcd_isr(0);
-  #endif
-}
-
-#endif
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
index af1fa619c..8f5e3b457 100644
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
@@ -54,9 +54,14 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+
+#define QHD_MAX          12
+#define QTD_NEXT_INVALID 0x01
+
 typedef struct {
-  dcd_qhd_t qhd[DCD_QHD_MAX] ATTR_ALIGNED(64); ///< Must be at 2K alignment
-  dcd_qtd_t qtd[DCD_QTD_MAX] ATTR_ALIGNED(32);
+  // Must be at 2K alignment
+  dcd_qhd_t qhd[QHD_MAX] ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[QHD_MAX] ATTR_ALIGNED(32);
 }dcd_data_t;
 
 #if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
@@ -229,7 +234,6 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
-  // TODO USB1 only has 4 non-control enpoint (USB0 has 5)
   // TODO not support ISO yet
   TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
@@ -237,6 +241,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t const dir    = edpt_dir(p_endpoint_desc->bEndpointAddress);
   uint8_t const ep_idx = 2*epnum + dir;
 
+  // USB0 has 5, USB1 has 3 non-control endpoints
+  TU_ASSERT( epnum <= (rhport ? 3 : 5) );
+
   //------------- Prepare Queue Head -------------//
   dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
   tu_memclr(p_qhd, sizeof(dcd_qhd_t));
@@ -351,7 +358,7 @@ void hal_dcd_isr(uint8_t rhport)
 
     if ( edpt_complete )
     {
-      for(uint8_t ep_idx = 0; ep_idx < DCD_QHD_MAX; ep_idx++)
+      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
       {
         if ( BIT_TEST_(edpt_complete, ep_idx2bit(ep_idx)) )
         {
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h b/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
index cd54cae7c..faf0e3b0f 100644
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.h
@@ -52,10 +52,6 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-#define DCD_QHD_MAX 12
-#define DCD_QTD_MAX 12
-
-#define QTD_NEXT_INVALID 0x01
 
 /*---------- ENDPTCTRL ----------*/
 enum {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 1bcf6aa8d..d808a0518 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -53,8 +53,9 @@
 #define OPT_MCU_LPC13XX        3 ///< NXP LPC13xx
 #define OPT_MCU_LPC175X_6X     4 ///< NXP LPC175x, LPC176x
 #define OPT_MCU_LPC177X_8X     5 ///< NXP LPC177x, LPC178x
-#define OPT_MCU_LPC18XX        6 ///< NXP LPC18xx series
-#define OPT_MCU_LPC43XX        7 ///< NXP LPC43xx series
+#define OPT_MCU_LPC18XX        6 ///< NXP LPC18xx
+#define OPT_MCU_LPC40XX        7 ///< NXP LPC40xx
+#define OPT_MCU_LPC43XX        8 ///< NXP LPC43xx
 
 #define OPT_MCU_NRF5X        100 ///< Nordic nRF5x series
 
-- 
cgit v1.3.1


From 6c2404ca49772430585edda57c0b90064af02ab6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Dec 2018 16:32:20 +0700
Subject: adding ea4088 quickstart, able to blink

---
 .../device/cdc_msc_hid/ses/cdc_msc_hid.emProject   |     1 +
 .../cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s      |   128 +
 .../cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js      |    19 +
 .../ses/lpc40xx/LPC4088FBD208_MemoryMap.xml        |     6 +
 .../ses/lpc40xx/LPC408x_7x_Registers.xml           | 18992 +++++++++++++++++++
 .../cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s   |   458 +
 .../cdc_msc_hid/ses/lpc40xx/flash_placement.xml    |    37 +
 .../cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject      |   118 +
 .../device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s    |   415 +
 hw/bsp/board.h                                     |     2 +
 hw/bsp/ea4088qs/board_ea4088qs.c                   |   101 +-
 hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c       |     8 +-
 hw/bsp/mcb1800/board_mcb1800.c                     |     1 +
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c           |     2 +-
 14 files changed, 20280 insertions(+), 8 deletions(-)
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
 create mode 100644 examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
index 4da3d9d67..9d0672b8c 100644
--- a/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
+++ b/examples/device/cdc_msc_hid/ses/cdc_msc_hid.emProject
@@ -8,4 +8,5 @@
   <import file_name="lpc13xx/lpc13xx.emProject" />
   <import file_name="lpc11u6x/lpc11u6x.emProject" />
   <import file_name="lpc18xx/lpc18xx.emProject" />
+  <import file_name="lpc40xx/lpc40xx.emProject" />
 </solution>
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s
new file mode 100644
index 000000000..03bf54def
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Startup.s
@@ -0,0 +1,128 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                         Preprocessor Definitions                          *
+ *                         ------------------------                          *
+ * NO_FPU_ENABLE                                                             *
+ *                                                                           *
+ *   If defined, FPU will not be enabled.                                    *
+ *                                                                           *
+ * NO_STACK_INIT                                                             *
+ *                                                                           *
+ *   If defined, the stack pointer will not be initialised.                  *
+ *                                                                           *
+ * NO_SYSTEM_INIT                                                            *
+ *                                                                           *
+ *   If defined, the SystemInit() function will not be called. By default    *
+ *   SystemInit() is called after reset to enable the clocks and memories to *
+ *   be initialised prior to any C startup initialisation.                   *
+ *                                                                           *
+ * NO_VTOR_CONFIG                                                            *
+ *                                                                           *
+ *   If defined, the vector table offset register will not be configured.    *
+ *                                                                           *
+ * MEMORY_INIT                                                               *
+ *                                                                           *
+ *   If defined, the MemoryInit() function will be called. By default        *
+ *   MemoryInit() is called after SystemInit() to enable an external memory  *
+ *   controller.                                                             *
+ *                                                                           *
+ * STACK_INIT_VAL                                                            *
+ *                                                                           *
+ *   If defined, specifies the initial stack pointer value. If undefined,    *
+ *   the stack pointer will be initialised to point to the end of the        *
+ *   RAM segment.                                                            *
+ *                                                                           *
+ * VECTORS_IN_RAM                                                            *
+ *                                                                           *
+ *   If defined, the exception vectors will be copied from Flash to RAM.     *
+ *                                                                           *
+ *****************************************************************************/
+
+  .syntax unified
+
+  .global Reset_Handler
+  .extern _vectors
+
+  .section .init, "ax"
+  .thumb_func
+
+  .equ VTOR_REG, 0xE000ED08
+  .equ FPU_CPACR_REG, 0xE000ED88
+
+#ifndef STACK_INIT_VAL
+#define STACK_INIT_VAL __RAM_segment_end__
+#endif
+
+Reset_Handler:
+#ifndef NO_STACK_INIT
+  /* Initialise main stack */
+  ldr r0, =STACK_INIT_VAL
+  bic r0, #0x7
+  mov sp, r0
+#endif
+
+#ifndef NO_SYSTEM_INIT
+  /* Initialise system */
+  ldr r0, =SystemInit
+  blx r0
+  .pushsection .init_array, "aw", %init_array
+  .word SystemCoreClockUpdate
+  .popsection
+#endif
+
+#ifdef MEMORY_INIT
+  ldr r0, =MemoryInit
+  blx r0
+#endif
+
+#ifdef VECTORS_IN_RAM
+  /* Copy exception vectors into RAM */
+  ldr r0, =__vectors_start__
+  ldr r1, =__vectors_end__
+  ldr r2, =__vectors_ram_start__
+1:
+  cmp r0, r1
+  beq 2f
+  ldr r3, [r0]
+  str r3, [r2]
+  adds r0, r0, #4
+  adds r2, r2, #4
+  b 1b
+2:
+#endif
+
+#ifndef NO_VTOR_CONFIG
+  /* Configure vector table offset register */
+  ldr r0, =VTOR_REG
+#ifdef VECTORS_IN_RAM
+  ldr r1, =_vectors_ram
+#else
+  ldr r1, =_vectors
+#endif
+  str r1, [r0]
+#endif
+
+#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
+  /* Enable FPU */
+  ldr r0, =FPU_CPACR_REG
+  ldr r1, [r0]
+  orr r1, r1, #(0xF << 20)
+  str r1, [r0]
+  dsb
+  isb
+#endif
+
+  /* Jump to program start */
+  b _start
+
+
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js
new file mode 100644
index 000000000..20560af43
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4000_Target.js
@@ -0,0 +1,19 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+function Reset() {
+  TargetInterface.resetAndStop();
+}
+
+function EnableTrace(traceInterfaceType) {
+  // TODO: Enable trace
+}
+
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
new file mode 100644
index 000000000..9b8f2d9b4
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC4088FBD208_MemoryMap.xml
@@ -0,0 +1,6 @@
+<!DOCTYPE Board_Memory_Definition_File>
+<root name="LPC4088FBD208">
+  <MemorySegment name="FLASH" start="0x00000000" size="0x00080000" access="ReadOnly" />
+  <MemorySegment name="RAM" start="0x10000000" size="0x00010000" access="Read/Write" />
+  <MemorySegment name="RAM2" start="0x20000000" size="0x00008000" access="Read/Write" />
+</root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml
new file mode 100644
index 000000000..4a4c08179
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Registers.xml
@@ -0,0 +1,18992 @@
+<!DOCTYPE Register_Definition_File>
+<Processor name="LPC408x_7x" description="LPC408x/7x M4">
+  <RegisterGroup name="FLASHCTRL" start="0x00200000" description="EEPROM/flash">
+    <Register start="+0x020" size="4" name="FMSSTART" access="Read/Write" description="Signature start address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="START" description="Signature generation start address (corresponds to AHB byte address bits[20:4])." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x024" size="4" name="FMSSTOP" access="Read/Write" description="Signature stop-address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="STOP" description="BIST stop address divided by 16 (corresponds to AHB byte address [20:4])." />
+      <BitField start="17" size="1" name="SIG_START" description="Start control bit for signature generation.">
+        <Enum name="STOP" start="0" description="Signature generation is stopped" />
+        <Enum name="START" start="1" description="Initiate signature generation" />
+      </BitField>
+      <BitField start="18" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C" size="4" name="FMSW0" access="ReadOnly" description="128-bit signature Word 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW0_31_0" description="Word 0 of 128-bit signature (bits 31 to 0)." />
+    </Register>
+    <Register start="+0x030" size="4" name="FMSW1" access="ReadOnly" description="128-bit signature Word 1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW1_63_32" description="Word 1 of 128-bit signature (bits 63 to 32)." />
+    </Register>
+    <Register start="+0x034" size="4" name="FMSW2" access="ReadOnly" description="128-bit signature Word 2" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW2_95_64" description="Word 2 of 128-bit signature (bits 95 to 64)." />
+    </Register>
+    <Register start="+0x038" size="4" name="FMSW3" access="ReadOnly" description="128-bit signature Word 3" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="SW3_127_96" description="Word 3 of 128-bit signature (bits 127 to 96)." />
+    </Register>
+    <Register start="+0x080" size="4" name="EECMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CMD" description="Command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved" />
+      <BitField start="3" size="1" name="RDPREFETCH" description="Read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. When this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. The address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x084" size="4" name="EEADDR" access="Read/Write" description="EEPROM address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="ADDR" description="EEPROM Address.  Lower 6 bits are don't care." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x088" size="4" name="EEWDATA" access="WriteOnly" description="EEPROM write data register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="WDATA" description="Write data. In case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data." />
+    </Register>
+    <Register start="+0x08C" size="4" name="EERDATA" access="ReadOnly" description="EEPROM read data register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="RDATA" description="Read data. In case of: 8-bit read operations: bits [7:0] contain read data, others are zero. 16-bit read operations: bits [15:0] contain read data, others are zero. 32-bit read operations: bits [31:0] contain read data." />
+    </Register>
+    <Register start="+0x090" size="4" name="EEWSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PHASE3" description="Wait states 3 (minus 1 encoded). The number of system clock periods required to give a minimum time of 15 ns." />
+      <BitField start="8" size="8" name="PHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods required to give a minimum time of 55 ns." />
+      <BitField start="16" size="8" name="PHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods required to give a minimum time of 35 ns." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x094" size="4" name="EECLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x098" size="4" name="EEPWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0: not in power down mode. 1: power down mode (this will put all EEPROM devices in power down)." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="STAT" access="ReadOnly" description="Signature generation status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="SIG_DONE" description="When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag." />
+      <BitField start="3" size="23" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="26" size="1" name="END_OF_RDWR" description="EEPROM read/write operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written in the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="28" size="1" name="END_OF_PROG1" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when 1 is written to the corresponding bit of the EEINTSTATSET register. - cleared when 1 is written to the corresponding bit of the EEINTSTATCLR register." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="26" size="1" name="EE_RW_DONE" description="EEPROM read/write operation finished interrupt enable bit. Bit is: - set when 1 is written to the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="28" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when 1 is written in the corresponding bit of the EEINTENSET register. - cleared when 1 is written to the corresponding bit of the EEINTENCLR register." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="STATCLR" access="WriteOnly" description="Signature generation status clear register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="SIG_DONE_CLR" description="Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register." />
+      <BitField start="3" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="26" size="1" name="RDWR_CLR_ST" description="Clear read/write operation finished interrupt status bit (EEPROM). 0 leave corresponding bit unchanged. 1 clear corresponding bit." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="28" size="1" name="PROG1_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device 1. 0 leave corresponding bit unchanged. 1 clear corresponding bit." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="ENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="26" size="1" name="RDWR_CLR_EN" description="Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="28" size="1" name="PROG1_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="ENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="26" size="1" name="RDWR_SET_EN" description="Set read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: set corresponding bit." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="28" size="1" name="PROG1_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: set corresponding bit." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPDMA" start="0x20080000" description="General Purpose DMA controller Modification">
+    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled." />
+      <BitField start="1" size="1" name="M" description="AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="SRCADDR0" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="SRCADDR1" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+64" size="4" name="SRCADDR2" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+96" size="4" name="SRCADDR3" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+128" size="4" name="SRCADDR4" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+160" size="4" name="SRCADDR5" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+192" size="4" name="SRCADDR6" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+224" size="4" name="SRCADDR7" access="Read/Write" description="DMA Channel 0 Source Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x104+0" size="4" name="DESTADDR0" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+32" size="4" name="DESTADDR1" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+64" size="4" name="DESTADDR2" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+96" size="4" name="DESTADDR3" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+128" size="4" name="DESTADDR4" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+160" size="4" name="DESTADDR5" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+192" size="4" name="DESTADDR6" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+224" size="4" name="DESTADDR7" access="Read/Write" description="DMA Channel 0 Destination Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x108+0" size="4" name="LLI0" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+32" size="4" name="LLI1" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+64" size="4" name="LLI2" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+96" size="4" name="LLI3" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+128" size="4" name="LLI4" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+160" size="4" name="LLI5" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+192" size="4" name="LLI6" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+224" size="4" name="LLI7" access="Read/Write" description="DMA Channel 0 Linked List Item Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x10C+0" size="4" name="CONTROL0" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+32" size="4" name="CONTROL1" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+64" size="4" name="CONTROL2" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+96" size="4" name="CONTROL3" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+128" size="4" name="CONTROL4" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+160" size="4" name="CONTROL5" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+192" size="4" name="CONTROL6" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x10C+224" size="4" name="CONTROL7" access="Read/Write" description="DMA Channel 0 Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256" />
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved" />
+      <BitField start="24" size="2" name="RESERVED" description="Reserved, and must be written as 0." />
+      <BitField start="26" size="1" name="SI" description="Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer." />
+      <BitField start="27" size="1" name="DI" description="Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer." />
+      <BitField start="28" size="1" name="PROT1" description="This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode." />
+      <BitField start="29" size="1" name="PROT2" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable." />
+      <BitField start="30" size="1" name="PROT3" description="This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable." />
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled." />
+    </Register>
+    <Register start="+0x110+0" size="4" name="CONFIG0" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+32" size="4" name="CONFIG1" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+64" size="4" name="CONFIG2" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+96" size="4" name="CONFIG3" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+128" size="4" name="CONFIG4" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+160" size="4" name="CONFIG5" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+192" size="4" name="CONFIG6" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110+224" size="4" name="CONFIG7" access="Read/Write" description="DMA Channel 0 Configuration Register[1]" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared." />
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification." />
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification." />
+      <BitField start="11" size="3" name="TRANSFERTYPE" description="This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field." />
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ETHERNET" start="0x20084000" description="Ethernet">
+    <Register start="+0x000" size="4" name="MAC1" access="Read/Write" description="MAC configuration register 1." reset_value="0x8000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXENABLE" description="RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream." />
+      <BitField start="1" size="1" name="PARF" description="PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames." />
+      <BitField start="2" size="1" name="RXFLOWCTRL" description="RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored." />
+      <BitField start="3" size="1" name="TXFLOWCTRL" description="TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked." />
+      <BitField start="4" size="1" name="LOOPBACK" description="Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation." />
+      <BitField start="5" size="3" name="RESERVED" description="Unused" />
+      <BitField start="8" size="1" name="RESETTX" description="Setting this bit will put the Transmit Function logic in reset." />
+      <BitField start="9" size="1" name="RESETMCSTX" description="Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control." />
+      <BitField start="10" size="1" name="RESETRX" description="Setting this bit will put the Ethernet receive logic in reset." />
+      <BitField start="11" size="1" name="RESETMCSRX" description="Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control." />
+      <BitField start="12" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="1" name="SIMRESET" description="SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function." />
+      <BitField start="15" size="1" name="SOFTRESET" description="SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="MAC2" access="Read/Write" description="MAC configuration register 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FULLDUPLEX" description="When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode." />
+      <BitField start="1" size="1" name="FLC" description="FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame." />
+      <BitField start="2" size="1" name="HFEN" description="HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received." />
+      <BitField start="3" size="1" name="DELAYEDCRC" description="DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header." />
+      <BitField start="4" size="1" name="CRCEN" description="CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC." />
+      <BitField start="5" size="1" name="PADCRCEN" description="PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function." />
+      <BitField start="6" size="1" name="VLANPADEN" description="VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
+      <BitField start="7" size="1" name="AUTODETPADEN" description="AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared." />
+      <BitField start="8" size="1" name="PPENF" description="PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed." />
+      <BitField start="9" size="1" name="LPENF" description="LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard." />
+      <BitField start="10" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="12" size="1" name="NOBACKOFF" description="When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard." />
+      <BitField start="13" size="1" name="BP_NOBACKOFF" description="BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent." />
+      <BitField start="14" size="1" name="EXCESSDEFER" description="When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="IPGT" access="Read/Write" description="Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="BTOBINTEGAP" description="BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="IPGR" access="Read/Write" description="Non Back-to-Back Inter-Packet-Gap register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="NBTOBINTEGAP2" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode)." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="7" name="NBTOBINTEGAP1" description="NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)" />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="CLRT" access="Read/Write" description="Collision window / Retry register." reset_value="0x370F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RETRANSMAX" description="RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5." />
+      <BitField start="4" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="6" name="COLLWIN" description="COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="MAXF" access="Read/Write" description="Maximum Frame register." reset_value="0x0600" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MAXFLEN" description="MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x018" size="4" name="SUPP" access="Read/Write" description="PHY Support register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RESERVED" description="Unused" />
+      <BitField start="8" size="1" name="SPEED" description="This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected." />
+      <BitField start="9" size="23" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x01C" size="4" name="TEST" access="Read/Write" description="Test register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCPQ" description="SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time." />
+      <BitField start="1" size="1" name="TESTPAUSE" description="This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received." />
+      <BitField start="2" size="1" name="TESTBP" description="TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure." />
+      <BitField start="3" size="29" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x020" size="4" name="MCFG" access="Read/Write" description="MII Mgmt Configuration register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCANINC" description="SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY." />
+      <BitField start="1" size="1" name="SUPPPREAMBLE" description="SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble." />
+      <BitField start="2" size="4" name="CLOCKSEL" description="CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field." />
+      <BitField start="6" size="9" name="RESERVED" description="Unused" />
+      <BitField start="15" size="1" name="RESETMIIMGMT" description="RESET MII MGMT. This bit resets the MII Management hardware." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x024" size="4" name="MCMD" access="Read/Write" description="MII Mgmt Command register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="READ" description="This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data)." />
+      <BitField start="1" size="1" name="SCAN" description="This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example." />
+      <BitField start="2" size="30" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x028" size="4" name="MADR" access="Read/Write" description="MII Mgmt Address register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="REGADDR" description="REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed." />
+      <BitField start="5" size="3" name="RESERVED" description="Unused" />
+      <BitField start="8" size="5" name="PHYADDR" description="PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved)." />
+      <BitField start="13" size="19" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x02C" size="4" name="MWTD" access="WriteOnly" description="MII Mgmt Write Data register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="WRITEDATA" description="WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR)." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x030" size="4" name="MRDD" access="ReadOnly" description="MII Mgmt Read Data register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="READDATA" description="READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x034" size="4" name="MIND" access="ReadOnly" description="MII Mgmt Indicators register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="BUSY" description="When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle." />
+      <BitField start="1" size="1" name="SCANNING" description="When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress." />
+      <BitField start="2" size="1" name="NOTVALID" description="When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid." />
+      <BitField start="3" size="1" name="MIILINKFAIL" description="When 1 is returned - indicates that an MII Mgmt link fail has occurred." />
+      <BitField start="4" size="28" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x040" size="4" name="SA0" access="Read/Write" description="Station Address 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SADDR2" description="STATION ADDRESS, 2nd octet. This field holds the second octet of the station address." />
+      <BitField start="8" size="8" name="SADDR1" description="STATION ADDRESS, 1st octet. This field holds the first octet of the station address." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x044" size="4" name="SA1" access="Read/Write" description="Station Address 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SADDR4" description="STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address." />
+      <BitField start="8" size="8" name="SADDR3" description="STATION ADDRESS, 3rd octet. This field holds the third octet of the station address." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x048" size="4" name="SA2" access="Read/Write" description="Station Address 2 register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SADDR6" description="STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address." />
+      <BitField start="8" size="8" name="SADDR5" description="STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x100" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXENABLE" description="Enable receive." />
+      <BitField start="1" size="1" name="TXENABLE" description="Enable transmit." />
+      <BitField start="2" size="1" name="RESERVED" description="Unused" />
+      <BitField start="3" size="1" name="REGRESET" description="When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately." />
+      <BitField start="4" size="1" name="TXRESET" description="When a  1  is written, the transmit datapath is reset." />
+      <BitField start="5" size="1" name="RXRESET" description="When a  1  is written, the receive datapath is reset." />
+      <BitField start="6" size="1" name="PASSRUNTFRAME" description="When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out." />
+      <BitField start="7" size="1" name="PASSRXFILTER" description="When set to  1 , disables receive filtering i.e. all frames received are written to memory." />
+      <BitField start="8" size="1" name="TXFLOWCONTROL" description="Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex." />
+      <BitField start="9" size="1" name="RMII" description="When set to  1 , RMII mode is selected; if 0, MII mode is selected." />
+      <BitField start="10" size="1" name="FULLDUPLEX" description="When set to  1 , indicates full duplex operation." />
+      <BitField start="11" size="21" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x104" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXSTATUS" description="If 1, the receive channel is active. If 0, the receive channel is inactive." />
+      <BitField start="1" size="1" name="TXSTATUS" description="If 1, the transmit channel is active. If 0, the transmit channel is inactive." />
+      <BitField start="2" size="30" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x108" size="4" name="RXDESCRIPTOR" access="Read/Write" description="Receive descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
+      <BitField start="2" size="30" name="RXDESCRIPTOR" description="MSBs of receive descriptor base address." />
+    </Register>
+    <Register start="+0x10C" size="4" name="RXSTATUS" access="Read/Write" description="Receive status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Fixed to 000" />
+      <BitField start="3" size="29" name="RXSTATUS" description="MSBs of receive status base address." />
+    </Register>
+    <Register start="+0x110" size="4" name="RXDESCRIPTORNUMBER" access="Read/Write" description="Receive number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RXDESCRIPTORN" description="RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x114" size="4" name="RXPRODUCEINDEX" access="ReadOnly" description="Receive produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RXPRODUCEIX" description="Index of the descriptor that is going to be filled next by the receive datapath." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x118" size="4" name="RXCONSUMEINDEX" access="Read/Write" description="Receive consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RXCONSUMEIX" description="Index of the descriptor that is going to be processed next by the receive" />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x11C" size="4" name="TXDESCRIPTOR" access="Read/Write" description="Transmit descriptor base address register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
+      <BitField start="2" size="30" name="TXD" description="TxDescriptor. MSBs of transmit descriptor base address." />
+    </Register>
+    <Register start="+0x120" size="4" name="TXSTATUS" access="Read/Write" description="Transmit status base address register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Fixed to 00" />
+      <BitField start="2" size="30" name="TXSTAT" description="TxStatus. MSBs of transmit status base address." />
+    </Register>
+    <Register start="+0x124" size="4" name="TXDESCRIPTORNUMBER" access="Read/Write" description="Transmit number of descriptors register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXDN" description="TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x128" size="4" name="TXPRODUCEINDEX" access="Read/Write" description="Transmit produce index register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXPI" description="TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x12C" size="4" name="TXCONSUMEINDEX" access="ReadOnly" description="Transmit consume index register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXCI" description="TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x158" size="4" name="TSV0" access="ReadOnly" description="Transmit status vector 0 register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
+      <BitField start="1" size="1" name="LCE" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
+      <BitField start="2" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
+      <BitField start="3" size="1" name="DONE" description="Transmission of packet was completed." />
+      <BitField start="4" size="1" name="MULTICAST" description="Packet's destination was a multicast address." />
+      <BitField start="5" size="1" name="BROADCAST" description="Packet's destination was a broadcast address." />
+      <BitField start="6" size="1" name="PACKETDEFER" description="Packet was deferred for at least one attempt, but less than an excessive defer." />
+      <BitField start="7" size="1" name="EXDF" description="Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode." />
+      <BitField start="8" size="1" name="EXCOL" description="Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions." />
+      <BitField start="9" size="1" name="LCOL" description="Late Collision. Collision occurred beyond collision window, 512 bit times." />
+      <BitField start="10" size="1" name="GIANT" description="Byte count in frame was greater than can be represented in the transmit byte count field in TSV1." />
+      <BitField start="11" size="1" name="UNDERRUN" description="Host side caused buffer underrun." />
+      <BitField start="12" size="16" name="TOTALBYTES" description="The total number of bytes transferred including collided attempts." />
+      <BitField start="28" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
+      <BitField start="29" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
+      <BitField start="30" size="1" name="BACKPRESSURE" description="Carrier-sense method backpressure was previously applied." />
+      <BitField start="31" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
+    </Register>
+    <Register start="+0x15C" size="4" name="TSV1" access="ReadOnly" description="Transmit status vector 1 register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TBC" description="Transmit byte count. The total number of bytes in the frame, not counting the collided bytes." />
+      <BitField start="16" size="4" name="TCC" description="Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented." />
+      <BitField start="20" size="12" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x160" size="4" name="RSV" access="ReadOnly" description="Receive status vector register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RBC" description="Received byte count. Indicates length of received frame." />
+      <BitField start="16" size="1" name="PPI" description="Packet previously ignored. Indicates that a packet was dropped." />
+      <BitField start="17" size="1" name="RXDVSEEN" description="RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet." />
+      <BitField start="18" size="1" name="CESEEN" description="Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected." />
+      <BitField start="19" size="1" name="RCV" description="Receive code violation. Indicates that received PHY data does not represent a valid receive code." />
+      <BitField start="20" size="1" name="CRCERR" description="CRC error. The attached CRC in the packet did not match the internally generated CRC." />
+      <BitField start="21" size="1" name="LCERR" description="Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field." />
+      <BitField start="22" size="1" name="LOR" description="Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the &quot;Length out of range&quot; error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame." />
+      <BitField start="23" size="1" name="ROK" description="Receive OK. The packet had valid CRC and no symbol errors." />
+      <BitField start="24" size="1" name="MULTICAST" description="The packet destination was a multicast address." />
+      <BitField start="25" size="1" name="BROADCAST" description="The packet destination was a broadcast address." />
+      <BitField start="26" size="1" name="DRIBBLENIBBLE" description="Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out." />
+      <BitField start="27" size="1" name="CONTROLFRAME" description="The frame was a control frame." />
+      <BitField start="28" size="1" name="PAUSE" description="The frame was a control frame with a valid PAUSE opcode." />
+      <BitField start="29" size="1" name="UO" description="Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode." />
+      <BitField start="30" size="1" name="VLAN" description="Frame's length/type field contained 0x8100 which is the VLAN protocol identifier." />
+      <BitField start="31" size="1" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x170" size="4" name="FLOWCONTROLCOUNTER" access="Read/Write" description="Flow control counter register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MC" description="MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame." />
+      <BitField start="16" size="16" name="PT" description="PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles." />
+    </Register>
+    <Register start="+0x174" size="4" name="FLOWCONTROLSTATUS" access="ReadOnly" description="Flow control status register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MCC" description="MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register." />
+      <BitField start="16" size="16" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x200" size="4" name="RXFILTERCTRL" access="Read/Write" description="Receive filter control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AUE" description="AcceptUnicastEn. When set to 1, all unicast frames are accepted." />
+      <BitField start="1" size="1" name="ABE" description="AcceptBroadcastEn. When set to 1, all broadcast frames are accepted." />
+      <BitField start="2" size="1" name="AME" description="AcceptMulticastEn. When set to 1, all multicast frames are accepted." />
+      <BitField start="3" size="1" name="AUHE" description="AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted." />
+      <BitField start="4" size="1" name="AMHE" description="AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted." />
+      <BitField start="5" size="1" name="APE" description="AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted." />
+      <BitField start="6" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="12" size="1" name="MPEW" description="MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match." />
+      <BitField start="13" size="1" name="RFEW" description="RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match." />
+      <BitField start="14" size="18" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x204" size="4" name="RXFILTERWOLSTATUS" access="ReadOnly" description="Receive filter WoL status register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AUW" description="AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL." />
+      <BitField start="1" size="1" name="ABW" description="AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL." />
+      <BitField start="2" size="1" name="AMW" description="AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL." />
+      <BitField start="3" size="1" name="AUHW" description="AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL." />
+      <BitField start="4" size="1" name="AMHW" description="AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL." />
+      <BitField start="5" size="1" name="APW" description="AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL." />
+      <BitField start="6" size="1" name="RESERVED" description="Unused" />
+      <BitField start="7" size="1" name="RFW" description="RxFilterWoL. When the value is 1, the receive filter caused WoL." />
+      <BitField start="8" size="1" name="MPW" description="MagicPacketWoL. When the value is 1, the magic packet filter caused WoL." />
+      <BitField start="9" size="23" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x208" size="4" name="RXFILTERWOLCLEAR" access="WriteOnly" description="Receive filter WoL clear register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AUWCLR" description="AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="1" size="1" name="ABWCLR" description="AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="2" size="1" name="AMWCLR" description="AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="3" size="1" name="AUHWCLR" description="AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="4" size="1" name="AMHWCLR" description="AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="5" size="1" name="APWCLR" description="AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="6" size="1" name="RESERVED" description="Unused" />
+      <BitField start="7" size="1" name="RFWCLR" description="RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="8" size="1" name="MPWCLR" description="MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared." />
+      <BitField start="9" size="23" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0x210" size="4" name="HASHFILTERL" access="Read/Write" description="Hash filter table LSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HFL" description="HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering." />
+    </Register>
+    <Register start="+0x214" size="4" name="HASHFILTERH" access="Read/Write" description="Hash filter table MSBs register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HFH" description="Bits 63:32 of the imperfect filter hash table for receive filtering." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="INTSTATUS" access="ReadOnly" description="Interrupt status register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXOVERRUNINT" description="Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error." />
+      <BitField start="1" size="1" name="RXERRORINT" description="Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun." />
+      <BitField start="2" size="1" name="RXFINISHEDINT" description="Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
+      <BitField start="3" size="1" name="RXDONEINT" description="Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
+      <BitField start="4" size="1" name="TXUNDERRUNINT" description="Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error." />
+      <BitField start="5" size="1" name="TXERRORINT" description="Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun." />
+      <BitField start="6" size="1" name="TXFINISHEDINT" description="Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
+      <BitField start="7" size="1" name="TXDONEINT" description="Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
+      <BitField start="8" size="4" name="RESERVED" description="Unused" />
+      <BitField start="12" size="1" name="SOFTINT" description="Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register." />
+      <BitField start="13" size="1" name="WAKEUPINT" description="Interrupt triggered by a Wake-up event detected by the receive filter." />
+      <BitField start="14" size="18" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0xFE4" size="4" name="INTENABLE" access="Read/Write" description="Interrupt enable register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXOVERRUNINTEN" description="Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations." />
+      <BitField start="1" size="1" name="RXERRORINTEN" description="Enable for interrupt trigger on receive errors." />
+      <BitField start="2" size="1" name="RXFINISHEDINTEN" description="Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
+      <BitField start="3" size="1" name="RXDONEINTEN" description="Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set." />
+      <BitField start="4" size="1" name="TXUNDERRUNINTEN" description="Enable for interrupt trigger on transmit buffer or descriptor underrun situations." />
+      <BitField start="5" size="1" name="TXERRORINTEN" description="Enable for interrupt trigger on transmit errors." />
+      <BitField start="6" size="1" name="TXFINISHEDINTEN" description="Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex." />
+      <BitField start="7" size="1" name="TXDONEINTEN" description="Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set." />
+      <BitField start="8" size="4" name="RESERVED" description="Unused" />
+      <BitField start="12" size="1" name="SOFTINTEN" description="Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register." />
+      <BitField start="13" size="1" name="WAKEUPINTEN" description="Enable for interrupt triggered by a Wake-up event detected by the receive filter." />
+      <BitField start="14" size="18" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0xFE8" size="4" name="INTCLEAR" access="WriteOnly" description="Interrupt clear register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXOVERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="1" size="1" name="RXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="2" size="1" name="RXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="3" size="1" name="RXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="4" size="1" name="TXUNDERRUNINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="5" size="1" name="TXERRORINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="6" size="1" name="TXFINISHEDINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="7" size="1" name="TXDONEINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="8" size="4" name="RESERVED" description="Unused" />
+      <BitField start="12" size="1" name="SOFTINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="13" size="1" name="WAKEUPINTCLR" description="Writing a 1 clears the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="14" size="18" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0xFEC" size="4" name="INTSET" access="WriteOnly" description="Interrupt set register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXOVERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="1" size="1" name="RXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="2" size="1" name="RXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="3" size="1" name="RXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="4" size="1" name="TXUNDERRUNINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="5" size="1" name="TXERRORINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="6" size="1" name="TXFINISHEDINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="7" size="1" name="TXDONEINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="8" size="4" name="RESERVED" description="Unused" />
+      <BitField start="12" size="1" name="SOFTINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="13" size="1" name="WAKEUPINTSET" description="Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus." />
+      <BitField start="14" size="18" name="RESERVED" description="Unused" />
+    </Register>
+    <Register start="+0xFF4" size="4" name="POWERDOWN" access="Read/Write" description="Power-down register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="RESERVED" description="Unused" />
+      <BitField start="31" size="1" name="PD" description="PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LCD" start="0x20088000" description="LCD controller Modification ">
+    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
+      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
+      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
+      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
+    </Register>
+    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
+      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
+      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
+      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
+    </Register>
+    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the input clock, LCD_DCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCD_DCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16)." />
+      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LVD)." />
+      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal." />
+      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal. 0 = LCD_FP pin is active HIGH and inactive LOW. 1 = LCD_FP pin is active LOW and inactive HIGH." />
+      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal. 0 = LCD_LP pin is active HIGH and inactive LOW. 1 = LCD_LP pin is active LOW and inactive HIGH." />
+      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK." />
+      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state. 0 = LCD_ENAB_M output pin is active HIGH in TFT mode. 1 = LCD_ENAB_M output pin is active LOW in TFT mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the LCD_TIMH register for the LCD display to work correctly." />
+      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
+      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCD_DCLK. Program with the number of LCDCLK clock periods minus 1." />
+      <BitField start="7" size="9" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCD_LE disabled (held LOW). 1 = LCD_LE signal active." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
+    </Register>
+    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are low. 1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
+      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel. Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
+      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
+      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
+      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
+      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
+      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
+      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
+      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more information on the data format." />
+      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
+      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
+      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
+      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the LCD_CTRL register) is reached." />
+      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the LCD_INTMSK register is set." />
+      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set." />
+      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the VCompIM bit in the LCD_INTMSK register is set." />
+      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the LCD_INTMSK register is set." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set." />
+      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set." />
+      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set." />
+      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
+      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
+      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
+      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
+    </Register>
+    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRON" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
+      <BitField start="1" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRSIZE" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
+      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RED" description="Red color component" />
+      <BitField start="8" size="8" name="GREEN" description="Green color component" />
+      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RED" description="Red color component" />
+      <BitField start="8" size="8" name="GREEN" description="Green color component" />
+      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USB" start="0x2008C000" description=" USB device controller ">
+    <Register start="+0x100" size="4" name="INTST" access="ReadOnly" description="OTG Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TMR" description="Timer time-out." />
+      <BitField start="1" size="1" name="REMOVE_PU" description="Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor." />
+      <BitField start="2" size="1" name="HNP_FAILURE" description="HNP failed. This bit is set by hardware to indicate that the HNP switching has failed." />
+      <BitField start="3" size="1" name="HNP_SUCCESS" description="HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x104" size="4" name="INTEN" access="Read/Write" description="OTG Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TMR_EN" description="1 = enable the corresponding bit in the IntSt register." />
+      <BitField start="1" size="1" name="REMOVE_PU_EN" description="1 = enable the corresponding bit in the IntSt register." />
+      <BitField start="2" size="1" name="HNP_FAILURE_EN" description="1 = enable the corresponding bit in the IntSt register." />
+      <BitField start="3" size="1" name="HNP_SUCCES_EN" description="1 = enable the corresponding bit in the IntSt register." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x108" size="4" name="INTSET" access="WriteOnly" description="OTG Interrupt Set" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TMR_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
+      <BitField start="1" size="1" name="REMOVE_PU_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
+      <BitField start="2" size="1" name="HNP_FAILURE_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
+      <BitField start="3" size="1" name="HNP_SUCCES_SET" description="0 = no effect. 1 = set the corresponding bit in the IntSt register." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x10C" size="4" name="INCLR" access="WriteOnly" description="OTG Interrupt Clear" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TMR_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
+      <BitField start="1" size="1" name="REMOVE_PU_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
+      <BitField start="2" size="1" name="HNP_FAILURE_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
+      <BitField start="3" size="1" name="HNP_SUCCES_CLR" description="0 = no effect. 1 = clear the corresponding bit in the IntSt register." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110" size="4" name="PORTSEL" access="Read/Write" description="USB Port Select. The USBPortSel register is identical to the OTGStCtrl register (see Section 15.8.6). In device-only operations only bits 0 and 1 of this register are used to control the routing of USB pins to Port 1 or Port 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="PORTSEL" description="Selects which USB port the device controller signals are mapped to. Other values are reserved.">
+        <Enum name="PORTU1" start="0x0" description="The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1." />
+        <Enum name="PORTU2" start="0x3" description="The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2." />
+      </BitField>
+      <BitField start="2" size="2" name="TMR_SCALE" description="Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved" />
+      <BitField start="4" size="1" name="TMR_MODE" description="Timer mode selection. 0: monoshot 1: free running" />
+      <BitField start="5" size="1" name="TMR_EN" description="Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0." />
+      <BitField start="6" size="1" name="TMR_RST" description="Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="B_HNP_TRACK" description="Enable HNP tracking for B-device (peripheral), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
+      <BitField start="9" size="1" name="A_HNP_TRACK" description="Enable HNP tracking for A-device (host), see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
+      <BitField start="10" size="1" name="PU_REMOVED" description="When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 15.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set." />
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="16" name="TMR_CNT" description="Current timer count value." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x114" size="4" name="TMR" access="Read/Write" description="OTG Timer" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TIMEOUT_CNT" description="The TMR interrupt is set when TMR_CNT reaches this value." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x200" size="4" name="DEVINTST" access="ReadOnly" description="USB Device Interrupt Status" reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FRAME" description="The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers." />
+      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit." />
+      <BitField start="2" size="1" name="EP_SLOW" description="Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit." />
+      <BitField start="3" size="1" name="DEV_STAT" description="Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366." />
+      <BitField start="4" size="1" name="CCEMPTY" description="The command code register (USBCmdCode) is empty (New command can be written)." />
+      <BitField start="5" size="1" name="CDFULL" description="Command data register (USBCmdData) is full (Data can be read now)." />
+      <BitField start="6" size="1" name="RxENDPKT" description="The current packet in the endpoint buffer is transferred to the CPU." />
+      <BitField start="7" size="1" name="TxENDPKT" description="The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen)." />
+      <BitField start="8" size="1" name="EP_RLZED" description="Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed." />
+      <BitField start="9" size="1" name="ERR_INT" description="Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368" />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204" size="4" name="DEVINTEN" access="Read/Write" description="USB Device Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FRAMEEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="1" size="1" name="EP_FASTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="2" size="1" name="EP_SLOWEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="3" size="1" name="DEV_STATEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="4" size="1" name="CCEMPTYEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="5" size="1" name="CDFULLEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="6" size="1" name="RxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="7" size="1" name="TxENDPKTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="8" size="1" name="EP_RLZEDEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="9" size="1" name="ERR_INTEN" description="0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x208" size="4" name="DEVINTCLR" access="WriteOnly" description="USB Device Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FRAMECLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="1" size="1" name="EP_FASTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="2" size="1" name="EP_SLOWCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="3" size="1" name="DEV_STATCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="4" size="1" name="CCEMPTYCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="5" size="1" name="CDFULLCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="6" size="1" name="RxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="7" size="1" name="TxENDPKTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="8" size="1" name="EP_RLZEDCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="9" size="1" name="ERR_INTCLR" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x20C" size="4" name="DEVINTSET" access="WriteOnly" description="USB Device Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FRAMESET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="1" size="1" name="EP_FASTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="2" size="1" name="EP_SLOWSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="3" size="1" name="DEV_STATSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="4" size="1" name="CCEMPTYSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="5" size="1" name="CDFULLSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="6" size="1" name="RxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="7" size="1" name="TxENDPKTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="8" size="1" name="EP_RLZEDSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="9" size="1" name="ERR_INTSET" description="0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x22C" size="4" name="DEVINTPRI" access="WriteOnly" description="USB Device Interrupt Priority" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FRAME" description="Frame interrupt routing">
+        <Enum name="LP" start="0" description="FRAME interrupt is routed to USB_INT_REQ_LP." />
+        <Enum name="HP" start="1" description="FRAME interrupt is routed to USB_INT_REQ_HP." />
+      </BitField>
+      <BitField start="1" size="1" name="EP_FAST" description="Fast endpoint interrupt routing">
+        <Enum name="LP" start="0" description="EP_FAST interrupt is routed to USB_INT_REQ_LP." />
+        <Enum name="HP" start="1" description="EP_FAST interrupt is routed to USB_INT_REQ_HP." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x230" size="4" name="EPINTST" access="ReadOnly" description="USB Endpoint Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPST0" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="1" size="1" name="EPST1" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="2" size="1" name="EPST2" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="3" size="1" name="EPST3" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="4" size="1" name="EPST4" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="5" size="1" name="EPST5" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="6" size="1" name="EPST6" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="7" size="1" name="EPST7" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="8" size="1" name="EPST8" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="9" size="1" name="EPST9" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="10" size="1" name="EPST10" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="11" size="1" name="EPST11" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="12" size="1" name="EPST12" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="13" size="1" name="EPST13" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="14" size="1" name="EPST14" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="15" size="1" name="EPST15" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="16" size="1" name="EPST16" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="17" size="1" name="EPST17" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="18" size="1" name="EPST18" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="19" size="1" name="EPST19" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="20" size="1" name="EPST20" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="21" size="1" name="EPST21" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="22" size="1" name="EPST22" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="23" size="1" name="EPST23" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="24" size="1" name="EPST24" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="25" size="1" name="EPST25" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="26" size="1" name="EPST26" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="27" size="1" name="EPST27" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="28" size="1" name="EPST28" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="29" size="1" name="EPST29" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="30" size="1" name="EPST30" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+      <BitField start="31" size="1" name="EPST31" description="1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received." />
+    </Register>
+    <Register start="+0x234" size="4" name="EPINTEN" access="Read/Write" description="USB Endpoint Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPEN0" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="1" size="1" name="EPEN1" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="2" size="1" name="EPEN2" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="3" size="1" name="EPEN3" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="4" size="1" name="EPEN4" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="5" size="1" name="EPEN5" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="6" size="1" name="EPEN6" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="7" size="1" name="EPEN7" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="8" size="1" name="EPEN8" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="9" size="1" name="EPEN9" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="10" size="1" name="EPEN10" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="11" size="1" name="EPEN11" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="12" size="1" name="EPEN12" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="13" size="1" name="EPEN13" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="14" size="1" name="EPEN14" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="15" size="1" name="EPEN15" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="16" size="1" name="EPEN16" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="17" size="1" name="EPEN17" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="18" size="1" name="EPEN18" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="19" size="1" name="EPEN19" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="20" size="1" name="EPEN20" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="21" size="1" name="EPEN21" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="22" size="1" name="EPEN22" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="23" size="1" name="EPEN23" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="24" size="1" name="EPEN24" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="25" size="1" name="EPEN25" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="26" size="1" name="EPEN26" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="27" size="1" name="EPEN27" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="28" size="1" name="EPEN28" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="29" size="1" name="EPEN29" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="30" size="1" name="EPEN30" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+      <BitField start="31" size="1" name="EPEN31" description="0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint." />
+    </Register>
+    <Register start="+0x238" size="4" name="EPINTCLR" access="WriteOnly" description="USB Endpoint Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPCLR0" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="1" size="1" name="EPCLR1" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="2" size="1" name="EPCLR2" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="3" size="1" name="EPCLR3" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="4" size="1" name="EPCLR4" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="5" size="1" name="EPCLR5" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="6" size="1" name="EPCLR6" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="7" size="1" name="EPCLR7" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="8" size="1" name="EPCLR8" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="9" size="1" name="EPCLR9" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="10" size="1" name="EPCLR10" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="11" size="1" name="EPCLR11" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="12" size="1" name="EPCLR12" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="13" size="1" name="EPCLR13" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="14" size="1" name="EPCLR14" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="15" size="1" name="EPCLR15" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="16" size="1" name="EPCLR16" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="17" size="1" name="EPCLR17" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="18" size="1" name="EPCLR18" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="19" size="1" name="EPCLR19" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="20" size="1" name="EPCLR20" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="21" size="1" name="EPCLR21" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="22" size="1" name="EPCLR22" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="23" size="1" name="EPCLR23" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="24" size="1" name="EPCLR24" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="25" size="1" name="EPCLR25" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="26" size="1" name="EPCLR26" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="27" size="1" name="EPCLR27" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="28" size="1" name="EPCLR28" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="29" size="1" name="EPCLR29" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="30" size="1" name="EPCLR30" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+      <BitField start="31" size="1" name="EPCLR31" description="0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint." />
+    </Register>
+    <Register start="+0x23C" size="4" name="EPINTSET" access="WriteOnly" description="USB Endpoint Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPSET0" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="1" size="1" name="EPSET1" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="2" size="1" name="EPSET2" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="3" size="1" name="EPSET3" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="4" size="1" name="EPSET4" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="5" size="1" name="EPSET5" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="6" size="1" name="EPSET6" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="7" size="1" name="EPSET7" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="8" size="1" name="EPSET8" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="9" size="1" name="EPSET9" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="10" size="1" name="EPSET10" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="11" size="1" name="EPSET11" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="12" size="1" name="EPSET12" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="13" size="1" name="EPSET13" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="14" size="1" name="EPSET14" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="15" size="1" name="EPSET15" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="16" size="1" name="EPSET16" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="17" size="1" name="EPSET17" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="18" size="1" name="EPSET18" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="19" size="1" name="EPSET19" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="20" size="1" name="EPSET20" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="21" size="1" name="EPSET21" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="22" size="1" name="EPSET22" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="23" size="1" name="EPSET23" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="24" size="1" name="EPSET24" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="25" size="1" name="EPSET25" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="26" size="1" name="EPSET26" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="27" size="1" name="EPSET27" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="28" size="1" name="EPSET28" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="29" size="1" name="EPSET29" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="30" size="1" name="EPSET30" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+      <BitField start="31" size="1" name="EPSET31" description="0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt." />
+    </Register>
+    <Register start="+0x240" size="4" name="EPINTPRI" access="WriteOnly" description="USB Endpoint Priority" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPPRI0" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="1" size="1" name="EPPRI1" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="2" size="1" name="EPPRI2" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="3" size="1" name="EPPRI3" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="4" size="1" name="EPPRI4" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="5" size="1" name="EPPRI5" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="6" size="1" name="EPPRI6" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="7" size="1" name="EPPRI7" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="8" size="1" name="EPPRI8" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="9" size="1" name="EPPRI9" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="10" size="1" name="EPPRI10" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="11" size="1" name="EPPRI11" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="12" size="1" name="EPPRI12" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="13" size="1" name="EPPRI13" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="14" size="1" name="EPPRI14" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="15" size="1" name="EPPRI15" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="16" size="1" name="EPPRI16" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="17" size="1" name="EPPRI17" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="18" size="1" name="EPPRI18" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="19" size="1" name="EPPRI19" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="20" size="1" name="EPPRI20" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="21" size="1" name="EPPRI21" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="22" size="1" name="EPPRI22" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="23" size="1" name="EPPRI23" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="24" size="1" name="EPPRI24" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="25" size="1" name="EPPRI25" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="26" size="1" name="EPPRI26" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="27" size="1" name="EPPRI27" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="28" size="1" name="EPPRI28" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="29" size="1" name="EPPRI29" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="30" size="1" name="EPPRI30" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+      <BitField start="31" size="1" name="EPPRI31" description="0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt" />
+    </Register>
+    <Register start="+0x244" size="4" name="REEP" access="Read/Write" description="USB Realize Endpoint" reset_value="0x3" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPR0" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="1" size="1" name="EPR1" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="2" size="1" name="EPR2" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="3" size="1" name="EPR3" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="4" size="1" name="EPR4" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="5" size="1" name="EPR5" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="6" size="1" name="EPR6" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="7" size="1" name="EPR7" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="8" size="1" name="EPR8" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="9" size="1" name="EPR9" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="10" size="1" name="EPR10" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="11" size="1" name="EPR11" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="12" size="1" name="EPR12" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="13" size="1" name="EPR13" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="14" size="1" name="EPR14" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="15" size="1" name="EPR15" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="16" size="1" name="EPR16" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="17" size="1" name="EPR17" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="18" size="1" name="EPR18" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="19" size="1" name="EPR19" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="20" size="1" name="EPR20" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="21" size="1" name="EPR21" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="22" size="1" name="EPR22" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="23" size="1" name="EPR23" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="24" size="1" name="EPR24" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="25" size="1" name="EPR25" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="26" size="1" name="EPR26" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="27" size="1" name="EPR27" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="28" size="1" name="EPR28" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="29" size="1" name="EPR29" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="30" size="1" name="EPR30" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+      <BitField start="31" size="1" name="EPR31" description="0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized." />
+    </Register>
+    <Register start="+0x248" size="4" name="EPIN" access="WriteOnly" description="USB Endpoint Index" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="PHY_EP" description="Physical endpoint number (0-31)" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x24C" size="4" name="MAXPSIZE" access="Read/Write" description="USB MaxPacketSize" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="MPS" description="The maximum packet size value." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x218" size="4" name="RXDATA" access="ReadOnly" description="USB Receive Data" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RX_DATA" description="Data received." />
+    </Register>
+    <Register start="+220" size="4" name="RXPLEN" access="ReadOnly" description="USB Receive Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt." />
+      <BitField start="10" size="1" name="DV" description="Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.">
+        <Enum name="DATA_IS_INVALID_" start="0" description="Data is invalid." />
+        <Enum name="DATA_IS_VALID_" start="1" description="Data is valid." />
+      </BitField>
+      <BitField start="11" size="1" name="PKT_RDY" description="The PKT_LNGTH field is valid and the packet is ready for reading." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x21C" size="4" name="TXDATA" access="WriteOnly" description="USB Transmit Data" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TX_DATA" description="Transmit Data." />
+    </Register>
+    <Register start="+0x224" size="4" name="TXPLEN" access="WriteOnly" description="USB Transmit Packet Length" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="PKT_LNGTH" description="The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x228" size="4" name="CTRL" access="Read/Write" description="USB Control" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RD_EN" description="Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="WR_EN" description="Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="2" size="4" name="LOG_ENDPOINT" description="Logical Endpoint number." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x210" size="4" name="CMDCODE" access="WriteOnly" description="USB Command Code" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="8" name="CMD_PHASE" description="The command phase:">
+        <Enum name="READ" start="0x02" description="Read" />
+        <Enum name="WRITE" start="0x01" description="Write" />
+        <Enum name="COMMAND" start="0x05" description="Command" />
+      </BitField>
+      <BitField start="16" size="8" name="CMD_CODE_WDATA" description="This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA)." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x214" size="4" name="CMDDATA" access="ReadOnly" description="USB Command Data" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CMD_RDATA" description="Command Read Data." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x250" size="4" name="DMARST" access="ReadOnly" description="USB DMA Request Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0)." />
+      <BitField start="1" size="1" name="EPRST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0)." />
+      <BitField start="2" size="1" name="EPRST2" description="Endpoint xx (2 &lt;=  xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="3" size="1" name="EPRST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="4" size="1" name="EPRST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="5" size="1" name="EPRST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="6" size="1" name="EPRST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="7" size="1" name="EPRST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="8" size="1" name="EPRST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="9" size="1" name="EPRST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="10" size="1" name="EPRST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="11" size="1" name="EPRST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="12" size="1" name="EPRST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="13" size="1" name="EPRST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="14" size="1" name="EPRST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="15" size="1" name="EPRST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="16" size="1" name="EPRST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="17" size="1" name="EPRST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="18" size="1" name="EPRST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="19" size="1" name="EPRST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="20" size="1" name="EPRST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="21" size="1" name="EPRST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="22" size="1" name="EPRST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="23" size="1" name="EPRST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="24" size="1" name="EPRST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="25" size="1" name="EPRST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="26" size="1" name="EPRST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="27" size="1" name="EPRST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="28" size="1" name="EPRST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="29" size="1" name="EPRST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="30" size="1" name="EPRST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+      <BitField start="31" size="1" name="EPRST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx." />
+    </Register>
+    <Register start="+0x254" size="4" name="DMARCLR" access="WriteOnly" description="USB DMA Request Clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRCLR0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
+      <BitField start="1" size="1" name="EPRCLR1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
+      <BitField start="2" size="1" name="EPRCLR2" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="3" size="1" name="EPRCLR3" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="4" size="1" name="EPRCLR4" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="5" size="1" name="EPRCLR5" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="6" size="1" name="EPRCLR6" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="7" size="1" name="EPRCLR7" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="8" size="1" name="EPRCLR8" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="9" size="1" name="EPRCLR9" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="10" size="1" name="EPRCLR10" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="11" size="1" name="EPRCLR11" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="12" size="1" name="EPRCLR12" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="13" size="1" name="EPRCLR13" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="14" size="1" name="EPRCLR14" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="15" size="1" name="EPRCLR15" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="16" size="1" name="EPRCLR16" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="17" size="1" name="EPRCLR17" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="18" size="1" name="EPRCLR18" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="19" size="1" name="EPRCLR19" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="20" size="1" name="EPRCLR20" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="21" size="1" name="EPRCLR21" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="22" size="1" name="EPRCLR22" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="23" size="1" name="EPRCLR23" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="24" size="1" name="EPRCLR24" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="25" size="1" name="EPRCLR25" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="26" size="1" name="EPRCLR26" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="27" size="1" name="EPRCLR27" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="28" size="1" name="EPRCLR28" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="29" size="1" name="EPRCLR29" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="30" size="1" name="EPRCLR30" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+      <BitField start="31" size="1" name="EPRCLR31" description="Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt." />
+    </Register>
+    <Register start="+0x258" size="4" name="DMARSET" access="WriteOnly" description="USB DMA Request Set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRSET0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0)." />
+      <BitField start="1" size="1" name="EPRSET1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0)." />
+      <BitField start="2" size="1" name="EPRSET2" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="3" size="1" name="EPRSET3" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="4" size="1" name="EPRSET4" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="5" size="1" name="EPRSET5" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="6" size="1" name="EPRSET6" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="7" size="1" name="EPRSET7" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="8" size="1" name="EPRSET8" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="9" size="1" name="EPRSET9" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="10" size="1" name="EPRSET10" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="11" size="1" name="EPRSET11" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="12" size="1" name="EPRSET12" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="13" size="1" name="EPRSET13" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="14" size="1" name="EPRSET14" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="15" size="1" name="EPRSET15" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="16" size="1" name="EPRSET16" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="17" size="1" name="EPRSET17" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="18" size="1" name="EPRSET18" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="19" size="1" name="EPRSET19" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="20" size="1" name="EPRSET20" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="21" size="1" name="EPRSET21" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="22" size="1" name="EPRSET22" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="23" size="1" name="EPRSET23" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="24" size="1" name="EPRSET24" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="25" size="1" name="EPRSET25" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="26" size="1" name="EPRSET26" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="27" size="1" name="EPRSET27" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="28" size="1" name="EPRSET28" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="29" size="1" name="EPRSET29" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="30" size="1" name="EPRSET30" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+      <BitField start="31" size="1" name="EPRSET31" description="Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt." />
+    </Register>
+    <Register start="+0x280" size="4" name="UDCAH" access="Read/Write" description="USB UDCA Head" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries." />
+      <BitField start="7" size="25" name="UDCA_ADDR" description="Start address of the UDCA." />
+    </Register>
+    <Register start="+0x284" size="4" name="EPDMAST" access="ReadOnly" description="USB Endpoint DMA Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EP_DMA_ST0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0)." />
+      <BitField start="1" size="1" name="EP_DMA_ST1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
+      <BitField start="2" size="1" name="EP_DMA_ST2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="3" size="1" name="EP_DMA_ST3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="4" size="1" name="EP_DMA_ST4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="5" size="1" name="EP_DMA_ST5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="6" size="1" name="EP_DMA_ST6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="7" size="1" name="EP_DMA_ST7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="8" size="1" name="EP_DMA_ST8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="9" size="1" name="EP_DMA_ST9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="10" size="1" name="EP_DMA_ST10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="11" size="1" name="EP_DMA_ST11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="12" size="1" name="EP_DMA_ST12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="13" size="1" name="EP_DMA_ST13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="14" size="1" name="EP_DMA_ST14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="15" size="1" name="EP_DMA_ST15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="16" size="1" name="EP_DMA_ST16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="17" size="1" name="EP_DMA_ST17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="18" size="1" name="EP_DMA_ST18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="19" size="1" name="EP_DMA_ST19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="20" size="1" name="EP_DMA_ST20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="21" size="1" name="EP_DMA_ST21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="22" size="1" name="EP_DMA_ST22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="23" size="1" name="EP_DMA_ST23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="24" size="1" name="EP_DMA_ST24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="25" size="1" name="EP_DMA_ST25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="26" size="1" name="EP_DMA_ST26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="27" size="1" name="EP_DMA_ST27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="28" size="1" name="EP_DMA_ST28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="29" size="1" name="EP_DMA_ST29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="30" size="1" name="EP_DMA_ST30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+      <BitField start="31" size="1" name="EP_DMA_ST31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled." />
+    </Register>
+    <Register start="+0x288" size="4" name="EPDMAEN" access="WriteOnly" description="USB Endpoint DMA Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EP_DMA_EN0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0)." />
+      <BitField start="1" size="1" name="EP_DMA_EN1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0)." />
+      <BitField start="2" size="30" name="EP_DMA_EN" description="Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx." />
+    </Register>
+    <Register start="+0x28C" size="4" name="EPDMADIS" access="WriteOnly" description="USB Endpoint DMA Disable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EP_DMA_DIS0" description="Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0)." />
+      <BitField start="1" size="1" name="EP_DMA_DIS1" description="Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0)." />
+      <BitField start="2" size="1" name="EP_DMA_DIS2" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="3" size="1" name="EP_DMA_DIS3" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="4" size="1" name="EP_DMA_DIS4" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="5" size="1" name="EP_DMA_DIS5" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="6" size="1" name="EP_DMA_DIS6" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="7" size="1" name="EP_DMA_DIS7" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="8" size="1" name="EP_DMA_DIS8" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="9" size="1" name="EP_DMA_DIS9" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="10" size="1" name="EP_DMA_DIS10" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="11" size="1" name="EP_DMA_DIS11" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="12" size="1" name="EP_DMA_DIS12" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="13" size="1" name="EP_DMA_DIS13" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="14" size="1" name="EP_DMA_DIS14" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="15" size="1" name="EP_DMA_DIS15" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="16" size="1" name="EP_DMA_DIS16" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="17" size="1" name="EP_DMA_DIS17" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="18" size="1" name="EP_DMA_DIS18" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="19" size="1" name="EP_DMA_DIS19" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="20" size="1" name="EP_DMA_DIS20" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="21" size="1" name="EP_DMA_DIS21" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="22" size="1" name="EP_DMA_DIS22" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="23" size="1" name="EP_DMA_DIS23" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="24" size="1" name="EP_DMA_DIS24" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="25" size="1" name="EP_DMA_DIS25" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="26" size="1" name="EP_DMA_DIS26" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="27" size="1" name="EP_DMA_DIS27" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="28" size="1" name="EP_DMA_DIS28" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="29" size="1" name="EP_DMA_DIS29" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="30" size="1" name="EP_DMA_DIS30" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+      <BitField start="31" size="1" name="EP_DMA_DIS31" description="Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx." />
+    </Register>
+    <Register start="+0x290" size="4" name="DMAINTST" access="ReadOnly" description="USB DMA Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt bit.">
+        <Enum name="ALL_BITS_IN_THE_USBE" start="0" description="All bits in the USBEoTIntSt register are 0." />
+        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBEoTIntSt is set." />
+      </BitField>
+      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt bit.">
+        <Enum name="ALL_BITS_IN_THE_USBN" start="0" description="All bits in the USBNDDRIntSt register are 0." />
+        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBNDDRIntSt is set." />
+      </BitField>
+      <BitField start="2" size="1" name="ERR" description="System Error Interrupt bit.">
+        <Enum name="ALL_BITS_IN_THE_USBS" start="0" description="All bits in the USBSysErrIntSt register are 0." />
+        <Enum name="AT_LEAST_ONE_BIT_IN_" start="1" description="At least one bit in the USBSysErrIntSt is set." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x294" size="4" name="DMAINTEN" access="Read/Write" description="USB DMA Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EOT" description="End of Transfer Interrupt enable bit.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NDDR" description="New DD Request Interrupt enable bit.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="ERR" description="System Error Interrupt enable bit.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x2A0" size="4" name="EOTINTST" access="ReadOnly" description="USB End of Transfer Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPTXINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="1" size="1" name="EPTXINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="2" size="1" name="EPTXINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="3" size="1" name="EPTXINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="4" size="1" name="EPTXINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="5" size="1" name="EPTXINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="6" size="1" name="EPTXINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="7" size="1" name="EPTXINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="8" size="1" name="EPTXINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="9" size="1" name="EPTXINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="10" size="1" name="EPTXINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="11" size="1" name="EPTXINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="12" size="1" name="EPTXINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="13" size="1" name="EPTXINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="14" size="1" name="EPTXINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="15" size="1" name="EPTXINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="16" size="1" name="EPTXINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="17" size="1" name="EPTXINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="18" size="1" name="EPTXINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="19" size="1" name="EPTXINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="20" size="1" name="EPTXINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="21" size="1" name="EPTXINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="22" size="1" name="EPTXINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="23" size="1" name="EPTXINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="24" size="1" name="EPTXINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="25" size="1" name="EPTXINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="26" size="1" name="EPTXINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="27" size="1" name="EPTXINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="28" size="1" name="EPTXINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="29" size="1" name="EPTXINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="30" size="1" name="EPTXINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+      <BitField start="31" size="1" name="EPTXINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx." />
+    </Register>
+    <Register start="+0x2A4" size="4" name="EOTINTCLR" access="WriteOnly" description="USB End of Transfer Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPTXINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="1" size="1" name="EPTXINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="2" size="1" name="EPTXINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="3" size="1" name="EPTXINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="4" size="1" name="EPTXINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="5" size="1" name="EPTXINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="6" size="1" name="EPTXINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="7" size="1" name="EPTXINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="8" size="1" name="EPTXINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="9" size="1" name="EPTXINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="10" size="1" name="EPTXINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="11" size="1" name="EPTXINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="12" size="1" name="EPTXINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="13" size="1" name="EPTXINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="14" size="1" name="EPTXINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="15" size="1" name="EPTXINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="16" size="1" name="EPTXINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="17" size="1" name="EPTXINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="18" size="1" name="EPTXINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="19" size="1" name="EPTXINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="20" size="1" name="EPTXINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="21" size="1" name="EPTXINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="22" size="1" name="EPTXINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="23" size="1" name="EPTXINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="24" size="1" name="EPTXINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="25" size="1" name="EPTXINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="26" size="1" name="EPTXINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="27" size="1" name="EPTXINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="28" size="1" name="EPTXINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="29" size="1" name="EPTXINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="30" size="1" name="EPTXINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="31" size="1" name="EPTXINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+    </Register>
+    <Register start="+0x2A8" size="4" name="EOTINTSET" access="WriteOnly" description="USB End of Transfer Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPTXINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="1" size="1" name="EPTXINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="2" size="1" name="EPTXINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="3" size="1" name="EPTXINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="4" size="1" name="EPTXINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="5" size="1" name="EPTXINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="6" size="1" name="EPTXINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="7" size="1" name="EPTXINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="8" size="1" name="EPTXINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="9" size="1" name="EPTXINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="10" size="1" name="EPTXINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="11" size="1" name="EPTXINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="12" size="1" name="EPTXINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="13" size="1" name="EPTXINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="14" size="1" name="EPTXINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="15" size="1" name="EPTXINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="16" size="1" name="EPTXINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="17" size="1" name="EPTXINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="18" size="1" name="EPTXINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="19" size="1" name="EPTXINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="20" size="1" name="EPTXINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="21" size="1" name="EPTXINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="22" size="1" name="EPTXINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="23" size="1" name="EPTXINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="24" size="1" name="EPTXINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="25" size="1" name="EPTXINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="26" size="1" name="EPTXINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="27" size="1" name="EPTXINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="28" size="1" name="EPTXINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="29" size="1" name="EPTXINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="30" size="1" name="EPTXINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+      <BitField start="31" size="1" name="EPTXINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register." />
+    </Register>
+    <Register start="+0x2AC" size="4" name="NDDRINTST" access="ReadOnly" description="USB New DD Request Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPNDDINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="1" size="1" name="EPNDDINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="2" size="1" name="EPNDDINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="3" size="1" name="EPNDDINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="4" size="1" name="EPNDDINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="5" size="1" name="EPNDDINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="6" size="1" name="EPNDDINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="7" size="1" name="EPNDDINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="8" size="1" name="EPNDDINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="9" size="1" name="EPNDDINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="10" size="1" name="EPNDDINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="11" size="1" name="EPNDDINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="12" size="1" name="EPNDDINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="13" size="1" name="EPNDDINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="14" size="1" name="EPNDDINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="15" size="1" name="EPNDDINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="16" size="1" name="EPNDDINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="17" size="1" name="EPNDDINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="18" size="1" name="EPNDDINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="19" size="1" name="EPNDDINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="20" size="1" name="EPNDDINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="21" size="1" name="EPNDDINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="22" size="1" name="EPNDDINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="23" size="1" name="EPNDDINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="24" size="1" name="EPNDDINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="25" size="1" name="EPNDDINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="26" size="1" name="EPNDDINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="27" size="1" name="EPNDDINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="28" size="1" name="EPNDDINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="29" size="1" name="EPNDDINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="30" size="1" name="EPNDDINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+      <BitField start="31" size="1" name="EPNDDINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx." />
+    </Register>
+    <Register start="+0x2B0" size="4" name="NDDRINTCLR" access="WriteOnly" description="USB New DD Request Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPNDDINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="1" size="1" name="EPNDDINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="2" size="1" name="EPNDDINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="3" size="1" name="EPNDDINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="4" size="1" name="EPNDDINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="5" size="1" name="EPNDDINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="6" size="1" name="EPNDDINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="7" size="1" name="EPNDDINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="8" size="1" name="EPNDDINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="9" size="1" name="EPNDDINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="10" size="1" name="EPNDDINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="11" size="1" name="EPNDDINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="12" size="1" name="EPNDDINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="13" size="1" name="EPNDDINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="14" size="1" name="EPNDDINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="15" size="1" name="EPNDDINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="16" size="1" name="EPNDDINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="17" size="1" name="EPNDDINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="18" size="1" name="EPNDDINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="19" size="1" name="EPNDDINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="20" size="1" name="EPNDDINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="21" size="1" name="EPNDDINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="22" size="1" name="EPNDDINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="23" size="1" name="EPNDDINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="24" size="1" name="EPNDDINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="25" size="1" name="EPNDDINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="26" size="1" name="EPNDDINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="27" size="1" name="EPNDDINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="28" size="1" name="EPNDDINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="29" size="1" name="EPNDDINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="30" size="1" name="EPNDDINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="31" size="1" name="EPNDDINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+    </Register>
+    <Register start="+0x2B4" size="4" name="NDDRINTSET" access="WriteOnly" description="USB New DD Request Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPNDDINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="1" size="1" name="EPNDDINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="2" size="1" name="EPNDDINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="3" size="1" name="EPNDDINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="4" size="1" name="EPNDDINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="5" size="1" name="EPNDDINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="6" size="1" name="EPNDDINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="7" size="1" name="EPNDDINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="8" size="1" name="EPNDDINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="9" size="1" name="EPNDDINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="10" size="1" name="EPNDDINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="11" size="1" name="EPNDDINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="12" size="1" name="EPNDDINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="13" size="1" name="EPNDDINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="14" size="1" name="EPNDDINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="15" size="1" name="EPNDDINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="16" size="1" name="EPNDDINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="17" size="1" name="EPNDDINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="18" size="1" name="EPNDDINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="19" size="1" name="EPNDDINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="20" size="1" name="EPNDDINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="21" size="1" name="EPNDDINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="22" size="1" name="EPNDDINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="23" size="1" name="EPNDDINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="24" size="1" name="EPNDDINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="25" size="1" name="EPNDDINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="26" size="1" name="EPNDDINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="27" size="1" name="EPNDDINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="28" size="1" name="EPNDDINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="29" size="1" name="EPNDDINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="30" size="1" name="EPNDDINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+      <BitField start="31" size="1" name="EPNDDINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register." />
+    </Register>
+    <Register start="+0x2B8" size="4" name="SYSERRINTST" access="ReadOnly" description="USB System Error Interrupt Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPERRINTST0" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="1" size="1" name="EPERRINTST1" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="2" size="1" name="EPERRINTST2" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="3" size="1" name="EPERRINTST3" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="4" size="1" name="EPERRINTST4" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="5" size="1" name="EPERRINTST5" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="6" size="1" name="EPERRINTST6" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="7" size="1" name="EPERRINTST7" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="8" size="1" name="EPERRINTST8" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="9" size="1" name="EPERRINTST9" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="10" size="1" name="EPERRINTST10" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="11" size="1" name="EPERRINTST11" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="12" size="1" name="EPERRINTST12" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="13" size="1" name="EPERRINTST13" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="14" size="1" name="EPERRINTST14" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="15" size="1" name="EPERRINTST15" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="16" size="1" name="EPERRINTST16" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="17" size="1" name="EPERRINTST17" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="18" size="1" name="EPERRINTST18" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="19" size="1" name="EPERRINTST19" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="20" size="1" name="EPERRINTST20" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="21" size="1" name="EPERRINTST21" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="22" size="1" name="EPERRINTST22" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="23" size="1" name="EPERRINTST23" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="24" size="1" name="EPERRINTST24" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="25" size="1" name="EPERRINTST25" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="26" size="1" name="EPERRINTST26" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="27" size="1" name="EPERRINTST27" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="28" size="1" name="EPERRINTST28" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="29" size="1" name="EPERRINTST29" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="30" size="1" name="EPERRINTST30" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+      <BitField start="31" size="1" name="EPERRINTST31" description="Endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx." />
+    </Register>
+    <Register start="+0x2BC" size="4" name="SYSERRINTCLR" access="WriteOnly" description="USB System Error Interrupt Clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPERRINTCLR0" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="1" size="1" name="EPERRINTCLR1" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="2" size="1" name="EPERRINTCLR2" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="3" size="1" name="EPERRINTCLR3" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="4" size="1" name="EPERRINTCLR4" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="5" size="1" name="EPERRINTCLR5" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="6" size="1" name="EPERRINTCLR6" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="7" size="1" name="EPERRINTCLR7" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="8" size="1" name="EPERRINTCLR8" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="9" size="1" name="EPERRINTCLR9" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="10" size="1" name="EPERRINTCLR10" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="11" size="1" name="EPERRINTCLR11" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="12" size="1" name="EPERRINTCLR12" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="13" size="1" name="EPERRINTCLR13" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="14" size="1" name="EPERRINTCLR14" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="15" size="1" name="EPERRINTCLR15" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="16" size="1" name="EPERRINTCLR16" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="17" size="1" name="EPERRINTCLR17" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="18" size="1" name="EPERRINTCLR18" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="19" size="1" name="EPERRINTCLR19" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="20" size="1" name="EPERRINTCLR20" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="21" size="1" name="EPERRINTCLR21" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="22" size="1" name="EPERRINTCLR22" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="23" size="1" name="EPERRINTCLR23" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="24" size="1" name="EPERRINTCLR24" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="25" size="1" name="EPERRINTCLR25" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="26" size="1" name="EPERRINTCLR26" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="27" size="1" name="EPERRINTCLR27" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="28" size="1" name="EPERRINTCLR28" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="29" size="1" name="EPERRINTCLR29" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="30" size="1" name="EPERRINTCLR30" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="31" size="1" name="EPERRINTCLR31" description="Clear endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+    </Register>
+    <Register start="+0x2C0" size="4" name="SYSERRINTSET" access="WriteOnly" description="USB System Error Interrupt Set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPERRINTSET0" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="1" size="1" name="EPERRINTSET1" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="2" size="1" name="EPERRINTSET2" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="3" size="1" name="EPERRINTSET3" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="4" size="1" name="EPERRINTSET4" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="5" size="1" name="EPERRINTSET5" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="6" size="1" name="EPERRINTSET6" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="7" size="1" name="EPERRINTSET7" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="8" size="1" name="EPERRINTSET8" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="9" size="1" name="EPERRINTSET9" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="10" size="1" name="EPERRINTSET10" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="11" size="1" name="EPERRINTSET11" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="12" size="1" name="EPERRINTSET12" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="13" size="1" name="EPERRINTSET13" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="14" size="1" name="EPERRINTSET14" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="15" size="1" name="EPERRINTSET15" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="16" size="1" name="EPERRINTSET16" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="17" size="1" name="EPERRINTSET17" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="18" size="1" name="EPERRINTSET18" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="19" size="1" name="EPERRINTSET19" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="20" size="1" name="EPERRINTSET20" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="21" size="1" name="EPERRINTSET21" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="22" size="1" name="EPERRINTSET22" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="23" size="1" name="EPERRINTSET23" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="24" size="1" name="EPERRINTSET24" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="25" size="1" name="EPERRINTSET25" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="26" size="1" name="EPERRINTSET26" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="27" size="1" name="EPERRINTSET27" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="28" size="1" name="EPERRINTSET28" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="29" size="1" name="EPERRINTSET29" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="30" size="1" name="EPERRINTSET30" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+      <BitField start="31" size="1" name="EPERRINTSET31" description="Set endpoint xx (2 &lt;= xx  &lt;= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register." />
+    </Register>
+    <Register start="+0x300" size="4" name="I2C_RX" access="ReadOnly" description="I2C Receive" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RX_DATA" description="Receive data." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x300" size="4" name="I2C_TX" access="WriteOnly" description="I2C Transmit" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="TXDATA" description="Transmit data." />
+      <BitField start="8" size="1" name="START" description="When 1, issue a START condition before transmitting this byte." />
+      <BitField start="9" size="1" name="STOP" description="When 1, issue a STOP condition after transmitting this byte." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x304" size="4" name="I2C_STS" access="ReadOnly" description="I2C Status" reset_value="0x0A00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TDI" description="Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.">
+        <Enum name="TRANSACTION_HAS_NOT_" start="0" description="Transaction has not completed." />
+        <Enum name="TRANSACTION_COMPLETE" start="1" description="Transaction completed." />
+      </BitField>
+      <BitField start="1" size="1" name="AFI" description="Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.">
+        <Enum name="NO_ARBITRATION_FAILU" start="0" description="No arbitration failure on last transmission." />
+        <Enum name="ARBITRATION_FAILURE_" start="1" description="Arbitration failure occurred on last transmission." />
+      </BitField>
+      <BitField start="2" size="1" name="NAI" description="No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.">
+        <Enum name="LAST_TRANSMISSION_RE" start="0" description="Last transmission received an acknowledge." />
+        <Enum name="LAST_TRANSMISSION_DI" start="1" description="Last transmission did not receive an acknowledge." />
+      </BitField>
+      <BitField start="3" size="1" name="DRMI" description="Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.">
+        <Enum name="MASTER_TRANSMITTER_D" start="0" description="Master transmitter does not need data." />
+        <Enum name="MASTER_TRANSMITTER_N" start="1" description="Master transmitter needs data." />
+      </BitField>
+      <BitField start="4" size="1" name="DRSI" description="Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.">
+        <Enum name="SLAVE_TRANSMITTER_DO" start="0" description="Slave transmitter does not need data." />
+        <Enum name="SLAVE_TRANSMITTER_NE" start="1" description="Slave transmitter needs data." />
+      </BitField>
+      <BitField start="5" size="1" name="Active" description="Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen.." />
+      <BitField start="6" size="1" name="SCL" description="The current value of the SCL signal." />
+      <BitField start="7" size="1" name="SDA" description="The current value of the SDA signal." />
+      <BitField start="8" size="1" name="RFF" description="Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.">
+        <Enum name="RX_FIFO_IS_NOT_FULL" start="0" description="RX FIFO is not full" />
+        <Enum name="RX_FIFO_IS_FULL" start="1" description="RX FIFO is full" />
+      </BitField>
+      <BitField start="9" size="1" name="RFE" description="Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.">
+        <Enum name="RX_FIFO_CONTAINS_DAT" start="0" description="RX FIFO contains data." />
+        <Enum name="RX_FIFO_IS_EMPTY" start="1" description="RX FIFO is empty" />
+      </BitField>
+      <BitField start="10" size="1" name="TFF" description="Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.">
+        <Enum name="TX_FIFO_IS_NOT_FULL_" start="0" description="TX FIFO is not full." />
+        <Enum name="TX_FIFO_IS_FULL" start="1" description="TX FIFO is full" />
+      </BitField>
+      <BitField start="11" size="1" name="TFE" description="Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.">
+        <Enum name="TX_FIFO_CONTAINS_VAL" start="0" description="TX FIFO contains valid data." />
+        <Enum name="TX_FIFO_IS_EMPTY" start="1" description="TX FIFO is empty" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x308" size="4" name="I2C_CTL" access="Read/Write" description="I2C Control" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TDIE" description="Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.">
+        <Enum name="DISABLE_THE_TDI_INTE" start="0" description="Disable the TDI interrupt." />
+        <Enum name="ENABLE_THE_TDI_INTER" start="1" description="Enable the TDI interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="AFIE" description="Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.">
+        <Enum name="DISABLE_THE_AFI_" start="0" description="Disable the AFI." />
+        <Enum name="ENABLE_THE_AFI_" start="1" description="Enable the AFI." />
+      </BitField>
+      <BitField start="2" size="1" name="NAIE" description="Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.">
+        <Enum name="DISABLE_THE_NAI_" start="0" description="Disable the NAI." />
+        <Enum name="ENABLE_THE_NAI_" start="1" description="Enable the NAI." />
+      </BitField>
+      <BitField start="3" size="1" name="DRMIE" description="Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.">
+        <Enum name="DISABLE_THE_DRMI_INT" start="0" description="Disable the DRMI interrupt." />
+        <Enum name="ENABLE_THE_DRMI_INTE" start="1" description="Enable the DRMI interrupt." />
+      </BitField>
+      <BitField start="4" size="1" name="DRSIE" description="Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.">
+        <Enum name="DISABLE_THE_DRSI_INT" start="0" description="Disable the DRSI interrupt." />
+        <Enum name="ENABLE_THE_DRSI_INTE" start="1" description="Enable the DRSI interrupt." />
+      </BitField>
+      <BitField start="5" size="1" name="REFIE" description="Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.">
+        <Enum name="DISABLE_THE_RFFI_" start="0" description="Disable the RFFI." />
+        <Enum name="ENABLE_THE_RFFI_" start="1" description="Enable the RFFI." />
+      </BitField>
+      <BitField start="6" size="1" name="RFDAIE" description="Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).">
+        <Enum name="DISABLE_THE_DAI_" start="0" description="Disable the DAI." />
+        <Enum name="ENABLE_THE_DAI_" start="1" description="Enable the DAI." />
+      </BitField>
+      <BitField start="7" size="1" name="TFFIE" description="Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.">
+        <Enum name="DISABLE_THE_TFFI_" start="0" description="Disable the TFFI." />
+        <Enum name="ENABLE_THE_TFFI_" start="1" description="Enable the TFFI." />
+      </BitField>
+      <BitField start="8" size="1" name="SRST" description="Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.">
+        <Enum name="SEE_THE_TEXT_" start="0" description="See the text." />
+        <Enum name="RESET_THE_I2C_TO_IDL" start="1" description="Reset the I2C to idle state. Self clearing." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x30C" size="4" name="I2C_CLKHI" access="Read/Write" description="I2C Clock High" reset_value="0xB9" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CDHI" description="Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x310" size="4" name="I2C_CLKLO" access="WriteOnly" description="I2C Clock Low" reset_value="0xB9" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CDLO" description="Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFF4" size="4" name="CLKCTRL" access="Read/Write" description="OTG clock controller" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="HOST_CLK_EN" description="Host clock enable">
+        <Enum name="DISABLE_THE_HOST_CLO" start="0" description="Disable the Host clock." />
+        <Enum name="ENABLE_THE_HOST_CLOC" start="1" description="Enable the Host clock." />
+      </BitField>
+      <BitField start="1" size="1" name="DEV_CLK_EN" description="Device clock enable">
+        <Enum name="DISABLE_THE_DEVICE_C" start="0" description="Disable the Device clock." />
+        <Enum name="ENABLE_THE_DEVICE_CL" start="1" description="Enable the Device clock." />
+      </BitField>
+      <BitField start="2" size="1" name="I2C_CLK_EN" description="I2C clock enable">
+        <Enum name="DISABLE_THE_I2C_CLOC" start="0" description="Disable the I2C clock." />
+        <Enum name="ENABLE_THE_I2C_CLOCK" start="1" description="Enable the I2C clock." />
+      </BitField>
+      <BitField start="3" size="1" name="OTG_CLK_EN" description="OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.">
+        <Enum name="DISABLE_THE_OTG_CLOC" start="0" description="Disable the OTG clock." />
+        <Enum name="ENABLE_THE_OTG_CLOCK" start="1" description="Enable the OTG clock." />
+      </BitField>
+      <BitField start="4" size="1" name="AHB_CLK_EN" description="AHB master clock enable">
+        <Enum name="DISABLE_THE_AHB_CLOC" start="0" description="Disable the AHB clock." />
+        <Enum name="ENABLE_THE_AHB_CLOCK" start="1" description="Enable the AHB clock." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFF8" size="4" name="OTGClkSt" access="ReadOnly" description="OTG clock status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="HOST_CLK_ON" description="Host clock status.">
+        <Enum name="HOST_CLOCK_IS_NOT_AV" start="0" description="Host clock is not available." />
+        <Enum name="HOST_CLOCK_IS_AVAILA" start="1" description="Host clock is available." />
+      </BitField>
+      <BitField start="1" size="1" name="DEV_CLK_ON" description="Device clock status.">
+        <Enum name="DEVICE_CLOCK_IS_NOT_" start="0" description="Device clock is not available." />
+        <Enum name="DEVICE_CLOCK_IS_AVAI" start="1" description="Device clock is available." />
+      </BitField>
+      <BitField start="2" size="1" name="I2C_CLK_ON" description="I2C clock status.">
+        <Enum name="I2C_CLOCK_IS_NOT_AVA" start="0" description="I2C clock is not available." />
+        <Enum name="I2C_CLOCK_IS_AVAILAB" start="1" description="I2C clock is available." />
+      </BitField>
+      <BitField start="3" size="1" name="OTG_CLK_ON" description="OTG clock status.">
+        <Enum name="OTG_CLOCK_IS_NOT_AVA" start="0" description="OTG clock is not available." />
+        <Enum name="OTG_CLOCK_IS_AVAILAB" start="1" description="OTG clock is available." />
+      </BitField>
+      <BitField start="4" size="1" name="AHB_CLK_ON" description="AHB master clock status.">
+        <Enum name="AHB_CLOCK_IS_NOT_AVA" start="0" description="AHB clock is not available." />
+        <Enum name="AHB_CLOCK_IS_AVAILAB" start="1" description="AHB clock is available." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRC" start="0x20090000" description="CRC engine ">
+    <Register start="+0x000" size="4" name="MODE" access="Read/Write" description="CRC mode register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CRC_POLY" description="Select CRC polynomial">
+        <Enum name="CRC_CCITT_POLYNOMIAL" start="0x0" description="CRC-CCITT polynomial" />
+        <Enum name="CRC_16_POLYNOMIAL" start="0x1" description="CRC-16 polynomial" />
+        <Enum name="CRC_32_POLYNOMIAL" start="0x2" description="CRC-32 polynomial" />
+      </BitField>
+      <BitField start="2" size="1" name="BIT_RVS_WR" description="Select bit order for CRC_WR_DATA">
+        <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_WR_DATA (per byte)" />
+        <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_WR_DATA (per byte)" />
+      </BitField>
+      <BitField start="3" size="1" name="CMPL_WR" description="Select one's complement for CRC_WR_DATA">
+        <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_WR_DATA" />
+        <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_WR_DATA" />
+      </BitField>
+      <BitField start="4" size="1" name="BIT_RVS_SUM" description="Select bit order revers for CRC_SUM">
+        <Enum name="NO_BIT_ORDER_REVERSE" start="0" description="No bit order reverse for CRC_SUM" />
+        <Enum name="BIT_ORDER_REVERSE_FO" start="1" description="Bit order reverse for CRC_SUM" />
+      </BitField>
+      <BitField start="5" size="1" name="CMPL_SUM" description="Select one's complement for CRC_SUM">
+        <Enum name="NO_ONES_COMPLEMENT_" start="0" description="No one's complement for CRC_SUM" />
+        <Enum name="ONES_COMPLEMENT_FOR" start="1" description="One's complement for CRC_SUM" />
+      </BitField>
+      <BitField start="6" size="26" name="Reserved" description="Always 0 when read" />
+    </Register>
+    <Register start="+0x004" size="4" name="SEED" access="Read/Write" description="CRC seed register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRC_SEED" description="A write access to this register will load CRC seed value to CRC_SUM register with selected bit order and 1's complement pre-processes. A write access to this register will overrule the CRC calculation in progresses." />
+    </Register>
+    <Register start="+0x008" size="4" name="SUM" access="ReadOnly" description="CRC checksum register" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRC_SUM" description="The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes." />
+    </Register>
+    <Register start="+0x008" size="4" name="DATA" access="WriteOnly" description="CRC data register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="CRC_WR_DATA" description="Data written to this register will be taken to perform CRC calculation with selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO" start="0x20098000" description="GPIO">
+    <Register start="+0x000+0" size="4" name="DIR0" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+    </Register>
+    <Register start="+0x000+32" size="4" name="DIR1" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+    </Register>
+    <Register start="+0x000+64" size="4" name="DIR2" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+    </Register>
+    <Register start="+0x000+96" size="4" name="DIR3" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+    </Register>
+    <Register start="+0x000+128" size="4" name="DIR4" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+    </Register>
+    <Register start="+0x000+160" size="4" name="DIR5" access="Read/Write" description="GPIO Port Direction control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PDIR0" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="1" size="1" name="PDIR1" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="2" size="1" name="PDIR2" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="3" size="1" name="PDIR3" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="4" size="1" name="PDIR4" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="5" size="1" name="PDIR5" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="6" size="1" name="PDIR6" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="7" size="1" name="PDIR7" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="8" size="1" name="PDIR8" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="9" size="1" name="PDIR9" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="10" size="1" name="PDIR10" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="11" size="1" name="PDIR11" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="12" size="1" name="PDIR12" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="13" size="1" name="PDIR13" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="14" size="1" name="PDIR14" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="15" size="1" name="PDIR15" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="16" size="1" name="PDIR16" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="17" size="1" name="PDIR17" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="18" size="1" name="PDIR18" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="19" size="1" name="PDIR19" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="20" size="1" name="PDIR20" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="21" size="1" name="PDIR21" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="22" size="1" name="PDIR22" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="23" size="1" name="PDIR23" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="24" size="1" name="PDIR24" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="25" size="1" name="PDIR25" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="26" size="1" name="PDIR26" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="27" size="1" name="PDIR27" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="28" size="1" name="PDIR28" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="29" size="1" name="PDIR29" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="30" size="1" name="PDIR30" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+      <BitField start="31" size="1" name="PDIR31" description="Fast GPIO Direction PORTx control bits. Bit 0 in xDIR controls pin Px[0], bit 31 in xDIR controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="MASK0" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+    </Register>
+    <Register start="+0x010+32" size="4" name="MASK1" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+    </Register>
+    <Register start="+0x010+64" size="4" name="MASK2" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+    </Register>
+    <Register start="+0x010+96" size="4" name="MASK3" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+    </Register>
+    <Register start="+0x010+128" size="4" name="MASK4" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+    </Register>
+    <Register start="+0x010+160" size="4" name="MASK5" access="Read/Write" description="Mask register for Port." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMASK0" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="1" size="1" name="PMASK1" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="2" size="1" name="PMASK2" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="3" size="1" name="PMASK3" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="4" size="1" name="PMASK4" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="5" size="1" name="PMASK5" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="6" size="1" name="PMASK6" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="7" size="1" name="PMASK7" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="8" size="1" name="PMASK8" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="9" size="1" name="PMASK9" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="10" size="1" name="PMASK10" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="11" size="1" name="PMASK11" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="12" size="1" name="PMASK12" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="13" size="1" name="PMASK13" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="14" size="1" name="PMASK14" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="15" size="1" name="PMASK15" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="16" size="1" name="PMASK16" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="17" size="1" name="PMASK17" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="18" size="1" name="PMASK18" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="19" size="1" name="PMASK19" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="20" size="1" name="PMASK20" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="21" size="1" name="PMASK21" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="22" size="1" name="PMASK22" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="23" size="1" name="PMASK23" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="24" size="1" name="PMASK24" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="25" size="1" name="PMASK25" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="26" size="1" name="PMASK26" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="27" size="1" name="PMASK27" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="28" size="1" name="PMASK28" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="29" size="1" name="PMASK29" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="30" size="1" name="PMASK30" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+      <BitField start="31" size="1" name="PMASK31" description="Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's xSET, xCLR, and xPIN register(s). Current state of the pin can be read from the xPIN register. 1 = Controlled pin is not affected by writes into the port's xSET, xCLR and xPIN register(s). When the xPIN register is read, this bit will not be updated with the state of the physical pin." />
+    </Register>
+    <Register start="+0x014+0" size="4" name="PIN0" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x014+32" size="4" name="PIN1" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x014+64" size="4" name="PIN2" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x014+96" size="4" name="PIN3" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x014+128" size="4" name="PIN4" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x014+160" size="4" name="PIN5" access="Read/Write" description="Port Pin value register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VAL0" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="VAL1" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="VAL2" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="VAL3" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="VAL4" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="VAL5" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="VAL6" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="VAL7" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="VAL8" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="VAL9" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="VAL10" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="VAL11" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="VAL12" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="VAL13" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="VAL14" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="VAL15" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="VAL16" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="VAL17" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="VAL18" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="VAL19" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="VAL20" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="VAL21" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="VAL22" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="VAL23" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="VAL24" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="VAL25" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="VAL26" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="VAL27" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="VAL28" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="VAL29" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="VAL30" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="VAL31" description="Fast GPIO output value Set bits. Bit 0 in xCLR corresponds to pin Px[0], bit 31 in xCLR corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="SET0" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x018+32" size="4" name="SET1" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x018+64" size="4" name="SET2" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x018+96" size="4" name="SET3" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x018+128" size="4" name="SET4" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x018+160" size="4" name="SET5" access="Read/Write" description="Port Output Set register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSET0" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="1" size="1" name="PSET1" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="2" size="1" name="PSET2" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="3" size="1" name="PSET3" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="4" size="1" name="PSET4" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="5" size="1" name="PSET5" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="6" size="1" name="PSET6" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="7" size="1" name="PSET7" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="8" size="1" name="PSET8" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="9" size="1" name="PSET9" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="10" size="1" name="PSET10" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="11" size="1" name="PSET11" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="12" size="1" name="PSET12" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="13" size="1" name="PSET13" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="14" size="1" name="PSET14" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="15" size="1" name="PSET15" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="16" size="1" name="PSET16" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="17" size="1" name="PSET17" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="18" size="1" name="PSET18" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="19" size="1" name="PSET19" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="20" size="1" name="PSET20" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="21" size="1" name="PSET21" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="22" size="1" name="PSET22" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="23" size="1" name="PSET23" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="24" size="1" name="PSET24" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="25" size="1" name="PSET25" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="26" size="1" name="PSET26" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="27" size="1" name="PSET27" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="28" size="1" name="PSET28" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="29" size="1" name="PSET29" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="30" size="1" name="PSET30" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+      <BitField start="31" size="1" name="PSET31" description="Fast GPIO output value Set bits. Bit 0 in xSET controls pin Px[0], bit 31 in xSET controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH." />
+    </Register>
+    <Register start="+0x01C+0" size="4" name="CLR0" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+    </Register>
+    <Register start="+0x01C+32" size="4" name="CLR1" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+    </Register>
+    <Register start="+0x01C+64" size="4" name="CLR2" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+    </Register>
+    <Register start="+0x01C+96" size="4" name="CLR3" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+    </Register>
+    <Register start="+0x01C+128" size="4" name="CLR4" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+    </Register>
+    <Register start="+0x01C+160" size="4" name="CLR5" access="WriteOnly" description="Port Output Clear register using MASK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLR0" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="1" size="1" name="PCLR1" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="2" size="1" name="PCLR2" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="3" size="1" name="PCLR3" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="4" size="1" name="PCLR4" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="5" size="1" name="PCLR5" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="6" size="1" name="PCLR6" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="7" size="1" name="PCLR7" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="8" size="1" name="PCLR8" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="9" size="1" name="PCLR9" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="10" size="1" name="PCLR10" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="11" size="1" name="PCLR11" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="12" size="1" name="PCLR12" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="13" size="1" name="PCLR13" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="14" size="1" name="PCLR14" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="15" size="1" name="PCLR15" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="16" size="1" name="PCLR16" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="17" size="1" name="PCLR17" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="18" size="1" name="PCLR18" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="19" size="1" name="PCLR19" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="20" size="1" name="PCLR20" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="21" size="1" name="PCLR21" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="22" size="1" name="PCLR22" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="23" size="1" name="PCLR23" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="24" size="1" name="PCLR24" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="25" size="1" name="PCLR25" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="26" size="1" name="PCLR26" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="27" size="1" name="PCLR27" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="28" size="1" name="PCLR28" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="29" size="1" name="PCLR29" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="30" size="1" name="PCLR30" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+      <BitField start="31" size="1" name="PCLR31" description="Fast GPIO output value Clear bits. Bit 0 in xCLR controls pin Px[0], bit 31 controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EMC" start="0x2009C000" description="External Memory Controller (EMC)">
+    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled:">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled&#xa;(POR and warm reset value)." />
+      </BitField>
+      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map:">
+        <Enum name="NORMAL" start="0" description="Normal memory map." />
+        <Enum name="RESET" start="1" description="Reset memory map. Static memory EMC_CS1 is&#xa;mirrored onto EMC_CS0 and EMC_DYCS0 (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode:">
+        <Enum name="WARMRESET" start="0" description="Normal mode (warm&#xa;reset value)." />
+        <Enum name="LOWPOWER" start="1" description="Low-power&#xa;mode. Entering low-power mode reduces memory controller power consumption.&#xa;Dynamic memory is refreshed as necessary. The memory controller&#xa;returns to normal functional mode by clearing the low-power mode&#xa;bit (L), or by POR. This bit must only be modified when the EMC&#xa;is in idle state.[1]" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="B" description="Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not.">
+        <Enum name="IDLE" start="0" description="EMC&#xa;is idle (warm reset value)." />
+        <Enum name="BUSY" start="1" description="EMC&#xa;is busy performing memory transactions, commands, auto-refresh cycles,&#xa;or is in self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="1" size="1" name="S" description="Write buffer status.This bit enables the EMC to enter low-power mode or disabled mode cleanly.">
+        <Enum name="EMPTY" start="0" description="Write buffers&#xa;empty (POR reset value)" />
+        <Enum name="DATA" start="1" description="Write&#xa;buffers contain data." />
+      </BitField>
+      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC.">
+        <Enum name="NORMAL" start="0" description="Normal mode" />
+        <Enum name="SELFREFRESH" start="1" description="Self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM" description="Endian mode. On power-on reset, the value of the endian bit is 0. All data must be flushed in the EMC before switching between little-endian and big-endian modes.">
+        <Enum name="LITTLEENDIAN" start="0" description="Little-endian&#xa;mode (POR reset value)." />
+        <Enum name="BIGENDIAN" start="1" description="Big-endian&#xa;mode." />
+      </BitField>
+      <BitField start="1" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="CLKR" description="CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC.">
+        <Enum name="PORRESET" start="0" description="1:1(POR reset value)" />
+        <Enum name="DONOTUSE" start="1" description="1:2 (this option is not available on the LPC178x/177x)" />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x006" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
+        <Enum name="POWERSAVE" start="0" description="Clock enable of idle devices are deasserted to save power (POR reset value)." />
+        <Enum name="HIGH" start="1" description="All clock enables are driven HIGH continuously.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
+        <Enum name="STOP" start="0" description="CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
+        <Enum name="RUN" start="1" description="CLKOUT runs continuously (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
+        <Enum name="NORMAL_MODE_" start="0" description="Normal mode." />
+        <Enum name="ENTER_SELF_REFRESH_M" start="1" description="Enter self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
+        <Enum name="CLKOUT_ENABLED_POR_" start="0" description="CLKOUT enabled (POR reset value)." />
+        <Enum name="CLKOUT_DISABLED" start="1" description="CLKOUT disabled.[3]" />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
+        <Enum name="NORMAL" start="0x0" description="Issue SDRAM NORMAL operation command (POR reset value)." />
+        <Enum name="MODE" start="0x1" description="Issue SDRAM MODE command." />
+        <Enum name="PALL" start="0x2" description="Issue SDRAM PALL (precharge all) command." />
+        <Enum name="NOP" start="0x3" description="Issue SDRAM NOP (no operation) command)" />
+      </BitField>
+      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles" />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures dynamic memory read strategy." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RD" description="Read data strategy">
+        <Enum name="CLOCK_OUT_DELAYED_ST" start="0x0" description="Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value." />
+        <Enum name="COMMAND_DELAYED_STRA" start="0x1" description="Command delayed strategy, using EMCCLKDELAY (command delayed, clock out not delayed)." />
+        <Enum name="COMMAND_DELAYED_STRA" start="0x2" description="Command delayed strategy plus one clock cycle, using EMCCLKDELAY (command delayed, clock out not delayed)." />
+        <Enum name="COMMAND_DELAYED_STRA" start="0x3" description="Command delayed strategy plus two clock cycles, using EMCCLKDELAY (command delayed, clock out not delayed)." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Precharge command period." reset_value="0x0F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Time for exit self-refresh to active command." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Latency for active bank A to active bank B." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Time for load mode register to active command." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Time for long static memory read and write transfers." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Configuration information for EMC_DYCS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM_POR_RESET_VAL" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="LOW_POWER_SDRAM_" start="0x1" description="Low-power SDRAM." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="6" name="AM0" description="See Table 133. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="1" name="AM1" description="See  Table 133. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="BUFFER_DISABLED_FOR_" start="0" description="Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_FOR_A" start="1" description="Buffer enabled for accesses to this chip select.[2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITES_PROTECTED_" start="1" description="Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="RAS and CAS latencies for EMC_DYCS0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="ONE_CCLK_CYCLE_" start="0x1" description="One CCLK cycle." />
+        <Enum name="TWO_CCLK_CYCLES_" start="0x2" description="Two CCLK cycles." />
+        <Enum name="THREE_CCLK_CYCLES_P" start="0x3" description="Three CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT_" start="0x1" description="16 bit." />
+        <Enum name="32_BIT_" start="0x2" description="32 bit." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
+        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
+        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
+        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
+        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
+        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
+        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT_" start="0x1" description="16 bit." />
+        <Enum name="32_BIT_" start="0x2" description="32 bit." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
+        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
+        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
+        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
+        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
+        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
+        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT_" start="0x1" description="16 bit." />
+        <Enum name="32_BIT_" start="0x2" description="32 bit." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
+        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
+        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
+        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
+        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
+        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
+        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Configuration for EMC_CS0." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT_POR_RESET_VAL" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT_" start="0x1" description="16 bit." />
+        <Enum name="32_BIT_" start="0x2" description="32 bit." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED_POR_RESET_" start="0" description="Disabled (POR reset value)." />
+        <Enum name="ASYNCHRONOUS_PAGE_MO" start="1" description="Asynchronous page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW_CHIP_SELE" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH_CHIP_SEL" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLS3:0 signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLS3:0 signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH.">
+        <Enum name="BLSHIGH" start="0" description="For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in BLS3:0 are LOW (POR reset value)." />
+        <Enum name="BLSLOW" start="1" description="For reads the respective active bits in BLS3:0 are LOW. For writes the respective active bits in BLS3:0 are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait (EW) uses the EMCStaticExtendedWait register to time both the read and write transfers rather than the EMCStaticWaitRd and EMCStaticWaitWr registers. This enables much longer transactions. [1]">
+        <Enum name="EXTENDED_WAIT_DISABL" start="0" description="Extended wait disabled (POR reset value)." />
+        <Enum name="EXTENDED_WAIT_ENABLE" start="1" description="Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2]">
+        <Enum name="BUFFER_DISABLED_POR" start="0" description="Buffer disabled (POR reset value)." />
+        <Enum name="BUFFER_ENABLED_" start="1" description="Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect">
+        <Enum name="WRITES_NOT_PROTECTED" start="0" description="Writes not protected (POR reset value)." />
+        <Enum name="WRITE_PROTECTED_" start="1" description="Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Delay from EMC_CS0 to write enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Delay from EMC_CS0 or address change, whichever is later, to output enable." reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Delay from EMC_CS0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK. 0x1F = 32 CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Delay for asynchronous page mode sequential accesses for EMC_CS0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tCCLK. 0x1F = 32 CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Delay from EMC_CS0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK. 0x1F = 33 CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Number of bus turnaround cycles EMC_CS0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turn-around cycles. 0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is (WAITTURN + 1) x tCCLK. 0xF = 16 CCLK turn-around cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDT" start="0x40000000" description=" Windowed Watchdog Timer (WWDT) ">
+    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only. See Table 652.">
+        <Enum name="STOP" start="0" description="The watchdog timer is stopped." />
+        <Enum name="RUN" start="1" description="The watchdog timer is running." />
+      </BitField>
+      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only. See Table 652.">
+        <Enum name="NORESET" start="0" description="A watchdog timeout will not cause a chip reset." />
+        <Enum name="RESET" start="1" description="A watchdog timeout will cause a chip reset." />
+      </BitField>
+      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section  WDTOF." />
+      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section  WDINT." />
+      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only. See Section  WDPROTECT.">
+        <Enum name="CHANGE" start="0" description="The watchdog reload value (WDTC) can be changed at any time." />
+        <Enum name="CHANGE_W_CNT" start="1" description="The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. The value in this register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="Count" description="Watchdog time-out interval." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
+    </Register>
+    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="Count" description="Counter timer value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog Warning Interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="WARNINT" description="Watchdog warning interrupt compare value." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog Window compare value." reset_value="0xFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="WINDOW" description="Watchdog window value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER0" start="0x40004000" description=" Timer0/1/2/3 ">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
+        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
+        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER1" start="0x40008000" description=" Timer0/1/2/3 ">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
+        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
+        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART0" start="0x4000C000" description="UART0/2/3 ">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
+        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
+        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
+        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
+        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
+        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
+        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
+        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
+        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
+        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
+        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
+        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
+        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
+        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
+        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select">
+        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
+        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control">
+        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
+        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
+        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
+        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
+        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
+        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
+        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
+        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
+        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
+        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0_" start="0" description="Mode 0." />
+        <Enum name="MODE_1_" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART_" start="0" description="No restart." />
+        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
+        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
+        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
+        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
+        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART1" start="0x40010000" description="UART1">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="DLAB =0 Receiver Buffer Register. Contains the next received character to be read." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="DLAB =0. Transmit Holding Register. The next character to be transmitted is written here." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
+        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
+        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
+        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
+        <Enum name="DISABLE_THE_MODEM_IN" start="0" description="Disable the modem interrupt." />
+        <Enum name="ENABLE_THE_MODEM_INT" start="1" description="Enable the modem interrupt." />
+      </BitField>
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
+        <Enum name="DISABLE_THE_CTS_INTE" start="0" description="Disable the CTS interrupt." />
+        <Enum name="ENABLE_THE_CTS_INTER" start="1" description="Enable the CTS interrupt." />
+      </BitField>
+      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
+        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="1   - Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="2a - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="3   - THRE Interrupt." />
+        <Enum name="MODEM" start="0x0" description="4   - Modem Interrupt." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
+        <Enum name="MUST_NOT_BE_USED_IN_" start="0" description="Must not be used in the application." />
+        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UART1 FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
+        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
+        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCED1STICK_PAR" start="0x2" description="Forced 1 stick parity." />
+        <Enum name="FORCED0STICK_PAR" start="0x3" description="Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
+        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
+        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
+        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
+        <Enum name="DISABLE_MODEM_LOOPBA" start="0" description="Disable modem loopback mode." />
+        <Enum name="ENABLE_MODEM_LOOPBAC" start="1" description="Enable modem loopback mode." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
+        <Enum name="DISABLE_AUTO_RTS_FLO" start="0" description="Disable auto-rts flow control." />
+        <Enum name="ENABLE_AUTO_RTS_FLOW" start="1" description="Enable auto-rts flow control." />
+      </BitField>
+      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
+        <Enum name="DISABLE_AUTO_CTS_FLO" start="0" description="Disable auto-cts flow control." />
+        <Enum name="ENABLE_AUTO_CTS_FLOW" start="1" description="Enable auto-cts flow control." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="The UART1 receiver FIFO is empty." />
+        <Enum name="NOTEMPTY" start="1" description="The UART1 receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
+        <Enum name="VALID" start="0" description="THR contains valid data." />
+        <Enum name="THR_IS_EMPTY_" start="1" description="THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="VALID" start="0" description="THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
+        <Enum name="NOERROR" start="0" description="RBR contains no UART1 RX errors or FCR[0]=0." />
+        <Enum name="ERRORS" start="1" description="UART1 RBR contains at least one UART1 RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, CTS." />
+        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, CTS." />
+      </BitField>
+      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DSR." />
+        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DSR." />
+      </BitField>
+      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, RI." />
+        <Enum name="LOW_TO_HIGH_TRANSITI" start="1" description="Low-to-high transition detected on RI." />
+      </BitField>
+      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE_DETECTED_O" start="0" description="No change detected on modem input, DCD." />
+        <Enum name="STATE_CHANGE_DETECTE" start="1" description="State change detected on modem input, DCD." />
+      </BitField>
+      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
+      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
+      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
+      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0_" start="0" description="Mode 0." />
+        <Enum name="MODE_1_" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart" />
+        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
+        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="WRITING_A_0_HAS_NO_I" start="0" description="Writing a 0 has no impact." />
+        <Enum name="WRITING_A_1_WILL_CLE" start="1" description="Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_IN_THIS_MOD" start="1" description="Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
+        <Enum name="ENABLED_" start="0" description="Enabled." />
+        <Enum name="DISABLED_" start="1" description="Disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect (AAD) enable.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SEL" description="Direction control.">
+        <Enum name="RTS_IF_DIRECTION_CO" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
+        <Enum name="DTR_IF_DIRECTION_CO" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
+      </BitField>
+      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
+        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
+        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
+        <Enum name="LOW_THE_DIRECTION_C" start="0" description="LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH_THE_DIRECTION_" start="1" description="HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PWM0" start="0x40014000" description="Pulse Width Modulators (PWM0/1)">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
+      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
+      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
+      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
+      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
+      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
+      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
+      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CE" description="Counter Enable">
+        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
+        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CR" description="Counter Reset">
+        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
+        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
+        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
+      </BitField>
+      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
+        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
+        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
+      </BitField>
+      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
+      </BitField>
+      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
+      </BitField>
+      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
+      </BitField>
+      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
+      </BitField>
+      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
+    </Register>
+    <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
+    </Register>
+    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
+      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
+      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
+      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
+      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
+      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
+      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
+        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
+        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
+        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
+        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
+        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PWM1" start="0x40018000" description="Pulse Width Modulators (PWM0/1)">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMMR0INT" description="Interrupt flag for PWM match channel 0." />
+      <BitField start="1" size="1" name="PWMMR1INT" description="Interrupt flag for PWM match channel 1." />
+      <BitField start="2" size="1" name="PWMMR2INT" description="Interrupt flag for PWM match channel 2." />
+      <BitField start="3" size="1" name="PWMMR3INT" description="Interrupt flag for PWM match channel 3." />
+      <BitField start="4" size="1" name="PWMCAP0INT" description="Interrupt flag for capture input 0" />
+      <BitField start="5" size="1" name="PWMCAP1INT" description="Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR)." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="PWMMR4INT" description="Interrupt flag for PWM match channel 4." />
+      <BitField start="9" size="1" name="PWMMR5INT" description="Interrupt flag for PWM match channel 5." />
+      <BitField start="10" size="1" name="PWMMR6INT" description="Interrupt flag for PWM match channel 6." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CE" description="Counter Enable">
+        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and PWM Prescale Counter are enabled for counting." />
+        <Enum name="THE_COUNTERS_ARE_DIS" start="0" description="The counters are disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CR" description="Counter Reset">
+        <Enum name="THE_PWM_TIMER_COUNTE" start="1" description="The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero." />
+        <Enum name="CLEAR_RESET_" start="0" description="Clear reset." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="3" size="1" name="PWMEN" description="PWM Enable">
+        <Enum name="PWM_MODE_IS_ENABLED_" start="1" description="PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective." />
+        <Enum name="TIMER_MODE_IS_ENABLE" start="0" description="Timer mode is enabled (counter resets to 0)." />
+      </BitField>
+      <BitField start="4" size="1" name="MDIS" description="Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).">
+        <Enum name="MASTER_USE_PWM0_IS_" start="1" description="Master use. PWM0 is the master, and both PWMs are enabled for counting." />
+        <Enum name="INDIVIDUAL_USE_THE_" start="0" description="Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. Determines how often the PWM counter is incremented." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. Prescaler for the main PWM counter." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWMMR0I" description="Interrupt PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR0" start="1" description="Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="1" size="1" name="PWMMR0R" description="Reset PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR0_THE" start="1" description="Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="PWMMR0S" description="Stop PWM0">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR0_THE_" start="1" description="Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMMR1I" description="Interrupt PWM1">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR1" start="1" description="Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMMR1R" description="Reset PWM1">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR1_THE" start="1" description="Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMMR1S" description="Stop PWM1">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR1_THE_" start="1" description="Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMMR2I" description="Interrupt PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR2" start="1" description="Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="7" size="1" name="PWMMR2R" description="Reset PWM0">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR2_THE" start="1" description="Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="PWMMR2S" description="Stop PWM0">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR2_THE_" start="1" description="Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
+      </BitField>
+      <BitField start="9" size="1" name="PWMMR3I" description="Interrupt PWM3">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR3" start="1" description="Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMMR3R" description="Reset PWM3">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR3_THE" start="1" description="Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMMR3S" description="Stop PWM0">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR3_THE_" start="1" description="Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMMR4I" description="Interrupt PWM4">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR4" start="1" description="Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMMR4R" description="Reset PWM4">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR4_THE" start="1" description="Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMMR4S" description="Stop PWM4">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR4_THE_" start="1" description="Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC." />
+      </BitField>
+      <BitField start="15" size="1" name="PWMMR5I" description="Interrupt PWM5">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR5" start="1" description="Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="16" size="1" name="PWMMR5R" description="Reset PWM5">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR5_THE" start="1" description="Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it." />
+      </BitField>
+      <BitField start="17" size="1" name="PWMMR5S" description="Stop PWM5">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR5_THE_" start="1" description="Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC." />
+      </BitField>
+      <BitField start="18" size="1" name="PWMMR6I" description="Interrupt PWM6">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="INTERRUPT_ON_PWMMR6" start="1" description="Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC." />
+      </BitField>
+      <BitField start="19" size="1" name="PWMMR6R" description="Reset PWM6">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="RESET_ON_PWMMR6_THE" start="1" description="Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it." />
+      </BitField>
+      <BitField start="20" size="1" name="PWMMR6S" description="Stop PWM6">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="STOP_ON_PWMMR6_THE_" start="1" description="Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0_R" description="Capture on PWMn_CAP0 rising edge">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0_F" description="Capture on PWMn_CAP0 falling edge">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0_I" description="Interrupt on PWMn_CAP0 event">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="INTERRUPT_A_CR0_LOA" start="1" description="Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1_R" description="Capture on PWMn_CAP1 rising edge. Reserved for PWM0.">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="RISING_EDGE_A_SYNCH" start="1" description="Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1_F" description="Capture on PWMn_CAP1 falling edge. Reserved for PWM0.">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="FALLING_EDGE_A_SYNC" start="1" description="Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1_I" description="Interrupt on PWMn_CAP1 event. Reserved for PWM0.">
+        <Enum name="DISABLED_THIS_FEATU" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="INTERRUPT_A_CR1_LOA" start="1" description="Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR[0]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR[1]" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
+    </Register>
+    <Register start="+0x040" size="4" name="MR4" access="Read/Write" description="Match Register. Match registers&#xa;are continuously compared to the PWM counter in order to control PWM&#xa;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x044" size="4" name="MR5" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x048" size="4" name="MR6" access="Read/Write" description="Match Register. Match registers&#xa;&#x9;&#x9;&#x9;&#x9;are continuously compared to the PWM counter in order to control PWM&#xa;&#x9;&#x9;&#x9;&#x9;output edges." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x04C" size="4" name="PCR" access="Read/Write" description="PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="2" size="1" name="PWMSEL2" description="PWM[2] output single/double edge mode control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="3" size="1" name="PWMSEL3" description="PWM[3] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="4" size="1" name="PWMSEL4" description="PWM[4] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="5" size="1" name="PWMSEL5" description="PWM[5] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="6" size="1" name="PWMSEL6" description="PWM[6] output edge control.">
+        <Enum name="SINGLE_EDGE_CONTROLL" start="0" description="Single edge controlled mode is selected." />
+        <Enum name="DOUBLE_EDGE_CONTROLL" start="1" description="Double edge controlled mode is selected." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="9" size="1" name="PWMENA1" description="PWM[1] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="PWMENA2" description="PWM[2] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="11" size="1" name="PWMENA3" description="PWM[3] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="PWMENA4" description="PWM[4] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="13" size="1" name="PWMENA5" description="PWM[5] output enable control.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="14" size="1" name="PWMENA6" description="PWM[6] output enable control. See PWMENA1 for details.">
+        <Enum name="THE_PWM_OUTPUT_IS_DI" start="0" description="The PWM output is disabled." />
+        <Enum name="THE_PWM_OUTPUT_IS_EN" start="1" description="The PWM output is enabled." />
+      </BitField>
+      <BitField start="15" size="17" name="RESERVED" description="Unused, always zero." />
+    </Register>
+    <Register start="+0x050" size="4" name="LER" access="Read/Write" description="Load Enable Register. Enables use of updated PWM match values." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MAT0LATCHEN" description="Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7." />
+      <BitField start="1" size="1" name="MAT1LATCHEN" description="Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details." />
+      <BitField start="2" size="1" name="MAT2LATCHEN" description="Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details." />
+      <BitField start="3" size="1" name="MAT3LATCHEN" description="Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details." />
+      <BitField start="4" size="1" name="MAT4LATCHEN" description="Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details." />
+      <BitField start="5" size="1" name="MAT5LATCHEN" description="Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details." />
+      <BitField start="6" size="1" name="MAT6LATCHEN" description="Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MOD" description="Counter/  Timer Mode">
+        <Enum name="TIMER_MODE_THE_TC_I" start="0x0" description="Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register." />
+        <Enum name="RISING_EDGE_COUNTER_" start="0x1" description="Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2." />
+        <Enum name="FALLING_EDGE_COUNTER" start="0x2" description="Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2." />
+        <Enum name="DUAL_EDGE_COUNTER_MO" start="0x3" description="Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CIS" description="Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.">
+        <Enum name="FOR_PWM0_00_EQ_PWM0_" start="0x0" description="For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C0" start="0x4001C000" description="I2C bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="COMPARATOR" start="0x40020000" description="Comparators">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Comparator block control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CMP_PD_IREF" description="Controls the current source used by the comparators. These bits must be set when either comparator is used.">
+        <Enum name="DISABLED" start="0x0" description="The comparator current source is disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator current source is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="The comparator current source is disabled in Power-down mode and restored automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="The comparator current source is powered up." />
+      </BitField>
+      <BitField start="2" size="2" name="CMP_PD_VBG" description="Controls the bandgap reference source that is used by the comparators. These bits must be set when either comparator is used.">
+        <Enum name="DISABLED" start="0x0" description="The comparator bandgap reference is disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The comparator bandgap reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="The comparator bandgap reference is disabled in Power-down mode and restored automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="The comparator bandgap reference is powered up." />
+      </BitField>
+      <BitField start="4" size="2" name="CMP_VTEMP" description="Controls the voltage reference of the temperature sensor. These bits must be set when the temperature sensor is used.">
+        <Enum name="DISABLED" start="0x0" description="The temperature sensor voltage reference is disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor voltage reference is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor voltage reference is disabled in Power-down mode and restored automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="The temperature sensor voltage reference is powered up." />
+      </BitField>
+      <BitField start="6" size="2" name="CMP_TEMPSEN" description="Enables the temperature sensor. These bits must be set when the temperature sensor is used.">
+        <Enum name="DISABLED" start="0x0" description="Temperature sensor is disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The temperature sensor is disabled in Deep Sleep and Power-down modes and restored automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="The temperature sensor is disabled in Power-down mode and restored automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="Temperature sensor is enabled." />
+      </BitField>
+      <BitField start="8" size="1" name="CMP_ROSCCTL" description="Selects the inputs for the flip/flops that provide the CMP_ROSC output.">
+        <Enum name="CMP1" start="0" description="The CMP_ROSC output is set by CMP1 and reset by CMP0." />
+        <Enum name="CMP0" start="1" description="The CMP_ROSC output is set by CMP0 and reset by CMP1." />
+      </BitField>
+      <BitField start="9" size="1" name="CMP_EXT_RESET" description="Selects the reset source for the CMP_ROSC output.">
+        <Enum name="INTRESET" start="0" description="The CMP_ROSC output is reset by the internal chip reset." />
+        <Enum name="CMP_RESETIN" start="1" description="The CMP_ROSC output is reset by the CMP_RESET input." />
+      </BitField>
+      <BitField start="10" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="CMP_T0CAP2" description="Selects the input for Timer 0 capture input 2.">
+        <Enum name="COMP0" start="0" description="T0CAP2 is connected to comparator 0 level output." />
+        <Enum name="COMP1" start="1" description="T0CAP2 is connected to comparator 1 level output." />
+      </BitField>
+      <BitField start="13" size="1" name="CMP_T0CAP3" description="Selects the input for Timer 0 capture input 3.">
+        <Enum name="COMP0" start="0" description="T0CAP3 is connected to comparator 0 edge output." />
+        <Enum name="COMP1" start="1" description="T0CAP3 is connected to comparator 1 edge output." />
+      </BitField>
+      <BitField start="14" size="1" name="CMP_T1CAP2" description="Selects the input for Timer 1 capture input 2.">
+        <Enum name="COMP1" start="0" description="T1CAP2 is connected to comparator 1 edge output." />
+        <Enum name="COMP0" start="1" description="T1CAP2 is connected to comparator 0 level output." />
+      </BitField>
+      <BitField start="15" size="1" name="CMP_T1CAP3" description="Selects the input for Timer 1 capture input 3.">
+        <Enum name="COMP1" start="0" description="T1CAP3 is connected to comparator 1 level output." />
+        <Enum name="COMP0" start="1" description="T1CAP3 is connected to comparator 0 edge output." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="CTRL0" access="Read/Write" description="Comparator 0 control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CMP0_EN" description="Comparator 0 enable control.">
+        <Enum name="DISABLED" start="0x0" description="Comparator 0 disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 0 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 0 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="Comparator 0 is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CMP0_OE" description="Comparator 0 output enable.">
+        <Enum name="DISABLED" start="0" description="Comparator 0 output is disabled." />
+        <Enum name="ENABLED" start="1" description="Comparator 0 output is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CMP0_STAT" description="Comparator 0 status. This bit reflects the comparator 0 output, and is not affected by CMP0_OE." />
+      <BitField start="4" size="3" name="CMP0_VM" description="Comparator 0 VM input select.">
+        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
+        <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." />
+        <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." />
+        <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." />
+        <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." />
+        <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." />
+        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
+        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="3" name="CMP0_VP" description="Comparator 0 VP input select.">
+        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
+        <Enum name="CMP0_IN0" start="0x1" description="CMP0_IN[0]." />
+        <Enum name="CMP0_IN1" start="0x2" description="CMP0_IN[1]." />
+        <Enum name="CMP0_IN2" start="0x3" description="CMP0_IN[2]." />
+        <Enum name="CMP0_IN3" start="0x4" description="CMP0_IN[3]." />
+        <Enum name="CMP1_IN0" start="0x5" description="CMP1_IN[0]." />
+        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
+        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
+      </BitField>
+      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="CMP0_SYNC" description="Comparator 0 output synchronization control.">
+        <Enum name="DIRECT" start="0" description="The comparator 0 output is used directly." />
+        <Enum name="SYNCH" start="1" description="The comparator 0 output is synchronized with the internal bus clock for output to other peripherals." />
+      </BitField>
+      <BitField start="13" size="2" name="CMP0_HYS" description="Comparator 0 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.">
+        <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." />
+        <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." />
+        <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." />
+        <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." />
+      </BitField>
+      <BitField start="15" size="1" name="CMP0_INTPOL" description="Selects the polarity of the CMP0 output for purposes of generating level interrupts. See Table 412.">
+        <Enum name="NOTINVERTED" start="0" description="The CMP0 output is used as-is for generating interrupts." />
+        <Enum name="INVERTED" start="1" description="The CMP0 output is used inverted for generating interrupts." />
+      </BitField>
+      <BitField start="16" size="1" name="CMP0_INTTYPE" description="Select comparator 0 interrupt type. See Table 412.">
+        <Enum name="EDGE" start="0" description="Comparator 0 interrupt is edge triggered." />
+        <Enum name="LEVEL" start="1" description="Comparator 0 interrupt is level triggered." />
+      </BitField>
+      <BitField start="17" size="2" name="CMP0_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP0_IntType = 0. See Table 412.">
+        <Enum name="FALLING" start="0x0" description="Comparator 0 interrupt is active on falling edges." />
+        <Enum name="RISING" start="0x1" description="Comparator 0 interrupt is active on rising edges." />
+        <Enum name="DUALEDGE" start="0x2" description="Comparator 0 Interrupt is active on both edges." />
+      </BitField>
+      <BitField start="19" size="1" name="CMP0_INTFLAG" description="Comparator 0 interrupt flag.">
+        <Enum name="NOTPENDING" start="0" description="The Comparator 0 interrupt is not pending." />
+        <Enum name="PENDING" start="1" description="The Comparator 0 interrupt is pending. Writing a 1 to this bit clears the flag." />
+      </BitField>
+      <BitField start="20" size="2" name="CMP0_VLADEN" description="Voltage ladder enable for comparator 0.">
+        <Enum name="DISABLED" start="0x0" description="The Comparator 0 voltage ladder is disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 0 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 0 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="The Comparator 0 voltage ladder is enabled." />
+      </BitField>
+      <BitField start="22" size="1" name="CMP0_VLADREF" description="Voltage reference select for comparator 0 voltage ladder.">
+        <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." />
+        <Enum name="VDDA_PIN_" start="1" description="VDDA pin." />
+      </BitField>
+      <BitField start="23" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="5" name="CMP0_VSEL" description="Voltage ladder value for comparator 0. The reference voltage Vref depends on the setting of CMP0_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x  Vref0 / 31. 00010 = 2 x Vref0 / 31. ... 11111 = Vref0" />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x008" size="4" name="CTRL1" access="Read/Write" description="Comparator 1 control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CMP1_EN" description="Comparator 1 enable control.">
+        <Enum name="DISABLED" start="0x0" description="Comparator 1 disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="Comparator 1 is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="Comparator 1 is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="Comparator 1 is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CMP1_OE" description="Comparator 1 output enable.">
+        <Enum name="DISABLED" start="0" description="Comparator 1 output is disabled." />
+        <Enum name="ENABLED" start="1" description="Comparator 1 output is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CMP1_STAT" description="Comparator 1 status. This bit reflects the comparator 1 output, and is not affected by CMP1_OE." />
+      <BitField start="4" size="3" name="CMP1_VM" description="Comparator 1 VM input select.">
+        <Enum name="VREF_DIVIDER_1_" start="0x0" description="Vref divider 1." />
+        <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." />
+        <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." />
+        <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." />
+        <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." />
+        <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." />
+        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
+        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="3" name="CMP1_VP" description="Comparator 1 VP input select.">
+        <Enum name="VREF_DIVIDER_0_" start="0x0" description="Vref divider 0." />
+        <Enum name="CMP1_IN0" start="0x1" description="CMP1_IN[0]." />
+        <Enum name="CMP1_IN1" start="0x2" description="CMP1_IN[1]." />
+        <Enum name="CMP1_IN2" start="0x3" description="CMP1_IN[2]." />
+        <Enum name="CMP1_IN3" start="0x4" description="CMP1_IN[3]." />
+        <Enum name="CMP0_IN0" start="0x5" description="CMP0_IN[0]." />
+        <Enum name="INTERNAL_0_9_V_BAND_" start="0x6" description="internal 0.9 V band gap reference." />
+        <Enum name="TEMPERATURE_SENSOR_" start="0x7" description="temperature sensor." />
+      </BitField>
+      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="CMP1_SYNC" description="Comparator 1 output synchronization control.">
+        <Enum name="DIRECT" start="0" description="The comparator 1 output is used directly." />
+        <Enum name="SYNCH" start="1" description="The comparator 1 output is synchronized with the internal bus clock for output to other peripherals." />
+      </BitField>
+      <BitField start="13" size="2" name="CMP1_HYS" description="Comparator 1 hysteresis control. When enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. The difference must be in the direction opposite of the current comparator output.">
+        <Enum name="HYSTERESISOFF" start="0x0" description="Hysteresis is turned off, comparator output will change as the input voltages cross." />
+        <Enum name="HYSTERESIS_EQ_5_MV_" start="0x1" description="Hysteresis = 5 mV." />
+        <Enum name="HYSTERESIS_EQ_10_MV_" start="0x2" description="Hysteresis = 10 mV." />
+        <Enum name="HYSTERESIS_EQ_15_MV_" start="0x3" description="Hysteresis = 15 mV." />
+      </BitField>
+      <BitField start="15" size="1" name="CMP1_INTPOL" description="Selects the polarity of the CMP1 output for purposes of generating level interrupts. See Table 412.">
+        <Enum name="NOTINVERTED" start="0" description="The CMP1 output is used as-is for generating interrupts." />
+        <Enum name="INVERTED" start="1" description="The CMP1 output is used inverted for generating interrupts." />
+      </BitField>
+      <BitField start="16" size="1" name="CMP1_INTTYPE" description="Select comparator 1 interrupt type. See Table 412.">
+        <Enum name="EDGE" start="0" description="Comparator 1 interrupt is edge triggered." />
+        <Enum name="LEVEL" start="1" description="Comparator 1 interrupt is level triggered." />
+      </BitField>
+      <BitField start="17" size="2" name="CMP1_INTEDGE" description="Select edge triggered interrupt to be active on either high or low transitions, when CMP1_IntType = 0. See Table 412.">
+        <Enum name="FALLING" start="0x0" description="Comparator 1 interrupt is active on falling edges." />
+        <Enum name="RISING" start="0x1" description="Comparator 1 interrupt is active on rising edges." />
+        <Enum name="DUALEDGE" start="0x2" description="Comparator 1 Interrupt is active on both edges." />
+      </BitField>
+      <BitField start="19" size="1" name="CMP1_INTFLAG" description="Comparator 1 interrupt flag.">
+        <Enum name="NOTPENDING" start="0" description="The Comparator 1 interrupt is not pending." />
+        <Enum name="PENDING" start="1" description="The Comparator 1 interrupt is pending. Writing a 1 to this bit clears the flag." />
+      </BitField>
+      <BitField start="20" size="2" name="CMP1_VLADEN" description="Voltage ladder enable for comparator 1.">
+        <Enum name="DISABLED" start="0x0" description="The Comparator 1 voltage ladder is disabled." />
+        <Enum name="DIS_DEEPSLP_PWRDWN" start="0x1" description="The Comparator 1 voltage ladder is disabled in Deep Sleep and Power-down modes and re-enabled automatically when exiting those modes." />
+        <Enum name="DIS_PWRDWN" start="0x2" description="The Comparator 1 voltage ladder is disabled in Power-down mode and re-enabled automatically when exiting Power-down." />
+        <Enum name="ENABLED" start="0x3" description="The Comparator 1 voltage ladder is enabled." />
+      </BitField>
+      <BitField start="22" size="1" name="CMP1_VLADREF" description="Voltage reference select for comparator 1 voltage ladder.">
+        <Enum name="VREF_CMP_PIN_" start="0" description="VREF_CMP pin." />
+        <Enum name="VDDA_PIN_" start="1" description="VDDA pin." />
+      </BitField>
+      <BitField start="23" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="5" name="CMP1_VSel" description="Voltage ladder value for comparator 1. The reference voltage Vref depends on the setting of CMP1_VLADREF (either VDD(3V3) or voltage on pin VREF_CMP). 00000 = Vss. 00001 = 1 x Vref1 / 31. 00010 = 2 x Vref1 / 31. ... 11111 = Vref1." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RTC" start="0x40024000" description=" Real Time Clock (RTC) ">
+    <Register start="+0x000" size="4" name="ILR" access="Read/Write" description="Interrupt Location Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
+      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
+        <Enum name="THE_TIME_COUNTERS_AR" start="1" description="The time counters are enabled." />
+        <Enum name="THE_TIME_COUNTERS_AR" start="0" description="The time counters are disabled so that they may be initialized." />
+      </BitField>
+      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
+        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
+        <Enum name="NO_EFFECT_" start="0" description="No effect." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
+      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
+        <Enum name="THE_CALIBRATION_COUN" start="1" description="The calibration counter is disabled and reset to zero." />
+        <Enum name="THE_CALIBRATION_COUN" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
+      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
+      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
+      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
+      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
+      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
+      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
+      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
+      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
+      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
+      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
+      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
+      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
+      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
+      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="21" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
+      <BitField start="27" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="3" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Counter" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
+      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
+        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
+        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
+      </BitField>
+    </Register>
+    <Register start="+0x044+0" size="4" name="GPREG0" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="GP" description="General purpose storage." />
+    </Register>
+    <Register start="+0x044+4" size="4" name="GPREG1" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="GP" description="General purpose storage." />
+    </Register>
+    <Register start="+0x044+8" size="4" name="GPREG2" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="GP" description="General purpose storage." />
+    </Register>
+    <Register start="+0x044+12" size="4" name="GPREG3" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="GP" description="General purpose storage." />
+    </Register>
+    <Register start="+0x044+16" size="4" name="GPREG4" access="Read/Write" description="General Purpose Register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="GP" description="General purpose storage." />
+    </Register>
+    <Register start="+0x05C" size="4" name="RTC_AUX" access="Read/Write" description="RTC Auxiliary control register" reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="1" name="RTC_OSCF" description="RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag." />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="1" name="RTC_PDOUT" description="When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x058" size="4" name="RTC_AUXEN" access="Read/Write" description="RTC Auxiliary Enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="1" name="RTC_OSCFEN" description="Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x64" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x06C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x084" size="4" name="ERCONTROL" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wakeup enable for channel 0.">
+        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 0." />
+        <Enum name="AN_EVENT_IN_CHANNEL_" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
+        <Enum name="NOGPREG" start="0" description="Channel 0 has no influence on the general purpose registers." />
+        <Enum name="CLRGPREG" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin RTC_EV0.">
+        <Enum name="NEG" start="0" description="A channel 0 event is defined as a negative edge on RTC_EV0." />
+        <Enum name="POS" start="1" description="A channel 0 event is defined as a positive edge on RTC_EV0." />
+      </BitField>
+      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0.[1]">
+        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
+      </BitField>
+      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wakeup enable for channel 1.">
+        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 1." />
+        <Enum name="WAKEUP" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
+        <Enum name="NOGPREG" start="0" description="Channel 1 has no influence on the general purpose registers." />
+        <Enum name="CLRGPREG" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin RTC_EV1.">
+        <Enum name="NEG" start="0" description="A channel 1 event is defined as a negative edge on RTC_EV1." />
+        <Enum name="POS" start="1" description="A channel 1 event is defined as a positive edge on RTC_EV1." />
+      </BitField>
+      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1.[1]">
+        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
+      </BitField>
+      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wakeup enable for channel 2.">
+        <Enum name="NO_INTERRUPT_OR_WAKE" start="0" description="No interrupt or wakeup will be generated by event channel 2." />
+        <Enum name="WAKEUP" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
+        <Enum name="NOGPREG" start="0" description="Channel 2 has no influence on the general purpose registers." />
+        <Enum name="CLRGPREG" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin RTC_EV2.">
+        <Enum name="NEG" start="0" description="A channel 2 event is defined as a negative edge on RTC_EV2." />
+        <Enum name="POS" start="1" description="A channel 2 event is defined as a positive edge on RTC_EV2." />
+      </BitField>
+      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2.[1]">
+        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
+      </BitField>
+      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2]">
+        <Enum name="DISABLED" start="0x0" description="Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
+        <Enum name="ENABLE_EVENT_MONITOR16HZ" start="0x1" description="Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
+        <Enum name="ENABLE_EVENT_MONITOR64HZ" start="0x2" description="Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
+        <Enum name="ENABLE_EVENT_MONITOR1KHZ" start="0x3" description="Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
+      </BitField>
+    </Register>
+    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EV0" description="Event flag for channel 0 (RTC_EV0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 0." />
+        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 0." />
+      </BitField>
+      <BitField start="1" size="1" name="EV1" description="Event flag for channel 1 (RTC_EV1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 1." />
+        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 1." />
+      </BitField>
+      <BitField start="2" size="1" name="EV2" description="Event flag for channel 2 (RTC_EV2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_EVENT_CHANGE_ON_C" start="0" description="No event change on channel 2." />
+        <Enum name="AT_LEAST_ONE_EVENT_H" start="1" description="At least one event has occurred on channel 2." />
+      </BitField>
+      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NOGPCLR" start="0" description="General purpose registers have not been asynchronous cleared." />
+        <Enum name="GPCLR" start="1" description="General purpose registers have been asynchronous cleared." />
+      </BitField>
+      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wakeup request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_INTERRUPTWAKEUP_" start="0" description="No interrupt/wakeup request is pending" />
+        <Enum name="INTWAKEUP_PEND" start="1" description="An interrupt/wakeup request is pending." />
+      </BitField>
+    </Register>
+    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOINT" start="0x40028080" description="GPIO">
+    <Register start="+0x000" size="4" name="STATUS" access="ReadOnly" description="GPIO overall Interrupt Status." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P0Int" description="Port 0 GPIO interrupt pending.">
+        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 0." />
+        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 0." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="P2Int" description="Port 2 GPIO interrupt pending.">
+        <Enum name="NO_PENDING_INTERRUPT" start="0" description="No pending interrupts on Port 2." />
+        <Enum name="AT_LEAST_ONE_PENDING" start="1" description="At least one pending interrupt on Port 2." />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STATR0" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P0_0REI" description="Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="1" size="1" name="P0_1REI" description="Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="2" size="1" name="P0_2REI" description="Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="3" size="1" name="P0_3REI" description="Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="4" size="1" name="P0_4REI" description="Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="5" size="1" name="P0_5REI" description="Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="6" size="1" name="P0_6REI" description="Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="7" size="1" name="P0_7REI" description="Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="8" size="1" name="P0_8REI" description="Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="9" size="1" name="P0_9REI" description="Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="10" size="1" name="P0_10REI" description="Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="11" size="1" name="P0_11REI" description="Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="12" size="1" name="P0_12REI" description="Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="13" size="1" name="P0_13REI" description="Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="14" size="1" name="P0_14REI" description="Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="15" size="1" name="P0_15REI" description="Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="16" size="1" name="P0_16REI" description="Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="17" size="1" name="P0_17REI" description="Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="18" size="1" name="P0_18REI" description="Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="19" size="1" name="P0_19REI" description="Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="20" size="1" name="P0_20REI" description="Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="21" size="1" name="P0_21REI" description="Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="22" size="1" name="P0_22REI" description="Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="23" size="1" name="P0_23REI" description="Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="24" size="1" name="P0_24REI" description="Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="25" size="1" name="P0_25REI" description="Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="26" size="1" name="P0_26REI" description="Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="27" size="1" name="P0_27REI" description="Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="28" size="1" name="P0_28REI" description="Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="29" size="1" name="P0_29REI" description="Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="30" size="1" name="P0_30REI" description="Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="31" size="1" name="P0_31REI" description="Status of Rising Edge Interrupt for P0[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+    </Register>
+    <Register start="+0x008" size="4" name="STATF0" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P0_0FEI" description="Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="1" size="1" name="P0_1FEI" description="Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="2" size="1" name="P0_2FEI" description="Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="3" size="1" name="P0_3FEI" description="Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="4" size="1" name="P0_4FEI" description="Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="5" size="1" name="P0_5FEI" description="Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="6" size="1" name="P0_6FEI" description="Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="7" size="1" name="P0_7FEI" description="Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="8" size="1" name="P0_8FEI" description="Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="9" size="1" name="P0_9FEI" description="Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="10" size="1" name="P0_10FEI" description="Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="11" size="1" name="P0_11FEI" description="Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="12" size="1" name="P0_12FEI" description="Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="13" size="1" name="P0_13FEI" description="Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="14" size="1" name="P0_14FEI" description="Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="15" size="1" name="P0_15FEI" description="Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="16" size="1" name="P0_16FEI" description="Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="17" size="1" name="P0_17FEI" description="Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="18" size="1" name="P0_18FEI" description="Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="19" size="1" name="P0_19FEI" description="Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="20" size="1" name="P0_20FEI" description="Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="21" size="1" name="P0_21FEI" description="Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="22" size="1" name="P0_22FEI" description="Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="23" size="1" name="P0_23FEI" description="Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="24" size="1" name="P0_24FEI" description="Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="25" size="1" name="P0_25FEI" description="Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="26" size="1" name="P0_26FEI" description="Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="27" size="1" name="P0_27FEI" description="Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="28" size="1" name="P0_28FEI" description="Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="29" size="1" name="P0_29FEI" description="Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="30" size="1" name="P0_30FEI" description="Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="31" size="1" name="P0_31FEI" description="Status of Falling Edge Interrupt for P0[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CLR0" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P0_0CI" description="Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="1" size="1" name="P0_1CI" description="Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="2" size="1" name="P0_2CI" description="Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="3" size="1" name="P0_3CI" description="Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="4" size="1" name="P0_4CI" description="Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="5" size="1" name="P0_5CI" description="Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="6" size="1" name="P0_6CI" description="Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="7" size="1" name="P0_7CI" description="Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="8" size="1" name="P0_8CI" description="Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="9" size="1" name="P0_9CI" description="Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="10" size="1" name="P0_10CI" description="Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="11" size="1" name="P0_11CI" description="Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="12" size="1" name="P0_12CI" description="Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="13" size="1" name="P0_13CI" description="Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="14" size="1" name="P0_14CI" description="Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="15" size="1" name="P0_15CI" description="Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="16" size="1" name="P0_16CI" description="Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="17" size="1" name="P0_17CI" description="Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="18" size="1" name="P0_18CI" description="Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="19" size="1" name="P0_19CI" description="Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="20" size="1" name="P0_20CI" description="Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="21" size="1" name="P0_21CI" description="Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="22" size="1" name="P0_22CI" description="Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="23" size="1" name="P0_23CI" description="Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="24" size="1" name="P0_24CI" description="Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="25" size="1" name="P0_25CI" description="Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="26" size="1" name="P0_26CI" description="Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="27" size="1" name="P0_27CI" description="Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="28" size="1" name="P0_28CI" description="Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="29" size="1" name="P0_29CI" description="Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="30" size="1" name="P0_30CI" description="Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="31" size="1" name="P0_31CI" description="Clear GPIO port Interrupts for P0[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+    </Register>
+    <Register start="+0x010" size="4" name="ENR0" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P0_0ER" description="Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="1" size="1" name="P0_1ER" description="Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="2" size="1" name="P0_2ER" description="Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="3" size="1" name="P0_3ER" description="Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="4" size="1" name="P0_4ER" description="Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="5" size="1" name="P0_5ER" description="Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="6" size="1" name="P0_6ER" description="Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="7" size="1" name="P0_7ER" description="Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="8" size="1" name="P0_8ER" description="Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="9" size="1" name="P0_9ER" description="Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="10" size="1" name="P0_10ER" description="Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="11" size="1" name="P0_11ER" description="Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="12" size="1" name="P0_12ER" description="Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="13" size="1" name="P0_13ER" description="Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="14" size="1" name="P0_14ER" description="Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="15" size="1" name="P0_15ER" description="Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="16" size="1" name="P0_16ER" description="Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="17" size="1" name="P0_17ER" description="Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="18" size="1" name="P0_18ER" description="Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="19" size="1" name="P0_19ER" description="Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="20" size="1" name="P0_20ER" description="Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="21" size="1" name="P0_21ER" description="Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="22" size="1" name="P0_22ER" description="Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="23" size="1" name="P0_23ER" description="Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="24" size="1" name="P0_24ER" description="Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="25" size="1" name="P0_25ER" description="Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="26" size="1" name="P0_26ER" description="Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="27" size="1" name="P0_27ER" description="Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="28" size="1" name="P0_28ER" description="Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="29" size="1" name="P0_29ER" description="Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="30" size="1" name="P0_30ER" description="Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="31" size="1" name="P0_31ER" description="Enable rising edge interrupt for P0[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+    </Register>
+    <Register start="+0x014" size="4" name="ENF0" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P0_0EF" description="Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="1" size="1" name="P0_1EF" description="Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="2" size="1" name="P0_2EF" description="Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="3" size="1" name="P0_3EF" description="Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="4" size="1" name="P0_4EF" description="Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="5" size="1" name="P0_5EF" description="Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="6" size="1" name="P0_6EF" description="Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="7" size="1" name="P0_7EF" description="Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="8" size="1" name="P0_8EF" description="Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="9" size="1" name="P0_9EF" description="Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="10" size="1" name="P0_10EF" description="Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="11" size="1" name="P0_11EF" description="Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="12" size="1" name="P0_12EF" description="Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="13" size="1" name="P0_13EF" description="Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="14" size="1" name="P0_14EF" description="Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="15" size="1" name="P0_15EF" description="Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="16" size="1" name="P0_16EF" description="Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="17" size="1" name="P0_17EF" description="Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="18" size="1" name="P0_18EF" description="Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="19" size="1" name="P0_19EF" description="Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="20" size="1" name="P0_20EF" description="Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="21" size="1" name="P0_21EF" description="Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="22" size="1" name="P0_22EF" description="Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="23" size="1" name="P0_23EF" description="Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="24" size="1" name="P0_24EF" description="Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="25" size="1" name="P0_25EF" description="Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="26" size="1" name="P0_26EF" description="Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="27" size="1" name="P0_27EF" description="Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="28" size="1" name="P0_28EF" description="Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="29" size="1" name="P0_29EF" description="Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="30" size="1" name="P0_30EF" description="Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="31" size="1" name="P0_31EF" description="Enable falling edge interrupt for P0[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+    </Register>
+    <Register start="+0x024" size="4" name="STATR2" access="ReadOnly" description="GPIO Interrupt Status for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P2_0REI" description="Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="1" size="1" name="P2_1REI" description="Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="2" size="1" name="P2_2REI" description="Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="3" size="1" name="P2_3REI" description="Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="4" size="1" name="P2_4REI" description="Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="5" size="1" name="P2_5REI" description="Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="6" size="1" name="P2_6REI" description="Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="7" size="1" name="P2_7REI" description="Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="8" size="1" name="P2_8REI" description="Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="9" size="1" name="P2_9REI" description="Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="10" size="1" name="P2_10REI" description="Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="11" size="1" name="P2_11REI" description="Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="12" size="1" name="P2_12REI" description="Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="13" size="1" name="P2_13REI" description="Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="14" size="1" name="P2_14REI" description="Status of Rising Edge Interrupt for P2[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="15" size="1" name="P2_15REI" description="Status of Rising Edge Interrupt for P2[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="16" size="1" name="P2_16REI" description="Status of Rising Edge Interrupt for P2[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="17" size="1" name="P2_17REI" description="Status of Rising Edge Interrupt for P2[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="18" size="1" name="P2_18REI" description="Status of Rising Edge Interrupt for P2[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="19" size="1" name="P2_19REI" description="Status of Rising Edge Interrupt for P2[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="20" size="1" name="P2_20REI" description="Status of Rising Edge Interrupt for P2[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="21" size="1" name="P2_21REI" description="Status of Rising Edge Interrupt for P2[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="22" size="1" name="P2_22REI" description="Status of Rising Edge Interrupt for P2[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="23" size="1" name="P2_23REI" description="Status of Rising Edge Interrupt for P2[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="24" size="1" name="P2_24REI" description="Status of Rising Edge Interrupt for P2[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="25" size="1" name="P2_25REI" description="Status of Rising Edge Interrupt for P2[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="26" size="1" name="P2_26REI" description="Status of Rising Edge Interrupt for P2[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="27" size="1" name="P2_27REI" description="Status of Rising Edge Interrupt for P2[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="28" size="1" name="P2_28REI" description="Status of Rising Edge Interrupt for P2[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="29" size="1" name="P2_29REI" description="Status of Rising Edge Interrupt for P2[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="30" size="1" name="P2_30REI" description="Status of Rising Edge Interrupt for P2[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+      <BitField start="31" size="1" name="P2_31REI" description="Status of Rising Edge Interrupt for P2[31]. 0 = No rising edge detected. 1 = Rising edge interrupt generated." />
+    </Register>
+    <Register start="+0x028" size="4" name="STATF2" access="ReadOnly" description="GPIO Interrupt Status for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P2_0FEI" description="Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="1" size="1" name="P2_1FEI" description="Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="2" size="1" name="P2_2FEI" description="Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="3" size="1" name="P2_3FEI" description="Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="4" size="1" name="P2_4FEI" description="Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="5" size="1" name="P2_5FEI" description="Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="6" size="1" name="P2_6FEI" description="Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="7" size="1" name="P2_7FEI" description="Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="8" size="1" name="P2_8FEI" description="Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="9" size="1" name="P2_9FEI" description="Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="10" size="1" name="P2_10FEI" description="Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="11" size="1" name="P2_11FEI" description="Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="12" size="1" name="P2_12FEI" description="Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="13" size="1" name="P2_13FEI" description="Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="14" size="1" name="P2_14FEI" description="Status of Falling Edge Interrupt for P2[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="15" size="1" name="P2_15FEI" description="Status of Falling Edge Interrupt for P2[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="16" size="1" name="P2_16FEI" description="Status of Falling Edge Interrupt for P2[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="17" size="1" name="P2_17FEI" description="Status of Falling Edge Interrupt for P2[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="18" size="1" name="P2_18FEI" description="Status of Falling Edge Interrupt for P2[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="19" size="1" name="P2_19FEI" description="Status of Falling Edge Interrupt for P2[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="20" size="1" name="P2_20FEI" description="Status of Falling Edge Interrupt for P2[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="21" size="1" name="P2_21FEI" description="Status of Falling Edge Interrupt for P2[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="22" size="1" name="P2_22FEI" description="Status of Falling Edge Interrupt for P2[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="23" size="1" name="P2_23FEI" description="Status of Falling Edge Interrupt for P2[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="24" size="1" name="P2_24FEI" description="Status of Falling Edge Interrupt for P2[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="25" size="1" name="P2_25FEI" description="Status of Falling Edge Interrupt for P2[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="26" size="1" name="P2_26FEI" description="Status of Falling Edge Interrupt for P2[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="27" size="1" name="P2_27FEI" description="Status of Falling Edge Interrupt for P2[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="28" size="1" name="P2_28FEI" description="Status of Falling Edge Interrupt for P2[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="29" size="1" name="P2_29FEI" description="Status of Falling Edge Interrupt for P2[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="30" size="1" name="P2_30FEI" description="Status of Falling Edge Interrupt for P2[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+      <BitField start="31" size="1" name="P2_31FEI" description="Status of Falling Edge Interrupt for P2[31]. 0 = No falling edge detected. 1 = Falling edge interrupt generated." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CLR2" access="WriteOnly" description="GPIO Interrupt Clear." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P2_0CI" description="Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="1" size="1" name="P2_1CI" description="Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="2" size="1" name="P2_2CI" description="Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="3" size="1" name="P2_3CI" description="Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="4" size="1" name="P2_4CI" description="Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="5" size="1" name="P2_5CI" description="Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="6" size="1" name="P2_6CI" description="Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="7" size="1" name="P2_7CI" description="Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="8" size="1" name="P2_8CI" description="Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="9" size="1" name="P2_9CI" description="Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="10" size="1" name="P2_10CI" description="Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="11" size="1" name="P2_11CI" description="Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="12" size="1" name="P2_12CI" description="Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="13" size="1" name="P2_13CI" description="Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="14" size="1" name="P2_14CI" description="Clear GPIO port Interrupts for P2[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="15" size="1" name="P2_15CI" description="Clear GPIO port Interrupts for P2[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="16" size="1" name="P2_16CI" description="Clear GPIO port Interrupts for P2[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="17" size="1" name="P2_17CI" description="Clear GPIO port Interrupts for P2[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="18" size="1" name="P2_18CI" description="Clear GPIO port Interrupts for P2[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="19" size="1" name="P2_19CI" description="Clear GPIO port Interrupts for P2[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="20" size="1" name="P2_20CI" description="Clear GPIO port Interrupts for P2[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="21" size="1" name="P2_21CI" description="Clear GPIO port Interrupts for P2[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="22" size="1" name="P2_22CI" description="Clear GPIO port Interrupts for P2[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="23" size="1" name="P2_23CI" description="Clear GPIO port Interrupts for P2[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="24" size="1" name="P2_24CI" description="Clear GPIO port Interrupts for P2[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="25" size="1" name="P2_25CI" description="Clear GPIO port Interrupts for P2[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="26" size="1" name="P2_26CI" description="Clear GPIO port Interrupts for P2[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="27" size="1" name="P2_27CI" description="Clear GPIO port Interrupts for P2[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="28" size="1" name="P2_28CI" description="Clear GPIO port Interrupts for P2[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="29" size="1" name="P2_29CI" description="Clear GPIO port Interrupts for P2[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="30" size="1" name="P2_30CI" description="Clear GPIO port Interrupts for P2[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+      <BitField start="31" size="1" name="P2_31CI" description="Clear GPIO port Interrupts for P2[31]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF." />
+    </Register>
+    <Register start="+0x030" size="4" name="ENR2" access="Read/Write" description="GPIO Interrupt Enable for Rising edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P2_0ER" description="Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="1" size="1" name="P2_1ER" description="Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="2" size="1" name="P2_2ER" description="Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="3" size="1" name="P2_3ER" description="Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="4" size="1" name="P2_4ER" description="Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="5" size="1" name="P2_5ER" description="Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="6" size="1" name="P2_6ER" description="Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="7" size="1" name="P2_7ER" description="Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="8" size="1" name="P2_8ER" description="Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="9" size="1" name="P2_9ER" description="Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="10" size="1" name="P2_10ER" description="Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="11" size="1" name="P2_11ER" description="Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="12" size="1" name="P2_12ER" description="Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="13" size="1" name="P2_13ER" description="Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="14" size="1" name="P2_14ER" description="Enable rising edge interrupt for P2[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="15" size="1" name="P2_15ER" description="Enable rising edge interrupt for P2[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="16" size="1" name="P2_16ER" description="Enable rising edge interrupt for P2[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="17" size="1" name="P2_17ER" description="Enable rising edge interrupt for P2[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="18" size="1" name="P2_18ER" description="Enable rising edge interrupt for P2[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="19" size="1" name="P2_19ER" description="Enable rising edge interrupt for P2[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="20" size="1" name="P2_20ER" description="Enable rising edge interrupt for P2[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="21" size="1" name="P2_21ER" description="Enable rising edge interrupt for P2[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="22" size="1" name="P2_22ER" description="Enable rising edge interrupt for P2[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="23" size="1" name="P2_23ER" description="Enable rising edge interrupt for P2[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="24" size="1" name="P2_24ER" description="Enable rising edge interrupt for P2[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="25" size="1" name="P2_25ER" description="Enable rising edge interrupt for P2[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="26" size="1" name="P2_26ER" description="Enable rising edge interrupt for P2[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="27" size="1" name="P2_27ER" description="Enable rising edge interrupt for P2[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="28" size="1" name="P2_28ER" description="Enable rising edge interrupt for P2[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="29" size="1" name="P2_29ER" description="Enable rising edge interrupt for P2[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="30" size="1" name="P2_30ER" description="Enable rising edge interrupt for P2[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+      <BitField start="31" size="1" name="P2_31ER" description="Enable rising edge interrupt for P2[31]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt." />
+    </Register>
+    <Register start="+0x034" size="4" name="ENF2" access="Read/Write" description="GPIO Interrupt Enable for Falling edge for Port 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="P2_0EF" description="Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="1" size="1" name="P2_1EF" description="Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="2" size="1" name="P2_2EF" description="Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="3" size="1" name="P2_3EF" description="Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="4" size="1" name="P2_4EF" description="Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="5" size="1" name="P2_5EF" description="Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="6" size="1" name="P2_6EF" description="Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="7" size="1" name="P2_7EF" description="Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="8" size="1" name="P2_8EF" description="Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="9" size="1" name="P2_9EF" description="Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="10" size="1" name="P2_10EF" description="Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="11" size="1" name="P2_11EF" description="Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="12" size="1" name="P2_12EF" description="Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="13" size="1" name="P2_13EF" description="Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="14" size="1" name="P2_14EF" description="Enable falling edge interrupt for P2[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="15" size="1" name="P2_15EF" description="Enable falling edge interrupt for P2[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="16" size="1" name="P2_16EF" description="Enable falling edge interrupt for P2[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="17" size="1" name="P2_17EF" description="Enable falling edge interrupt for P2[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="18" size="1" name="P2_18EF" description="Enable falling edge interrupt for P2[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="19" size="1" name="P2_19EF" description="Enable falling edge interrupt for P2[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="20" size="1" name="P2_20EF" description="Enable falling edge interrupt for P2[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="21" size="1" name="P2_21EF" description="Enable falling edge interrupt for P2[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="22" size="1" name="P2_22EF" description="Enable falling edge interrupt for P2[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="23" size="1" name="P2_23EF" description="Enable falling edge interrupt for P2[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="24" size="1" name="P2_24EF" description="Enable falling edge interrupt for P2[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="25" size="1" name="P2_25EF" description="Enable falling edge interrupt for P2[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="26" size="1" name="P2_26EF" description="Enable falling edge interrupt for P2[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="27" size="1" name="P2_27EF" description="Enable falling edge interrupt for P2[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="28" size="1" name="P2_28EF" description="Enable falling edge interrupt for P2[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="29" size="1" name="P2_29EF" description="Enable falling edge interrupt for P2[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="30" size="1" name="P2_30EF" description="Enable falling edge interrupt for P2[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+      <BitField start="31" size="1" name="P2_31EF" description="Enable falling edge interrupt for P2[31]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IOCON" start="0x4002C000" description="IOCON pin configuration">
+    <Register start="+0x0" size="4" name="P0_0" access="Read/Write" description="I/O configuration register for pin P0[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[0]">
+        <Enum name="P0_0" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="CAN_RD1" start="0x1" description="CAN1 receiver input." />
+        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
+        <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="U0_TXD" start="0x4" description="Transmitter output for UART0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x4" size="4" name="P0_1" access="Read/Write" description="I/O configuration register for pin P0[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[1]">
+        <Enum name="P0_1" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="CAN_TD1" start="0x1" description="CAN1 transmitter output." />
+        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
+        <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="U0_RXD" start="0x4" description="Receiver input for UART0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x8" size="4" name="P0_2" access="Read/Write" description="I/O configuration register for pin P0[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[2]">
+        <Enum name="P0_2" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U0_TXD" start="0x1" description="Transmitter output for UART0." />
+        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xC" size="4" name="P0_3" access="Read/Write" description="I/O configuration register for pin P0[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[3]">
+        <Enum name="P0_3" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U0_RXD" start="0x1" description="Receiver input for UART0." />
+        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x10" size="4" name="P0_4" access="Read/Write" description="I/O configuration register for pin P0[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[4]">
+        <Enum name="P0_4" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2S_RX_SCK" start="0x1" description="I2S Receive clock. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal SCK in the                                             I2S-bus                                         specification." />
+        <Enum name="CAN_RD2" start="0x2" description="CAN2 receiver input." />
+        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
+        <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer                                 applications." />
+        <Enum name="LCD_VD_0" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x14" size="4" name="P0_5" access="Read/Write" description="I/O configuration register for pin P0[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[5]">
+        <Enum name="P0_5" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2S_RX_WS" start="0x1" description="I2S Receive word select. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal WS in the                                             I2S-bus                                         specification." />
+        <Enum name="CAN_TD2" start="0x2" description="CAN2 transmitter output." />
+        <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." />
+        <Enum name="CMP_RESET" start="0x5" description="Comparator reset." />
+        <Enum name="LCD_VD_1" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x18" size="4" name="P0_6" access="Read/Write" description="I/O configuration register for pin P0[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[6]">
+        <Enum name="P0_6" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2S_RX_SDA" start="0x1" description="I2S Receive data. It is driven                                     by the transmitter and read by the receiver. Corresponds to the                                     signal SD in the                                             I2S-bus                                         specification." />
+        <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." />
+        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
+        <Enum name="U1_RTS" start="0x4" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+        <Enum name="CMP_ROSC" start="0x5" description="Comparator relaxation oscillator for 555 timer                                 applications." />
+        <Enum name="LCD_VD_8" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1C" size="4" name="P0_7" access="Read/Write" description="I/O configuration register for pin P0[7] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[7] ">
+        <Enum name="P0_7" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2S_TX_SCK" start="0x1" description="I2S transmit clock. It is                                     driven by the master and received by the slave. Corresponds to                                     the signal SCK in the                                             I2S-bus                                         specification." />
+        <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." />
+        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
+        <Enum name="RTC_EV0" start="0x4" description="Event input 0 to Event Monitor/Recorder." />
+        <Enum name="CMP_VREF" start="0x5" description="Comparator reference voltage." />
+        <Enum name="LCD_VD_9" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
+        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
+        <Enum name="DISABLED" start="1" description="No input filtering is done." />
+      </BitField>
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x20" size="4" name="P0_8" access="Read/Write" description="I/O configuration register for pin P0[8] " reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[8] ">
+        <Enum name="P0_8" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2S_TX_WS" start="0x1" description="I2S Transmit word select. It                                     is driven by the master and received by the slave. Corresponds                                     to the signal WS in the                                             I2S-bus                                         specification." />
+        <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." />
+        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
+        <Enum name="RTC_EV1" start="0x4" description="Event input 1 to Event Monitor/Recorder." />
+        <Enum name="CMP1_IN_3" start="0x5" description="Comparator 1, input 3." />
+        <Enum name="LCD_VD_16" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
+        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
+        <Enum name="DISABLED" start="1" description="No input filtering is done." />
+      </BitField>
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x24" size="4" name="P0_9" access="Read/Write" description="I/O configuration register for pin P0[9]" reset_value="0x000000A0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[9]">
+        <Enum name="P0_9" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2S_TX_SDA" start="0x1" description="I2S transmit data. It is                                     driven by the transmitter and read by the receiver. Corresponds                                     to the signal SD in the                                             I2S-bus                                         specification." />
+        <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." />
+        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
+        <Enum name="RTC_EV2" start="0x4" description="Event input 2 to Event Monitor/Recorder." />
+        <Enum name="CMP1_IN_2" start="0x5" description="Comparator 1, input 2." />
+        <Enum name="LCD_VD_17" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="FILTER" description="Glitch filter control">
+        <Enum name="ENABLED" start="0" description="Noise pulses below approximately 10 ns are filtered&#xa;                                out." />
+        <Enum name="DISABLED" start="1" description="No input filtering is done." />
+      </BitField>
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x28" size="4" name="P0_10" access="Read/Write" description="I/O configuration register for pin P0[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[10]">
+        <Enum name="P0_10" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U2_TXD" start="0x1" description="Transmitter output for UART2." />
+        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
+        <Enum name="LCD_VD_5" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x2C" size="4" name="P0_11" access="Read/Write" description="I/O configuration register for pin P0[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[11]">
+        <Enum name="P0_11" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U2_RXD" start="0x1" description="Receiver input for UART2." />
+        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
+        <Enum name="LCD_VD_10" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x30" size="4" name="P0_12" access="Read/Write" description="I/O configuration register for pin P0[12]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[12]">
+        <Enum name="P0_12" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_PPWR2" start="0x1" description="Port Power enable signal for USB port 2." />
+        <Enum name="SSP1_MISO" start="0x2" description="Master In Slave Out for SSP1." />
+        <Enum name="ADC0_IN_6" start="0x3" description="A/D converter 0, input 6. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x34" size="4" name="P0_13" access="Read/Write" description="I/O configuration register for pin P0[13]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[13]">
+        <Enum name="P0_13" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_UP_LED2" start="0x1" description="USB port 2 GoodLink LED indicator. It is LOW when the                                     device is configured (non-control endpoints enabled), or when                                     the host is enabled and has detected a device on the bus. It is                                     HIGH when the device is not configured, or when host is enabled                                     and has not detected a device on the bus, or during global                                     suspend. It transitions between LOW and HIGH (flashes) when the                                     host is enabled and detects activity on the bus." />
+        <Enum name="SSP1_MOSI" start="0x2" description="Master Out Slave In for SSP1." />
+        <Enum name="ADC0_IN_7" start="0x3" description="A/D converter 0, input 7. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x38" size="4" name="P0_14" access="Read/Write" description="I/O configuration register for pin P0[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[14]">
+        <Enum name="P0_14" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_HSTEN2" start="0x1" description="Host Enabled status for USB port 2." />
+        <Enum name="SSP1_SSEL" start="0x2" description="Slave Select for SSP1." />
+        <Enum name="USB_CONNECT2" start="0x3" description="SoftConnect control for USB port 2. Signal used to switch                                     an external 1.5 kW resistor under                                     software control. Used with the SoftConnect USB                                     feature." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x3C" size="4" name="P0_15" access="Read/Write" description="I/O configuration register for pin P0[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[15]">
+        <Enum name="P0_15" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_TXD" start="0x1" description="Transmitter output for UART1." />
+        <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." />
+        <Enum name="SPIFI_IO_2" start="0x5" description="Data bit 0 for SPIFI." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x40" size="4" name="P0_16" access="Read/Write" description="I/O configuration register for pin P0[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[16]">
+        <Enum name="P0_16" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_RXD" start="0x1" description="Receiver input for UART1." />
+        <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." />
+        <Enum name="SPIFI_IO_3" start="0x5" description="Data bit 0 for SPIFI." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x44" size="4" name="P0_17" access="Read/Write" description="I/O configuration register for pin P0[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[17]">
+        <Enum name="P0_17" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_CTS" start="0x1" description="Clear to Send input for UART1." />
+        <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." />
+        <Enum name="SPIFI_IO_1" start="0x5" description="Data bit 0 for SPIFI." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x48" size="4" name="P0_18" access="Read/Write" description="I/O configuration register for pin P0[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[18]">
+        <Enum name="P0_18" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_DCD" start="0x1" description="Data Carrier Detect input for UART1." />
+        <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." />
+        <Enum name="SPIFI_IO_0" start="0x5" description="Data bit 0 for SPIFI." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x4C" size="4" name="P0_19" access="Read/Write" description="I/O configuration register for pin P0[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[19]">
+        <Enum name="P0_19" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_DSR" start="0x1" description="Data Set Ready input for UART1." />
+        <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." />
+        <Enum name="I2C1_SDA" start="0x3" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="LCD_VD_13" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x50" size="4" name="P0_20" access="Read/Write" description="I/O configuration register for pin P0[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[20]">
+        <Enum name="P0_20" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_DTR" start="0x1" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+        <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." />
+        <Enum name="I2C1_SCL" start="0x3" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="LCD_VD_14" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x54" size="4" name="P0_21" access="Read/Write" description="I/O configuration register for pin P0[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[21]">
+        <Enum name="P0_21" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_RI" start="0x1" description="Ring Indicator input for UART1." />
+        <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power                                     supply." />
+        <Enum name="U4_OE" start="0x3" description="RS-485/EIA-485 output enable signal for                                     UART4." />
+        <Enum name="CAN_RD1" start="0x4" description="CAN1 receiver input." />
+        <Enum name="U4_SCLK" start="0x5" description="USART 4 clock input or output in synchronous                                     mode." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x58" size="4" name="P0_22" access="Read/Write" description="I/O configuration register for pin P0[22]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[22]">
+        <Enum name="P0_22" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U1_RTS" start="0x1" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+        <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." />
+        <Enum name="U4_TXD" start="0x3" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
+        <Enum name="CAN_TD1" start="0x4" description="CAN1 transmitter output." />
+        <Enum name="SPIFI_CLK" start="0x5" description="Clock output for SPIFI." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
+        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x5C" size="4" name="P0_23" access="Read/Write" description="I/O configuration register for pin P0[23]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[23]">
+        <Enum name="P0_23" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ADC0_IN_0" start="0x1" description="A/D converter 0, input 0. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+        <Enum name="I2S_RX_SCK" start="0x2" description="Receive Clock. It is driven by the master and received by                                     the slave. Corresponds to the signal SCK in the                                             I2S-bus                                         specification." />
+        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
+      </BitField>
+    </Register>
+    <Register start="+0x60" size="4" name="P0_24" access="Read/Write" description="I/O configuration register for pin P0[24]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[24]">
+        <Enum name="P0_24" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ADC0_IN_1" start="0x1" description="A/D converter 0, input 1. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+        <Enum name="I2S_RX_WS" start="0x2" description="Receive Word Select. It is driven by the master and                                     received by the slave. Corresponds to the signal WS in the                                             I2S-bus                                         specification." />
+        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
+      </BitField>
+    </Register>
+    <Register start="+0x64" size="4" name="P0_25" access="Read/Write" description="I/O configuration register for pin P0[25]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[25]">
+        <Enum name="P0_25" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ADC0_IN_2" start="0x1" description="A/D converter 0, input 2. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+        <Enum name="I2S_RX_SDA" start="0x2" description="Receive data. It is driven by the transmitter and read by                                     the receiver. Corresponds to the signal SD in the                                             I2S-bus                                         specification." />
+        <Enum name="U3_TXD" start="0x3" description="Transmitter output for UART3." />
+      </BitField>
+    </Register>
+    <Register start="+0x68" size="4" name="P0_26" access="Read/Write" description="I/O configuration register for pin P0[26]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[26]">
+        <Enum name="P0_26" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ADC0_IN_3" start="0x1" description="A/D converter 0, input 3. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+        <Enum name="DAC_OUT" start="0x2" description="D/A converter output. When configured as the DAC output,                                     the digital function of the pin must be disabled." />
+        <Enum name="U3_RXD" start="0x3" description="Receiver input for UART3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
+        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
+      </BitField>
+      <BitField start="11" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="1" name="DACEN" description="DAC output enable.">
+        <Enum name="DISABLE" start="0" description="DAC disable." />
+        <Enum name="ENABLE" start="1" description="DAC enable." />
+      </BitField>
+      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x6C" size="4" name="P0_27" access="Read/Write" description="I/O configuration register for pin P0[27]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[27]">
+        <Enum name="P0_27" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2C0_SDA" start="0x1" description="I2C0 data input/output. (This                                     pin uses a specialized I2C pad)." />
+        <Enum name="USB_SDA1" start="0x2" description="I2C serial data for communication with an external USB                                     transceiver." />
+      </BitField>
+      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
+        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
+        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
+        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
+        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x70" size="4" name="P0_28" access="Read/Write" description="I/O configuration register for pin P0[28]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[28]">
+        <Enum name="P0_28" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="I2C0_SCL" start="0x1" description="I2C0 clock input/output (this                                     pin uses a specialized I2C pad." />
+        <Enum name="USB_SCL1" start="0x2" description="I2C serial clock for communication with an external USB                                     transceiver." />
+      </BitField>
+      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
+        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
+        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
+        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
+        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x74" size="4" name="P0_29" access="Read/Write" description="I/O configuration register for pin P0[29]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[29]">
+        <Enum name="P0_29" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_DP1" start="0x1" description="USB port 1 bidirectional D+ line." />
+        <Enum name="EINT0" start="0x2" description="External interrupt 0 input." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x78" size="4" name="P0_30" access="Read/Write" description="I/O configuration register for pin P0[30]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[30]">
+        <Enum name="P0_30" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_DM1" start="0x1" description="USB port 1 bidirectional D-                                     line." />
+        <Enum name="EINT1" start="0x2" description="External interrupt 1 input." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x7C" size="4" name="P0_31" access="Read/Write" description="I/O configuration register for pin P0[31]" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P0[31]">
+        <Enum name="P0_31" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_DP2" start="0x1" description="USB port 2 bidirectional D+ line." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x80" size="4" name="P1_0" access="Read/Write" description="I/O configuration register for pin P1[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[0]">
+        <Enum name="P1_0" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TXD0" start="0x1" description="Ethernet transmit data 0 (RMII/MII                                     interface)." />
+        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
+        <Enum name="SSP2_SCK" start="0x4" description="Serial clock for SSP2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x84" size="4" name="P1_1" access="Read/Write" description="I/O configuration register for pin P1[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[1]">
+        <Enum name="P1_1" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TXD1" start="0x1" description="Ethernet transmit data 1 (RMII/MII                                     interface)." />
+        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
+        <Enum name="SSP2_MOSI" start="0x4" description="Master Out Slave In for SSP2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x88" size="4" name="P1_2" access="Read/Write" description="I/O configuration register for pin P1[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[2]">
+        <Enum name="P1_2" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TXD2" start="0x1" description="Ethernet transmit data 2 (MII interface)." />
+        <Enum name="SD_CLK" start="0x2" description="Clock output line for SD card interface." />
+        <Enum name="PWM0_1" start="0x3" description="Pulse Width Modulator 0, output 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x8C" size="4" name="P1_3" access="Read/Write" description="I/O configuration register for pin P1[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[3]">
+        <Enum name="P1_3" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TXD3" start="0x1" description="Ethernet transmit data 3 (MII interface)." />
+        <Enum name="SD_CMD" start="0x2" description="Command line for SD card interface." />
+        <Enum name="PWM0_2" start="0x3" description="Pulse Width Modulator 0, output 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x90" size="4" name="P1_4" access="Read/Write" description="I/O configuration register for pin P1[4] " reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[4] ">
+        <Enum name="P1_4" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TX_EN" start="0x1" description="Ethernet transmit data enable (RMII/MII                                     interface)." />
+        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
+        <Enum name="SSP2_MISO" start="0x4" description="Master In Slave Out for SSP2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x94" size="4" name="P1_5" access="Read/Write" description="I/O configuration register for pin P1[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[5]">
+        <Enum name="P1_5" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TX_ER" start="0x1" description="Ethernet Transmit Error (MII interface)." />
+        <Enum name="SD_PWR" start="0x2" description="Power Supply Enable for external SD card power                                     supply." />
+        <Enum name="PWM0_3" start="0x3" description="Pulse Width Modulator 0, output 3." />
+        <Enum name="CMP1_IN_1" start="0x5" description="Comparator 1, input 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x98" size="4" name="P1_6" access="Read/Write" description="I/O configuration register for pin P1[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[6]">
+        <Enum name="P1_6" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_TX_CLK" start="0x1" description="Ethernet Transmit Clock (MII interface)." />
+        <Enum name="SD_DAT_0" start="0x2" description="Data line 0 for SD card interface." />
+        <Enum name="PWM0_4" start="0x3" description="Pulse Width Modulator 0, output 4." />
+        <Enum name="CMP0_IN_3" start="0x5" description="Comparator 0, input 3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x9C" size="4" name="P1_7" access="Read/Write" description="I/O configuration register for pin P1[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[7]">
+        <Enum name="P1_7" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_COL" start="0x1" description="Ethernet Collision detect (MII interface)." />
+        <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." />
+        <Enum name="PWM0_5" start="0x3" description="Pulse Width Modulator 0, output 5." />
+        <Enum name="CMP1_IN_0" start="0x5" description="Comparator 1, input 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xA0" size="4" name="P1_8" access="Read/Write" description="I/O configuration register for pin P1[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[8]">
+        <Enum name="P1_8" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_CRS_CRS_DV" start="0x1" description="Ethernet Carrier Sense (MII interface) or Ethernet                                     Carrier Sense/Data Valid (RMII interface)." />
+        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
+        <Enum name="SSP2_SSEL" start="0x4" description="Slave Select for SSP2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xA4" size="4" name="P1_9" access="Read/Write" description="I/O configuration register for pin P1[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[9]">
+        <Enum name="P1_9" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RXD0" start="0x1" description="Ethernet receive data 0 (RMII/MII interface)." />
+        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xA8" size="4" name="P1_10" access="Read/Write" description="I/O configuration register for pin P1[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[10]">
+        <Enum name="P1_10" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RXD1" start="0x1" description="Ethernet receive data 1 (RMII/MII interface)." />
+        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xAC" size="4" name="P1_11" access="Read/Write" description="I/O configuration register for pin P1[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[11]">
+        <Enum name="P1_11" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RXD2" start="0x1" description="Ethernet Receive Data 2 (MII interface)." />
+        <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." />
+        <Enum name="PWM0_6" start="0x3" description="Pulse Width Modulator 0, output 6." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xB0" size="4" name="P1_12" access="Read/Write" description="I/O configuration register for pin P1[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[12]">
+        <Enum name="P1_12" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RXD3" start="0x1" description="Ethernet Receive Data (MII interface)." />
+        <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." />
+        <Enum name="PWM0_CAP0" start="0x3" description="Capture input for PWM0, channel 0." />
+        <Enum name="CMP1_OUT" start="0x5" description="Comparator 1, output." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xB4" size="4" name="P1_13" access="Read/Write" description="I/O configuration register for pin P1[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[13]">
+        <Enum name="P1_13" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RX_DV" start="0x1" description="Ethernet Receive Data Valid (MII interface)." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xB8" size="4" name="P1_14" access="Read/Write" description="I/O configuration register for pin P1[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[14]">
+        <Enum name="P1_14" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RX_ER" start="0x1" description="Ethernet receive error (RMII/MII interface)." />
+        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
+        <Enum name="CMP0_IN_0" start="0x5" description="Comparator 0, input 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xBC" size="4" name="P1_15" access="Read/Write" description="I/O configuration register for pin P1[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[15]">
+        <Enum name="P1_15" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_RX_CLK_REF_CLK" start="0x1" description="Ethernet Receive Clock (MII interface) or Ethernet                                     Reference Clock (RMII interface)." />
+        <Enum name="I2C2_SDA" start="0x3" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xC0" size="4" name="P1_16" access="Read/Write" description="I/O configuration register for pin P1[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[16]">
+        <Enum name="P1_16" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_MDC" start="0x1" description="Ethernet MIIM clock." />
+        <Enum name="I2S_TX_MCLK" start="0x2" description="I2S transmit master clock." />
+        <Enum name="CMP0_IN_1" start="0x5" description="Comparator 0, input 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xC4" size="4" name="P1_17" access="Read/Write" description="I/O configuration register for pin P1[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[17]">
+        <Enum name="P1_17" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="ENET_MDIO" start="0x1" description="Ethernet MIIM data input and output." />
+        <Enum name="I2S_RX_MCLK" start="0x2" description="I2S receive master clock." />
+        <Enum name="CMP0_IN_2" start="0x5" description="Comparator 0, input 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xC8" size="4" name="P1_18" access="Read/Write" description="I/O configuration register for pin P1[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[18]">
+        <Enum name="P1_18" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_UP_LED1" start="0x1" description="It is LOW when the device is configured (non-control                                     endpoints enabled), or when the host is enabled and has detected                                     a device on the bus. It is HIGH when the device is not                                     configured, or when host is enabled and has not detected a                                     device on the bus, or during global suspend. It transitions                                     between LOW and HIGH (flashes) when the host is enabled and                                     detects activity on the bus." />
+        <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, channel 1 output." />
+        <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." />
+        <Enum name="SSP1_MISO" start="0x5" description="Master In Slave Out for SSP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xCC" size="4" name="P1_19" access="Read/Write" description="I/O configuration register for pin P1[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[19]">
+        <Enum name="P1_19" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_TX_E1" start="0x1" description="Transmit Enable signal for USB port 1 (OTG                                     transceiver)." />
+        <Enum name="USB_PPWR1" start="0x2" description="Port Power enable signal for USB port 1." />
+        <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." />
+        <Enum name="MC_0A" start="0x4" description="Motor control PWM channel 0, output A." />
+        <Enum name="SSP1_SCK" start="0x5" description="Serial clock for SSP1." />
+        <Enum name="U2_OE" start="0x6" description="RS-485/EIA-485 output enable signal for                                     UART2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xD0" size="4" name="P1_20" access="Read/Write" description="I/O configuration register for pin P1[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[20]">
+        <Enum name="P1_20" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_TX_DP1" start="0x1" description="D+ transmit data for USB port 1 (OTG                                     transceiver)." />
+        <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, channel 2 output." />
+        <Enum name="QEI_PHA" start="0x3" description="Quadrature Encoder Interface PHA input." />
+        <Enum name="MC_FB0" start="0x4" description="Motor control PWM channel 0 feedback input." />
+        <Enum name="SSP0_SCK" start="0x5" description="Serial clock for SSP0." />
+        <Enum name="LCD_VD_6" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_10" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xD4" size="4" name="P1_21" access="Read/Write" description="I/O configuration register for pin P1[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[21]">
+        <Enum name="P1_21" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_TX_DM1" start="0x1" description="D- transmit data for USB port                                     1 (OTG transceiver)." />
+        <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, channel 3 output." />
+        <Enum name="SSP0_SSEL" start="0x3" description="Slave Select for SSP0." />
+        <Enum name="MC_ABORT" start="0x4" description="Motor control PWM, active low fast abort." />
+        <Enum name="LCD_VD_7" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_11" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xD8" size="4" name="P1_22" access="Read/Write" description="I/O configuration register for pin P1[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[22]">
+        <Enum name="P1_22" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_RCV1" start="0x1" description="Differential receive data for USB port 1 (OTG                                     transceiver)." />
+        <Enum name="USB_PWRD1" start="0x2" description="Power Status for USB port 1 (host power                                     switch)." />
+        <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." />
+        <Enum name="MC_0B" start="0x4" description="Motor control PWM channel 0, output B." />
+        <Enum name="SSP1_MOSI" start="0x5" description="Master Out Slave In for SSP1." />
+        <Enum name="LCD_VD_8" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_12" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xDC" size="4" name="P1_23" access="Read/Write" description="I/O configuration register for pin P1[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[23]">
+        <Enum name="P1_23" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_RX_DP1" start="0x1" description="D+ receive data for USB port 1 (OTG                                     transceiver)." />
+        <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, channel 4 output." />
+        <Enum name="QEI_PHB" start="0x3" description="Quadrature Encoder Interface PHB input." />
+        <Enum name="MC_FB1" start="0x4" description="Motor control PWM channel 1 feedback input." />
+        <Enum name="SSP0_MISO" start="0x5" description="Master In Slave Out for SSP0." />
+        <Enum name="LCD_VD_9" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_13" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xE0" size="4" name="P1_24" access="Read/Write" description="I/O configuration register for pin P1[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[24]">
+        <Enum name="P1_24" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_RX_DM1" start="0x1" description="D- receive data for USB port 1                                     (OTG transceiver)." />
+        <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, channel 5 output." />
+        <Enum name="QEI_IDX" start="0x3" description="Quadrature Encoder Interface INDEX input." />
+        <Enum name="MC_FB2" start="0x4" description="Motor control PWM channel 2 feedback input." />
+        <Enum name="SSP0_MOSI" start="0x5" description="Master Out Slave in for SSP0." />
+        <Enum name="LCD_VD_10" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_14" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xE4" size="4" name="P1_25" access="Read/Write" description="I/O configuration register for pin P1[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[25]">
+        <Enum name="P1_25" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_LS1" start="0x1" description="Low Speed status for USB port 1 (OTG                                     transceiver)." />
+        <Enum name="USB_HSTEN1" start="0x2" description="Host Enabled status for USB port 1." />
+        <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." />
+        <Enum name="MC_1A" start="0x4" description="Motor control PWM channel 1, output A." />
+        <Enum name="CLKOUT" start="0x5" description="Selectable clock output." />
+        <Enum name="LCD_VD_11" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_15" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xE8" size="4" name="P1_26" access="Read/Write" description="I/O configuration register for pin P1[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[26]">
+        <Enum name="P1_26" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_SSPND1" start="0x1" description="USB port 1 Bus Suspend status (OTG                                     transceiver)." />
+        <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, channel 6 output." />
+        <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." />
+        <Enum name="MC_1B" start="0x4" description="Motor control PWM channel 1, output B." />
+        <Enum name="SSP1_SSEL" start="0x5" description="Slave Select for SSP1." />
+        <Enum name="LCD_VD_12" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_20" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xEC" size="4" name="P1_27" access="Read/Write" description="I/O configuration register for pin P1[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[27]">
+        <Enum name="P1_27" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_INT1" start="0x1" description="USB port 1 OTG transceiver interrupt (OTG                                     transceiver)." />
+        <Enum name="USB_OVRCR1" start="0x2" description="USB port 1 Over-Current status." />
+        <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." />
+        <Enum name="CLKOUT" start="0x4" description="Selectable clock output." />
+        <Enum name="LCD_VD_13" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_21" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xF0" size="4" name="P1_28" access="Read/Write" description="I/O configuration register for pin P1[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[28]">
+        <Enum name="P1_28" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_SCL1" start="0x1" description="USB port 1 I2C serial clock                                     (OTG transceiver)." />
+        <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." />
+        <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." />
+        <Enum name="MC_2A" start="0x4" description="Motor control PWM channel 2, output A." />
+        <Enum name="SSP0_SSEL" start="0x5" description="Slave Select for SSP0." />
+        <Enum name="LCD_VD_14" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_22" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xF4" size="4" name="P1_29" access="Read/Write" description="I/O configuration register for pin P1[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[29]">
+        <Enum name="P1_29" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_SDA1" start="0x1" description="USB port 1 I2C serial data                                     (OTG transceiver)." />
+        <Enum name="PWM1_CAP1" start="0x2" description="Capture input for PWM1, channel 1." />
+        <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." />
+        <Enum name="MC_2B" start="0x4" description="Motor control PWM channel 2, output B." />
+        <Enum name="U4_TXD" start="0x5" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
+        <Enum name="LCD_VD_15" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_23" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xF8" size="4" name="P1_30" access="Read/Write" description="I/O configuration register for pin P1[30]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[30]">
+        <Enum name="P1_30" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_PWRD2" start="0x1" description="Power Status for USB port 2." />
+        <Enum name="USB_VBUS" start="0x2" description="Monitors the presence of USB bus power.This signal must be HIGH for USB reset to                                     occur." />
+        <Enum name="ADC0_IN_4" start="0x3" description="A/D converter 0, input 4. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+        <Enum name="I2C0_SDA" start="0x4" description="I2C0 data input/output (this                                     pin does not use a specialized I2C pad." />
+        <Enum name="U3_OE" start="0x5" description="RS-485/EIA-485 output enable signal for                                     UART3." />
+      </BitField>
+    </Register>
+    <Register start="+0xFC" size="4" name="P1_31" access="Read/Write" description="I/O configuration register for pin P1[31]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P1[31]">
+        <Enum name="P1_31" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_OVRCR2" start="0x1" description="Over-Current status for USB port 2." />
+        <Enum name="SSP1_SCK" start="0x2" description="Serial Clock for SSP1." />
+        <Enum name="ADC0_IN_5" start="0x3" description="A/D converter 0, input 5. When configured as an ADC                                     input, the digital function of the pin must be                                     disabled." />
+        <Enum name="I2C0_SCL" start="0x4" description="I2C0 clock input/output (this                                     pin does not use a specialized I2C pad." />
+      </BitField>
+    </Register>
+    <Register start="+0x100" size="4" name="P2_0" access="Read/Write" description="I/O configuration register for pin P2[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[0]">
+        <Enum name="P2_0" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_1" start="0x1" description="Pulse Width Modulator 1, channel 1 output." />
+        <Enum name="U1_TXD" start="0x2" description="Transmitter output for UART1." />
+        <Enum name="LCD_PWR" start="0x7" description="LCD panel power enable." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x104" size="4" name="P2_1" access="Read/Write" description="I/O configuration register for pin P2[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[1]">
+        <Enum name="P2_1" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_2" start="0x1" description="Pulse Width Modulator 1, channel 2 output." />
+        <Enum name="U1_RXD" start="0x2" description="Receiver input for UART1." />
+        <Enum name="LCD_LE" start="0x7" description="Line end signal." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x108" size="4" name="P2_2" access="Read/Write" description="I/O configuration register for pin P2[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[2]">
+        <Enum name="P2_2" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_3" start="0x1" description="Pulse Width Modulator 1, channel 3 output." />
+        <Enum name="U1_CTS" start="0x2" description="Clear to Send input for UART1." />
+        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
+        <Enum name="TRACEDATA_3" start="0x5" description="Trace data, bit 3." />
+        <Enum name="LCD_DCLK" start="0x7" description="LCD panel clock." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x10C" size="4" name="P2_3" access="Read/Write" description="I/O configuration register for pin P2[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[3]">
+        <Enum name="P2_3" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_4" start="0x1" description="Pulse Width Modulator 1, channel 4 output." />
+        <Enum name="U1_DCD" start="0x2" description="Data Carrier Detect input for UART1." />
+        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
+        <Enum name="TRACEDATA_2" start="0x5" description="Trace data, bit 2." />
+        <Enum name="LCD_FP" start="0x7" description="Frame pulse (STN). Vertical synchronization pulse                                     (TFT)." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x110" size="4" name="P2_4" access="Read/Write" description="I/O configuration register for pin P2[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[4]">
+        <Enum name="P2_4" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_5" start="0x1" description="Pulse Width Modulator 1, channel 5 output." />
+        <Enum name="U1_DSR" start="0x2" description="Data Set Ready input for UART1." />
+        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
+        <Enum name="TRACEDATA_1" start="0x5" description="Trace data, bit 1." />
+        <Enum name="LCD_ENAB_M" start="0x7" description="STN AC bias drive or TFT data enable output." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x114" size="4" name="P2_5" access="Read/Write" description="I/O configuration register for pin P2[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[5]">
+        <Enum name="P2_5" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_6" start="0x1" description="Pulse Width Modulator 1, channel 6 output." />
+        <Enum name="U1_DTR" start="0x2" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
+        <Enum name="TRACEDATA_0" start="0x5" description="Trace data, bit 0." />
+        <Enum name="LCD_LP" start="0x7" description="Line synchronization pulse (STN). Horizontal                                     synchronization pulse (TFT)." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x118" size="4" name="P2_6" access="Read/Write" description="I/O configuration register for pin P2[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[6]">
+        <Enum name="P2_6" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="PWM1_CAP0" start="0x1" description="Capture input for PWM1, channel 0." />
+        <Enum name="U1_RI" start="0x2" description="Ring Indicator input for UART1." />
+        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
+        <Enum name="U2_OE" start="0x4" description="RS-485/EIA-485 output enable signal for                                     UART2." />
+        <Enum name="TRACECLK" start="0x5" description="Trace clock." />
+        <Enum name="LCD_VD_0" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_4" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x11C" size="4" name="P2_7" access="Read/Write" description="I/O configuration register for pin P2[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[7]">
+        <Enum name="P2_7" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="CAN_RD2" start="0x1" description="CAN2 receiver input." />
+        <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+        <Enum name="SPIFI_CS" start="0x5" description="Chip select output for SPIFI." />
+        <Enum name="LCD_VD_1" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_5" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x120" size="4" name="P2_8" access="Read/Write" description="I/O configuration register for pin P2[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[8]">
+        <Enum name="P2_8" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="CAN_TD2" start="0x1" description="CAN2 transmitter output." />
+        <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." />
+        <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." />
+        <Enum name="ENET_MDC" start="0x4" description="Ethernet MIIM clock." />
+        <Enum name="LCD_VD_2" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_6" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x124" size="4" name="P2_9" access="Read/Write" description="I/O configuration register for pin P2[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[9]">
+        <Enum name="P2_9" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="USB_CONNECT1" start="0x1" description="USB1 SoftConnect control. Signal used to switch an                                     external 1.5 kW resistor under the                                     software control. Used with the SoftConnect USB                                     feature." />
+        <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." />
+        <Enum name="U4_RXD" start="0x3" description="Receiver input for USART4." />
+        <Enum name="ENET_MDIO" start="0x4" description="Ethernet MIIM data input and output." />
+        <Enum name="LCD_VD_3" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_7" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x128" size="4" name="P2_10" access="Read/Write" description="I/O configuration register for pin P2[10]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[10]">
+        <Enum name="P2_10" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter.A LOW on this pin while RESET is LOW forces the on-chip&#xa;                                    boot loader to take over control of the part after a reset and&#xa;                                    go into ISP mode. " />
+        <Enum name="EINT0" start="0x1" description="External interrupt 0 input." />
+        <Enum name="NMI" start="0x2" description="Non-maskable interrupt input." />
+      </BitField>
+    </Register>
+    <Register start="+0x12C" size="4" name="P2_11" access="Read/Write" description="I/O configuration register for pin P2[11]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[11]">
+        <Enum name="P2_11" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
+        <Enum name="EINT1" start="0x1" description="External interrupt 1 input." />
+        <Enum name="SD_DAT_1" start="0x2" description="Data line 1 for SD card interface." />
+        <Enum name="I2S_TX_SCK" start="0x3" description="Transmit Clock. It is driven by the master and received                                     by the slave. Corresponds to the signal SCK in the                                             I2S-bus                                         specification." />
+        <Enum name="LCD_CLKIN" start="0x7" description="LCD clock." />
+      </BitField>
+    </Register>
+    <Register start="+0x130" size="4" name="P2_12" access="Read/Write" description="I/O configuration register for pin P2[12]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[12]">
+        <Enum name="P2_12" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
+        <Enum name="EINT2" start="0x1" description="External interrupt 2 input." />
+        <Enum name="SD_DAT_2" start="0x2" description="Data line 2 for SD card interface." />
+        <Enum name="I2S_TX_WS" start="0x3" description="Transmit Word Select. It is driven by the master and                                     received by the slave. Corresponds to the signal WS in the                                             I2S-bus                                         specification." />
+        <Enum name="LCD_VD_4" start="0x4" description="LCD data." />
+        <Enum name="LCD_VD_3" start="0x5" description="LCD data." />
+        <Enum name="LCD_VD_8" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_18" start="0x7" description="LCD data." />
+      </BitField>
+    </Register>
+    <Register start="+0x134" size="4" name="P2_13" access="Read/Write" description="I/O configuration register for pin P2[13]" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[13]">
+        <Enum name="P2_13" start="0x0" description="General purpose digital input/output pin. This pin&#xa;                                    includes a 5 ns input glitch filter." />
+        <Enum name="EINT3" start="0x1" description="External interrupt 3 input." />
+        <Enum name="SD_DAT_3" start="0x2" description="Data line 3 for SD card interface." />
+        <Enum name="I2S_TX_SDA" start="0x3" description="Transmit data. It is driven by the transmitter and read                                     by the receiver. Corresponds to the signal SD in the                                             I2S-bus                                         specification." />
+        <Enum name="LCD_VD_5" start="0x5" description="LCD data." />
+        <Enum name="LCD_VD_9" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_19" start="0x7" description="LCD data." />
+      </BitField>
+    </Register>
+    <Register start="+0x138" size="4" name="P2_14" access="Read/Write" description="I/O configuration register for pin P2[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[14]">
+        <Enum name="P2_14" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CS2" start="0x1" description="LOW active Chip Select 2 signal." />
+        <Enum name="I2C1_SDA" start="0x2" description="I2C1 data input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="T2_CAP0" start="0x3" description="Capture input for Timer 2, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x13C" size="4" name="P2_15" access="Read/Write" description="I/O configuration register for pin P2[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[15]">
+        <Enum name="P2_15" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CS3" start="0x1" description="LOW active Chip Select 3 signal." />
+        <Enum name="I2C1_SCL" start="0x2" description="I2C1 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="T2_CAP1" start="0x3" description="Capture input for Timer 2, channel 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140" size="4" name="P2_16" access="Read/Write" description="I/O configuration register for pin P2[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[16]">
+        <Enum name="P2_16" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CAS" start="0x1" description="LOW active SDRAM Column Address Strobe." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x144" size="4" name="P2_17" access="Read/Write" description="I/O configuration register for pin P2[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[17]">
+        <Enum name="P2_17" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_RAS" start="0x1" description="LOW active SDRAM Row Address Strobe." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x148" size="4" name="P2_18" access="Read/Write" description="I/O configuration register for pin P2[18]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[18]">
+        <Enum name="P2_18" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CLK_0" start="0x1" description="SDRAM clock 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
+        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x14C" size="4" name="P2_19" access="Read/Write" description="I/O configuration register for pin P2[19]" reset_value="0x000001B0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[19]">
+        <Enum name="P2_19" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CLK_1" start="0x1" description="SDRAM clock 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="ADMODE" description="Selects Analog/Digital mode.">
+        <Enum name="ANALOG_INPUT_MODE_" start="0" description="Analog input mode." />
+        <Enum name="DIGITAL_FUNCTIONAL_M" start="1" description="Digital functional mode." />
+      </BitField>
+      <BitField start="8" size="1" name="FILTR" description="Selects 10 ns input glitch filter.">
+        <Enum name="FILTER_DISABLED_" start="0" description="Filter disabled." />
+        <Enum name="FILTER_ENABLED_" start="1" description="Filter enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x150" size="4" name="P2_20" access="Read/Write" description="I/O configuration register for pin P2[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[20]">
+        <Enum name="P2_20" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DYCS0" start="0x1" description="SDRAM chip select 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x154" size="4" name="P2_21" access="Read/Write" description="I/O configuration register for pin P2[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[21]">
+        <Enum name="P2_21" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DYCS1" start="0x1" description="SDRAM chip select 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x158" size="4" name="P2_22" access="Read/Write" description="I/O configuration register for pin P2[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[22]">
+        <Enum name="P2_22" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DYCS2" start="0x1" description="SDRAM chip select 2." />
+        <Enum name="SSP0_SCK" start="0x2" description="Serial clock for SSP0." />
+        <Enum name="T3_CAP0" start="0x3" description="Capture input for Timer 3, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x15C" size="4" name="P2_23" access="Read/Write" description="I/O configuration register for pin P2[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[23]">
+        <Enum name="P2_23" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DYCS3" start="0x1" description="SDRAM chip select 3." />
+        <Enum name="SSP0_SSEL" start="0x2" description="Slave Select for SSP0." />
+        <Enum name="T3_CAP1" start="0x3" description="Capture input for Timer 3, channel 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x160" size="4" name="P2_24" access="Read/Write" description="I/O configuration register for pin P2[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[24]">
+        <Enum name="P2_24" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CKE0" start="0x1" description="SDRAM clock enable 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x164" size="4" name="P2_25" access="Read/Write" description="I/O configuration register for pin P2[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[25]">
+        <Enum name="P2_25" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CKE1" start="0x1" description="SDRAM clock enable 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x168" size="4" name="P2_26" access="Read/Write" description="I/O configuration register for pin P2[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[26]">
+        <Enum name="P2_26" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CKE2" start="0x1" description="SDRAM clock enable 2." />
+        <Enum name="SSP0_MISO" start="0x2" description="Master In Slave Out for SSP0." />
+        <Enum name="T3_MAT0" start="0x3" description="Match output for Timer 3, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x16C" size="4" name="P2_27" access="Read/Write" description="I/O configuration register for pin P2[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[27]">
+        <Enum name="P2_27" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CKE3" start="0x1" description="SDRAM clock enable 3." />
+        <Enum name="SSP0_MOSI" start="0x2" description="Master Out Slave In for SSP0." />
+        <Enum name="T3_MAT1" start="0x3" description="Match output for Timer 3, channel 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x170" size="4" name="P2_28" access="Read/Write" description="I/O configuration register for pin P2[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[28]">
+        <Enum name="P2_28" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DQM0" start="0x1" description="Data mask 0 used with SDRAM and static                                     devices." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x174" size="4" name="P2_29" access="Read/Write" description="I/O configuration register for pin P2[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[29]">
+        <Enum name="P2_29" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DQM1" start="0x1" description="Data mask 1 used with SDRAM and static                                     devices." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x178" size="4" name="P2_30" access="Read/Write" description="I/O configuration register for pin P2[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[30]">
+        <Enum name="P2_30" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DQM2" start="0x1" description="Data mask 2 used with SDRAM and static                                     devices." />
+        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x17C" size="4" name="P2_31" access="Read/Write" description="I/O configuration register for pin P2[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P2[31]">
+        <Enum name="P2_31" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_DQM3" start="0x1" description="Data mask 3 used with SDRAM and static                                     devices." />
+        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x180" size="4" name="P3_0" access="Read/Write" description="I/O configuration register for pin P3[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[0]">
+        <Enum name="P3_0" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_0" start="0x1" description="External memory data line 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x184" size="4" name="P3_1" access="Read/Write" description="I/O configuration register for pin P3[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[1]">
+        <Enum name="P3_1" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_1" start="0x1" description="External memory data line 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x188" size="4" name="P3_2" access="Read/Write" description="I/O configuration register for pin P3[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[2]">
+        <Enum name="P3_2" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_2" start="0x1" description="External memory data line 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x18C" size="4" name="P3_3" access="Read/Write" description="I/O configuration register for pin P3[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[3]">
+        <Enum name="P3_3" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_3" start="0x1" description="External memory data line 3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x190" size="4" name="P3_4" access="Read/Write" description="I/O configuration register for pin P3[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[4]">
+        <Enum name="P3_4" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_4" start="0x1" description="External memory data line 4." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x194" size="4" name="P3_5" access="Read/Write" description="I/O configuration register for pin P3[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[5]">
+        <Enum name="P3_5" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_5" start="0x1" description="External memory data line 5." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x198" size="4" name="P3_6" access="Read/Write" description="I/O configuration register for pin P3[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[6]">
+        <Enum name="P3_6" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_6" start="0x1" description="External memory data line 6." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x19C" size="4" name="P3_7" access="Read/Write" description="I/O configuration register for pin P3[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[7]">
+        <Enum name="P3_7" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_7" start="0x1" description="External memory data line 7." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1A0" size="4" name="P3_8" access="Read/Write" description="I/O configuration register for pin P3[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[8]">
+        <Enum name="P3_8" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_8" start="0x1" description="External memory data line 8." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1A4" size="4" name="P3_9" access="Read/Write" description="I/O configuration register for pin P3[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[9]">
+        <Enum name="P3_9" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_9" start="0x1" description="External memory data line 9." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1A8" size="4" name="P3_10" access="Read/Write" description="I/O configuration register for pin P3[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[10]">
+        <Enum name="P3_10" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_10" start="0x1" description="External memory data line 10." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1AC" size="4" name="P3_11" access="Read/Write" description="I/O configuration register for pin P3[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[11]">
+        <Enum name="P3_11" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_11" start="0x1" description="External memory data line 11." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1B0" size="4" name="P3_12" access="Read/Write" description="I/O configuration register for pin P3[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[12]">
+        <Enum name="P3_12" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_12" start="0x1" description="External memory data line 12." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1B4" size="4" name="P3_13" access="Read/Write" description="I/O configuration register for pin P3[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[13]">
+        <Enum name="P3_13" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_13" start="0x1" description="External memory data line 13." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1B8" size="4" name="P3_14" access="Read/Write" description="I/O configuration register for pin P3[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[14]">
+        <Enum name="P3_14" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_14" start="0x1" description="External memory data line 14. " />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1BC" size="4" name="P3_15" access="Read/Write" description="I/O configuration register for pin P3[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[15]">
+        <Enum name="P3_15" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_15" start="0x1" description="External memory data line 15. " />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1C0" size="4" name="P3_16" access="Read/Write" description="I/O configuration register for pin P3[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[16]">
+        <Enum name="P3_16" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_16" start="0x1" description="External memory data line 16." />
+        <Enum name="PWM0_1" start="0x2" description="Pulse Width Modulator 0, output 1." />
+        <Enum name="U1_TXD" start="0x3" description="Transmitter output for UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1C4" size="4" name="P3_17" access="Read/Write" description="I/O configuration register for pin P3[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[17]">
+        <Enum name="P3_17" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_17" start="0x1" description="External memory data line 17." />
+        <Enum name="PWM0_2" start="0x2" description="Pulse Width Modulator 0, output 2." />
+        <Enum name="U1_RXD" start="0x3" description="Receiver input for UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1C8" size="4" name="P3_18" access="Read/Write" description="I/O configuration register for pin P3[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[18]">
+        <Enum name="P3_18" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_18" start="0x1" description="External memory data line 18." />
+        <Enum name="PWM0_3" start="0x2" description="Pulse Width Modulator 0, output 3." />
+        <Enum name="U1_CTS" start="0x3" description="Clear to Send input for UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1CC" size="4" name="P3_19" access="Read/Write" description="I/O configuration register for pin P3[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[19]">
+        <Enum name="P3_19" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_19" start="0x1" description="External memory data line 19." />
+        <Enum name="PWM0_4" start="0x2" description="Pulse Width Modulator 0, output 4." />
+        <Enum name="U1_DCD" start="0x3" description="Data Carrier Detect input for UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1D0" size="4" name="P3_20" access="Read/Write" description="I/O configuration register for pin P3[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[20]">
+        <Enum name="P3_20" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_20" start="0x1" description="External memory data line 20." />
+        <Enum name="PWM0_5" start="0x2" description="Pulse Width Modulator 0, output 5." />
+        <Enum name="U1_DSR" start="0x3" description="Data Set Ready input for UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1D4" size="4" name="P3_21" access="Read/Write" description="I/O configuration register for pin P3[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[21]">
+        <Enum name="P3_21" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_21" start="0x1" description="External memory data line 21." />
+        <Enum name="PWM0_6" start="0x2" description="Pulse Width Modulator 0, output 6." />
+        <Enum name="U1_DTR" start="0x3" description="Data Terminal Ready output for UART1. Can also be                                     configured to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1D8" size="4" name="P3_22" access="Read/Write" description="I/O configuration register for pin P3[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[22]">
+        <Enum name="P3_22" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_22" start="0x1" description="External memory data line 22." />
+        <Enum name="PWM0_CAP0" start="0x2" description="Capture input for PWM0, channel 0." />
+        <Enum name="U1_RI" start="0x3" description="Ring Indicator input for UART1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1DC" size="4" name="P3_23" access="Read/Write" description="I/O configuration register for pin P3[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[23]">
+        <Enum name="P3_23" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_23" start="0x1" description="External memory data line 23." />
+        <Enum name="PWM1_CAP0" start="0x2" description="Capture input for PWM1, channel 0." />
+        <Enum name="T0_CAP0" start="0x3" description="Capture input for Timer 0, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1E0" size="4" name="P3_24" access="Read/Write" description="I/O configuration register for pin P3[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[24]">
+        <Enum name="P3_24" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_24" start="0x1" description="External memory data line 24." />
+        <Enum name="PWM1_1" start="0x2" description="Pulse Width Modulator 1, output 1." />
+        <Enum name="T0_CAP1" start="0x3" description="Capture input for Timer 0, channel 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1E4" size="4" name="P3_25" access="Read/Write" description="I/O configuration register for pin P3[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[25]">
+        <Enum name="P3_25" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_25" start="0x1" description="External memory data line 25." />
+        <Enum name="PWM1_2" start="0x2" description="Pulse Width Modulator 1, output 2." />
+        <Enum name="T0_MAT0" start="0x3" description="Match output for Timer 0, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1E8" size="4" name="P3_26" access="Read/Write" description="I/O configuration register for pin P3[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[26]">
+        <Enum name="P3_26" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_26" start="0x1" description="External memory data line 26." />
+        <Enum name="PWM1_3" start="0x2" description="Pulse Width Modulator 1, output 3." />
+        <Enum name="T0_MAT1" start="0x3" description="Match output for Timer 0, channel 1." />
+        <Enum name="STCLK" start="0x4" description="System tick timer clock input." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1EC" size="4" name="P3_27" access="Read/Write" description="I/O configuration register for pin P3[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[27]">
+        <Enum name="P3_27" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_27" start="0x1" description="External memory data line 27." />
+        <Enum name="PWM1_4" start="0x2" description="Pulse Width Modulator 1, output 4." />
+        <Enum name="T1_CAP0" start="0x3" description="Capture input for Timer 1, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1F0" size="4" name="P3_28" access="Read/Write" description="I/O configuration register for pin P3[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[28]">
+        <Enum name="P3_28" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_28" start="0x1" description="External memory data line 28." />
+        <Enum name="PWM1_5" start="0x2" description="Pulse Width Modulator 1, output 5." />
+        <Enum name="T1_CAP1" start="0x3" description="Capture input for Timer 1, channel 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1F4" size="4" name="P3_29" access="Read/Write" description="I/O configuration register for pin P3[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[29]">
+        <Enum name="P3_29" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_29" start="0x1" description="External memory data line 29." />
+        <Enum name="PWM1_6" start="0x2" description="Pulse Width Modulator 1, output 6." />
+        <Enum name="T1_MAT0" start="0x3" description="Match output for Timer 1, channel 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1F8" size="4" name="P3_30" access="Read/Write" description="I/O configuration register for pin P3[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[30]">
+        <Enum name="P3_30" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_30" start="0x1" description="External memory data line 30." />
+        <Enum name="U1_RTS" start="0x2" description="Request to Send output for UART1. Can also be configured                                     to be an RS-485/EIA-485 output enable signal for                                     UART1." />
+        <Enum name="T1_MAT1" start="0x3" description="Match output for Timer 1, channel 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1FC" size="4" name="P3_31" access="Read/Write" description="I/O configuration register for pin P3[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P3[31]">
+        <Enum name="P3_31" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_D_31" start="0x1" description="External memory data line 31." />
+        <Enum name="T1_MAT2" start="0x3" description="Match output for Timer 1, channel 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200" size="4" name="P4_0" access="Read/Write" description="I/O configuration register for pin P4[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[0]">
+        <Enum name="P4_0" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_0" start="0x1" description="External memory address line 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x204" size="4" name="P4_1" access="Read/Write" description="I/O configuration register for pin P4[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[1]">
+        <Enum name="P4_1" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_1" start="0x1" description="External memory address line 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x208" size="4" name="P4_2" access="Read/Write" description="I/O configuration register for pin P4[2]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[2]">
+        <Enum name="P4_2" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_2" start="0x1" description="External memory address line 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x20C" size="4" name="P4_3" access="Read/Write" description="I/O configuration register for pin P4[3]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[3]">
+        <Enum name="P4_3" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_3" start="0x1" description="External memory address line 3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x210" size="4" name="P4_4" access="Read/Write" description="I/O configuration register for pin P4[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[4]">
+        <Enum name="P4_4" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_4" start="0x1" description="External memory address line 4." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x214" size="4" name="P4_5" access="Read/Write" description="I/O configuration register for pin P4[5]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[5]">
+        <Enum name="P4_5" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_5" start="0x1" description="External memory address line 5." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x218" size="4" name="P4_6" access="Read/Write" description="I/O configuration register for pin P4[6]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[6]">
+        <Enum name="P4_6" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_6" start="0x1" description="External memory address line 6." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x21C" size="4" name="P4_7" access="Read/Write" description="I/O configuration register for pin P4[7]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[7]">
+        <Enum name="P4_7" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_7" start="0x1" description="External memory address line 7." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x220" size="4" name="P4_8" access="Read/Write" description="I/O configuration register for pin P4[8]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[8]">
+        <Enum name="P4_8" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_8" start="0x1" description="External memory address line 8." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x224" size="4" name="P4_9" access="Read/Write" description="I/O configuration register for pin P4[9]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[9]">
+        <Enum name="P4_9" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_9" start="0x1" description="External memory address line 9." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x228" size="4" name="P4_10" access="Read/Write" description="I/O configuration register for pin P4[10]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[10]">
+        <Enum name="P4_10" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_10" start="0x1" description="External memory address line 10." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x22C" size="4" name="P4_11" access="Read/Write" description="I/O configuration register for pin P4[11]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[11]">
+        <Enum name="P4_11" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_11" start="0x1" description="External memory address line 11." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x230" size="4" name="P4_12" access="Read/Write" description="I/O configuration register for pin P4[12]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[12]">
+        <Enum name="P4_12" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_12" start="0x1" description="External memory address line 12." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x234" size="4" name="P4_13" access="Read/Write" description="I/O configuration register for pin P4[13]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[13]">
+        <Enum name="P4_13" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_13" start="0x1" description="External memory address line 13." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x238" size="4" name="P4_14" access="Read/Write" description="I/O configuration register for pin P4[14]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[14]">
+        <Enum name="P4_14" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_14" start="0x1" description="External memory address line 14." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x23C" size="4" name="P4_15" access="Read/Write" description="I/O configuration register for pin P4[15]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[15]">
+        <Enum name="P4_15" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_15" start="0x1" description="External memory address line 15." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240" size="4" name="P4_16" access="Read/Write" description="I/O configuration register for pin P4[16]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[16]">
+        <Enum name="P4_16" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_16" start="0x1" description="External memory address line 16." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x244" size="4" name="P4_17" access="Read/Write" description="I/O configuration register for pin P4[17]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[17]">
+        <Enum name="P4_17" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_17" start="0x1" description="External memory address line 17." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x248" size="4" name="P4_18" access="Read/Write" description="I/O configuration register for pin P4[18]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[18]">
+        <Enum name="P4_18" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_18" start="0x1" description="External memory address line 18." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x24C" size="4" name="P4_19" access="Read/Write" description="I/O configuration register for pin P4[19]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[19]">
+        <Enum name="P4_19" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_19" start="0x1" description="External memory address line 19." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x250" size="4" name="P4_20" access="Read/Write" description="I/O configuration register for pin P4[20]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[20]">
+        <Enum name="P4_20" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_20" start="0x1" description="External memory address line 20." />
+        <Enum name="I2C2_SDA" start="0x2" description="I2C2 data input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="SSP1_SCK" start="0x3" description="Serial Clock for SSP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x254" size="4" name="P4_21" access="Read/Write" description="I/O configuration register for pin P4[21]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[21]">
+        <Enum name="P4_21" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_21" start="0x1" description="External memory address line 21." />
+        <Enum name="I2C2_SCL" start="0x2" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="SSP1_SSEL" start="0x3" description="Slave Select for SSP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x258" size="4" name="P4_22" access="Read/Write" description="I/O configuration register for pin P4[22]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[22]">
+        <Enum name="P4_22" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_22" start="0x1" description="External memory address line 22." />
+        <Enum name="U2_TXD" start="0x2" description="Transmitter output for UART2." />
+        <Enum name="SSP1_MISO" start="0x3" description="Master In Slave Out for SSP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x25C" size="4" name="P4_23" access="Read/Write" description="I/O configuration register for pin P4[23]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[23]">
+        <Enum name="P4_23" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_23" start="0x1" description="External memory address line 23." />
+        <Enum name="U2_RXD" start="0x2" description="Receiver input for UART2." />
+        <Enum name="SSP1_MOSI" start="0x3" description="Master Out Slave In for SSP1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x260" size="4" name="P4_24" access="Read/Write" description="I/O configuration register for pin P4[24]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[24]">
+        <Enum name="P4_24" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_OE" start="0x1" description="LOW active Output Enable signal." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x264" size="4" name="P4_25" access="Read/Write" description="I/O configuration register for pin P4[25]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[25]">
+        <Enum name="P4_25" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_WE" start="0x1" description="LOW active Write Enable signal." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x268" size="4" name="P4_26" access="Read/Write" description="I/O configuration register for pin P4[26]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[26]">
+        <Enum name="P4_26" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_BLS0" start="0x1" description="LOW active Byte Lane select signal 0." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x26C" size="4" name="P4_27" access="Read/Write" description="I/O configuration register for pin P4[27]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[27]">
+        <Enum name="P4_27" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_BLS1" start="0x1" description="LOW active Byte Lane select signal 1." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x270" size="4" name="P4_28" access="Read/Write" description="I/O configuration register for pin P4[28]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[28]">
+        <Enum name="P4_28" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_BLS2" start="0x1" description="LOW active Byte Lane select signal 2." />
+        <Enum name="U3_TXD" start="0x2" description="Transmitter output for UART3." />
+        <Enum name="T2_MAT0" start="0x3" description="Match output for Timer 2, channel 0." />
+        <Enum name="LCD_VD_6" start="0x5" description="LCD data." />
+        <Enum name="LCD_VD_10" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_2" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x274" size="4" name="P4_29" access="Read/Write" description="I/O configuration register for pin P4[29]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[29]">
+        <Enum name="P4_29" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_BLS3" start="0x1" description="LOW active Byte Lane select signal 3." />
+        <Enum name="U3_RXD" start="0x2" description="Receiver input for UART3." />
+        <Enum name="T2_MAT1" start="0x3" description="Match output for Timer 2, channel 1." />
+        <Enum name="I2C2_SCL" start="0x4" description="I2C2 clock input/output (this                                     pin does not use a specialized I2C pad)." />
+        <Enum name="LCD_VD_7" start="0x5" description="LCD data." />
+        <Enum name="LCD_VD_11" start="0x6" description="LCD data." />
+        <Enum name="LCD_VD_3" start="0x7" description="LCD data." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x278" size="4" name="P4_30" access="Read/Write" description="I/O configuration register for pin P4[30]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[30]">
+        <Enum name="P4_30" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CS0" start="0x1" description="LOW active Chip Select 0 signal." />
+        <Enum name="CMP0_OUT" start="0x5" description="Comparator 0, output." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x27C" size="4" name="P4_31" access="Read/Write" description="I/O configuration register for pin P4[31]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P4[31]">
+        <Enum name="P4_31" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_CS1" start="0x1" description="LOW active Chip Select 1 signal." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x280" size="4" name="P5_0" access="Read/Write" description="I/O configuration register for pin P5[0]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[0]">
+        <Enum name="P5_0" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_24" start="0x1" description="External memory address line 24." />
+        <Enum name="SSP2_MOSI" start="0x2" description="Master Out Slave In for SSP2." />
+        <Enum name="T2_MAT2" start="0x3" description="Match output for Timer 2, channel 2." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x284" size="4" name="P5_1" access="Read/Write" description="I/O configuration register for pin P5[1]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[1]">
+        <Enum name="P5_1" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="EMC_A_25" start="0x1" description="External memory address line 25." />
+        <Enum name="SSP2_MISO" start="0x2" description="Master In Slave Out for SSP2." />
+        <Enum name="T2_MAT3" start="0x3" description="Match output for Timer 2, channel 3." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x288" size="4" name="P5_2" access="Read/Write" description="I/O configuration register for pin P5[2]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[2]">
+        <Enum name="P5_2" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="T3_MAT2" start="0x3" description="Match output for Timer 3, channel 2." />
+        <Enum name="I2C0_SDA" start="0x5" description="I2C0 data input/output (this                                     pin uses a specialized I2C pad that                                     supports I2C Fast Mode                                     Plus)." />
+      </BitField>
+      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
+        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
+        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
+        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
+        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x28C" size="4" name="P5_3" access="Read/Write" description="I/O configuration register for pin P5[3]" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[3]">
+        <Enum name="P5_3" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U4_RXD" start="0x4" description="Receiver input for USART4." />
+        <Enum name="I2C0_SCL" start="0x5" description="I2C0 clock input/output (this                                     pin uses a specialized I2C pad that                                     supports I2C Fast Mode                                     Plus." />
+      </BitField>
+      <BitField start="3" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="HS" description="Configures I2C features for standard mode, fast mode, and Fast Mode&#xa;                        Plus operation.">
+        <Enum name="ENABLED" start="0" description="I2C 50ns glitch filter and slew rate control&#xa;                                enabled." />
+        <Enum name="DISABLED" start="1" description="I2C 50ns glitch filter and slew rate control&#xa;                                disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="HIDRIVE" description="Controls sink current capability of the pin, only for P5[2] and&#xa;                        P5[3].">
+        <Enum name="LOWDRIVE" start="0" description="Output drive sink is 4 mA. This is sufficient for standard&#xa;                                and fast mode I2C." />
+        <Enum name="HIGHDRIVE" start="1" description="Output drive sink is 20 mA. This is needed for Fast Mode&#xa;                                Plus I2C. Refer to the appropriate specific device data sheet for&#xa;                                details." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x290" size="4" name="P5_4" access="Read/Write" description="I/O configuration register for pin P5[4]" reset_value="0x00000030" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FUNC" description="Selects pin function for pin P5[4]">
+        <Enum name="P5_4" start="0x0" description="General purpose digital input/output pin." />
+        <Enum name="U0_OE" start="0x1" description="RS-485/EIA-485 output enable signal for                                     UART0." />
+        <Enum name="T3_MAT3" start="0x3" description="Match output for Timer 3, channel 3." />
+        <Enum name="U4_TXD" start="0x4" description="Transmitter output for USART4 (input/output in smart card                                     mode)." />
+      </BitField>
+      <BitField start="3" size="2" name="MODE" description="Selects function mode (on-chip pull-up/pull-down resistor&#xa;                        control).">
+        <Enum name="INACTIVE_NO_PULL_DO" start="0x0" description="Inactive (no pull-down/pull-up resistor&#xa;                                enabled)." />
+        <Enum name="PULL_DOWN_RESISTOR_E" start="0x1" description="Pull-down resistor enabled." />
+        <Enum name="PULL_UP_RESISTOR_ENA" start="0x2" description="Pull-up resistor enabled." />
+        <Enum name="REPEATER_MODE_" start="0x3" description="Repeater mode." />
+      </BitField>
+      <BitField start="5" size="1" name="HYS" description="Hysteresis.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="ENABLE_" start="1" description="Enable." />
+      </BitField>
+      <BitField start="6" size="1" name="INV" description="Invert input">
+        <Enum name="INPUT_NOT_INVERTED_" start="0" description="Input not inverted (HIGH on pin reads as 1, LOW on pin&#xa;                                reads as 0)." />
+        <Enum name="INPUT_INVERTED_HIGH" start="1" description="Input inverted (HIGH on pin reads as 0, LOW on pin reads as&#xa;                                1)." />
+      </BitField>
+      <BitField start="7" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="SLEW" description="Driver slew rate">
+        <Enum name="STANDARD" start="0" description="Standard mode, output slew rate control is enabled. More&#xa;                                outputs can be switched simultaneously." />
+        <Enum name="FAST" start="1" description="Fast mode, slew rate control is disabled. Refer to the&#xa;                                appropriate specific device data sheet for details." />
+      </BitField>
+      <BitField start="10" size="1" name="OD" description="Open-drain mode.">
+        <Enum name="DISABLE_" start="0" description="Disable." />
+        <Enum name="OPEN_DRAIN_MODE_ENAB" start="1" description="Open-drain mode enabled. This is not a true open-drain&#xa;                                mode. Input cannot be pulled up above VDD." />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP1" start="0x40030000" description="SSP1 controller">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
+        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="NORMAL" start="0" description="During normal operation." />
+        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
+        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
+      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC" start="0x40034000" description="Analog-to-Digital Converter (ADC)">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="SEL" description="Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01." />
+      <BitField start="8" size="8" name="CLKDIV" description="The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
+      <BitField start="16" size="1" name="BURST" description="Burst mode">
+        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start." />
+        <Enum name="SW" start="0" description="Conversions are software controlled and require 31 clocks." />
+      </BitField>
+      <BitField start="17" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="21" size="1" name="PDN" description="Power down mode">
+        <Enum name="POWERED" start="1" description="The A/D converter is operational." />
+        <Enum name="POWERDOWN" start="0" description="The A/D converter is in power-down mode." />
+      </BitField>
+      <BitField start="22" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started:">
+        <Enum name="NO_START_THIS_VALUE" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
+        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
+        <Enum name="P2_10" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on the P2[10] pin." />
+        <Enum name="P1_27" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on the P1[27] pin." />
+        <Enum name="MAT0_1" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin." />
+        <Enum name="MAT0_3" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin." />
+        <Enum name="MAT1_0" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin." />
+        <Enum name="MAT1_1" start="0x7" description="Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin." />
+      </BitField>
+      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 010-111. In these cases:">
+        <Enum name="FALLLING" start="1" description="Start conversion on a falling edge on the selected CAP/MAT signal." />
+        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected CAP/MAT signal." />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="GDR" access="Read/Write" description="A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...)." />
+      <BitField start="27" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADINTEN0" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 0 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 0 will generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="ADINTEN1" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 1 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 1 will generate an interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="ADINTEN2" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 2 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 2 will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="ADINTEN3" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 3 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 3 will generate an interrupt." />
+      </BitField>
+      <BitField start="4" size="1" name="ADINTEN4" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 4 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 4 will generate an interrupt." />
+      </BitField>
+      <BitField start="5" size="1" name="ADINTEN5" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 5 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 5 will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="ADINTEN6" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 6 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 6 will generate an interrupt." />
+      </BitField>
+      <BitField start="7" size="1" name="ADINTEN7" description="Interrupt enable">
+        <Enum name="DISABLE" start="0" description="Completion of a conversion on ADC channel 7 will not generate an interrupt." />
+        <Enum name="ENABLE" start="1" description="Completion of a conversion on ADC channel 7 will generate an interrupt." />
+      </BitField>
+      <BitField start="8" size="1" name="ADGINTEN" description="Interrupt enable">
+        <Enum name="CHANNELS" start="0" description="Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts." />
+        <Enum name="GLOBAL" start="1" description="The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="12" name="RESULT" description="When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE0" description="This bit mirrors the DONE status flag from the result register for A/D channel 0." />
+      <BitField start="1" size="1" name="DONE1" description="This bit mirrors the DONE status flag from the result register for A/D channel 1." />
+      <BitField start="2" size="1" name="DONE2" description="This bit mirrors the DONE status flag from the result register for A/D channel 2." />
+      <BitField start="3" size="1" name="DONE3" description="This bit mirrors the DONE status flag from the result register for A/D channel 3." />
+      <BitField start="4" size="1" name="DONE4" description="This bit mirrors the DONE status flag from the result register for A/D channel 4." />
+      <BitField start="5" size="1" name="DONE5" description="This bit mirrors the DONE status flag from the result register for A/D channel 5." />
+      <BitField start="6" size="1" name="DONE6" description="This bit mirrors the DONE status flag from the result register for A/D channel 6." />
+      <BitField start="7" size="1" name="DONE7" description="This bit mirrors the DONE status flag from the result register for A/D channel 7." />
+      <BitField start="8" size="1" name="OVERRUN0" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0." />
+      <BitField start="9" size="1" name="OVERRUN1" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1." />
+      <BitField start="10" size="1" name="OVERRUN2" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2." />
+      <BitField start="11" size="1" name="OVERRUN3" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3." />
+      <BitField start="12" size="1" name="OVERRUN4" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4." />
+      <BitField start="13" size="1" name="OVERRUN5" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5." />
+      <BitField start="14" size="1" name="OVERRUN6" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6." />
+      <BitField start="15" size="1" name="OVERRUN7" description="This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7." />
+      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034" size="4" name="TRM" access="Read/Write" description="ADC trim register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="4" name="ADCOFFS" description="Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user." />
+      <BitField start="8" size="4" name="TRIM" description="written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CANAFRAM" start="0x40038000" description="CAN acceptance filter RAM">
+    <Register start="+0x000+0" size="4" name="MASK[0]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+4" size="4" name="MASK[1]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+8" size="4" name="MASK[2]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+12" size="4" name="MASK[3]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+16" size="4" name="MASK[4]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+20" size="4" name="MASK[5]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+24" size="4" name="MASK[6]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+28" size="4" name="MASK[7]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+32" size="4" name="MASK[8]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+36" size="4" name="MASK[9]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+40" size="4" name="MASK[10]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+44" size="4" name="MASK[11]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+48" size="4" name="MASK[12]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+52" size="4" name="MASK[13]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+56" size="4" name="MASK[14]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+60" size="4" name="MASK[15]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+64" size="4" name="MASK[16]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+68" size="4" name="MASK[17]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+72" size="4" name="MASK[18]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+76" size="4" name="MASK[19]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+80" size="4" name="MASK[20]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+84" size="4" name="MASK[21]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+88" size="4" name="MASK[22]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+92" size="4" name="MASK[23]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+96" size="4" name="MASK[24]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+100" size="4" name="MASK[25]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+104" size="4" name="MASK[26]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+108" size="4" name="MASK[27]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+112" size="4" name="MASK[28]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+116" size="4" name="MASK[29]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+120" size="4" name="MASK[30]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+124" size="4" name="MASK[31]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+128" size="4" name="MASK[32]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+132" size="4" name="MASK[33]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+136" size="4" name="MASK[34]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+140" size="4" name="MASK[35]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+144" size="4" name="MASK[36]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+148" size="4" name="MASK[37]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+152" size="4" name="MASK[38]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+156" size="4" name="MASK[39]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+160" size="4" name="MASK[40]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+164" size="4" name="MASK[41]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+168" size="4" name="MASK[42]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+172" size="4" name="MASK[43]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+176" size="4" name="MASK[44]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+180" size="4" name="MASK[45]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+184" size="4" name="MASK[46]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+188" size="4" name="MASK[47]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+192" size="4" name="MASK[48]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+196" size="4" name="MASK[49]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+200" size="4" name="MASK[50]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+204" size="4" name="MASK[51]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+208" size="4" name="MASK[52]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+212" size="4" name="MASK[53]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+216" size="4" name="MASK[54]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+220" size="4" name="MASK[55]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+224" size="4" name="MASK[56]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+228" size="4" name="MASK[57]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+232" size="4" name="MASK[58]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+236" size="4" name="MASK[59]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+240" size="4" name="MASK[60]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+244" size="4" name="MASK[61]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+248" size="4" name="MASK[62]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+252" size="4" name="MASK[63]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+256" size="4" name="MASK[64]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+260" size="4" name="MASK[65]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+264" size="4" name="MASK[66]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+268" size="4" name="MASK[67]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+272" size="4" name="MASK[68]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+276" size="4" name="MASK[69]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+280" size="4" name="MASK[70]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+284" size="4" name="MASK[71]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+288" size="4" name="MASK[72]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+292" size="4" name="MASK[73]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+296" size="4" name="MASK[74]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+300" size="4" name="MASK[75]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+304" size="4" name="MASK[76]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+308" size="4" name="MASK[77]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+312" size="4" name="MASK[78]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+316" size="4" name="MASK[79]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+320" size="4" name="MASK[80]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+324" size="4" name="MASK[81]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+328" size="4" name="MASK[82]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+332" size="4" name="MASK[83]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+336" size="4" name="MASK[84]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+340" size="4" name="MASK[85]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+344" size="4" name="MASK[86]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+348" size="4" name="MASK[87]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+352" size="4" name="MASK[88]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+356" size="4" name="MASK[89]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+360" size="4" name="MASK[90]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+364" size="4" name="MASK[91]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+368" size="4" name="MASK[92]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+372" size="4" name="MASK[93]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+376" size="4" name="MASK[94]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+380" size="4" name="MASK[95]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+384" size="4" name="MASK[96]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+388" size="4" name="MASK[97]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+392" size="4" name="MASK[98]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+396" size="4" name="MASK[99]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+400" size="4" name="MASK[100]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+404" size="4" name="MASK[101]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+408" size="4" name="MASK[102]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+412" size="4" name="MASK[103]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+416" size="4" name="MASK[104]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+420" size="4" name="MASK[105]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+424" size="4" name="MASK[106]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+428" size="4" name="MASK[107]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+432" size="4" name="MASK[108]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+436" size="4" name="MASK[109]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+440" size="4" name="MASK[110]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+444" size="4" name="MASK[111]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+448" size="4" name="MASK[112]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+452" size="4" name="MASK[113]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+456" size="4" name="MASK[114]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+460" size="4" name="MASK[115]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+464" size="4" name="MASK[116]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+468" size="4" name="MASK[117]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+472" size="4" name="MASK[118]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+476" size="4" name="MASK[119]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+480" size="4" name="MASK[120]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+484" size="4" name="MASK[121]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+488" size="4" name="MASK[122]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+492" size="4" name="MASK[123]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+496" size="4" name="MASK[124]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+500" size="4" name="MASK[125]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+504" size="4" name="MASK[126]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+508" size="4" name="MASK[127]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+512" size="4" name="MASK[128]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+516" size="4" name="MASK[129]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+520" size="4" name="MASK[130]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+524" size="4" name="MASK[131]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+528" size="4" name="MASK[132]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+532" size="4" name="MASK[133]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+536" size="4" name="MASK[134]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+540" size="4" name="MASK[135]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+544" size="4" name="MASK[136]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+548" size="4" name="MASK[137]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+552" size="4" name="MASK[138]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+556" size="4" name="MASK[139]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+560" size="4" name="MASK[140]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+564" size="4" name="MASK[141]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+568" size="4" name="MASK[142]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+572" size="4" name="MASK[143]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+576" size="4" name="MASK[144]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+580" size="4" name="MASK[145]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+584" size="4" name="MASK[146]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+588" size="4" name="MASK[147]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+592" size="4" name="MASK[148]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+596" size="4" name="MASK[149]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+600" size="4" name="MASK[150]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+604" size="4" name="MASK[151]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+608" size="4" name="MASK[152]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+612" size="4" name="MASK[153]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+616" size="4" name="MASK[154]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+620" size="4" name="MASK[155]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+624" size="4" name="MASK[156]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+628" size="4" name="MASK[157]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+632" size="4" name="MASK[158]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+636" size="4" name="MASK[159]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+640" size="4" name="MASK[160]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+644" size="4" name="MASK[161]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+648" size="4" name="MASK[162]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+652" size="4" name="MASK[163]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+656" size="4" name="MASK[164]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+660" size="4" name="MASK[165]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+664" size="4" name="MASK[166]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+668" size="4" name="MASK[167]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+672" size="4" name="MASK[168]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+676" size="4" name="MASK[169]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+680" size="4" name="MASK[170]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+684" size="4" name="MASK[171]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+688" size="4" name="MASK[172]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+692" size="4" name="MASK[173]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+696" size="4" name="MASK[174]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+700" size="4" name="MASK[175]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+704" size="4" name="MASK[176]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+708" size="4" name="MASK[177]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+712" size="4" name="MASK[178]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+716" size="4" name="MASK[179]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+720" size="4" name="MASK[180]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+724" size="4" name="MASK[181]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+728" size="4" name="MASK[182]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+732" size="4" name="MASK[183]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+736" size="4" name="MASK[184]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+740" size="4" name="MASK[185]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+744" size="4" name="MASK[186]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+748" size="4" name="MASK[187]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+752" size="4" name="MASK[188]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+756" size="4" name="MASK[189]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+760" size="4" name="MASK[190]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+764" size="4" name="MASK[191]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+768" size="4" name="MASK[192]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+772" size="4" name="MASK[193]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+776" size="4" name="MASK[194]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+780" size="4" name="MASK[195]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+784" size="4" name="MASK[196]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+788" size="4" name="MASK[197]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+792" size="4" name="MASK[198]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+796" size="4" name="MASK[199]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+800" size="4" name="MASK[200]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+804" size="4" name="MASK[201]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+808" size="4" name="MASK[202]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+812" size="4" name="MASK[203]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+816" size="4" name="MASK[204]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+820" size="4" name="MASK[205]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+824" size="4" name="MASK[206]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+828" size="4" name="MASK[207]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+832" size="4" name="MASK[208]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+836" size="4" name="MASK[209]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+840" size="4" name="MASK[210]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+844" size="4" name="MASK[211]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+848" size="4" name="MASK[212]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+852" size="4" name="MASK[213]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+856" size="4" name="MASK[214]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+860" size="4" name="MASK[215]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+864" size="4" name="MASK[216]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+868" size="4" name="MASK[217]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+872" size="4" name="MASK[218]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+876" size="4" name="MASK[219]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+880" size="4" name="MASK[220]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+884" size="4" name="MASK[221]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+888" size="4" name="MASK[222]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+892" size="4" name="MASK[223]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+896" size="4" name="MASK[224]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+900" size="4" name="MASK[225]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+904" size="4" name="MASK[226]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+908" size="4" name="MASK[227]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+912" size="4" name="MASK[228]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+916" size="4" name="MASK[229]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+920" size="4" name="MASK[230]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+924" size="4" name="MASK[231]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+928" size="4" name="MASK[232]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+932" size="4" name="MASK[233]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+936" size="4" name="MASK[234]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+940" size="4" name="MASK[235]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+944" size="4" name="MASK[236]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+948" size="4" name="MASK[237]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+952" size="4" name="MASK[238]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+956" size="4" name="MASK[239]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+960" size="4" name="MASK[240]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+964" size="4" name="MASK[241]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+968" size="4" name="MASK[242]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+972" size="4" name="MASK[243]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+976" size="4" name="MASK[244]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+980" size="4" name="MASK[245]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+984" size="4" name="MASK[246]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+988" size="4" name="MASK[247]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+992" size="4" name="MASK[248]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+996" size="4" name="MASK[249]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1000" size="4" name="MASK[250]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1004" size="4" name="MASK[251]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1008" size="4" name="MASK[252]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1012" size="4" name="MASK[253]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1016" size="4" name="MASK[254]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1020" size="4" name="MASK[255]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1024" size="4" name="MASK[256]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1028" size="4" name="MASK[257]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1032" size="4" name="MASK[258]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1036" size="4" name="MASK[259]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1040" size="4" name="MASK[260]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1044" size="4" name="MASK[261]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1048" size="4" name="MASK[262]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1052" size="4" name="MASK[263]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1056" size="4" name="MASK[264]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1060" size="4" name="MASK[265]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1064" size="4" name="MASK[266]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1068" size="4" name="MASK[267]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1072" size="4" name="MASK[268]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1076" size="4" name="MASK[269]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1080" size="4" name="MASK[270]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1084" size="4" name="MASK[271]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1088" size="4" name="MASK[272]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1092" size="4" name="MASK[273]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1096" size="4" name="MASK[274]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1100" size="4" name="MASK[275]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1104" size="4" name="MASK[276]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1108" size="4" name="MASK[277]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1112" size="4" name="MASK[278]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1116" size="4" name="MASK[279]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1120" size="4" name="MASK[280]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1124" size="4" name="MASK[281]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1128" size="4" name="MASK[282]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1132" size="4" name="MASK[283]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1136" size="4" name="MASK[284]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1140" size="4" name="MASK[285]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1144" size="4" name="MASK[286]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1148" size="4" name="MASK[287]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1152" size="4" name="MASK[288]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1156" size="4" name="MASK[289]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1160" size="4" name="MASK[290]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1164" size="4" name="MASK[291]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1168" size="4" name="MASK[292]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1172" size="4" name="MASK[293]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1176" size="4" name="MASK[294]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1180" size="4" name="MASK[295]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1184" size="4" name="MASK[296]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1188" size="4" name="MASK[297]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1192" size="4" name="MASK[298]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1196" size="4" name="MASK[299]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1200" size="4" name="MASK[300]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1204" size="4" name="MASK[301]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1208" size="4" name="MASK[302]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1212" size="4" name="MASK[303]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1216" size="4" name="MASK[304]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1220" size="4" name="MASK[305]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1224" size="4" name="MASK[306]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1228" size="4" name="MASK[307]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1232" size="4" name="MASK[308]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1236" size="4" name="MASK[309]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1240" size="4" name="MASK[310]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1244" size="4" name="MASK[311]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1248" size="4" name="MASK[312]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1252" size="4" name="MASK[313]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1256" size="4" name="MASK[314]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1260" size="4" name="MASK[315]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1264" size="4" name="MASK[316]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1268" size="4" name="MASK[317]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1272" size="4" name="MASK[318]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1276" size="4" name="MASK[319]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1280" size="4" name="MASK[320]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1284" size="4" name="MASK[321]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1288" size="4" name="MASK[322]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1292" size="4" name="MASK[323]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1296" size="4" name="MASK[324]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1300" size="4" name="MASK[325]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1304" size="4" name="MASK[326]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1308" size="4" name="MASK[327]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1312" size="4" name="MASK[328]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1316" size="4" name="MASK[329]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1320" size="4" name="MASK[330]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1324" size="4" name="MASK[331]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1328" size="4" name="MASK[332]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1332" size="4" name="MASK[333]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1336" size="4" name="MASK[334]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1340" size="4" name="MASK[335]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1344" size="4" name="MASK[336]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1348" size="4" name="MASK[337]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1352" size="4" name="MASK[338]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1356" size="4" name="MASK[339]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1360" size="4" name="MASK[340]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1364" size="4" name="MASK[341]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1368" size="4" name="MASK[342]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1372" size="4" name="MASK[343]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1376" size="4" name="MASK[344]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1380" size="4" name="MASK[345]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1384" size="4" name="MASK[346]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1388" size="4" name="MASK[347]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1392" size="4" name="MASK[348]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1396" size="4" name="MASK[349]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1400" size="4" name="MASK[350]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1404" size="4" name="MASK[351]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1408" size="4" name="MASK[352]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1412" size="4" name="MASK[353]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1416" size="4" name="MASK[354]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1420" size="4" name="MASK[355]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1424" size="4" name="MASK[356]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1428" size="4" name="MASK[357]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1432" size="4" name="MASK[358]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1436" size="4" name="MASK[359]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1440" size="4" name="MASK[360]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1444" size="4" name="MASK[361]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1448" size="4" name="MASK[362]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1452" size="4" name="MASK[363]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1456" size="4" name="MASK[364]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1460" size="4" name="MASK[365]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1464" size="4" name="MASK[366]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1468" size="4" name="MASK[367]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1472" size="4" name="MASK[368]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1476" size="4" name="MASK[369]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1480" size="4" name="MASK[370]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1484" size="4" name="MASK[371]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1488" size="4" name="MASK[372]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1492" size="4" name="MASK[373]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1496" size="4" name="MASK[374]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1500" size="4" name="MASK[375]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1504" size="4" name="MASK[376]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1508" size="4" name="MASK[377]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1512" size="4" name="MASK[378]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1516" size="4" name="MASK[379]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1520" size="4" name="MASK[380]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1524" size="4" name="MASK[381]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1528" size="4" name="MASK[382]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1532" size="4" name="MASK[383]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1536" size="4" name="MASK[384]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1540" size="4" name="MASK[385]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1544" size="4" name="MASK[386]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1548" size="4" name="MASK[387]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1552" size="4" name="MASK[388]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1556" size="4" name="MASK[389]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1560" size="4" name="MASK[390]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1564" size="4" name="MASK[391]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1568" size="4" name="MASK[392]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1572" size="4" name="MASK[393]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1576" size="4" name="MASK[394]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1580" size="4" name="MASK[395]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1584" size="4" name="MASK[396]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1588" size="4" name="MASK[397]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1592" size="4" name="MASK[398]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1596" size="4" name="MASK[399]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1600" size="4" name="MASK[400]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1604" size="4" name="MASK[401]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1608" size="4" name="MASK[402]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1612" size="4" name="MASK[403]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1616" size="4" name="MASK[404]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1620" size="4" name="MASK[405]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1624" size="4" name="MASK[406]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1628" size="4" name="MASK[407]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1632" size="4" name="MASK[408]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1636" size="4" name="MASK[409]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1640" size="4" name="MASK[410]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1644" size="4" name="MASK[411]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1648" size="4" name="MASK[412]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1652" size="4" name="MASK[413]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1656" size="4" name="MASK[414]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1660" size="4" name="MASK[415]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1664" size="4" name="MASK[416]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1668" size="4" name="MASK[417]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1672" size="4" name="MASK[418]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1676" size="4" name="MASK[419]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1680" size="4" name="MASK[420]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1684" size="4" name="MASK[421]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1688" size="4" name="MASK[422]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1692" size="4" name="MASK[423]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1696" size="4" name="MASK[424]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1700" size="4" name="MASK[425]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1704" size="4" name="MASK[426]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1708" size="4" name="MASK[427]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1712" size="4" name="MASK[428]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1716" size="4" name="MASK[429]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1720" size="4" name="MASK[430]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1724" size="4" name="MASK[431]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1728" size="4" name="MASK[432]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1732" size="4" name="MASK[433]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1736" size="4" name="MASK[434]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1740" size="4" name="MASK[435]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1744" size="4" name="MASK[436]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1748" size="4" name="MASK[437]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1752" size="4" name="MASK[438]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1756" size="4" name="MASK[439]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1760" size="4" name="MASK[440]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1764" size="4" name="MASK[441]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1768" size="4" name="MASK[442]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1772" size="4" name="MASK[443]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1776" size="4" name="MASK[444]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1780" size="4" name="MASK[445]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1784" size="4" name="MASK[446]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1788" size="4" name="MASK[447]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1792" size="4" name="MASK[448]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1796" size="4" name="MASK[449]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1800" size="4" name="MASK[450]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1804" size="4" name="MASK[451]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1808" size="4" name="MASK[452]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1812" size="4" name="MASK[453]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1816" size="4" name="MASK[454]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1820" size="4" name="MASK[455]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1824" size="4" name="MASK[456]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1828" size="4" name="MASK[457]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1832" size="4" name="MASK[458]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1836" size="4" name="MASK[459]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1840" size="4" name="MASK[460]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1844" size="4" name="MASK[461]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1848" size="4" name="MASK[462]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1852" size="4" name="MASK[463]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1856" size="4" name="MASK[464]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1860" size="4" name="MASK[465]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1864" size="4" name="MASK[466]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1868" size="4" name="MASK[467]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1872" size="4" name="MASK[468]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1876" size="4" name="MASK[469]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1880" size="4" name="MASK[470]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1884" size="4" name="MASK[471]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1888" size="4" name="MASK[472]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1892" size="4" name="MASK[473]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1896" size="4" name="MASK[474]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1900" size="4" name="MASK[475]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1904" size="4" name="MASK[476]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1908" size="4" name="MASK[477]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1912" size="4" name="MASK[478]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1916" size="4" name="MASK[479]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1920" size="4" name="MASK[480]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1924" size="4" name="MASK[481]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1928" size="4" name="MASK[482]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1932" size="4" name="MASK[483]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1936" size="4" name="MASK[484]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1940" size="4" name="MASK[485]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1944" size="4" name="MASK[486]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1948" size="4" name="MASK[487]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1952" size="4" name="MASK[488]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1956" size="4" name="MASK[489]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1960" size="4" name="MASK[490]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1964" size="4" name="MASK[491]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1968" size="4" name="MASK[492]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1972" size="4" name="MASK[493]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1976" size="4" name="MASK[494]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1980" size="4" name="MASK[495]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1984" size="4" name="MASK[496]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1988" size="4" name="MASK[497]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1992" size="4" name="MASK[498]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+1996" size="4" name="MASK[499]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2000" size="4" name="MASK[500]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2004" size="4" name="MASK[501]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2008" size="4" name="MASK[502]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2012" size="4" name="MASK[503]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2016" size="4" name="MASK[504]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2020" size="4" name="MASK[505]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2024" size="4" name="MASK[506]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2028" size="4" name="MASK[507]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2032" size="4" name="MASK[508]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2036" size="4" name="MASK[509]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2040" size="4" name="MASK[510]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+    <Register start="+0x000+2044" size="4" name="MASK[511]" access="Read/Write" description="CAN AF ram access register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="MASK" description="CAN AF RAM mask" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CANAF" start="0x4003C000" description="CAN controller">
+    <Register start="+0x000" size="4" name="AFMR" access="Read/Write" description="Acceptance Filter Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ACCOFF" description="if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored." />
+      <BitField start="1" size="1" name="ACCBP" description="All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers." />
+      <BitField start="2" size="1" name="EFCAN" description="FullCAN mode">
+        <Enum name="SOFTWARE_MUST_READ_A" start="0" description="Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers." />
+        <Enum name="THE_ACCEPTANCE_FILTE" start="1" description="The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="SFF_SA" access="Read/Write" description="Standard Frame Individual Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="9" name="SFF_SA" description="The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="SFF_GRP_SA" access="Read/Write" description="Standard Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="10" name="SFF_GRP_SA" description="The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="EFF_SA" access="Read/Write" description="Extended Frame Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="9" name="EFF_SA" description="The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="EFF_GRP_SA" access="Read/Write" description="Extended Frame Group Start Address Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="10" name="EFF_GRP_SA" description="The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="ENDOFTABLE" access="Read/Write" description="End of AF Tables register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="10" name="ENDOFTABLE" description="The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018" size="4" name="LUTERRAD" access="ReadOnly" description="LUT Error Address register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="9" name="LUTERRAD" description="It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x01C" size="4" name="LUTERR" access="ReadOnly" description="LUT Error Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LUTERR" description="This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="FCANIE" access="Read/Write" description="FullCAN interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FCANIE" description="Global FullCAN Interrupt Enable. When 1, this interrupt is enabled." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x024" size="4" name="FCANIC0" access="Read/Write" description="FullCAN interrupt and capture register0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="INTPND" description="FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31." />
+    </Register>
+    <Register start="+0x028" size="4" name="FCANIC1" access="Read/Write" description="FullCAN interrupt and capture register1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="IntPnd32" description="FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CCAN" start="0x40040000" description=" CAN controller">
+    <Register start="+0x000" size="4" name="TXSR" access="ReadOnly" description="CAN Central Transmit Status Register" reset_value="0x00030300" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TS1" description="When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR)." />
+      <BitField start="1" size="1" name="TS2" description="When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)" />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="TBS1" description="When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR)." />
+      <BitField start="9" size="1" name="TBS2" description="When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR)." />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+      <BitField start="16" size="1" name="TCS1" description="When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR)." />
+      <BitField start="17" size="1" name="TCS2" description="When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR)." />
+      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="RXSR" access="ReadOnly" description="CAN Central Receive Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS1" description="When 1, CAN1 is receiving a message (same as RS in CAN1GSR)." />
+      <BitField start="1" size="1" name="RS2" description="When 1, CAN2 is receiving a message (same as RS in CAN2GSR)." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="RB1" description="When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR)." />
+      <BitField start="9" size="1" name="RB2" description="When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR)." />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+      <BitField start="16" size="1" name="DOS1" description="When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR)." />
+      <BitField start="17" size="1" name="DOS2" description="When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR)." />
+      <BitField start="18" size="14" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="MSR" access="ReadOnly" description="CAN Central Miscellaneous Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E1" description="When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)" />
+      <BitField start="1" size="1" name="E2" description="When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)" />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="BS1" description="When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR)." />
+      <BitField start="9" size="1" name="BS2" description="When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR)." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CAN1" start="0x40044000" description="CAN controller  ">
+    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RM" description="Reset Mode.">
+        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
+        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
+      </BitField>
+      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
+        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
+        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
+      </BitField>
+      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
+        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
+        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
+      </BitField>
+      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
+        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
+        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
+      </BitField>
+      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
+        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
+        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
+      </BitField>
+      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
+        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
+        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="1" name="TM" description="Test Mode.">
+        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
+        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TR" description="Transmission Request.">
+        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
+        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
+      </BitField>
+      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
+        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
+        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
+      </BitField>
+      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
+        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
+        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
+      </BitField>
+      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
+        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
+        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
+      </BitField>
+      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
+        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
+        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
+      </BitField>
+      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
+        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
+        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
+      </BitField>
+      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
+        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
+        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
+      </BitField>
+      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
+        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
+        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
+        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
+        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
+      </BitField>
+      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
+        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
+        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
+      </BitField>
+      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
+        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
+        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
+        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
+        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
+      </BitField>
+      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
+        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
+        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
+      </BitField>
+      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
+        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
+      </BitField>
+      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
+        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
+        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
+      </BitField>
+      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
+        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
+        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
+      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
+      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
+        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
+        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
+      </BitField>
+      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
+        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
+        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
+        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
+        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
+      </BitField>
+      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
+    </Register>
+    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
+      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
+      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
+      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
+      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
+      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
+      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
+      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
+      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
+      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
+      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
+      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
+      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
+      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
+      <BitField start="23" size="1" name="SAM" description="Sampling">
+        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
+        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
+      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
+      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
+        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
+        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
+        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
+        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
+      </BitField>
+      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
+      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
+        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
+      </BitField>
+      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
+      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
+      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
+      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
+      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
+        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
+        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
+        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
+        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
+      </BitField>
+      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
+      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
+        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
+      </BitField>
+      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
+      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
+      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
+      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
+      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
+        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
+        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
+        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
+        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
+      </BitField>
+      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
+      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
+        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
+      </BitField>
+      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
+      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
+      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
+      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
+    </Register>
+    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
+      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
+    </Register>
+    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
+      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
+    </Register>
+    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
+      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
+    </Register>
+    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CAN2" start="0x40048000" description="CAN controller  ">
+    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Controls the operating mode of the CAN Controller." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RM" description="Reset Mode.">
+        <Enum name="NORMAL_THE_CAN_CONTR" start="0" description="Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written." />
+        <Enum name="RESET_CAN_OPERATION" start="1" description="Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted." />
+      </BitField>
+      <BitField start="1" size="1" name="LOM" description="Listen Only Mode.">
+        <Enum name="NORMAL_THE_CAN_CONT" start="0" description="Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value." />
+        <Enum name="LISTEN_ONLY_THE_CON" start="1" description="Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging." />
+      </BitField>
+      <BitField start="2" size="1" name="STM" description="Self Test Mode.">
+        <Enum name="NORMAL_A_TRANSMITTE" start="0" description="Normal. A transmitted message must be acknowledged to be considered successful." />
+        <Enum name="SELF_TEST_THE_CONTR" start="1" description="Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR." />
+      </BitField>
+      <BitField start="3" size="1" name="TPM" description="Transmit Priority Mode.">
+        <Enum name="CAN_ID_THE_TRANSMIT" start="0" description="CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier." />
+        <Enum name="LOCAL_PRIORITY_THE_" start="1" description="Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer." />
+      </BitField>
+      <BitField start="4" size="1" name="SM" description="Sleep Mode.">
+        <Enum name="WAKE_UP_NORMAL_OPER" start="0" description="Wake-up. Normal operation." />
+        <Enum name="SLEEP_THE_CAN_CONTR" start="1" description="Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565." />
+      </BitField>
+      <BitField start="5" size="1" name="RPM" description="Receive Polarity Mode.">
+        <Enum name="LOW_ACTIVE_RD_INPUT" start="0" description="Low active. RD input is active Low (dominant bit = 0)." />
+        <Enum name="HIGH_ACTIVE_RD_INPU" start="1" description="High active. RD input is active High (dominant bit = 1) -- reverse polarity." />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="1" name="TM" description="Test Mode.">
+        <Enum name="DISABLED_NORMAL_OPE" start="0" description="Disabled. Normal operation." />
+        <Enum name="ENABLED_THE_TD_PIN_" start="1" description="Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="CMR" access="WriteOnly" description="Command bits that affect the state of the CAN Controller" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TR" description="Transmission Request.">
+        <Enum name="ABSENT_NO_TRANSMISSI" start="0" description="Absent.No transmission request." />
+        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))" />
+      </BitField>
+      <BitField start="1" size="1" name="AT" description="Abort Transmission.">
+        <Enum name="NO_ACTION_DO_NOT_AB" start="0" description="No action. Do not abort the transmission." />
+        <Enum name="PRESENT_IF_NOT_ALRE" start="1" description="Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled." />
+      </BitField>
+      <BitField start="2" size="1" name="RRB" description="Release Receive Buffer.">
+        <Enum name="NO_ACTION_DO_NOT_RE" start="0" description="No action. Do not release the receive buffer." />
+        <Enum name="RELEASED_THE_INFORM" start="1" description="Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s)." />
+      </BitField>
+      <BitField start="3" size="1" name="CDO" description="Clear Data Overrun.">
+        <Enum name="NO_ACTION_DO_NOT_CL" start="0" description="No action. Do not clear the data overrun bit." />
+        <Enum name="CLEAR_THE_DATA_OVER" start="1" description="Clear. The Data Overrun bit in Status Register(s) is cleared." />
+      </BitField>
+      <BitField start="4" size="1" name="SRR" description="Self Reception Request.">
+        <Enum name="ABSENT_NO_SELF_RECE" start="0" description="Absent. No self reception request." />
+        <Enum name="PRESENT_THE_MESSAGE" start="1" description="Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter." />
+      </BitField>
+      <BitField start="5" size="1" name="STB1" description="Select Tx Buffer 1.">
+        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 1 is not selected for transmission." />
+        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 1 is selected for transmission." />
+      </BitField>
+      <BitField start="6" size="1" name="STB2" description="Select Tx Buffer 2.">
+        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 2 is not selected for transmission." />
+        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 2 is selected for transmission." />
+      </BitField>
+      <BitField start="7" size="1" name="STB3" description="Select Tx Buffer 3.">
+        <Enum name="NOT_SELECTED_TX_BUF" start="0" description="Not selected. Tx Buffer 3 is not selected for transmission." />
+        <Enum name="SELECTED_TX_BUFFER_" start="1" description="Selected. Tx Buffer 3 is selected for transmission." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="GSR" access="ReadOnly" description="Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1." reset_value="0x3C" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBS" description="Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.">
+        <Enum name="EMPTY_NO_MESSAGE_IS" start="0" description="Empty. No message is available." />
+        <Enum name="FULL_AT_LEAST_ONE_C" start="1" description="Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available." />
+      </BitField>
+      <BitField start="1" size="1" name="DOS" description="Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.">
+        <Enum name="ABSENT_NO_DATA_OVER" start="0" description="Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset)." />
+        <Enum name="OVERRUN_A_MESSAGE_W" start="1" description="Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer)." />
+      </BitField>
+      <BitField start="2" size="1" name="TBS" description="Transmit Buffer Status.">
+        <Enum name="LOCKED_AT_LEAST_ONE" start="0" description="Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s)." />
+        <Enum name="RELEASED_ALL_THREE_" start="1" description="Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="3" size="1" name="TCS" description="Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.">
+        <Enum name="INCOMPLETE_AT_LEAST" start="0" description="Incomplete. At least one requested transmission has not been successfully completed yet." />
+        <Enum name="COMPLETE_ALL_REQUES" start="1" description="Complete. All requested transmission(s) has (have) been successfully completed." />
+      </BitField>
+      <BitField start="4" size="1" name="RS" description="Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
+        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
+        <Enum name="RECEIVE_THE_CAN_CON" start="1" description="Receive. The CAN controller is receiving a message." />
+      </BitField>
+      <BitField start="5" size="1" name="TS" description="Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.">
+        <Enum name="IDLE_THE_CAN_CONTRO" start="0" description="Idle. The CAN controller is idle." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN controller is sending a message." />
+      </BitField>
+      <BitField start="6" size="1" name="ES" description="Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).">
+        <Enum name="OK_BOTH_ERROR_COUNT" start="0" description="OK. Both error counters are below the Error Warning Limit." />
+        <Enum name="ERROR_ONE_OR_BOTH_O" start="1" description="Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register." />
+      </BitField>
+      <BitField start="7" size="1" name="BS" description="Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.">
+        <Enum name="BUS_ON_THE_CAN_CONT" start="0" description="Bus-on. The CAN Controller is involved in bus activities" />
+        <Enum name="BUS_OFF_THE_CAN_CON" start="1" description="Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="8" name="RXERR" description="The current value of the Rx Error Counter (an 8-bit value)." />
+      <BitField start="24" size="8" name="TXERR" description="The current value of the Tx Error Counter (an 8-bit value)." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ICR" access="ReadOnly" description="Interrupt status, Arbitration Lost Capture, Error Code Capture" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RI" description="Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="1" size="1" name="TI1" description="Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="2" size="1" name="EI" description="Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="3" size="1" name="DOI" description="Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="4" size="1" name="WUI" description="Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="5" size="1" name="EPI" description="Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="6" size="1" name="ALI" description="Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="7" size="1" name="BEI" description="Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="8" size="1" name="IDI" description="ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="9" size="1" name="TI2" description="Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="10" size="1" name="TI3" description="Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.">
+        <Enum name="RESET" start="0" description="Reset" />
+        <Enum name="SET" start="1" description="Set" />
+      </BitField>
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="5" name="ERRBIT4_0" description="Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt." />
+      <BitField start="21" size="1" name="ERRDIR" description="When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.">
+        <Enum name="ERROR_OCCURRED_DURIN" start="0" description="Error occurred during transmitting." />
+        <Enum name="ERROR_OCCURRED_DURIN" start="1" description="Error occurred during receiving." />
+      </BitField>
+      <BitField start="22" size="2" name="ERRC1_0" description="When the CAN controller detects a bus error, the type of error is captured in this field:">
+        <Enum name="BIT_ERROR" start="0x0" description="Bit error" />
+        <Enum name="FORM_ERROR" start="0x1" description="Form error" />
+        <Enum name="STUFF_ERROR" start="0x2" description="Stuff error" />
+        <Enum name="OTHER_ERROR" start="0x3" description="Other error" />
+      </BitField>
+      <BitField start="24" size="8" name="ALCBIT" description="Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again." />
+    </Register>
+    <Register start="+0x010" size="4" name="IER" access="Read/Write" description="Interrupt Enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RIE" description="Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt." />
+      <BitField start="1" size="1" name="TIE1" description="Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
+      <BitField start="2" size="1" name="EIE" description="Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt." />
+      <BitField start="3" size="1" name="DOIE" description="Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt." />
+      <BitField start="4" size="1" name="WUIE" description="Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested." />
+      <BitField start="5" size="1" name="EPIE" description="Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested." />
+      <BitField start="6" size="1" name="ALIE" description="Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested." />
+      <BitField start="7" size="1" name="BEIE" description="Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt." />
+      <BitField start="8" size="1" name="IDIE" description="ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt." />
+      <BitField start="9" size="1" name="TIE2" description="Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
+      <BitField start="10" size="1" name="TIE3" description="Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="BTR" access="Read/Write" description="Bus Timing. Can only be written when RM in CANMOD is 1." reset_value="0x1C0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="BRP" description="Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock." />
+      <BitField start="10" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="2" name="SJW" description="The Synchronization Jump Width is (this value plus one) CAN clocks." />
+      <BitField start="16" size="4" name="TESG1" description="The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks." />
+      <BitField start="20" size="3" name="TESG2" description="The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks." />
+      <BitField start="23" size="1" name="SAM" description="Sampling">
+        <Enum name="THE_BUS_IS_SAMPLED_O" start="0" description="The bus is sampled once (recommended for high speed buses)" />
+        <Enum name="THE_BUS_IS_SAMPLED_3" start="1" description="The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)" />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018" size="4" name="EWL" access="Read/Write" description="Error Warning Limit. Can only be written when RM in CANMOD is 1." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="EWL" description="During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x3C3C3C" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBS_1" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
+      <BitField start="1" size="1" name="DOS_1" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
+      <BitField start="2" size="1" name="TBS1_1" description="Transmit Buffer Status 1.">
+        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
+        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="3" size="1" name="TCS1_1" description="Transmission Complete Status.">
+        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 1 is not complete." />
+        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed." />
+      </BitField>
+      <BitField start="4" size="1" name="RS_1" description="Receive Status. This bit is identical to the RS bit in the GSR." />
+      <BitField start="5" size="1" name="TS1_1" description="Transmit Status 1.">
+        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 1." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 1." />
+      </BitField>
+      <BitField start="6" size="1" name="ES_1" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
+      <BitField start="7" size="1" name="BS_1" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
+      <BitField start="8" size="1" name="RBS_2" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
+      <BitField start="9" size="1" name="DOS_2" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
+      <BitField start="10" size="1" name="TBS2_2" description="Transmit Buffer Status 2.">
+        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
+        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="11" size="1" name="TCS2_2" description="Transmission Complete Status.">
+        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 2 is not complete." />
+        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed." />
+      </BitField>
+      <BitField start="12" size="1" name="RS_2" description="Receive Status. This bit is identical to the RS bit in the GSR." />
+      <BitField start="13" size="1" name="TS2_2" description="Transmit Status 2.">
+        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 2." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 2." />
+      </BitField>
+      <BitField start="14" size="1" name="ES_2" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
+      <BitField start="15" size="1" name="BS_2" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
+      <BitField start="16" size="1" name="RBS_3" description="Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR." />
+      <BitField start="17" size="1" name="DOS_3" description="Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR." />
+      <BitField start="18" size="1" name="TBS3_3" description="Transmit Buffer Status 3.">
+        <Enum name="LOCKED_SOFTWARE_CAN" start="0" description="Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process." />
+        <Enum name="RELEASED_SOFTWARE_M" start="1" description="Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers." />
+      </BitField>
+      <BitField start="19" size="1" name="TCS3_3" description="Transmission Complete Status.">
+        <Enum name="INCOMPLETE_THE_PREV" start="0" description="Incomplete. The previously requested transmission for Tx Buffer 3 is not complete." />
+        <Enum name="COMPLETE_THE_PREVIO" start="1" description="Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed." />
+      </BitField>
+      <BitField start="20" size="1" name="RS_3" description="Receive Status. This bit is identical to the RS bit in the GSR." />
+      <BitField start="21" size="1" name="TS3_3" description="Transmit Status 3.">
+        <Enum name="IDLE_THERE_IS_NO_TR" start="0" description="Idle. There is no transmission from Tx Buffer 3." />
+        <Enum name="TRANSMIT_THE_CAN_CO" start="1" description="Transmit. The CAN Controller is transmitting a message from Tx Buffer 3." />
+      </BitField>
+      <BitField start="22" size="1" name="ES_3" description="Error Status. This bit is identical to the ES bit in the CANxGSR." />
+      <BitField start="23" size="1" name="BS_3" description="Bus Status. This bit is identical to the BS bit in the CANxGSR." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="RFS" access="Read/Write" description="Receive frame status. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="IDINDEX" description="ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values." />
+      <BitField start="10" size="1" name="BP" description="If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless." />
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="DLC" description="The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding." />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier." />
+      <BitField start="31" size="1" name="FF" description="A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below." />
+    </Register>
+    <Register start="+0x024" size="4" name="RID" access="Read/Write" description="Received Identifier. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="RDA" access="Read/Write" description="Received data bytes 1-4. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If the DLC field in CANRFS &gt;= 0001, this contains the first Data byte of the current received message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If the DLC field in CANRFS &gt;= 0010, this contains the first Data byte of the current received message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If the DLC field in CANRFS &gt;= 0011, this contains the first Data byte of the current received message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If the DLC field in CANRFS &gt;= 0100, this contains the first Data byte of the current received message." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RDB" access="Read/Write" description="Received data bytes 5-8. Can only be written when RM in CANMOD is 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If the DLC field in CANRFS &gt;= 0101, this contains the first Data byte of the current received message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If the DLC field in CANRFS &gt;= 0110, this contains the first Data byte of the current received message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If the DLC field in CANRFS &gt;= 0111, this contains the first Data byte of the current received message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If the DLC field in CANRFS &gt;= 1000, this contains the first Data byte of the current received message." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="TFI1" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
+      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
+    </Register>
+    <Register start="+0x030+16" size="4" name="TFI2" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
+      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
+    </Register>
+    <Register start="+0x030+32" size="4" name="TFI3" access="Read/Write" description="Transmit frame info (Tx Buffer )" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PRIO" description="If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="DLC" description="Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes" />
+      <BitField start="20" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="1" name="RTR" description="This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes." />
+      <BitField start="31" size="1" name="FF" description="If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format)." />
+    </Register>
+    <Register start="+0x034+0" size="4" name="TID1" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034+16" size="4" name="TID2" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034+32" size="4" name="TID3" access="Read/Write" description="Transmit&#xa;Identifier (Tx Buffer)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="ID" description="The 11-bit Identifier to be sent in the next transmit message." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x038+0" size="4" name="TDA1" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x038+16" size="4" name="TDA2" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x038+32" size="4" name="TDA3" access="Read/Write" description="Transmit&#xa;data bytes 1-4 (Tx Buffer)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA1" description="Data 1. If RTR = 0 and DLC &gt;= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA2" description="Data 2. If RTR = 0 and DLC &gt;= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA3" description="Data 3. If RTR = 0 and DLC &gt;= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA4" description="Data 4. If RTR = 0 and DLC &gt;= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x03C+0" size="4" name="TDB1" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x03C+16" size="4" name="TDB2" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
+    </Register>
+    <Register start="+0x03C+32" size="4" name="TDB3" access="Read/Write" description="Transmit&#xa;data bytes 5-8 (Tx Buffer )" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="DATA5" description="Data 5. If RTR = 0 and DLC &gt;= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message." />
+      <BitField start="8" size="8" name="DATA6" description="Data 6. If RTR = 0 and DLC &gt;= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message." />
+      <BitField start="16" size="8" name="DATA7" description="Data 7. If RTR = 0 and DLC &gt;= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message." />
+      <BitField start="24" size="8" name="DATA8" description="Data 8. If RTR = 0 and DLC &gt;= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C1" start="0x4005C000" description="I2C bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP0" start="0x40088000" description="SSP controller">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
+        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="NORMAL" start="0" description="During normal operation." />
+        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
+        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
+      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DAC" start="0x4008C000" description="Digital-to-Analog Converter (DAC) Modification">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN." />
+      <BitField start="16" size="1" name="BIAS" description="Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.">
+        <Enum name="FAST" start="0" description="The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz." />
+        <Enum name="SLOW" start="1" description="The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz." />
+      </BitField>
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC Control register. This register controls DMA and timer operation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA interrupt request">
+        <Enum name="CLEAR_ON_ANY_WRITE_T" start="0" description="Clear on any write to the DACR register." />
+        <Enum name="SET_BY_HARDWARE_WHEN" start="1" description="Set by hardware when the timer times out." />
+      </BitField>
+      <BitField start="1" size="1" name="DBLBUF_ENA" description="Double buffering">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE_WHEN_THIS_BI" start="1" description="Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
+      </BitField>
+      <BitField start="2" size="1" name="CNT_ENA" description="Time-out counter operation">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE" start="1" description="Enable" />
+      </BitField>
+      <BitField start="3" size="1" name="DMA_ENA" description="DMA access">
+        <Enum name="DISABLE" start="0" description="Disable" />
+        <Enum name="ENABLE_DMA_BURST_RE" start="1" description="Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672)." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER2" start="0x40090000" description=" Timer0/1/2/3 ">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
+        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
+        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER3" start="0x40094000" description=" Timer0/1/2/3 ">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR0 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR0 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR1 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR1 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR2 matches the value in the TC." />
+        <Enum name="INTERRUPT_IS_DISABLE" start="0" description="Interrupt is disabled" />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR2 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC" />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="INTERRUPT_IS_GENERAT" start="1" description="Interrupt is generated when MR3 matches the value in the TC." />
+        <Enum name="THIS_INTERRUPT_IS_DI" start="0" description="This interrupt is disabled" />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="TC_WILL_BE_RESET_IF_" start="1" description="TC will be reset if MR3 matches it." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="TC_AND_PC_WILL_BE_ST" start="1" description="TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+        <Enum name="FEATURE_DISABLED_" start="0" description="Feature disabled." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR[0]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR[1]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR[2]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR[3]" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="ENABLE" start="1" description="A CR0 load due to a CAPn.0 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="ENABLE" start="1" description="A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="ENABLE" start="1" description="A CR1 load due to a CAPn.1 event will generate an interrupt." />
+        <Enum name="DISABLE" start="0" description="This feature is disabled." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR[0]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR[1]" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="DO_NOTHING_" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="0x1" description="Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET_THE_CORRESPONDIN" start="0x2" description="Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE_THE_CORRESPON" start="0x3" description="Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE_EVERY_RI" start="0x0" description="Timer Mode: every rising PCLK edge" />
+        <Enum name="RISING" start="0x1" description="Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="FALLING" start="0x2" description="Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="DUALEDGE" start="0x3" description="Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAPN_0_FOR_TIMERN" start="0x0" description="CAPn.0 for TIMERn" />
+        <Enum name="CAPN_1_FOR_TIMERN" start="0x1" description="CAPn.1 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART2" start="0x40098000" description="UART0/2/3 ">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
+        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
+        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
+        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
+        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
+        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
+        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
+        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
+        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
+        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
+        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
+        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
+        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
+        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
+        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select">
+        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
+        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control">
+        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
+        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
+        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
+        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
+        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
+        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
+        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
+        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
+        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
+        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0_" start="0" description="Mode 0." />
+        <Enum name="MODE_1_" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART_" start="0" description="No restart." />
+        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
+        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
+        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
+        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
+        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART3" start="0x4009C000" description="UART0/2/3 ">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
+        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
+        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
+        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
+        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
+        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].">
+        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
+        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).">
+        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
+        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
+        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
+        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of UnFCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
+        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
+        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
+        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select">
+        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
+        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control">
+        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
+        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
+        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
+        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="The UARTn receiver FIFO is empty." />
+        <Enum name="NOTEMPTY" start="1" description="The UARTn receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
+        <Enum name="VALIDDATA" start="0" description="UnTHR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
+        <Enum name="VALIDDATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
+        <Enum name="NOERROR" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
+        <Enum name="ERRORS" start="1" description="UARTn RBR contains at least one UARTn RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
+        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0_" start="0" description="Mode 0." />
+        <Enum name="MODE_1_" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART_" start="0" description="No restart." />
+        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="7" size="1" name="TXEN" description="When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable.">
+        <Enum name="DISABLED" start="0" description="Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
+        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
+        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.">
+        <Enum name="DIRLOW" start="0" description="The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="DIRHIGH" start="1" description="The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C2" start="0x400A0000" description="I2C bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK[0]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK[1]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK[2]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK[3]" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART4" start="0x400A4000" description="UART4  ">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="The UART4 Receiver Buffer Register contains the oldest received byte in the UART4 Rx FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB =0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Writing to the UART4 Transmit Holding Register causes the data to be stored in the UART4 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="The UART4 Divisor Latch LSB Register, along with the U4DLM register, determines the baud rate of the UART4." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="The UART4 Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UART4." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE_THE_RDA_INTE" start="0" description="Disable the RDA interrupts." />
+        <Enum name="ENABLE_THE_RDA_INTER" start="1" description="Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].">
+        <Enum name="DISABLE_THE_THRE_INT" start="0" description="Disable the THRE interrupts." />
+        <Enum name="ENABLE_THE_THRE_INTE" start="1" description="Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].">
+        <Enum name="DISABLE_THE_RX_LINE_" start="0" description="Disable the RX line status interrupts." />
+        <Enum name="ENABLE_THE_RX_LINE_S" start="1" description="Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE_END_OF_AUTO_" start="0" description="Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE_END_OF_AUTO_B" start="1" description="Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE_AUTO_BAUD_TI" start="0" description="Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE_AUTO_BAUD_TIM" start="1" description="Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that U4IIR[0] is active low. The pending interrupt can be determined by evaluating U4IIR[3:1].">
+        <Enum name="AT_LEAST_ONE_INTERRU" start="0" description="At least one interrupt is pending." />
+        <Enum name="NO_INTERRUPT_IS_PEND" start="1" description="No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. U4IER[3:1] identifies an interrupt corresponding to the UART4 Rx or TX FIFO. All other combinations of U4IER[3:1] not listed below are reserved (000,100,101,111).">
+        <Enum name="1_RECEIVE_LINE_S" start="0x3" description="1   - Receive Line Status (RLS)." />
+        <Enum name="2A__RECEIVE_DATA_AV" start="0x2" description="2a - Receive Data Available (RDA)." />
+        <Enum name="2B__CHARACTER_TIME_" start="0x6" description="2b - Character Time-out Indicator (CTI)." />
+        <Enum name="3_THRE_INTERRUPT" start="0x1" description="3   - THRE Interrupt" />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of U4FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART FIFO usage and modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="UARTN_FIFOS_ARE_DISA" start="0" description="UARTn FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ACTIVE_HIGH_ENABLE_F" start="1" description="Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_IMPACT_ON_EITHER_" start="0" description="No impact on either of UARTn FIFOs." />
+        <Enum name="WRITING_A_LOGIC_1_TO" start="1" description="Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 20.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.">
+        <Enum name="TRIGGER_LEVEL_0_1_C" start="0x0" description="Trigger level 0 (1 character or 0x01)." />
+        <Enum name="TRIGGER_LEVEL_1_4_C" start="0x1" description="Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="TRIGGER_LEVEL_2_8_C" start="0x2" description="Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="TRIGGER_LEVEL_3_14_" start="0x3" description="Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length" />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length" />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length" />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length" />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select">
+        <Enum name="1_STOP_BIT_" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1_5_IF_" start="1" description="2 stop bits (1.5 if UnLCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select">
+        <Enum name="ODD_PARITY_NUMBER_O" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY_NUMBER_" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCED_1_STICK_PARIT" start="0x2" description="Forced 1 stick parity." />
+        <Enum name="FORCED_0_STICK_PARIT" start="0x3" description="Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control">
+        <Enum name="DISABLE_BREAK_TRANSM" start="0" description="Disable break transmission." />
+        <Enum name="ENABLE_BREAK_TRANSMI" start="1" description="Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit">
+        <Enum name="DISABLE_ACCESS_TO_DI" start="0" description="Disable access to Divisor Latches." />
+        <Enum name="ENABLE_ACCESS_TO_DIV" start="1" description="Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.">
+        <Enum name="THE_UARTN_RECEIVER_F" start="0" description="The UARTn receiver FIFO is empty." />
+        <Enum name="THE_UARTN_RECEIVER_F" start="1" description="The UARTn receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.">
+        <Enum name="OVERRUN_ERROR_STATUS" start="0" description="Overrun error status is inactive." />
+        <Enum name="OVERRUN_ERROR_STATUS" start="1" description="Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="PARITY_ERROR_STATUS_" start="0" description="Parity error status is inactive." />
+        <Enum name="PARITY_ERROR_STATUS_" start="1" description="Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="FRAMING_ERROR_STATUS" start="0" description="Framing error status is inactive." />
+        <Enum name="FRAMING_ERROR_STATUS" start="1" description="Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.">
+        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
+        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.">
+        <Enum name="UNTHR_CONTAINS_VALID" start="0" description="UnTHR contains valid data." />
+        <Enum name="UNTHR_IS_EMPTY_" start="1" description="UnTHR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.">
+        <Enum name="VALID_DATA" start="0" description="UnTHR and/or the UnTSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="UnTHR and the UnTSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.">
+        <Enum name="UNRBR_CONTAINS_NO_UA" start="0" description="UnRBR contains no UARTn RX errors or UnFCR[0]=0." />
+        <Enum name="UARTN_RBR_CONTAINS_A" start="1" description="UARTn RBR contains at least one UARTn RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Pad" description="A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="AUTO_BAUD_STOP_AUTO" start="0" description="Auto-baud stop (auto-baud is not running)." />
+        <Enum name="AUTO_BAUD_START_AUT" start="1" description="Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0_" start="0" description="Mode 0." />
+        <Enum name="MODE_1_" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART_" start="0" description="No restart." />
+        <Enum name="RESTART_IN_CASE_OF_T" start="1" description="Restart in case of time-out (counter restarts at next UARTn Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.">
+        <Enum name="NO_IMPACT_" start="0" description="No impact." />
+        <Enum name="CLEAR_THE_CORRESPOND" start="1" description="Clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA Control Register. Enables and configures the IrDA mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode">
+        <Enum name="DISABLED_IRDA_MODE_" start="0" description="Disabled. IrDA mode on UART4 is disabled, UART4 acts as a standard UART." />
+        <Enum name="ENABLED_IRDA_MODE_O" start="1" description="Enabled. IrDA mode on UART4 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED_" start="0" description="Not inverted." />
+        <Enum name="INVERTED_THIS_HAS_N" start="1" description="Inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1.">
+        <Enum name="2XTPCLK" start="0x0" description="2xTPCLK" />
+        <Enum name="4XTPCLK" start="0x1" description="4xTPCLK" />
+        <Enum name="8XTPCLK" start="0x2" description="8xTPCLK" />
+        <Enum name="16XTPCLK" start="0x3" description="16xTPCLK" />
+        <Enum name="32XTPCLK" start="0x4" description="32xTPCLK" />
+        <Enum name="64XTPCLK" start="0x5" description="64xTPCLK" />
+        <Enum name="128XTPCLK" start="0x6" description="128xTPCLK" />
+        <Enum name="256XTPCLK" start="0x7" description="256xTPCLK" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud Rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART4 baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud Rate pre-scaler multiplier value. This field must be greater or equal 1 for UART4 to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In smartcard mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart Card Interface control register. Enables and configures the smartcard Interface feature." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="SMART_CARD_INTERFACE" start="0" description="Smart card interface disabled." />
+        <Enum name="ASYNCHRONOUS_HALF_DU" start="1" description="Asynchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="A_NACK_RESPONSE_IS_E" start="0" description="A NACK response is enabled." />
+        <Enum name="A_NACK_RESPONSE_IS_I" start="1" description="A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt. See Section 20.6.18 RS-485/EIA-485 modes of operation." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED_" start="0" description="Enabled." />
+        <Enum name="DISABLED_" start="1" description="Disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLED_" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLE_AUTO_DIRECTI" start="0" description="Disable Auto Direction Control." />
+        <Enum name="ENABLE_AUTO_DIRECTIO" start="1" description="Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW_THE_DIRECTION_C" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH_THE_DIRECTION_" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (U4OE) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SYNCHRONOUS_SLAVE_MO" start="0" description="Synchronous slave mode (SCLK in)" />
+        <Enum name="SYNCHRONOUS_MASTER_M" start="1" description="Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Falling edge sampling.">
+        <Enum name="RXD_IS_SAMPLED_ON_TH" start="0" description="RxD is sampled on the rising edge of SCLK" />
+        <Enum name="RXD_IS_SAMPLED_ON_TH" start="1" description="RxD is sampled on the falling edge of SCLK" />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="THE_INPUT_CLOCK_IS_S" start="0" description="The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="THE_INPUT_CLOCK_IS_N" start="1" description="The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="SCLK_CYCLES_ONLY_WHE" start="0" description="SCLK cycles only when characters are being sent on TxD" />
+        <Enum name="SCLK_RUNS_CONTINUOUS" start="1" description="SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)" />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND_START_AND_STOP_" start="0" description="Send start and stop bits as in other modes." />
+        <Enum name="NOSTARTSTOPBIT" start="1" description="Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="CSCEN_IS_UNDER_SOFTW" start="0" description="CSCEN is under software control." />
+        <Enum name="HARDWARE_CLEARS_CSCE" start="1" description="Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2S" start="0x400A8000" description="I2S interface">
+    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
+      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
+      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
+      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
+        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
+        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
+      </BitField>
+      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
+        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
+        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
+      </BitField>
+      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCPWM" start="0x400B8000" description="Motor Control PWM">
+    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
+        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
+        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
+      </BitField>
+      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
+        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
+        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
+      </BitField>
+      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
+        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
+        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
+      </BitField>
+    </Register>
+    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
+    </Register>
+    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
+      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
+      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
+      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="TC[0]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="TC[1]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="TC[2]" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x024+0" size="4" name="LIM[0]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x024+4" size="4" name="LIM[1]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x024+8" size="4" name="LIM[2]" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MAT[0]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MAT[1]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MAT[2]" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
+      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
+      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
+      <BitField start="30" size="2" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
+        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
+        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
+      </BitField>
+      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
+        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
+        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
+        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
+        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
+        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
+        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
+        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
+        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
+        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
+        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x044+0" size="4" name="CAP[0]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x044+4" size="4" name="CAP[1]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x044+8" size="4" name="CAP[2]" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
+      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 0." />
+        <Enum name="FALLLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI0 does not affect counter 2." />
+        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI0 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI1 does not affect counter 2." />
+        <Enum name="RISING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI1 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
+        <Enum name="A_RISING_EDGE_ON_MCI" start="0" description="A rising edge on MCI2 does not affect counter 2." />
+        <Enum name="RISIING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
+        <Enum name="A_FALLING_EDGE_ON_MC" start="0" description="A falling edge on MCI2 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
+        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
+        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
+      </BitField>
+      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
+        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
+        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
+      </BitField>
+      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
+        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
+        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
+      </BitField>
+    </Register>
+    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+    </Register>
+    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+    </Register>
+    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
+      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
+      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="QEI" start="0x400BC000" description="Quadrature Encoder Interface (QEI)  ">
+    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
+      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared." />
+      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared." />
+      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When 1, complements the DIR bit." />
+      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal." />
+      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
+      <BitField start="3" size="1" name="INVINX" description="Invert Index. When 1, inverts the sense of the index input." />
+      <BitField start="4" size="1" name="CRESPI" description="Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration)." />
+      <BitField start="5" size="11" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="POS" description="Current position value." />
+    </Register>
+    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MAXPOS" description="Current maximum position value." />
+    </Register>
+    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="Position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
+    </Register>
+    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="Position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
+    </Register>
+    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="Position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
+    </Register>
+    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ENCPOS" description="Current index counter value." />
+    </Register>
+    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP0" description="Index compare value 0." />
+    </Register>
+    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
+    </Register>
+    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
+    </Register>
+    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
+    </Register>
+    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELCAP" description="Last velocity capture." />
+    </Register>
+    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELPC" description="Compare velocity pulse count." />
+    </Register>
+    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on PHA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay for PhA." />
+    </Register>
+    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on PHB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay for PhB." />
+    </Register>
+    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on IDX" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay for the index." />
+    </Register>
+    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width." />
+    </Register>
+    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
+    </Register>
+    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_INT" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_INT" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_INT" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_INT" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_INT" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_INT" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_INT" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_INT" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_INT" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV0_INT" description="Indicates that the index compare 0 value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_INT" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_INT" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_INT" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set." />
+      <BitField start="13" size="1" name="REV1_INT" description="Indicates that the index compare 1value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_INT" description="Indicates that the index compare 2 value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_INT" description="Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 sets the INX_Int bit in QEIINTSTAT." />
+      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 sets the TIN_Int bit in QEIINTSTAT." />
+      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 sets the VELC_Int bit in QEIINTSTAT." />
+      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 sets the DIR_Int bit in QEIINTSTAT." />
+      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 sets the ERR_Int bit in QEIINTSTAT." />
+      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT." />
+      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 sets the POS0_Int bit in QEIINTSTAT." />
+      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 sets the POS1_Int bit in QEIINTSTAT." />
+      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 sets the POS2_Int bit in QEIINTSTAT." />
+      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 sets the REV0_Int bit in QEIINTSTAT." />
+      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT." />
+      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT." />
+      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT." />
+      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 sets the REV1_Int bit in QEIINTSTAT." />
+      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 sets the REV2_Int bit in QEIINTSTAT." />
+      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 clears the INX_Int bit in QEIINTSTAT." />
+      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 clears the TIN_Int bit in QEIINTSTAT." />
+      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 clears the VELC_Int bit in QEIINTSTAT." />
+      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 clears the DIR_Int bit in QEIINTSTAT." />
+      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 clears the ERR_Int bit in QEIINTSTAT." />
+      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT." />
+      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 clears the POS0_Int bit in QEIINTSTAT." />
+      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 clears the POS1_Int bit in QEIINTSTAT." />
+      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 clears the POS2_Int bit in QEIINTSTAT." />
+      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 clears the REV0_Int bit in QEIINTSTAT." />
+      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT." />
+      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT." />
+      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT." />
+      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 clears the REV1_Int bit in QEIINTSTAT." />
+      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 clears the REV2_Int bit in QEIINTSTAT." />
+      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_INT" description="When 1, the INX_Int interrupt is enabled." />
+      <BitField start="1" size="1" name="TIM_INT" description="When 1, the TIN_Int interrupt is enabled." />
+      <BitField start="2" size="1" name="VELC_INT" description="When 1, the VELC_Int interrupt is enabled." />
+      <BitField start="3" size="1" name="DIR_INT" description="When 1, the DIR_Int interrupt is enabled." />
+      <BitField start="4" size="1" name="ERR_INT" description="When 1, the ERR_Int interrupt is enabled." />
+      <BitField start="5" size="1" name="ENCLK_INT" description="When 1, the ENCLK_Int interrupt is enabled." />
+      <BitField start="6" size="1" name="POS0_INT" description="When 1, the POS0_Int interrupt is enabled." />
+      <BitField start="7" size="1" name="POS1_INT" description="When 1, the POS1_Int interrupt is enabled." />
+      <BitField start="8" size="1" name="POS2_INT" description="When 1, the POS2_Int interrupt is enabled." />
+      <BitField start="9" size="1" name="REV0_INT" description="When 1, the REV0_Int interrupt is enabled." />
+      <BitField start="10" size="1" name="POS0REV_INT" description="When 1, the POS0REV_Int interrupt is enabled." />
+      <BitField start="11" size="1" name="POS1REV_INT" description="When 1, the POS1REV_Int interrupt is enabled." />
+      <BitField start="12" size="1" name="POS2REV_INT" description="When 1, the POS2REV_Int interrupt is enabled." />
+      <BitField start="13" size="1" name="REV1_INT" description="When 1, the REV1_Int interrupt is enabled." />
+      <BitField start="14" size="1" name="REV2_INT" description="When 1, the REV2_Int interrupt is enabled." />
+      <BitField start="15" size="1" name="MAXPOS_INT" description="When 1, the MAXPOS_Int interrupt is enabled." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 enables the INX_Int interrupt in the QEIIE register." />
+      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 enables the TIN_Int interrupt in the QEIIE register." />
+      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 enables the VELC_Int interrupt in the QEIIE register." />
+      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 enables the DIR_Int interrupt in the QEIIE register." />
+      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 enables the ERR_Int interrupt in the QEIIE register." />
+      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register." />
+      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 enables the POS0_Int interrupt in the QEIIE register." />
+      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 enables the POS1_Int interrupt in the QEIIE register." />
+      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 enables the POS2_Int interrupt in the QEIIE register." />
+      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 enables the REV0_Int interrupt in the QEIIE register." />
+      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register." />
+      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register." />
+      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register." />
+      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 enables the REV1_Int interrupt in the QEIIE register." />
+      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 enables the REV2_Int interrupt in the QEIIE register." />
+      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INX_INT" description="Writing a 1 disables the INX_Int interrupt in the QEIIE register." />
+      <BitField start="1" size="1" name="TIM_INT" description="Writing a 1 disables the TIN_Int interrupt in the QEIIE register." />
+      <BitField start="2" size="1" name="VELC_INT" description="Writing a 1 disables the VELC_Int interrupt in the QEIIE register." />
+      <BitField start="3" size="1" name="DIR_INT" description="Writing a 1 disables the DIR_Int interrupt in the QEIIE register." />
+      <BitField start="4" size="1" name="ERR_INT" description="Writing a 1 disables the ERR_Int interrupt in the QEIIE register." />
+      <BitField start="5" size="1" name="ENCLK_INT" description="Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register." />
+      <BitField start="6" size="1" name="POS0_INT" description="Writing a 1 disables the POS0_Int interrupt in the QEIIE register." />
+      <BitField start="7" size="1" name="POS1_INT" description="Writing a 1 disables the POS1_Int interrupt in the QEIIE register." />
+      <BitField start="8" size="1" name="POS2_INT" description="Writing a 1 disables the POS2_Int interrupt in the QEIIE register." />
+      <BitField start="9" size="1" name="REV0_INT" description="Writing a 1 disables the REV0_Int interrupt in the QEIIE register." />
+      <BitField start="10" size="1" name="POS0REV_INT" description="Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register." />
+      <BitField start="11" size="1" name="POS1REV_INT" description="Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register." />
+      <BitField start="12" size="1" name="POS2REV_INT" description="Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register." />
+      <BitField start="13" size="1" name="REV1_INT" description="Writing a 1 disables the REV1_Int interrupt in the QEIIE register." />
+      <BitField start="14" size="1" name="REV2_INT" description="Writing a 1 disables the REV2_Int interrupt in the QEIIE register." />
+      <BitField start="15" size="1" name="MAXPOS_INT" description="Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC" start="0x400C0000" description="SD card">
+    <Register start="+0x000" size="4" name="PWR" access="Read/Write" description="Power control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTRL" description="Power control">
+        <Enum name="POWER_OFF" start="0x0" description="Power-off" />
+        <Enum name="POWER_UP" start="0x2" description="Power-up" />
+        <Enum name="POWER_ON" start="0x3" description="Power-on" />
+      </BitField>
+      <BitField start="2" size="4" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="6" size="1" name="OPENDRAIN" description="SD_CMD output control." />
+      <BitField start="7" size="1" name="ROD" description="Rod control." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x004" size="4" name="CLOCK" access="Read/Write" description="Clock control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CLKDIV" description="Bus clock period: SD_CLK frequency = MCLK / [2x(ClkDiv+1)]." />
+      <BitField start="8" size="1" name="ENABLE" description="Enable SD card bus clock:">
+        <Enum name="CLOCK_DISABLED_" start="0" description="Clock disabled." />
+        <Enum name="CLOCK_ENABLED_" start="1" description="Clock enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="PWRSAVE" description="Disable SD_CLK output when bus is idle:">
+        <Enum name="ALWAYS_ENABLED_" start="0" description="Always enabled." />
+        <Enum name="CLOCK_ENABLED_WHEN_B" start="1" description="Clock enabled when bus is active." />
+      </BitField>
+      <BitField start="10" size="1" name="BYPASS" description="Enable bypass of clock divide logic:">
+        <Enum name="DISABLE_BYPASS_" start="0" description="Disable bypass." />
+        <Enum name="ENABLE_BYPASS_MCLK_" start="1" description="Enable bypass. MCLK driven to card bus output (SD_CLK)." />
+      </BitField>
+      <BitField start="11" size="1" name="WIDEBUS" description="Enable wide bus mode.">
+        <Enum name="STANDARD_BUS_MODE_O" start="0" description="Standard bus mode (only SD_DAT[0] used)." />
+        <Enum name="WIDE_BUS_MODE_SD_DA" start="1" description="Wide bus mode (SD_DAT[3:0] used)" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="ARGUMENT" access="Read/Write" description="Argument register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CmdArg" description="Command argument" />
+    </Register>
+    <Register start="+0x00C" size="4" name="COMMAND" access="Read/Write" description="Command register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="CmdIndex" description="Command index." />
+      <BitField start="6" size="1" name="Response" description="If set, CPSM waits for a response." />
+      <BitField start="7" size="1" name="LongRsp" description="If set, CPSM receives a 136 bit long response." />
+      <BitField start="8" size="1" name="Interrupt" description="If set, CPSM disables command timer and waits for interrupt request." />
+      <BitField start="9" size="1" name="Pending" description="If set, CPSM waits for CmdPend before it starts sending a command." />
+      <BitField start="10" size="1" name="Enable" description="If set, CPSM is enabled." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="RESPCMD" access="ReadOnly" description="Response command register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESPCMD" description="Response command index" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x014+0" size="4" name="RESPONSE0" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="STATUS" description="Card status" />
+    </Register>
+    <Register start="+0x014+4" size="4" name="RESPONSE1" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="STATUS" description="Card status" />
+    </Register>
+    <Register start="+0x014+8" size="4" name="RESPONSE2" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="STATUS" description="Card status" />
+    </Register>
+    <Register start="+0x014+12" size="4" name="RESPONSE3" access="ReadOnly" description="Response register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="STATUS" description="Card status" />
+    </Register>
+    <Register start="+0x024" size="4" name="DATATIMER" access="Read/Write" description="Data Timer." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATATIME" description="Data timeout period." />
+    </Register>
+    <Register start="+0x028" size="4" name="DATALENGTH" access="Read/Write" description="Data length register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATALENGTH" description="Data length value" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATACTRL" access="Read/Write" description="Data control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENABLE" description="Data transfer enable." />
+      <BitField start="1" size="1" name="DIRECTION" description="Data transfer direction">
+        <Enum name="FROM_CONTROLLER_TO_C" start="0" description="From controller to card." />
+        <Enum name="FROM_CARD_TO_CONTROL" start="1" description="From card to controller." />
+      </BitField>
+      <BitField start="2" size="1" name="MODE" description="Data transfer mode">
+        <Enum name="BLOCK_DATA_TRANSFER_" start="0" description="Block data transfer." />
+        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAENABLE" description="Enable DMA">
+        <Enum name="DMA_DISABLED_" start="0" description="DMA disabled." />
+        <Enum name="DMA_ENABLED_" start="1" description="DMA enabled." />
+      </BitField>
+      <BitField start="4" size="4" name="BLOCKSIZE" description="Data block length" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x030" size="4" name="DATACNT" access="ReadOnly" description="Data counter." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATACOUNT" description="Remaining data" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x034" size="4" name="STATUS" access="ReadOnly" description="Status register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CMDCRCFAIL" description="Command response received (CRC check failed)." />
+      <BitField start="1" size="1" name="DATACRCFAIL" description="Data block sent/received (CRC check failed)." />
+      <BitField start="2" size="1" name="CMDTIMEOUT" description="Command response timeout." />
+      <BitField start="3" size="1" name="DATATIMEOUT" description="Data timeout." />
+      <BitField start="4" size="1" name="TXUNDERRUN" description="Transmit FIFO underrun error." />
+      <BitField start="5" size="1" name="RXOVERRUN" description="Receive FIFO overrun error." />
+      <BitField start="6" size="1" name="CMDRESPEND" description="Command response received (CRC check passed)." />
+      <BitField start="7" size="1" name="CMDSENT" description="Command sent (no response required)." />
+      <BitField start="8" size="1" name="DATAEND" description="Data end (data counter is zero)." />
+      <BitField start="9" size="1" name="STARTBITERR" description="Start bit not detected on all data signals in wide bus mode." />
+      <BitField start="10" size="1" name="DATABLOCKEND" description="Data block sent/received (CRC check passed)." />
+      <BitField start="11" size="1" name="CMDACTIVE" description="Command transfer in progress." />
+      <BitField start="12" size="1" name="TXACTIVE" description="Data transmit in progress." />
+      <BitField start="13" size="1" name="RXACTIVE" description="Data receive in progress." />
+      <BitField start="14" size="1" name="TXFIFOHALFEMPTY" description="Transmit FIFO half empty." />
+      <BitField start="15" size="1" name="RXFIFOHALFFULL" description="Receive FIFO half full." />
+      <BitField start="16" size="1" name="TXFIFOFULL" description="Transmit FIFO full." />
+      <BitField start="17" size="1" name="RXFIFOFULL" description="Receive FIFO full." />
+      <BitField start="18" size="1" name="TXFIFOEMPTY" description="Transmit FIFO empty." />
+      <BitField start="19" size="1" name="RXFIFOEMPTY" description="Receive FIFO empty." />
+      <BitField start="20" size="1" name="TXDATAAVLBL" description="Data available in transmit FIFO." />
+      <BitField start="21" size="1" name="RXDATAAVLBL" description="Data available in receive FIFO." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="CLEAR" access="WriteOnly" description="Clear register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CMDCRCFAILCLR" description="Clears CmdCrcFail flag." />
+      <BitField start="1" size="1" name="DATACRCFAILCLR" description="Clears DataCrcFail flag." />
+      <BitField start="2" size="1" name="CMDTIMEOUTCLR" description="Clears CmdTimeOut flag." />
+      <BitField start="3" size="1" name="DATATIMEOUTCLR" description="Clears DataTimeOut flag." />
+      <BitField start="4" size="1" name="TXUNDERRUNCLR" description="Clears TxUnderrun flag." />
+      <BitField start="5" size="1" name="RXOVERRUNCLR" description="Clears RxOverrun flag." />
+      <BitField start="6" size="1" name="CMDRESPENDCLR" description="Clears CmdRespEnd flag." />
+      <BitField start="7" size="1" name="CMDSENTCLR" description="Clears CmdSent flag." />
+      <BitField start="8" size="1" name="DATAENDCLR" description="Clears DataEnd flag." />
+      <BitField start="9" size="1" name="STARTBITERRCLR" description="Clears StartBitErr flag." />
+      <BitField start="10" size="1" name="DATABLOCKENDCLR" description="Clears DataBlockEnd flag." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x03C" size="4" name="MASK0" access="Read/Write" description="Interrupt 0 mask register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASK0" description="Mask CmdCrcFail flag." />
+      <BitField start="1" size="1" name="MASK1" description="Mask DataCrcFail flag." />
+      <BitField start="2" size="1" name="MASK2" description="Mask CmdTimeOut flag." />
+      <BitField start="3" size="1" name="MASK3" description="Mask DataTimeOut flag." />
+      <BitField start="4" size="1" name="MASK4" description="Mask TxUnderrun flag." />
+      <BitField start="5" size="1" name="MASK5" description="Mask RxOverrun flag." />
+      <BitField start="6" size="1" name="MASK6" description="Mask CmdRespEnd flag." />
+      <BitField start="7" size="1" name="MASK7" description="Mask CmdSent flag." />
+      <BitField start="8" size="1" name="MASK8" description="Mask DataEnd flag." />
+      <BitField start="9" size="1" name="MASK9" description="Mask StartBitErr flag." />
+      <BitField start="10" size="1" name="MASK10" description="Mask DataBlockEnd flag." />
+      <BitField start="11" size="1" name="MASK11" description="Mask CmdActive flag." />
+      <BitField start="12" size="1" name="MASK12" description="Mask TxActive flag." />
+      <BitField start="13" size="1" name="MASK13" description="Mask RxActive flag." />
+      <BitField start="14" size="1" name="MASK14" description="Mask TxFifoHalfEmpty flag." />
+      <BitField start="15" size="1" name="MASK15" description="Mask RxFifoHalfFull flag." />
+      <BitField start="16" size="1" name="MASK16" description="Mask TxFifoFull flag." />
+      <BitField start="17" size="1" name="MASK17" description="Mask RxFifoFull flag." />
+      <BitField start="18" size="1" name="MASK18" description="Mask TxFifoEmpty flag." />
+      <BitField start="19" size="1" name="MASK19" description="Mask RxFifoEmpty flag." />
+      <BitField start="20" size="1" name="MASK20" description="Mask TxDataAvlbl flag." />
+      <BitField start="21" size="1" name="MASK21" description="Mask RxDataAvlbl flag." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x048" size="4" name="FIFOCNT" access="ReadOnly" description="FIFO Counter." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="15" name="DATACOUNT" description="Remaining data" />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x080+0" size="4" name="FIFO0" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+4" size="4" name="FIFO1" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+8" size="4" name="FIFO2" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+12" size="4" name="FIFO3" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+16" size="4" name="FIFO4" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+20" size="4" name="FIFO5" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+24" size="4" name="FIFO6" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+28" size="4" name="FIFO7" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+32" size="4" name="FIFO8" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+36" size="4" name="FIFO9" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+40" size="4" name="FIFO10" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+44" size="4" name="FIFO11" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+48" size="4" name="FIFO12" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+52" size="4" name="FIFO13" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+56" size="4" name="FIFO14" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+    <Register start="+0x080+60" size="4" name="FIFO15" access="Read/Write" description="Data FIFO Register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="FIFO data." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SYSCON" start="0x400FC000" description=" System and clock control ">
+    <Register start="+0x000" size="4" name="FLASHCFG" access="Read/Write" description="Flash Accelerator Configuration Register. Controls flash access timing." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved, user software should not change these bits from the reset value." />
+      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. All other values are reserved.">
+        <Enum name="FLASH_ACCESSES_USE_1" start="0x0" description="Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off." />
+        <Enum name="FLASH_ACCESSES_USE_2" start="0x1" description="Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost off." />
+        <Enum name="FLASH_ACCESSES_USE_3" start="0x2" description="Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost off." />
+        <Enum name="FLASH_ACCESSES_USE_4" start="0x3" description="Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost off. Use this setting for operation from 100 to 120 MHz operation with power boost on." />
+        <Enum name="FLASH_ACCESSES_USE_5" start="0x4" description="Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost off." />
+        <Enum name="FLASH_ACCESSES_USE_6" start="0x5" description="Flash accesses use 6 CPU clocks. Safe setting for any allowed conditions." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x080+0" size="4" name="PLLCON0" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x080+32" size="4" name="PLLCON1" access="Read/Write" description="PLL Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PLLE" description="PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL and allow it to lock to the requested frequency. See PLLSTAT register, Table 12." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x084+0" size="4" name="PLLCFG0" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value &quot;M&quot; in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." />
+      <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value &quot;P&quot; in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x084+32" size="4" name="PLLCFG1" access="Read/Write" description="PLL Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="MSEL" description="PLL Multiplier value. Supplies the value &quot;M&quot; in the PLL frequency calculations. Note: For details on selecting the right value for MSEL see Section 3.10.4." />
+      <BitField start="5" size="2" name="PSEL" description="PLL Divider value. Supplies the value &quot;P&quot; in the PLL frequency calculations. Note: For details on selecting the right value for PSEL see Section 3.10.4." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x088+0" size="4" name="PLLSTAT0" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." />
+      <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x088+32" size="4" name="PLLSTAT1" access="ReadOnly" description="PLL Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="MSEL" description="Read-back for the PLL Multiplier value. This is the value currently used by the related PLL." />
+      <BitField start="5" size="2" name="PSEL" description="Read-back for the PLL Divider value. This is the value currently used by the related PLL." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="PLLE_STAT" description="Read-back for the PLL Enable bit. When one, the related PLL is currently activated. When zero, the related PLL is turned off. This bit is automatically cleared when Power-down mode is activated." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="10" size="1" name="PLOCK" description="Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the related PLL is locked onto the requested frequency." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x08C+0" size="4" name="PLLFEED0" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x08C+32" size="4" name="PLLFEED1" access="WriteOnly" description="PLL Feed register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="PLLFEED" description="The PLL feed sequence must be written to this register in order for the related PLL's configuration and control register changes to take effect." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x0C0" size="4" name="PCON" access="Read/Write" description="Power Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PM0" description="Power mode control bit 0. This bit controls entry to the Power-down mode. See Section 3.3.6.1 below for details." />
+      <BitField start="1" size="1" name="PM1" description="Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See Section 3.3.6.1 below for details." />
+      <BitField start="2" size="1" name="BODRPM" description="Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection." />
+      <BitField start="3" size="1" name="BOGD" description="Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection." />
+      <BitField start="4" size="1" name="BORD" description="Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled. See the Section 3.6 for details of Brown-Out detection." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="SMFLAG" description="Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
+      <BitField start="9" size="1" name="DSFLAG" description="Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit." />
+      <BitField start="10" size="1" name="PDFLAG" description="Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
+      <BitField start="11" size="1" name="DPDFLAG" description="Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x0C4" size="4" name="PCONP0" access="Read/Write" description="Power Control for Peripherals" reset_value="0x0408829E" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PCLCD" description="LCD controller power/clock control bit." />
+      <BitField start="1" size="1" name="PCTIM0" description="Timer/Counter 0 power/clock control bit." />
+      <BitField start="2" size="1" name="PCTIM1" description="Timer/Counter 1 power/clock control bit." />
+      <BitField start="3" size="1" name="PCUART0" description="UART0 power/clock control bit." />
+      <BitField start="4" size="1" name="PCUART1" description="UART1 power/clock control bit." />
+      <BitField start="5" size="1" name="PCPWM0" description="PWM0 power/clock control bit." />
+      <BitField start="6" size="1" name="PCPWM1" description="PWM1 power/clock control bit." />
+      <BitField start="7" size="1" name="PCI2C0" description="I2C0 interface power/clock control bit." />
+      <BitField start="8" size="1" name="PCUART4" description="UART4 power/clock control bit." />
+      <BitField start="9" size="1" name="PCRTC" description="RTC and Event Monitor/Recorder power/clock control bit." />
+      <BitField start="10" size="1" name="PCSSP1" description="SSP 1 interface power/clock control bit." />
+      <BitField start="11" size="1" name="PCEMC" description="External Memory Controller power/clock control bit." />
+      <BitField start="12" size="1" name="PCADC" description="A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before attempting to set PDN." />
+      <BitField start="13" size="1" name="PCCAN1" description="CAN Controller 1 power/clock control bit." />
+      <BitField start="14" size="1" name="PCCAN2" description="CAN Controller 2 power/clock control bit." />
+      <BitField start="15" size="1" name="PCGPIO" description="Power/clock control bit for IOCON, GPIO, and GPIO interrupts." />
+      <BitField start="16" size="1" name="PCSPIFI" description="SPI Flash Interface power/clock control bit." />
+      <BitField start="17" size="1" name="PCMCPWM" description="Motor Control PWM power/clock control bit." />
+      <BitField start="18" size="1" name="PCQEI" description="Quadrature Encoder Interface power/clock control bit." />
+      <BitField start="19" size="1" name="PCI2C1" description="I2C1 interface power/clock control bit." />
+      <BitField start="20" size="1" name="PCSSP2" description="SSP2 interface power/clock control bit." />
+      <BitField start="21" size="1" name="PCSSP0" description="SSP0 interface power/clock control bit." />
+      <BitField start="22" size="1" name="PCTIM2" description="Timer 2 power/clock control bit." />
+      <BitField start="23" size="1" name="PCTIM3" description="Timer 3 power/clock control bit." />
+      <BitField start="24" size="1" name="PCUART2" description="UART 2 power/clock control bit." />
+      <BitField start="25" size="1" name="PCUART3" description="UART 3 power/clock control bit." />
+      <BitField start="26" size="1" name="PCI2C2" description="I2C interface 2 power/clock control bit." />
+      <BitField start="27" size="1" name="PCI2S" description="I2S interface power/clock control bit." />
+      <BitField start="28" size="1" name="PCSDC" description="SD Card interface power/clock control bit." />
+      <BitField start="29" size="1" name="PCGPDMA" description="GPDMA function power/clock control bit." />
+      <BitField start="30" size="1" name="PCENET" description="Ethernet block power/clock control bit." />
+      <BitField start="31" size="1" name="PCUSB" description="USB interface power/clock control bit." />
+    </Register>
+    <Register start="+0x0C8" size="4" name="PCONP1" access="Read/Write" description="Power Control for Peripherals" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="3" size="1" name="PCCMP" description="comparator 0/1 power/clock control bit." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x100" size="4" name="EMCCLKSEL" access="Read/Write" description="External Memory Controller Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EMCDIV" description="Selects the EMC clock rate relative to the CPU clock.">
+        <Enum name="THE_EMC_USES_THE_SAM" start="0" description="The EMC uses the same clock as the CPU." />
+        <Enum name="THE_EMC_USES_A_CLOCK" start="1" description="The EMC uses a clock at half the rate of the CPU." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x104" size="4" name="CCLKSEL" access="Read/Write" description="CPU Clock Selection register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="5" name="CCLKDIV" description="Selects the divide value for creating the CPU clock (CCLK) from the selected clock source. 0 = The divider is turned off., no clock will be provided to the CPU. This setting should typically not be used, the CPU will be halted and a reset will be required to restore operation. 1 = The input clock is divided by 1 to produce the CPU clock. 2 = The input clock is divided by 2 to produce the CPU clock. 3 = The input clock is divided by 3 to produce the CPU clock. ... 31 = The input clock is divided by 31 to produce the CPU clock." />
+      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="CCLKSEL" description="Selects the input clock for the CPU clock divider.">
+        <Enum name="SYSCLK_IS_USED_AS_TH" start="0" description="Sysclk is used as the input to the CPU clock divider." />
+        <Enum name="THE_OUTPUT_OF_THE_MA" start="1" description="The output of the Main PLL is used as the input to the CPU clock divider." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x108" size="4" name="USBCLKSEL" access="Read/Write" description="USB Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="USBDIV" description="Selects the divide value for creating the USB clock from the selected PLL output. Only the values shown below can produce even number multiples of 48 MHz from the PLL. Warning: Improper setting of this value will result in incorrect operation of the USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1 can provide a clock that meets USB accuracy and jitter specifications. Other values cannot produce the 48 MHz clock required for USB operation.">
+        <Enum name="THE_DIVIDER_IS_TURNE" start="0x0" description="The divider is turned off, no clock will be provided to the USB subsystem." />
+        <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x4" description="PLL0 output is divided by 4. PLL0 output must be 192 MHz." />
+        <Enum name="PLL0_OUTPUT_IS_DIVID" start="0x6" description="PLL0 output is divided by 6. PLL0 output must be 288 MHz." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="2" name="USBSEL" description="Selects the input clock for the USB clock divider.">
+        <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the USB clock divider. When this clock is selected, the USB can be accessed by software but cannot perform USB functions." />
+        <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the USB clock divider." />
+        <Enum name="ALTPLLOOUT" start="0x2" description="The output of the Alt PLL is used as the input to the USB clock divider." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x10C" size="4" name="CLKSRCSEL" access="Read/Write" description="Clock Source Select Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLKSRC" description="Selects the clock source for sysclk and PLL0 as follows:">
+        <Enum name="SELECTS_THE_INTERNAL" start="0" description="Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default)." />
+        <Enum name="SELECTS_THE_MAIN_OSC" start="1" description="Selects the main oscillator as the sysclk and PLL0 clock source." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x110" size="4" name="CANSLEEPCLR" access="Read/Write" description="Allows clearing the current CAN channel sleep state as well as reading that state." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="1" size="1" name="CAN1SLEEP" description="Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1." />
+      <BitField start="2" size="1" name="CAN2SLEEP" description="Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x114" size="4" name="CANWAKEFLAGS" access="Read/Write" description="Allows reading the wake-up state of the CAN channels." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="1" size="1" name="CAN1WAKE" description="Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit." />
+      <BitField start="2" size="1" name="CAN2WAKE" description="Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x140" size="4" name="EXTINT" access="Read/Write" description="External Interrupt Flag Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EINT0" description="In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
+      <BitField start="1" size="1" name="EINT1" description="In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
+      <BitField start="2" size="1" name="EINT2" description="In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
+      <BitField start="3" size="1" name="EINT3" description="In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.[1]" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x148" size="4" name="EXTMODE" access="Read/Write" description="External Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXTMODE0" description="Level or edge sensitivity select for EINT0.">
+        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
+        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
+      </BitField>
+      <BitField start="1" size="1" name="EXTMODE1" description="Level or edge sensitivity select for EINT1.">
+        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
+        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
+      </BitField>
+      <BitField start="2" size="1" name="EXTMODE2" description="Level or edge sensitivity select for EINT2.">
+        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
+        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
+      </BitField>
+      <BitField start="3" size="1" name="EXTMODE3" description="Level or edge sensitivity select for EINT3.">
+        <Enum name="LEVEL_SENSITIVE_" start="0" description="Level sensitive." />
+        <Enum name="EDGE_SENSITIVE_" start="1" description="Edge sensitive." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x14C" size="4" name="EXTPOLAR" access="Read/Write" description="External Interrupt Polarity Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXTPOLAR0" description="External interrupt polarity for EINT0.">
+        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE0)." />
+        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE0)." />
+      </BitField>
+      <BitField start="1" size="1" name="EXTPOLAR1" description="External interrupt polarity for EINT1.">
+        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE1)." />
+        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE1)." />
+      </BitField>
+      <BitField start="2" size="1" name="EXTPOLAR2" description="External interrupt polarity for EINT2.">
+        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE2)." />
+        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE2)." />
+      </BitField>
+      <BitField start="3" size="1" name="EXTPOLAR3" description="External interrupt polarity for EINT3.">
+        <Enum name="LOW_ACTIVE_OR_FALLIN" start="0" description="Low-active or falling-edge sensitive (depending on EXTMODE3)." />
+        <Enum name="HIGH_ACTIVE_OR_RISIN" start="1" description="High-active or rising-edge sensitive (depending on EXTMODE3)." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x180" size="4" name="RSID" access="Read/Write" description="Reset Source Identification Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="POR" description="Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset." />
+      <BitField start="1" size="1" name="EXTR" description="Assertion of the external RESET signal sets this bit. This bit is cleared only by software or POR." />
+      <BitField start="2" size="1" name="WDTR" description="This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR." />
+      <BitField start="3" size="1" name="BODR" description="This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not." />
+      <BitField start="4" size="1" name="SYSRESET" description="This bit is set if the processor has been reset due to a system reset request. Setting the SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is cleared only by software or POR." />
+      <BitField start="5" size="1" name="LOCKUP" description="This bit is set if the processor has been reset due to a &quot;lockup&quot;. The lockup state causes a chip reset. This bit is cleared only by software or POR." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x188" size="4" name="MATRIXARB" access="Read/Write" description="Matrix arbitration register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="PRI_ICODE" description="I-Code bus priority. Should be lower than PRI_DCODE for proper operation." />
+      <BitField start="2" size="2" name="PRI_DCODE" description="D-Code bus priority." />
+      <BitField start="4" size="2" name="PRI_SYS" description="System bus priority." />
+      <BitField start="6" size="2" name="PRI_GPDMA" description="General Purpose DMA controller priority." />
+      <BitField start="8" size="2" name="PRI_ETH" description="Ethernet DMA priority." />
+      <BitField start="10" size="2" name="PRI_LCD" description="LCD DMA priority." />
+      <BitField start="12" size="2" name="PRI_USB" description="USB DMA priority." />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="1" name="ROM_LAT" description="ROM latency select. Should always be 0." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1A0" size="4" name="SCS" access="Read/Write" description="System Control and Status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EMCSC" description="EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter.">
+        <Enum name="STATIC_MEMORY_ADDRES" start="0" description="Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift." />
+        <Enum name="STATIC_MEMORY_ADDRES" start="1" description="Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices." />
+      </BitField>
+      <BitField start="1" size="1" name="EMCRD" description="EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter.">
+        <Enum name="BOTH_EMC_RESETS_ARE_" start="0" description="Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition." />
+        <Enum name="MANY_PORTIONS_OF_THE" start="1" description="Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset." />
+      </BitField>
+      <BitField start="2" size="1" name="EMCBC" description="External Memory Controller burst control. Also see Section 9.10 in the EMC chapter.">
+        <Enum name="BURST_ENABLED_" start="0" description="Burst enabled." />
+        <Enum name="BURST_DISABLED_THIS" start="1" description="Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices." />
+      </BitField>
+      <BitField start="3" size="1" name="MCIPWRAL" description="MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR.">
+        <Enum name="SD_PWR_IS_ACTIVE_LOW" start="0" description="SD_PWR is active low (inverted output of the SD Card interface block)." />
+        <Enum name="SD_PWR_IS_ACTIVE_HIG" start="1" description="SD_PWR is active high (follows the output of the SD Card interface block)." />
+      </BitField>
+      <BitField start="4" size="1" name="OSCRS" description="Main oscillator range select.">
+        <Enum name="THE_FREQUENCY_RANGE_" start="0" description="The frequency range of the main oscillator is 1 MHz to 20 MHz." />
+        <Enum name="THE_FREQUENCY_RANGE_" start="1" description="The frequency range of the main oscillator is 15 MHz to 25 MHz." />
+      </BitField>
+      <BitField start="5" size="1" name="OSCEN" description="Main oscillator enable.">
+        <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is disabled." />
+        <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins." />
+      </BitField>
+      <BitField start="6" size="1" name="OSCSTAT" description="Main oscillator status.">
+        <Enum name="THE_MAIN_OSCILLATOR_" start="0" description="The main oscillator is not ready to be used as a clock source." />
+        <Enum name="THE_MAIN_OSCILLATOR_" start="1" description="The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1A8" size="4" name="PCLKSEL" access="Read/Write" description="Peripheral Clock Selection register" reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="PCLKDIV" description="Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals. 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. ... 31 = The input clock is divided by 31 to produce the APB peripheral clock." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1B0" size="4" name="PBOOST" access="Read/Write" description="Power boost register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="Boost" description="Boost control bits. 00 : Boost is off, operation must be below 100 MHz. 11 : Boost is on, operation up to 120 MHz is supported. Other values are not allowed." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1B4" size="4" name="SPIFICLKSEL" access="Read/Write" description="SPIFI Clock Selection register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="SPIFIDIV" description="Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. ... 31 = The input clock is divided by 31 to produce the SPIFI clock." />
+      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="2" name="SPIFISEL" description="Selects the input clock for the USB clock divider.">
+        <Enum name="SYSCLK" start="0x0" description="Sysclk is used as the input to the SPIFI clock divider." />
+        <Enum name="MAINPLLOUT" start="0x1" description="The output of the Main PLL is used as the input to the SPIFI clock divider." />
+        <Enum name="ALTPLLOUT" start="0x2" description="The output of the Alt PLL is used as the input to the SPIFI clock divider." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1B8" size="4" name="LCD_CFG" access="Read/Write" description="LCD Clock configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="CLKDIV" description="LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1C0" size="4" name="USBINTST" access="Read/Write" description="USB Interrupt Status" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="USB_INT_REQ_LP" description="Low priority interrupt line status. This bit is read-only." />
+      <BitField start="1" size="1" name="USB_INT_REQ_HP" description="High priority interrupt line status. This bit is read-only." />
+      <BitField start="2" size="1" name="USB_INT_REQ_DMA" description="DMA interrupt line status. This bit is read-only." />
+      <BitField start="3" size="1" name="USB_HOST_INT" description="USB host interrupt line status. This bit is read-only." />
+      <BitField start="4" size="1" name="USB_ATX_INT" description="External ATX interrupt line status. This bit is read-only." />
+      <BitField start="5" size="1" name="USB_OTG_INT" description="OTG interrupt line status. This bit is read-only." />
+      <BitField start="6" size="1" name="USB_I2C_INT" description="I2C module interrupt line status. This bit is read-only." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="1" name="USB_NEED_CLK" description="USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 3.12.8 &quot;Wake-up from Reduced Power Modes&quot; for details). Also see Section 3.10.3 &quot;PLLs and Power-down mode&quot; and Section 3.3.7 &quot;Power Control for Peripherals registers&quot; for considerations about the PLL and invoking the Power-down mode. This bit is read-only." />
+      <BitField start="9" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="31" size="1" name="EN_USB_INTS" description="Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines." />
+    </Register>
+    <Register start="+0x1C4" size="4" name="DMACREQSEL" access="Read/Write" description="Selects between alternative requests on DMA channels 0 through 7 and 10 through 15" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DMASEL00" description="Selects the DMA request for GPDMA input 0: 0 - (unused) 1 - Timer 0 match 0 is selected." />
+      <BitField start="1" size="1" name="DMASEL01" description="Selects the DMA request for GPDMA input 1: 0 - SD card interface is selected. 1 - Timer 0 match 1 is selected." />
+      <BitField start="2" size="1" name="DMASEL02" description="Selects the DMA request for GPDMA input 2: 0 - SSP0 transmit is selected. 1 - Timer 1 match 0 is selected." />
+      <BitField start="3" size="1" name="DMASEL03" description="Selects the DMA request for GPDMA input 3: 0 - SSP0 receive is selected. 1 - Timer 1 match 1 is selected." />
+      <BitField start="4" size="1" name="DMASEL04" description="Selects the DMA request for GPDMA input 4: 0 - SSP1 transmit is selected. 1 - Timer 2 match 0 is selected." />
+      <BitField start="5" size="1" name="DMASEL05" description="Selects the DMA request for GPDMA input 5: 0 - SSP1 receive is selected. 1 - Timer 2 match 1 is selected." />
+      <BitField start="6" size="1" name="DMASEL06" description="Selects the DMA request for GPDMA input 6: 0 - SSP2 transmit is selected. 1 - I2S channel 0 is selected." />
+      <BitField start="7" size="1" name="DMASEL07" description="Selects the DMA request for GPDMA input 7: 0 - SSP2 receive is selected. 1 - I2S channel 1 is selected." />
+      <BitField start="8" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="10" size="1" name="DMASEL10" description="Selects the DMA request for GPDMA input 10: 0 - UART0 transmit is selected. 1 - UART3 transmit is selected." />
+      <BitField start="11" size="1" name="DMASEL11" description="Selects the DMA request for GPDMA input 11: 0 - UART0 receive is selected. 1 - UART3 receive is selected." />
+      <BitField start="12" size="1" name="DMASEL12" description="Selects the DMA request for GPDMA input 12: 0 - UART1 transmit is selected. 1 - UART4 transmit is selected." />
+      <BitField start="13" size="1" name="DMASEL13" description="Selects the DMA request for GPDMA input 13: 0 - UART1 receive is selected. 1 - UART4 receive is selected." />
+      <BitField start="14" size="1" name="DMASEL14" description="Selects the DMA request for GPDMA input 14: 0 - UART2 transmit is selected. 1 - Timer 3 match 0 is selected." />
+      <BitField start="15" size="1" name="DMASEL15" description="Selects the DMA request for GPDMA input 15: 0 - UART2 receive is selected. 1 - Timer 3 match 1 is selected." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1C8" size="4" name="CLKOUTCFG" access="Read/Write" description="Clock Output Configuration register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="CLKOUTSEL" description="Selects the clock source for the CLKOUT function. 0x0 = Selects the CPU clock as the CLKOUT source. 0x1 = Selects the main oscillator as the CLKOUT source. 0x2 = Selects the Internal RC oscillator as the CLKOUT source. 0x3 = Selects the USB clock as the CLKOUT source. 0x4 = Selects the RTC oscillator as the CLKOUT source. 0x5 = Selects the SPIFI clock as the CLKOUT source. 0x6 = Selects the Watchdog oscillator as the CLKOUT source. Other settings are reserved. Do not use." />
+      <BitField start="4" size="4" name="CLKOUTDIV" description="Integer value to divide the output clock by, minus one. 0x0 = Clock is divided by 1. 0x1 = Clock is divided by 2. 0x2 = Clock is divided by 3. ... 0xF = Clock is divided by 16." />
+      <BitField start="8" size="1" name="CLKOUT_EN" description="CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT." />
+      <BitField start="9" size="1" name="CLKOUT_ACT" description="CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1CC" size="4" name="RSTCON0" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RSTLCD" description="LCD controller reset control bit." />
+      <BitField start="1" size="1" name="RSTTIM0" description="Timer/Counter 0 reset control bit." />
+      <BitField start="2" size="1" name="RSTTIM1" description="Timer/Counter 1 reset control bit." />
+      <BitField start="3" size="1" name="RSTUART0" description="UART0 reset control bit." />
+      <BitField start="4" size="1" name="RSTUART1" description="UART1 reset control bit." />
+      <BitField start="5" size="1" name="RSTPWM0" description="PWM0 reset control bit." />
+      <BitField start="6" size="1" name="RSTPWM1" description="PWM1 reset control bit." />
+      <BitField start="7" size="1" name="RSTI2C0" description="The I2C0 interface reset control bit." />
+      <BitField start="8" size="1" name="RSTUART4" description="UART4 reset control bit." />
+      <BitField start="9" size="1" name="RSTRTC" description="RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see Table 626 &quot;Register overview: Real-Time Clock (base address 0x4002 4000)&quot; for details." />
+      <BitField start="10" size="1" name="RSTSSP1" description="The SSP 1 interface reset control bit." />
+      <BitField start="11" size="1" name="RSTEMC" description="External Memory Controller reset control bit." />
+      <BitField start="12" size="1" name="RSTADC" description="A/D converter (ADC) reset control bit." />
+      <BitField start="13" size="1" name="RSTCAN1" description="CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." />
+      <BitField start="14" size="1" name="RSTCAN2" description="CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by a separate bit in the RSTCON1 register." />
+      <BitField start="15" size="1" name="RSTGPIO" description="Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a separate bit in the RSTCON1 register." />
+      <BitField start="16" size="1" name="RSTSPIFI" description="SPI Flash Interface reset control bit." />
+      <BitField start="17" size="1" name="RSTMCPWM" description="Motor Control PWM reset control bit." />
+      <BitField start="18" size="1" name="RSTQEI" description="Quadrature Encoder Interface reset control bit." />
+      <BitField start="19" size="1" name="RSTI2C1" description="The I2C1 interface reset control bit." />
+      <BitField start="20" size="1" name="RSTSSP2" description="The SSP2 interface reset control bit." />
+      <BitField start="21" size="1" name="RSTSSP0" description="The SSP0 interface reset control bit." />
+      <BitField start="22" size="1" name="RSTTIM2" description="Timer 2 reset control bit." />
+      <BitField start="23" size="1" name="RSTTIM3" description="Timer 3 reset control bit." />
+      <BitField start="24" size="1" name="RSTUART2" description="UART 2 reset control bit." />
+      <BitField start="25" size="1" name="RSTUART3" description="UART 3 reset control bit." />
+      <BitField start="26" size="1" name="RSTI2C2" description="I2C interface 2 reset control bit." />
+      <BitField start="27" size="1" name="RSTI2S" description="I2S interface reset control bit." />
+      <BitField start="28" size="1" name="RSTSDC" description="SD Card interface reset control bit." />
+      <BitField start="29" size="1" name="RSTGPDMA" description="GPDMA function reset control bit." />
+      <BitField start="30" size="1" name="RSTENET" description="Ethernet block reset control bit." />
+      <BitField start="31" size="1" name="RSTUSB" description="USB interface reset control bit." />
+    </Register>
+    <Register start="+0x1D0" size="4" name="RSTCON1" access="Read/Write" description="Individual peripheral reset control bits" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RSTIOCON" description="Reset control bit for the IOCON registers." />
+      <BitField start="1" size="1" name="RSTDAC" description="D/A converter (DAC) reset control bit." />
+      <BitField start="2" size="1" name="RSTCANACC" description="CAN acceptance filter reset control bit." />
+      <BitField start="3" size="1" name="RSTCMP" description="Comparator 0/1 reset control bit." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1DC" size="4" name="EMCDLYCTL" access="Read/Write" description="Values for the 4 programmable delays associated with SDRAM operation." reset_value="0x210" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="CMDDLY" description="Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet." />
+      <BitField start="5" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="8" size="5" name="FBCLKDLY" description="Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds." />
+      <BitField start="13" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="16" size="5" name="CLKOUT0DLY" description="Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet." />
+      <BitField start="21" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="24" size="5" name="CLKOUT1DLY" description="Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x1E0" size="4" name="EMCCAL" access="Read/Write" description="Controls the calibration counter for programmable delays and returns the result value." reset_value="0x1F00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CALVALUE" description="Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks of the IRC oscillator. This represents the composite effect of processing variation, internal regulator supply voltage, and ambient temperature." />
+      <BitField start="8" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="14" size="1" name="START" description="Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the measurement process. This bit is cleared automatically when the measurement is complete." />
+      <BitField start="15" size="1" name="DONE" description="Measurement completion flag. this bit is set when a calibration measurement is completed. This bit is cleared automatically when the START bit is set." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
+    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
+      <BitField name="WWDT" start="0" size="1" />
+      <BitField name="TIMER0" start="1" size="1" />
+      <BitField name="TIMER1" start="2" size="1" />
+      <BitField name="TIMER2" start="3" size="1" />
+      <BitField name="TIMER3" start="4" size="1" />
+      <BitField name="UART0" start="5" size="1" />
+      <BitField name="UART1" start="6" size="1" />
+      <BitField name="UART2" start="7" size="1" />
+      <BitField name="UART3" start="8" size="1" />
+      <BitField name="PWM1" start="9" size="1" />
+      <BitField name="I2C0" start="10" size="1" />
+      <BitField name="I2C1" start="11" size="1" />
+      <BitField name="I2C2" start="12" size="1" />
+      <BitField name="SSP0" start="14" size="1" />
+      <BitField name="SSP1" start="15" size="1" />
+      <BitField name="RTC" start="17" size="1" />
+      <BitField name="EINT0" start="18" size="1" />
+      <BitField name="EINT1" start="19" size="1" />
+      <BitField name="EINT2" start="20" size="1" />
+      <BitField name="EINT3" start="21" size="1" />
+      <BitField name="ADC" start="22" size="1" />
+      <BitField name="BOD" start="23" size="1" />
+      <BitField name="USB" start="24" size="1" />
+      <BitField name="CAN" start="25" size="1" />
+      <BitField name="GPDMA" start="26" size="1" />
+      <BitField name="I2S" start="27" size="1" />
+      <BitField name="ETHERNET" start="28" size="1" />
+      <BitField name="SDMMC" start="29" size="1" />
+      <BitField name="MCPWM" start="30" size="1" />
+      <BitField name="QEI" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
+      <BitField name="USB_NEED_CLK" start="1" size="1" />
+      <BitField name="UART4" start="3" size="1" />
+      <BitField name="SSP2" start="4" size="1" />
+      <BitField name="LCD" start="5" size="1" />
+      <BitField name="GPIOINT" start="6" size="1" />
+      <BitField name="PWM0" start="7" size="1" />
+      <BitField name="EEPROM" start="8" size="1" />
+      <BitField name="CMP0" start="9" size="1" />
+      <BitField name="CMP1" start="10" size="1" />
+    </Register>
+    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
+      <BitField name="WWDT" start="0" size="1" />
+      <BitField name="TIMER0" start="1" size="1" />
+      <BitField name="TIMER1" start="2" size="1" />
+      <BitField name="TIMER2" start="3" size="1" />
+      <BitField name="TIMER3" start="4" size="1" />
+      <BitField name="UART0" start="5" size="1" />
+      <BitField name="UART1" start="6" size="1" />
+      <BitField name="UART2" start="7" size="1" />
+      <BitField name="UART3" start="8" size="1" />
+      <BitField name="PWM1" start="9" size="1" />
+      <BitField name="I2C0" start="10" size="1" />
+      <BitField name="I2C1" start="11" size="1" />
+      <BitField name="I2C2" start="12" size="1" />
+      <BitField name="SSP0" start="14" size="1" />
+      <BitField name="SSP1" start="15" size="1" />
+      <BitField name="RTC" start="17" size="1" />
+      <BitField name="EINT0" start="18" size="1" />
+      <BitField name="EINT1" start="19" size="1" />
+      <BitField name="EINT2" start="20" size="1" />
+      <BitField name="EINT3" start="21" size="1" />
+      <BitField name="ADC" start="22" size="1" />
+      <BitField name="BOD" start="23" size="1" />
+      <BitField name="USB" start="24" size="1" />
+      <BitField name="CAN" start="25" size="1" />
+      <BitField name="GPDMA" start="26" size="1" />
+      <BitField name="I2S" start="27" size="1" />
+      <BitField name="ETHERNET" start="28" size="1" />
+      <BitField name="SDMMC" start="29" size="1" />
+      <BitField name="MCPWM" start="30" size="1" />
+      <BitField name="QEI" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
+      <BitField name="USB_NEED_CLK" start="1" size="1" />
+      <BitField name="UART4" start="3" size="1" />
+      <BitField name="SSP2" start="4" size="1" />
+      <BitField name="LCD" start="5" size="1" />
+      <BitField name="GPIOINT" start="6" size="1" />
+      <BitField name="PWM0" start="7" size="1" />
+      <BitField name="EEPROM" start="8" size="1" />
+      <BitField name="CMP0" start="9" size="1" />
+      <BitField name="CMP1" start="10" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
+      <BitField name="WWDT" start="0" size="1" />
+      <BitField name="TIMER0" start="1" size="1" />
+      <BitField name="TIMER1" start="2" size="1" />
+      <BitField name="TIMER2" start="3" size="1" />
+      <BitField name="TIMER3" start="4" size="1" />
+      <BitField name="UART0" start="5" size="1" />
+      <BitField name="UART1" start="6" size="1" />
+      <BitField name="UART2" start="7" size="1" />
+      <BitField name="UART3" start="8" size="1" />
+      <BitField name="PWM1" start="9" size="1" />
+      <BitField name="I2C0" start="10" size="1" />
+      <BitField name="I2C1" start="11" size="1" />
+      <BitField name="I2C2" start="12" size="1" />
+      <BitField name="SSP0" start="14" size="1" />
+      <BitField name="SSP1" start="15" size="1" />
+      <BitField name="RTC" start="17" size="1" />
+      <BitField name="EINT0" start="18" size="1" />
+      <BitField name="EINT1" start="19" size="1" />
+      <BitField name="EINT2" start="20" size="1" />
+      <BitField name="EINT3" start="21" size="1" />
+      <BitField name="ADC" start="22" size="1" />
+      <BitField name="BOD" start="23" size="1" />
+      <BitField name="USB" start="24" size="1" />
+      <BitField name="CAN" start="25" size="1" />
+      <BitField name="GPDMA" start="26" size="1" />
+      <BitField name="I2S" start="27" size="1" />
+      <BitField name="ETHERNET" start="28" size="1" />
+      <BitField name="SDMMC" start="29" size="1" />
+      <BitField name="MCPWM" start="30" size="1" />
+      <BitField name="QEI" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
+      <BitField name="USB_NEED_CLK" start="1" size="1" />
+      <BitField name="UART4" start="3" size="1" />
+      <BitField name="SSP2" start="4" size="1" />
+      <BitField name="LCD" start="5" size="1" />
+      <BitField name="GPIOINT" start="6" size="1" />
+      <BitField name="PWM0" start="7" size="1" />
+      <BitField name="EEPROM" start="8" size="1" />
+      <BitField name="CMP0" start="9" size="1" />
+      <BitField name="CMP1" start="10" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
+      <BitField name="WWDT" start="0" size="1" />
+      <BitField name="TIMER0" start="1" size="1" />
+      <BitField name="TIMER1" start="2" size="1" />
+      <BitField name="TIMER2" start="3" size="1" />
+      <BitField name="TIMER3" start="4" size="1" />
+      <BitField name="UART0" start="5" size="1" />
+      <BitField name="UART1" start="6" size="1" />
+      <BitField name="UART2" start="7" size="1" />
+      <BitField name="UART3" start="8" size="1" />
+      <BitField name="PWM1" start="9" size="1" />
+      <BitField name="I2C0" start="10" size="1" />
+      <BitField name="I2C1" start="11" size="1" />
+      <BitField name="I2C2" start="12" size="1" />
+      <BitField name="SSP0" start="14" size="1" />
+      <BitField name="SSP1" start="15" size="1" />
+      <BitField name="RTC" start="17" size="1" />
+      <BitField name="EINT0" start="18" size="1" />
+      <BitField name="EINT1" start="19" size="1" />
+      <BitField name="EINT2" start="20" size="1" />
+      <BitField name="EINT3" start="21" size="1" />
+      <BitField name="ADC" start="22" size="1" />
+      <BitField name="BOD" start="23" size="1" />
+      <BitField name="USB" start="24" size="1" />
+      <BitField name="CAN" start="25" size="1" />
+      <BitField name="GPDMA" start="26" size="1" />
+      <BitField name="I2S" start="27" size="1" />
+      <BitField name="ETHERNET" start="28" size="1" />
+      <BitField name="SDMMC" start="29" size="1" />
+      <BitField name="MCPWM" start="30" size="1" />
+      <BitField name="QEI" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
+      <BitField name="USB_NEED_CLK" start="1" size="1" />
+      <BitField name="UART4" start="3" size="1" />
+      <BitField name="SSP2" start="4" size="1" />
+      <BitField name="LCD" start="5" size="1" />
+      <BitField name="GPIOINT" start="6" size="1" />
+      <BitField name="PWM0" start="7" size="1" />
+      <BitField name="EEPROM" start="8" size="1" />
+      <BitField name="CMP0" start="9" size="1" />
+      <BitField name="CMP1" start="10" size="1" />
+    </Register>
+    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
+      <BitField name="WWDT" start="0" size="1" />
+      <BitField name="TIMER0" start="1" size="1" />
+      <BitField name="TIMER1" start="2" size="1" />
+      <BitField name="TIMER2" start="3" size="1" />
+      <BitField name="TIMER3" start="4" size="1" />
+      <BitField name="UART0" start="5" size="1" />
+      <BitField name="UART1" start="6" size="1" />
+      <BitField name="UART2" start="7" size="1" />
+      <BitField name="UART3" start="8" size="1" />
+      <BitField name="PWM1" start="9" size="1" />
+      <BitField name="I2C0" start="10" size="1" />
+      <BitField name="I2C1" start="11" size="1" />
+      <BitField name="I2C2" start="12" size="1" />
+      <BitField name="SSP0" start="14" size="1" />
+      <BitField name="SSP1" start="15" size="1" />
+      <BitField name="RTC" start="17" size="1" />
+      <BitField name="EINT0" start="18" size="1" />
+      <BitField name="EINT1" start="19" size="1" />
+      <BitField name="EINT2" start="20" size="1" />
+      <BitField name="EINT3" start="21" size="1" />
+      <BitField name="ADC" start="22" size="1" />
+      <BitField name="BOD" start="23" size="1" />
+      <BitField name="USB" start="24" size="1" />
+      <BitField name="CAN" start="25" size="1" />
+      <BitField name="GPDMA" start="26" size="1" />
+      <BitField name="I2S" start="27" size="1" />
+      <BitField name="ETHERNET" start="28" size="1" />
+      <BitField name="SDMMC" start="29" size="1" />
+      <BitField name="MCPWM" start="30" size="1" />
+      <BitField name="QEI" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
+      <BitField name="USB_NEED_CLK" start="1" size="1" />
+      <BitField name="UART4" start="3" size="1" />
+      <BitField name="SSP2" start="4" size="1" />
+      <BitField name="LCD" start="5" size="1" />
+      <BitField name="GPIOINT" start="6" size="1" />
+      <BitField name="PWM0" start="7" size="1" />
+      <BitField name="EEPROM" start="8" size="1" />
+      <BitField name="CMP0" start="9" size="1" />
+      <BitField name="CMP1" start="10" size="1" />
+    </Register>
+    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
+      <BitField name="WWDT" start="4" size="4" />
+      <BitField name="TIMER0" start="12" size="4" />
+      <BitField name="TIMER1" start="20" size="4" />
+      <BitField name="TIMER2" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
+      <BitField name="TIMER3" start="4" size="4" />
+      <BitField name="UART0" start="12" size="4" />
+      <BitField name="UART1" start="20" size="4" />
+      <BitField name="UART2" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
+      <BitField name="UART3" start="4" size="4" />
+      <BitField name="PWM1" start="12" size="4" />
+      <BitField name="I2C0" start="20" size="4" />
+      <BitField name="I2C1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
+      <BitField name="I2C2" start="4" size="4" />
+      <BitField name="SSP0" start="20" size="4" />
+      <BitField name="SSP1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
+      <BitField name="RTC" start="12" size="4" />
+      <BitField name="EINT0" start="20" size="4" />
+      <BitField name="EINT1" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
+      <BitField name="EINT2" start="4" size="4" />
+      <BitField name="EINT3" start="12" size="4" />
+      <BitField name="ADC" start="20" size="4" />
+      <BitField name="BOD" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
+      <BitField name="USB" start="4" size="4" />
+      <BitField name="CAN" start="12" size="4" />
+      <BitField name="GPDMA" start="20" size="4" />
+      <BitField name="I2S" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
+      <BitField name="ETHERNET" start="4" size="4" />
+      <BitField name="SDMMC" start="12" size="4" />
+      <BitField name="MCPWM" start="20" size="4" />
+      <BitField name="QEI" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
+      <BitField name="USB_NEED_CLK" start="12" size="4" />
+      <BitField name="UART4" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
+      <BitField name="SSP2" start="4" size="4" />
+      <BitField name="LCD" start="12" size="4" />
+      <BitField name="GPIOINT" start="20" size="4" />
+      <BitField name="PWM0" start="28" size="4" />
+    </Register>
+    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
+      <BitField name="EEPROM" start="4" size="4" />
+      <BitField name="CMP0" start="12" size="4" />
+      <BitField name="CMP1" start="20" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
+    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
+      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
+      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
+      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
+    </Register>
+    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
+      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
+    </Register>
+    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
+      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
+    </Register>
+    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
+      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
+      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
+      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCB" start="" description="System Control Block">
+    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
+      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
+      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
+      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
+    </Register>
+    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
+      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
+      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
+      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
+      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
+    </Register>
+    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
+      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
+      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
+      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
+      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
+      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
+      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
+      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
+      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
+      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
+      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
+    </Register>
+    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
+      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
+    </Register>
+    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
+      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
+      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
+      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
+      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
+      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
+      <BitField name="VECTRESET" start="0" size="1" description="" />
+    </Register>
+    <Register name="SCR" start="0xE000ED10" description="System Control Register">
+      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
+      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
+      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
+    </Register>
+    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
+      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
+      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
+      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
+      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
+      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
+      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
+    </Register>
+    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
+      <BitField name="PRI_6" start="20" size="4" description="Priority of system handler 6 (UsageFault)" />
+      <BitField name="PRI_5" start="12" size="4" description="Priority of system handler 5 (BusFault)" />
+      <BitField name="PRI_4" start="4" size="4" description="Priority of system handler 4 (MemManage)" />
+    </Register>
+    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
+      <BitField name="PRI_11" start="28" size="4" description="Priority of system handler 11 (SVCall)" />
+    </Register>
+    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
+      <BitField name="PRI_15" start="28" size="4" description="Priority of system handler 15 (SysTick)" />
+      <BitField name="PRI_14" start="20" size="4" description="Priority of system handler 14 (PendSV)" />
+    </Register>
+    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
+      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
+      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
+      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
+      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
+      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
+      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
+      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
+      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
+      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
+      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
+      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
+      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
+      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
+      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
+    </Register>
+    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
+      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
+      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
+      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
+      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
+      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
+      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
+    </Register>
+    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
+      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
+      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
+      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
+      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
+      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
+      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
+      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
+    </Register>
+    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
+      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
+      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
+      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
+      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
+      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
+      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
+    </Register>
+    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
+      <BitField name="DEBUGEVT" start="31" size="1" description="" />
+      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
+      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
+    </Register>
+    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
+      <BitField name="EXTERNAL" start="4" size="1" description="" />
+      <BitField name="VCATCH" start="3" size="1" description="" />
+      <BitField name="DWTTRAP" start="2" size="1" description="" />
+      <BitField name="BKPT" start="1" size="1" description="" />
+      <BitField name="HALTED" start="0" size="1" description="" />
+    </Register>
+    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
+    </Register>
+    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
+    </Register>
+    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
+      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
+    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
+      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
+      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
+      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
+    </Register>
+    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
+      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
+      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
+    </Register>
+    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
+      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
+    </Register>
+    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
+      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
+      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
+      <BitField name="REGION" start="0" size="4" description="MPU region field" />
+    </Register>
+    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
+      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
+      <BitField name="AP" start="24" size="3" description="Access permission field" />
+      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
+      <BitField name="S" start="18" size="1" description="Shareable bit" />
+      <BitField name="C" start="17" size="1" description="Memory access attribute" />
+      <BitField name="B" start="16" size="1" description="Memory access attribute" />
+      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
+      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
+      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
+    </Register>
+  </RegisterGroup>
+</Processor>
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s
new file mode 100644
index 000000000..025685469
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/LPC408x_7x_Vectors.s
@@ -0,0 +1,458 @@
+/*****************************************************************************
+ *                   SEGGER Microcontroller GmbH & Co. KG                    *
+ *            Solutions for real time microcontroller applications           *
+ *****************************************************************************
+ *                                                                           *
+ *               (c) 2017 SEGGER Microcontroller GmbH & Co. KG               *
+ *                                                                           *
+ *           Internet: www.segger.com   Support: support@segger.com          *
+ *                                                                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                         Preprocessor Definitions                          *
+ *                         ------------------------                          *
+ * VECTORS_IN_RAM                                                            *
+ *                                                                           *
+ *   If defined, an area of RAM will large enough to store the vector table  *
+ *   will be reserved.                                                       *
+ *                                                                           *
+ *****************************************************************************/
+
+  .syntax unified
+  .code 16
+
+  .section .init, "ax"
+  .align 0
+
+/*****************************************************************************
+ * Default Exception Handlers                                                *
+ *****************************************************************************/
+
+  .thumb_func
+  .weak NMI_Handler
+NMI_Handler:
+  b .
+
+  .thumb_func
+  .weak HardFault_Handler
+HardFault_Handler:
+  b .
+
+  .thumb_func
+  .weak SVC_Handler
+SVC_Handler:
+  b .
+
+  .thumb_func
+  .weak PendSV_Handler
+PendSV_Handler:
+  b .
+
+  .thumb_func
+  .weak SysTick_Handler
+SysTick_Handler:
+  b .
+
+  .thumb_func
+Dummy_Handler:
+  b .
+
+#if defined(__OPTIMIZATION_SMALL)
+
+  .weak WWDT_IRQHandler
+  .thumb_set WWDT_IRQHandler,Dummy_Handler
+
+  .weak TIMER0_IRQHandler
+  .thumb_set TIMER0_IRQHandler,Dummy_Handler
+
+  .weak TIMER1_IRQHandler
+  .thumb_set TIMER1_IRQHandler,Dummy_Handler
+
+  .weak TIMER2_IRQHandler
+  .thumb_set TIMER2_IRQHandler,Dummy_Handler
+
+  .weak TIMER3_IRQHandler
+  .thumb_set TIMER3_IRQHandler,Dummy_Handler
+
+  .weak UART0_IRQHandler
+  .thumb_set UART0_IRQHandler,Dummy_Handler
+
+  .weak UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Dummy_Handler
+
+  .weak UART2_IRQHandler
+  .thumb_set UART2_IRQHandler,Dummy_Handler
+
+  .weak UART3_IRQHandler
+  .thumb_set UART3_IRQHandler,Dummy_Handler
+
+  .weak PWM1_IRQHandler
+  .thumb_set PWM1_IRQHandler,Dummy_Handler
+
+  .weak I2C0_IRQHandler
+  .thumb_set I2C0_IRQHandler,Dummy_Handler
+
+  .weak I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Dummy_Handler
+
+  .weak I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Dummy_Handler
+
+  .weak SSP0_IRQHandler
+  .thumb_set SSP0_IRQHandler,Dummy_Handler
+
+  .weak SSP1_IRQHandler
+  .thumb_set SSP1_IRQHandler,Dummy_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Dummy_Handler
+
+  .weak EINT0_IRQHandler
+  .thumb_set EINT0_IRQHandler,Dummy_Handler
+
+  .weak EINT1_IRQHandler
+  .thumb_set EINT1_IRQHandler,Dummy_Handler
+
+  .weak EINT2_IRQHandler
+  .thumb_set EINT2_IRQHandler,Dummy_Handler
+
+  .weak EINT3_IRQHandler
+  .thumb_set EINT3_IRQHandler,Dummy_Handler
+
+  .weak ADC_IRQHandler
+  .thumb_set ADC_IRQHandler,Dummy_Handler
+
+  .weak BOD_IRQHandler
+  .thumb_set BOD_IRQHandler,Dummy_Handler
+
+  .weak USB_IRQHandler
+  .thumb_set USB_IRQHandler,Dummy_Handler
+
+  .weak CAN_IRQHandler
+  .thumb_set CAN_IRQHandler,Dummy_Handler
+
+  .weak GPDMA_IRQHandler
+  .thumb_set GPDMA_IRQHandler,Dummy_Handler
+
+  .weak I2S_IRQHandler
+  .thumb_set I2S_IRQHandler,Dummy_Handler
+
+  .weak ETHERNET_IRQHandler
+  .thumb_set ETHERNET_IRQHandler,Dummy_Handler
+
+  .weak SDMMC_IRQHandler
+  .thumb_set SDMMC_IRQHandler,Dummy_Handler
+
+  .weak MCPWM_IRQHandler
+  .thumb_set MCPWM_IRQHandler,Dummy_Handler
+
+  .weak QEI_IRQHandler
+  .thumb_set QEI_IRQHandler,Dummy_Handler
+
+  .weak USB_NEED_CLK_IRQHandler
+  .thumb_set USB_NEED_CLK_IRQHandler,Dummy_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Dummy_Handler
+
+  .weak SSP2_IRQHandler
+  .thumb_set SSP2_IRQHandler,Dummy_Handler
+
+  .weak LCD_IRQHandler
+  .thumb_set LCD_IRQHandler,Dummy_Handler
+
+  .weak GPIOINT_IRQHandler
+  .thumb_set GPIOINT_IRQHandler,Dummy_Handler
+
+  .weak PWM0_IRQHandler
+  .thumb_set PWM0_IRQHandler,Dummy_Handler
+
+  .weak EEPROM_IRQHandler
+  .thumb_set EEPROM_IRQHandler,Dummy_Handler
+
+  .weak CMP0_IRQHandler
+  .thumb_set CMP0_IRQHandler,Dummy_Handler
+
+  .weak CMP1_IRQHandler
+  .thumb_set CMP1_IRQHandler,Dummy_Handler
+
+#else
+
+  .thumb_func
+  .weak WWDT_IRQHandler
+WWDT_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER0_IRQHandler
+TIMER0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER1_IRQHandler
+TIMER1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER2_IRQHandler
+TIMER2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak TIMER3_IRQHandler
+TIMER3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak UART0_IRQHandler
+UART0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak UART1_IRQHandler
+UART1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak UART2_IRQHandler
+UART2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak UART3_IRQHandler
+UART3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PWM1_IRQHandler
+PWM1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2C0_IRQHandler
+I2C0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2C1_IRQHandler
+I2C1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2C2_IRQHandler
+I2C2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP0_IRQHandler
+SSP0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP1_IRQHandler
+SSP1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak RTC_IRQHandler
+RTC_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak EINT0_IRQHandler
+EINT0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak EINT1_IRQHandler
+EINT1_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak EINT2_IRQHandler
+EINT2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak EINT3_IRQHandler
+EINT3_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ADC_IRQHandler
+ADC_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak BOD_IRQHandler
+BOD_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USB_IRQHandler
+USB_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CAN_IRQHandler
+CAN_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak GPDMA_IRQHandler
+GPDMA_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak I2S_IRQHandler
+I2S_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak ETHERNET_IRQHandler
+ETHERNET_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SDMMC_IRQHandler
+SDMMC_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak MCPWM_IRQHandler
+MCPWM_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak QEI_IRQHandler
+QEI_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak USB_NEED_CLK_IRQHandler
+USB_NEED_CLK_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak UART4_IRQHandler
+UART4_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak SSP2_IRQHandler
+SSP2_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak LCD_IRQHandler
+LCD_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak GPIOINT_IRQHandler
+GPIOINT_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak PWM0_IRQHandler
+PWM0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak EEPROM_IRQHandler
+EEPROM_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CMP0_IRQHandler
+CMP0_IRQHandler:
+  b .
+
+  .thumb_func
+  .weak CMP1_IRQHandler
+CMP1_IRQHandler:
+  b .
+
+#endif
+
+/*****************************************************************************
+ * Vector Table                                                              *
+ *****************************************************************************/
+
+  .section .vectors, "ax"
+  .align 0
+  .global _vectors
+  .extern __stack_end__
+  .extern Reset_Handler
+
+_vectors:
+  .word __stack_end__
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word SVC_Handler
+  .word 0 /* Reserved */
+  .word 0 /* Reserved */
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDT_IRQHandler
+  .word TIMER0_IRQHandler
+  .word TIMER1_IRQHandler
+  .word TIMER2_IRQHandler
+  .word TIMER3_IRQHandler
+  .word UART0_IRQHandler
+  .word UART1_IRQHandler
+  .word UART2_IRQHandler
+  .word UART3_IRQHandler
+  .word PWM1_IRQHandler
+  .word I2C0_IRQHandler
+  .word I2C1_IRQHandler
+  .word I2C2_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word SSP0_IRQHandler
+  .word SSP1_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word RTC_IRQHandler
+  .word EINT0_IRQHandler
+  .word EINT1_IRQHandler
+  .word EINT2_IRQHandler
+  .word EINT3_IRQHandler
+  .word ADC_IRQHandler
+  .word BOD_IRQHandler
+  .word USB_IRQHandler
+  .word CAN_IRQHandler
+  .word GPDMA_IRQHandler
+  .word I2S_IRQHandler
+  .word ETHERNET_IRQHandler
+  .word SDMMC_IRQHandler
+  .word MCPWM_IRQHandler
+  .word QEI_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word USB_NEED_CLK_IRQHandler
+  .word Dummy_Handler /* Reserved */
+  .word UART4_IRQHandler
+  .word SSP2_IRQHandler
+  .word LCD_IRQHandler
+  .word GPIOINT_IRQHandler
+  .word PWM0_IRQHandler
+  .word EEPROM_IRQHandler
+  .word CMP0_IRQHandler
+  .word CMP1_IRQHandler
+_vectors_end:
+
+#ifdef VECTORS_IN_RAM
+  .section .vectors_ram, "ax"
+  .align 0
+  .global _vectors_ram
+
+_vectors_ram:
+  .space _vectors_end - _vectors, 0
+#endif
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml b/examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml
new file mode 100644
index 000000000..79bedc537
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/flash_placement.xml
@@ -0,0 +1,37 @@
+<!DOCTYPE Linker_Placement_File>
+<Root name="Flash Section Placement">
+  <MemorySegment name="$(FLASH_NAME:FLASH)">
+    <ProgramSection alignment="0x100" load="Yes" name=".vectors" start="$(FLASH_START:)" />
+    <ProgramSection alignment="4" load="Yes" name=".init" />
+    <ProgramSection alignment="4" load="Yes" name=".init_rodata" />
+    <ProgramSection alignment="4" load="Yes" name=".text" />
+    <ProgramSection alignment="4" load="Yes" name=".dtors" />
+    <ProgramSection alignment="4" load="Yes" name=".ctors" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata" />
+    <ProgramSection alignment="4" load="Yes" name=".ARM.exidx" address_symbol="__exidx_start" end_symbol="__exidx_end" />
+    <ProgramSection alignment="4" load="Yes" runin=".fast_run" name=".fast" />
+    <ProgramSection alignment="4" load="Yes" runin=".data_run" name=".data" />
+    <ProgramSection alignment="4" load="Yes" runin=".tdata_run" name=".tdata" />
+  </MemorySegment>
+  <MemorySegment name="$(RAM_NAME:RAM);SRAM">
+    <ProgramSection alignment="0x100" load="No" name=".vectors_ram" start="$(RAM_START:$(SRAM_START:))" />
+    <ProgramSection alignment="4" load="No" name=".fast_run" />
+    <ProgramSection alignment="4" load="No" name=".data_run" />
+    <ProgramSection alignment="4" load="No" name=".bss" />
+    <ProgramSection alignment="4" load="No" name=".tbss" />
+    <ProgramSection alignment="4" load="No" name=".tdata_run" />
+    <ProgramSection alignment="4" load="No" name=".non_init" />
+    <ProgramSection alignment="4" size="__HEAPSIZE__" load="No" name=".heap" />
+    <ProgramSection alignment="8" size="__STACKSIZE__" load="No" place_from_segment_end="Yes" name=".stack" />
+    <ProgramSection alignment="8" size="__STACKSIZE_PROCESS__" load="No" name=".stack_process" />
+  </MemorySegment>
+  <MemorySegment name="$(FLASH2_NAME:FLASH2)">
+    <ProgramSection alignment="4" load="Yes" name=".text2" />
+    <ProgramSection alignment="4" load="Yes" name=".rodata2" />
+    <ProgramSection alignment="4" load="Yes" runin=".data2_run" name=".data2" />
+  </MemorySegment>
+  <MemorySegment name="$(RAM2_NAME:RAM2)">
+    <ProgramSection alignment="4" load="No" name=".data2_run" />
+    <ProgramSection alignment="4" load="No" name=".bss2" />
+  </MemorySegment>
+</Root>
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject b/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
new file mode 100644
index 000000000..ed6840e06
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
@@ -0,0 +1,118 @@
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="lpc40xx" target="8" version="2">
+  <project Name="lpc40xx">
+    <configuration
+      Name="Common"
+      Placement="Flash"
+      Target="LPC4088FBD208"
+      arm_architecture="v7EM"
+      arm_core_type="Cortex-M4"
+      arm_endian="Little"
+      arm_fp_abi="Hard"
+      arm_fpu_type="FPv4-SP-D16"
+      arm_interwork="No"
+      arm_linker_heap_size="256"
+      arm_linker_process_stack_size="0"
+      arm_linker_stack_size="256"
+      arm_simulator_memory_simulation_parameter="ROM;0x00000000;0x00080000;RAM;0x10000000;0x00010000;RAM;0x20000000;0x00008000"
+      arm_target_debug_interface_type="ADIv5"
+      arm_target_device_name="LPC4088"
+      arm_target_interface_type="SWD"
+      c_preprocessor_definitions="CORE_M4;__LPC4000_FAMILY;__LPC408x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4088QS;CFG_TUSB_MCU=OPT_MCU_LPC40XX"
+      c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc"
+      debug_register_definition_file="$(ProjectDir)/LPC408x_7x_Registers.xml"
+      debug_target_connection="J-Link"
+      gcc_entry_point="Reset_Handler"
+      linker_memory_map_file="$(ProjectDir)/LPC4088FBD208_MemoryMap.xml"
+      linker_section_placement_file="$(ProjectDir)/flash_placement.xml"
+      macros="DeviceFamily=LPC4000;DeviceSubFamily=LPC408x;Target=LPC4088FBD208;Placement=Flash;rootDir=../../../../..;lpcDir=../../../../../hw/mcu/nxp/lpc_chip_40xx"
+      package_dependencies="LPC4000"
+      project_directory=""
+      project_type="Executable"
+      target_reset_script="Reset();"
+      target_trace_initialize_script="EnableTrace(&quot;$(TraceInterfaceType)&quot;)" />
+    <folder Name="System Files">
+      <file file_name="thumb_crt0.s" />
+      <file file_name="LPC4000_Startup.s" />
+      <file file_name="LPC408x_7x_Vectors.s">
+        <configuration Name="Common" file_type="Assembly" />
+      </file>
+      <file file_name="LPC4088FBD208_MemoryMap.xml" />
+      <file file_name="flash_placement.xml" />
+      <file file_name="LPC4000_Target.js">
+        <configuration Name="Common" file_type="Reset Script" />
+      </file>
+    </folder>
+    <configuration
+      Name="EA4088 QuickStart"
+      link_use_linker_script_file="No"
+      linker_section_placement_file="flash_placement.xml" />
+    <folder Name="hw">
+      <folder Name="bsp">
+        <file file_name="../../../../../hw/bsp/ansi_escape.h" />
+        <file file_name="../../../../../hw/bsp/board.h" />
+        <folder Name="ea4088qs">
+          <file file_name="../../../../../hw/bsp/ea4088qs/board_ea4088qs.c" />
+          <file file_name="../../../../../hw/bsp/ea4088qs/board_ea4088qs.h" />
+        </folder>
+      </folder>
+      <folder Name="mcu">
+        <folder Name="nxp">
+          <folder Name="lpc_chip_40xx">
+            <folder Name="inc">
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc175x_6x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc177x_8x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/chip_lpc407x_8x.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/clock_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/cmsis.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/cmsis_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cm4_simd.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cmFunc.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/core_cmInstr.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/gpio_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/sys_config.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/sysctl_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/uart_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/usb_17xx_40xx.h" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/inc/iocon_17xx_40xx.h" />
+            </folder>
+            <folder Name="src">
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/chip_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/clock_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/gpio_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/iocon_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/sysctl_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/sysinit_17xx_40xx.c" />
+              <file file_name="../../../../../hw/mcu/nxp/lpc_chip_40xx/src/uart_17xx_40xx.c" />
+            </folder>
+          </folder>
+        </folder>
+      </folder>
+    </folder>
+    <folder
+      Name="segger_rtt"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../../../../lib/segger_rtt"
+      recurse="No" />
+    <folder
+      Name="src"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../src"
+      recurse="Yes" />
+    <folder
+      Name="tinyusb"
+      exclude=""
+      filter="*.c;*.h"
+      path="../../../../../src"
+      recurse="Yes" />
+  </project>
+  <configuration
+    Name="EA4088 QuickStart"
+    c_preprocessor_definitions="DEBUG"
+    gcc_debugging_level="Level 3"
+    gcc_optimization_level="None" />
+</solution>
diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s b/examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s
new file mode 100644
index 000000000..17f88e0ca
--- /dev/null
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/thumb_crt0.s
@@ -0,0 +1,415 @@
+// **********************************************************************
+// *                    SEGGER Microcontroller GmbH                     *
+// *                        The Embedded Experts                        *
+// **********************************************************************
+// *                                                                    *
+// *            (c) 2014 - 2018 SEGGER Microcontroller GmbH             *
+// *            (c) 2001 - 2018 Rowley Associates Limited               *
+// *                                                                    *
+// *           www.segger.com     Support: support@segger.com           *
+// *                                                                    *
+// **********************************************************************
+// *                                                                    *
+// * All rights reserved.                                               *
+// *                                                                    *
+// * Redistribution and use in source and binary forms, with or         *
+// * without modification, are permitted provided that the following    *
+// * conditions are met:                                                *
+// *                                                                    *
+// * - Redistributions of source code must retain the above copyright   *
+// *   notice, this list of conditions and the following disclaimer.    *
+// *                                                                    *
+// * - Neither the name of SEGGER Microcontroller GmbH                  *
+// *   nor the names of its contributors may be used to endorse or      *
+// *   promote products derived from this software without specific     *
+// *   prior written permission.                                        *
+// *                                                                    *
+// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+// * DISCLAIMED.                                                        *
+// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR        *
+// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+// * DAMAGE.                                                            *
+// *                                                                    *
+// **********************************************************************
+//
+//
+//                           Preprocessor Definitions
+//                           ------------------------
+// APP_ENTRY_POINT
+//
+//   Defines the application entry point function, if undefined this setting
+//   defaults to "main".
+//
+// INITIALIZE_STACK
+//
+//   If defined, the contents of the stack will be initialized to a the
+//   value 0xCC.
+//
+// INITIALIZE_SECONDARY_SECTIONS
+//
+//   If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
+//
+// INITIALIZE_TCM_SECTIONS
+//
+//   If defined, the .data_tcm, .text_tcm, .rodata_tcm and .bss_tcm sections 
+//   will be initialized.
+//
+// INITIALIZE_USER_SECTIONS
+//
+//   If defined, the function InitializeUserMemorySections will be called prior
+//   to entering main in order to allow the user to initialize any user defined
+//   memory sections.
+//
+// FULL_LIBRARY
+//
+//  If defined then 
+//    - argc, argv are setup by the debug_getargs.
+//    - the exit symbol is defined and executes on return from main.
+//    - the exit symbol calls destructors, atexit functions and then debug_exit.
+//  
+//  If not defined then
+//    - argc and argv are zero.
+//    - the exit symbol is defined, executes on return from main and loops
+//
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+  .syntax unified
+
+  .global _start
+  .extern APP_ENTRY_POINT
+  .global exit
+  .weak exit
+
+#ifdef INITIALIZE_USER_SECTIONS
+  .extern InitializeUserMemorySections
+#endif
+
+  .section .init, "ax"
+  .code 16
+  .balign 2
+  .thumb_func
+
+_start:
+  /* Set up main stack if size > 0 */
+  ldr r1, =__stack_end__
+  ldr r0, =__stack_start__
+  subs r2, r1, r0
+  beq 1f
+#ifdef __ARM_EABI__
+  movs r2, #0x7
+  bics r1, r2
+#endif
+  mov sp, r1
+#ifdef INITIALIZE_STACK
+  movs r2, #0xCC
+  ldr r0, =__stack_start__
+  bl memory_set
+#endif
+1:
+
+  /* Set up process stack if size > 0 */
+  ldr r1, =__stack_process_end__
+  ldr r0, =__stack_process_start__
+  subs r2, r1, r0
+  beq 1f
+#ifdef __ARM_EABI__
+  movs r2, #0x7
+  bics r1, r2
+#endif
+  msr psp, r1
+  movs r2, #2
+  msr control, r2
+#ifdef INITIALIZE_STACK
+  movs r2, #0xCC
+  bl memory_set
+#endif
+1:
+
+  /* Copy initialized memory sections into RAM (if necessary). */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  ldr r2, =__data_end__
+  bl memory_copy
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  ldr r2, =__text_end__
+  bl memory_copy
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  ldr r2, =__fast_end__
+  bl memory_copy
+  ldr r0, =__ctors_load_start__
+  ldr r1, =__ctors_start__
+  ldr r2, =__ctors_end__
+  bl memory_copy
+  ldr r0, =__dtors_load_start__
+  ldr r1, =__dtors_start__
+  ldr r2, =__dtors_end__
+  bl memory_copy
+  ldr r0, =__rodata_load_start__
+  ldr r1, =__rodata_start__
+  ldr r2, =__rodata_end__
+  bl memory_copy
+  ldr r0, =__tdata_load_start__
+  ldr r1, =__tdata_start__
+  ldr r2, =__tdata_end__
+  bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+  ldr r0, =__data2_load_start__
+  ldr r1, =__data2_start__
+  ldr r2, =__data2_end__
+  bl memory_copy
+  ldr r0, =__text2_load_start__
+  ldr r1, =__text2_start__
+  ldr r2, =__text2_end__
+  bl memory_copy
+  ldr r0, =__rodata2_load_start__
+  ldr r1, =__rodata2_start__
+  ldr r2, =__rodata2_end__
+  bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+#ifdef INITIALIZE_TCM_SECTIONS
+  ldr r0, =__data_tcm_load_start__
+  ldr r1, =__data_tcm_start__
+  ldr r2, =__data_tcm_end__
+  bl memory_copy
+  ldr r0, =__text_tcm_load_start__
+  ldr r1, =__text_tcm_start__
+  ldr r2, =__text_tcm_end__
+  bl memory_copy
+  ldr r0, =__rodata_tcm_load_start__
+  ldr r1, =__rodata_tcm_start__
+  ldr r2, =__rodata_tcm_end__
+  bl memory_copy
+#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
+
+  /* Zero the bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  movs r2, #0
+  bl memory_set
+  ldr r0, =__tbss_start__
+  ldr r1, =__tbss_end__
+  movs r2, #0
+  bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+  ldr r0, =__bss2_start__
+  ldr r1, =__bss2_end__
+  mov r2, #0
+  bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+#ifdef INITIALIZE_TCM_SECTIONS
+  ldr r0, =__bss_tcm_start__
+  ldr r1, =__bss_tcm_end__
+  mov r2, #0
+  bl memory_set
+#endif /* #ifdef INITIALIZE_TCM_SECTIONS */
+
+  /* Initialize the heap */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  subs r1, r1, r0
+  cmp r1, #8
+  blt 1f
+  movs r2, #0
+  str r2, [r0]
+  adds r0, r0, #4
+  str r1, [r0]
+1:
+
+#ifdef INITIALIZE_USER_SECTIONS
+  ldr r2, =InitializeUserMemorySections
+  blx r2
+#endif
+
+  /* Call constructors */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+ctor_loop:
+  cmp r0, r1
+  beq ctor_end
+  ldr r2, [r0]
+  adds r0, #4
+  push {r0-r1}  
+  blx r2
+  pop {r0-r1}
+  b ctor_loop
+ctor_end:
+
+  /* Setup initial call frame */
+  movs r0, #0
+  mov lr, r0
+  mov r12, sp
+
+  .type start, function
+start:
+  /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+  movs r0, #ARGSSPACE
+  ldr r1, =args
+  ldr r2, =debug_getargs  
+  blx r2
+  ldr r1, =args
+#else
+  movs r0, #0
+  movs r1, #0
+#endif
+  ldr r2, =APP_ENTRY_POINT
+  blx r2
+
+  .thumb_func
+exit:
+#ifdef FULL_LIBRARY  
+  mov r5, r0 // save the exit parameter/return result
+
+  /* Call destructors */
+  ldr r0, =__dtors_start__
+  ldr r1, =__dtors_end__
+dtor_loop:
+  cmp r0, r1
+  beq dtor_end
+  ldr r2, [r0]
+  add r0, #4
+  push {r0-r1}
+  blx r2
+  pop {r0-r1}
+  b dtor_loop
+dtor_end:
+
+  /* Call atexit functions */
+  ldr r2, =_execute_at_exit_fns  
+  blx r2
+
+  /* Call debug_exit with return result/exit parameter */
+  mov r0, r5
+  ldr r2, =debug_exit  
+  blx r2
+#endif
+
+  /* Returned from application entry point, loop forever. */
+exit_loop:
+  b exit_loop
+
+  .thumb_func
+memory_copy:
+  cmp r0, r1
+  beq 2f
+  subs r2, r2, r1
+  beq 2f
+1:
+  ldrb r3, [r0]
+  adds r0, r0, #1
+  strb r3, [r1]
+  adds r1, r1, #1
+  subs r2, r2, #1
+  bne 1b
+2:
+  bx lr
+
+  .thumb_func
+memory_set:
+  cmp r0, r1
+  beq 1f
+  strb r2, [r0]
+  adds r0, r0, #1
+  b memory_set
+1:
+  bx lr
+
+  // default C/C++ library helpers
+
+.macro HELPER helper_name
+  .section .text.\helper_name, "ax", %progbits
+  .balign 2
+  .global \helper_name
+  .weak \helper_name  
+\helper_name:
+  .thumb_func
+.endm
+
+.macro JUMPTO name
+#if defined(__thumb__) && !defined(__thumb2__)
+  mov r12, r0
+  ldr r0, =\name
+  push {r0}
+  mov r0, r12
+  pop {pc}
+#else
+  b \name
+#endif
+.endm
+
+HELPER __aeabi_read_tp
+  ldr r0, =__tbss_start__-8
+  bx lr
+HELPER abort
+  b .
+HELPER __assert
+  b .
+HELPER __aeabi_assert
+  b .
+HELPER __sync_synchronize
+  bx lr
+HELPER __getchar
+  JUMPTO debug_getchar
+HELPER __putchar
+  JUMPTO debug_putchar
+HELPER __open
+  JUMPTO debug_fopen
+HELPER __close
+  JUMPTO debug_fclose
+HELPER __write   
+  mov r3, r0
+  mov r0, r1
+  movs r1, #1  
+  JUMPTO debug_fwrite
+HELPER __read  
+  mov r3, r0
+  mov r0, r1
+  movs r1, #1 
+  JUMPTO debug_fread
+HELPER __seek
+  push {r4, lr}
+  mov r4, r0
+  bl debug_fseek
+  cmp r0, #0
+  bne 1f
+  mov r0, r4
+  bl debug_ftell
+  pop {r4, pc}
+1:
+  ldr r0, =-1
+  pop {r4, pc}
+  // char __user_locale_name_buffer[];
+  .section .bss.__user_locale_name_buffer, "aw", %nobits
+  .global __user_locale_name_buffer
+  .weak __user_locale_name_buffer
+  __user_locale_name_buffer:
+  .word 0x0
+
+#ifdef FULL_LIBRARY
+  .bss
+args:
+  .space ARGSSPACE
+#endif
+
+  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
+  .section .stack, "wa", %nobits
+  .section .stack_process, "wa", %nobits
+  .section .heap, "wa", %nobits
+
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 306778ee3..e845fe16a 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -63,6 +63,8 @@
   #include "lpcxpresso1769/board_lpcxpresso1769.h"
 #elif defined BOARD_MCB1800
   #include "mcb1800/board_mcb1800.h"
+#elif defined BOARD_EA4088QS
+  #include "ea4088qs/board_ea4088qs.h"
 #elif defined BOARD_EA4357
   #include "ea4357/board_ea4357.h"
 
diff --git a/hw/bsp/ea4088qs/board_ea4088qs.c b/hw/bsp/ea4088qs/board_ea4088qs.c
index 9df56c183..79e00a57e 100644
--- a/hw/bsp/ea4088qs/board_ea4088qs.c
+++ b/hw/bsp/ea4088qs/board_ea4088qs.c
@@ -40,14 +40,109 @@
 
 #include "../board.h"
 
-#define LED_PORT      0
-#define LED_PIN       22
+#define LED_PORT      2
+#define LED_PIN       19
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
 
-//------------- IMPLEMENTATION -------------//
+/* Pin muxing configuration */
+static const PINMUX_GRP_T pinmuxing[] =
+{
+	/* LEDs */
+	{0x2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
+};
+
+
+// Invoked by startup code
+void SystemInit(void)
+{
+  /* Enable IOCON clock */
+  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+  Chip_SetupXtalClocking();
+}
+
+void board_init(void)
+{
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / BOARD_TICKS_HZ);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  Chip_GPIO_Init(LPC_GPIO);
+
+  //------------- LED -------------//
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
+
+  //------------- BUTTON -------------//
+//  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
+
+
+  //------------- UART -------------//
+
+	//------------- USB -------------//
+}
+
+
+//------------- LED -------------//
+void board_led_control(bool state)
+{
+  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
+}
+
+//------------- Buttons -------------//
+static bool button_read(uint8_t id)
+{
+//  return !BIT_TEST_( GPIO_ReadValue(buttons[id].gpio_port), buttons[id].gpio_pin ); // button is active low
+}
+
+uint32_t board_buttons(void)
+{
+  uint32_t result = 0;
+
+//  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) result |= (button_read(i) ? BIT_(i) : 0);
+
+  return result;
+}
+
+
+//------------- UART -------------//
+uint8_t  board_uart_getchar(void)
+{
+  //return UART_ReceiveByte(BOARD_UART_PORT);
+}
+void board_uart_putchar(uint8_t c)
+{
+  //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
+}
+
+
+/*------------------------------------------------------------------*/
+/* TUSB HAL MILLISECOND
+ *------------------------------------------------------------------*/
+#if CFG_TUSB_OS == OPT_OS_NONE
+
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t tusb_hal_millis(void)
+{
+  return board_tick2ms(system_ticks);
+}
+
+#endif
 
 #endif
diff --git a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
index a17454d29..34e05932a 100644
--- a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
@@ -46,6 +46,10 @@
 
 #define BOARD_UART_PORT   LPC_UART3
 
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
+
 /* Pin muxing configuration */
 static const PINMUX_GRP_T pinmuxing[] =
 {
@@ -65,10 +69,6 @@ enum {
   BOARD_BUTTON_COUNT = 5
 };
 
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
 // Invoked by startup code
 void SystemInit(void)
 {
diff --git a/hw/bsp/mcb1800/board_mcb1800.c b/hw/bsp/mcb1800/board_mcb1800.c
index a8a37a5e3..2aed87418 100644
--- a/hw/bsp/mcb1800/board_mcb1800.c
+++ b/hw/bsp/mcb1800/board_mcb1800.c
@@ -145,6 +145,7 @@ void board_init(void)
   //------------- USB -------------//
 }
 
+//------------- LED -------------//
 void board_led_control(bool state)
 {
   Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 549420f22..6ed1792ce 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -41,7 +41,7 @@
 #if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "device/dcd.h"
-#include "dcd_lpc175x_6x.h"
+#include "dcd_lpc17_40.h"
 #include "chip.h"
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From fe8346e642c369ad0e0b5bbf3a10d8e7d16a10fc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Dec 2018 18:38:01 +0700
Subject: move pinmux out of dcd into bsp

---
 hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c | 25 +++++++++++++++----------
 src/portable/nxp/lpc17_40/hal_lpc17_40.c     | 10 ++--------
 2 files changed, 17 insertions(+), 18 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
index 34e05932a..257c74b63 100644
--- a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
@@ -53,16 +53,21 @@ const uint32_t RTCOscRateIn = 32768;
 /* Pin muxing configuration */
 static const PINMUX_GRP_T pinmuxing[] =
 {
-	{0,  0,   IOCON_MODE_INACT | IOCON_FUNC2},	/* TXD3 */
-	{0,  1,   IOCON_MODE_INACT | IOCON_FUNC2},	/* RXD3 */
-	{0,  22,  IOCON_MODE_INACT | IOCON_FUNC0},	/* Led 0 */
-
-	/* Joystick buttons. */
-	{2, 3,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_UP */
-	{0, 15, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_DOWN */
-	{2, 4,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_LEFT */
-	{0, 16, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_RIGHT */
-	{0, 17, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_PRESS */
+  {0,  0,   IOCON_MODE_INACT | IOCON_FUNC2},	/* TXD3 */
+  {0,  1,   IOCON_MODE_INACT | IOCON_FUNC2},	/* RXD3 */
+  {0,  22,  IOCON_MODE_INACT | IOCON_FUNC0},	/* Led 0 */
+
+  /* Joystick buttons. */
+  {2, 3,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_UP */
+  {0, 15, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_DOWN */
+  {2, 4,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_LEFT */
+  {0, 16, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_RIGHT */
+  {0, 17, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_PRESS */
+
+  // USB
+  {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
+  {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
+  {2,  9, IOCON_MODE_INACT | IOCON_FUNC1}, // Connect
 };
 
 enum {
diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
index 668cabd80..cebddd883 100644
--- a/src/portable/nxp/lpc17_40/hal_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
@@ -66,24 +66,18 @@ bool tusb_hal_init(void)
 
   Chip_USB_Init();
 
-  /* Configure P0.29 as D+, P0.30 as D- */
-  Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC1);
-  Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC1);
-
 #if MODE_HOST_SUPPORTED
+  // TODO move pin config to BSP
   PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 22, .Funcnum = 2} ); // P1.22 as USB_PWRD
   PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 19, .Funcnum = 2} ); // P1.19 as USB_PPWR
 
   // Enable host
   LPC_USB->USBClkCtrl = USBCLK_HOST;
   while ((LPC_USB->USBClkSt & USBCLK_HOST) != USBCLK_HOST);
-  LPC_USB->OTGStCtrl = 0x3;
+  LPC_USB->OTGClkSt = 0x3;
 #endif
 
 #if TUSB_OPT_DEVICE_ENABLED
-  // P2_9 as USB Connect
-  Chip_IOCON_PinMux(LPC_IOCON, 2, 9, IOCON_MODE_INACT, IOCON_FUNC1);
-
   // Enable Device
   LPC_USB->USBClkCtrl = USBCLK_DEVCIE;
   while ((LPC_USB->USBClkSt & USBCLK_DEVCIE) != USBCLK_DEVCIE);
-- 
cgit v1.3.1


From dd9c7b4249618cb8113b0a37226bc6947818ecf0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Dec 2018 08:47:23 +0700
Subject: lpc40xx device work, moving Chip_USB_Init out of tinyusb

---
 .../cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject      |  2 +-
 examples/device/cdc_msc_hid/src/tusb_config.h      |  4 +-
 hw/bsp/ea4088qs/board_ea4088qs.c                   | 33 +++++++++++++++-
 hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c       | 45 ++++++++++++++--------
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c           |  2 +-
 src/portable/nxp/lpc17_40/hal_lpc17_40.c           | 24 ------------
 src/tusb_option.h                                  |  4 ++
 7 files changed, 70 insertions(+), 44 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject b/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
index ed6840e06..6bcd7d4a7 100644
--- a/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
+++ b/examples/device/cdc_msc_hid/ses/lpc40xx/lpc40xx.emProject
@@ -18,7 +18,7 @@
       arm_target_debug_interface_type="ADIv5"
       arm_target_device_name="LPC4088"
       arm_target_interface_type="SWD"
-      c_preprocessor_definitions="CORE_M4;__LPC4000_FAMILY;__LPC408x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4088QS;CFG_TUSB_MCU=OPT_MCU_LPC40XX"
+      c_preprocessor_definitions="CORE_M4;__LPC4000_FAMILY;__LPC408x_SUBFAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;BOARD_EA4088QS;CFG_TUSB_MCU=OPT_MCU_LPC40XX;CFG_TUSB_MEM_SECTION= __attribute__((section(&quot;.bss2&quot;)))"
       c_user_include_directories="../../src;$(rootDir)/hw;$(rootDir)/src;$(lpcDir)/inc"
       debug_register_definition_file="$(ProjectDir)/LPC408x_7x_Registers.xml"
       debug_target_connection="J-Link"
diff --git a/examples/device/cdc_msc_hid/src/tusb_config.h b/examples/device/cdc_msc_hid/src/tusb_config.h
index a9a356f20..30bf05fab 100644
--- a/examples/device/cdc_msc_hid/src/tusb_config.h
+++ b/examples/device/cdc_msc_hid/src/tusb_config.h
@@ -99,9 +99,9 @@
 // #define CFG_TUD_DESC_VID          0xCAFE
 // #define CFG_TUD_DESC_PID          0x0001
 
-// LPC175x_6x's endpoint type (bulk/interrupt/iso) are fixed by its number
+// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
 // Therefor we need to force endpoint number to correct type on lpc17xx
-#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
 #define CFG_TUD_DESC_CDC_EPNUM_NOTIF      1
 #define CFG_TUD_DESC_CDC_EPNUM            2
 #define CFG_TUD_DESC_MSC_EPNUM            5
diff --git a/hw/bsp/ea4088qs/board_ea4088qs.c b/hw/bsp/ea4088qs/board_ea4088qs.c
index 79e00a57e..af48b363b 100644
--- a/hw/bsp/ea4088qs/board_ea4088qs.c
+++ b/hw/bsp/ea4088qs/board_ea4088qs.c
@@ -39,6 +39,7 @@
 #ifdef BOARD_EA4088QS
 
 #include "../board.h"
+#include "tusb.h"
 
 #define LED_PORT      2
 #define LED_PIN       19
@@ -55,9 +56,25 @@ const uint32_t RTCOscRateIn = 32768;
 static const PINMUX_GRP_T pinmuxing[] =
 {
 	/* LEDs */
-	{0x2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
+	{2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
 };
 
+static const PINMUX_GRP_T pin_usb_mux[] =
+{
+	// USB1 as Host
+	{0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
+	{0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
+	{1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
+	{1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
+
+	// USB2 as Device
+	{0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
+	{0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
+	{0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
+
+	/* VBUS is not connected on this board, so leave the pin at default setting. */
+	/*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
+};
 
 // Invoked by startup code
 void SystemInit(void)
@@ -90,6 +107,20 @@ void board_init(void)
   //------------- UART -------------//
 
 	//------------- USB -------------//
+  // Port1 as Host, Port2: Device
+  Chip_USB_Init();
+
+  enum {
+    USBCLK  = 0x1B // Host + Device + OTG + AHB
+  };
+
+  LPC_USB->OTGClkCtrl = USBCLK;
+  while ( (LPC_USB->OTGClkSt & USBCLK) != USBCLK );
+
+  // USB1 = host, USB2 = device
+  LPC_USB->StCtrl = 0x3;
+
+  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
 }
 
 
diff --git a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
index 257c74b63..00141e9a1 100644
--- a/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
@@ -40,6 +40,7 @@
 #ifdef BOARD_LPCXPRESSO1769
 
 #include "../board.h"
+#include "tusb.h"
 
 #define LED_PORT      0
 #define LED_PIN       22
@@ -63,11 +64,19 @@ static const PINMUX_GRP_T pinmuxing[] =
   {2, 4,  IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_LEFT */
   {0, 16, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_RIGHT */
   {0, 17, IOCON_MODE_INACT | IOCON_FUNC0},	/* JOYSTICK_PRESS */
+};
 
-  // USB
+static const PINMUX_GRP_T pin_usb_mux[] =
+{
   {0, 29, IOCON_MODE_INACT | IOCON_FUNC1}, // D+
   {0, 30, IOCON_MODE_INACT | IOCON_FUNC1}, // D-
   {2,  9, IOCON_MODE_INACT | IOCON_FUNC1}, // Connect
+
+  {1, 19, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PPWR
+  {1, 22, IOCON_MODE_INACT | IOCON_FUNC2}, // USB_PWRD
+
+	/* VBUS is not connected on this board, so leave the pin at default setting. */
+	/*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
 };
 
 enum {
@@ -101,18 +110,6 @@ void board_init(void)
   //------------- BUTTON -------------//
 //  for(uint8_t i=0; i<BOARD_BUTTON_COUNT; i++) GPIO_SetDir(buttons[i].port, BIT_(buttons[i].pin), 0);
 
-#if TUSB_OPT_DEVICE_ENABLED
-  //------------- USB Device -------------//
-  // VBUS sense is wrongly connected to P0_5 (instead of P1_30). So we need to always pull P1_30 to high
-  // so that USB device block can work. However, Device Controller (thus tinyusb) cannot able to determine
-  // if device is disconnected or not
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) {
-      .Portnum = 1, .Pinnum = 30,
-      .Funcnum = 2, .Pinmode = PINSEL_PINMODE_PULLUP} );
-
-  //P0_21 instead of P2_9 as USB connect
-#endif
-
 #if 0
   //------------- UART -------------//
   PINSEL_CFG_Type PinCfg =
@@ -137,8 +134,26 @@ void board_init(void)
 	UART_TxCmd(BOARD_UART_PORT, ENABLE); // Enable UART Transmit
 #endif
 
-	/* VBUS is not connected on the NXP LPCXpresso LPC1769, so leave the pin at default setting. */
-	/*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
+	//------------- USB -------------//
+	Chip_USB_Init();
+
+  enum {
+    USBCLK_DEVCIE = 0x12,     // AHB + Device
+    USBCLK_HOST   = 0x19,     // AHB + Host + OTG
+//    0x1B // Host + Device + OTG + AHB
+  };
+
+  uint32_t const clk_en = TUSB_OPT_DEVICE_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
+
+  LPC_USB->OTGClkCtrl = clk_en;
+  while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
+
+#if MODE_HOST_SUPPORTED
+  // set portfunc to host !!!
+  LPC_USB->StCtrl = 0x3; // should be 1
+#endif
+
+  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
 }
 
 /*------------------------------------------------------------------*/
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 6ed1792ce..8504cbf51 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -103,7 +103,7 @@ typedef struct
 
 } dcd_data_t;
 
-ATTR_ALIGNED(128) static dcd_data_t _dcd;
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(128) static dcd_data_t _dcd;
 
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
index cebddd883..70df70510 100644
--- a/src/portable/nxp/lpc17_40/hal_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
@@ -59,30 +59,6 @@ void tusb_hal_int_disable(uint8_t rhport)
 //--------------------------------------------------------------------+
 bool tusb_hal_init(void)
 {
-  enum {
-    USBCLK_DEVCIE = 0x12,     // AHB + Device
-    USBCLK_HOST   = 0x19,     // AHB + Host + OTG (!)
-  };
-
-  Chip_USB_Init();
-
-#if MODE_HOST_SUPPORTED
-  // TODO move pin config to BSP
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 22, .Funcnum = 2} ); // P1.22 as USB_PWRD
-  PINSEL_ConfigPin( &(PINSEL_CFG_Type) { .Portnum = 1, .Pinnum = 19, .Funcnum = 2} ); // P1.19 as USB_PPWR
-
-  // Enable host
-  LPC_USB->USBClkCtrl = USBCLK_HOST;
-  while ((LPC_USB->USBClkSt & USBCLK_HOST) != USBCLK_HOST);
-  LPC_USB->OTGClkSt = 0x3;
-#endif
-
-#if TUSB_OPT_DEVICE_ENABLED
-  // Enable Device
-  LPC_USB->USBClkCtrl = USBCLK_DEVCIE;
-  while ((LPC_USB->USBClkSt & USBCLK_DEVCIE) != USBCLK_DEVCIE);
-#endif
-
   return true;
 }
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index d808a0518..c558b30ff 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -153,6 +153,10 @@
 #define CFG_TUSB_MEM_SECTION
 #endif
 
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          ATTR_ALIGNED(4)
+#endif
+
 #ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS OPT_OS_NONE
 #endif
-- 
cgit v1.3.1


From 9176b7b1da80ae8872deba74263431b843650c13 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Dec 2018 08:51:11 +0700
Subject: renane file

---
 hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.h  |   2 -
 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c  | 407 ++++++++++++++++++++++++
 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c | 407 ------------------------
 3 files changed, 407 insertions(+), 409 deletions(-)
 create mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
 delete mode 100644 src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c

(limited to 'src')

diff --git a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.h b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.h
index 02b1ad81d..74e68e5e2 100644
--- a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.h
+++ b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.h
@@ -45,8 +45,6 @@
 
 #include "chip.h"
 
-#define BOARD_LED0      17
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
new file mode 100644
index 000000000..1ae070a73
--- /dev/null
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
@@ -0,0 +1,407 @@
+/**************************************************************************/
+/*!
+    @file     dcd_lpc11_13_15.c
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
+
+#include "chip.h"
+#include "device/dcd.h"
+#include "dcd_lpc11_13_15.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// Number of endpoints
+#define EP_COUNT 10
+
+// only SRAM1 & USB RAM can be used for transfer
+#define SRAM_REGION   0x20000000
+
+/* Although device controller are the same. DMA of
+ * - LPC11u can only transfer up to nbytes = 64
+ * - LPC13 can transfer nbytes = 1023 (maximum)
+ * - LPC15 can ???
+ */
+enum {
+  DMA_NBYTES_MAX = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
+};
+
+enum {
+  INT_SOF_MASK           = BIT_(30),
+  INT_DEVICE_STATUS_MASK = BIT_(31)
+};
+
+enum {
+  CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
+  CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
+  CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
+  CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16), ///< reflect the softconnect only, does not reflect the actual attached state
+  CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
+  CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
+  CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
+  CMDSTAT_RESET_CHANGE_MASK   = BIT_(26),
+  CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
+};
+
+typedef struct ATTR_PACKED
+{
+  // Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
+  volatile uint16_t buffer_offset;
+
+  volatile uint16_t nbytes : 10 ;
+  uint16_t is_iso          : 1  ;
+  uint16_t toggle_mode     : 1  ;
+  uint16_t toggle_reset    : 1  ;
+  uint16_t stall           : 1  ;
+  uint16_t disable         : 1  ;
+  volatile uint16_t active : 1  ;
+}ep_cmd_sts_t;
+
+TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
+
+typedef struct
+{
+  uint16_t total_bytes;
+  uint16_t xferred_bytes;
+
+  uint16_t nbytes;
+}xfer_dma_t;
+
+// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
+// current_td is used to keep track of number of remaining & xferred bytes of the current request.
+typedef struct
+{
+  // 256 byte aligned, 2 for double buffer (not used)
+  // Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
+  ep_cmd_sts_t ep[EP_COUNT][2];
+
+  xfer_dma_t dma[EP_COUNT];
+
+  ATTR_ALIGNED(64) uint8_t setup_packet[8];
+}dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
+// EP list must be 256-byte aligned
+CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) static dcd_data_t _dcd;
+
+static inline uint16_t get_buf_offset(void const * buffer)
+{
+  uint32_t addr = (uint32_t) buffer;
+  TU_ASSERT( (addr & 0x3f) == 0, 0 );
+  return ( (addr >> 6) & 0xFFFFUL ) ;
+}
+
+static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
+{
+  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
+}
+
+//--------------------------------------------------------------------+
+// CONTROLLER API
+//--------------------------------------------------------------------+
+void tusb_hal_int_enable(uint8_t rhport)
+{
+  (void) rhport; // discard compiler's warning
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void tusb_hal_int_disable(uint8_t rhport)
+{
+  (void) rhport; // discard compiler's warning
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+bool tusb_hal_init(void)
+{
+  // TODO remove
+  return true;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+
+  LPC_USB->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  LPC_USB->DEVCMDSTAT |= dev_addr;
+}
+
+bool dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  // Setup PLL clock, and power
+  Chip_USB_Init();
+
+  LPC_USB->EPLISTSTART  = (uint32_t) _dcd.ep;
+  LPC_USB->DATABUFSTART = SRAM_REGION;
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK;
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
+                          CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+
+  NVIC_EnableIRQ(USB0_IRQn);
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  if ( edpt_number(ep_addr) == 0 )
+  {
+    // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
+    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 1;
+  }
+  else
+  {
+    uint8_t const ep_id = ep_addr2id(ep_addr);
+    _dcd.ep[ep_id][0].stall = 1;
+  }
+}
+
+bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const ep_id = ep_addr2id(ep_addr);
+  return _dcd.ep[ep_id][0].stall;
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
+{
+  uint8_t const ep_id = ep_addr2id(edpt_addr);
+
+  _dcd.ep[ep_id][0].stall        = 0;
+  _dcd.ep[ep_id][0].toggle_reset = 1;
+  _dcd.ep[ep_id][0].toggle_mode  = 0;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void) rhport;
+
+  // TODO not support ISO yet
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
+
+  //------------- Prepare Queue Head -------------//
+  uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
+
+  // Check if endpoint is available
+  TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
+
+  tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
+  _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+
+  // Enable EP interrupt
+  LPC_USB->INTEN |= BIT_(ep_id);
+
+  return true;
+}
+
+bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const ep_id = ep_addr2id(ep_addr);
+  return _dcd.ep[ep_id][0].active;
+}
+
+static void prepare_ep_xfer(uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
+{
+  uint16_t const nbytes = tu_min16(total_bytes, DMA_NBYTES_MAX);
+
+  _dcd.dma[ep_id].nbytes = nbytes;
+
+  _dcd.ep[ep_id][0].buffer_offset = buf_offset;
+  _dcd.ep[ep_id][0].nbytes        = nbytes;
+  _dcd.ep[ep_id][0].active        = 1;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  uint8_t const ep_id = ep_addr2id(ep_addr);
+
+  tu_varclr(&_dcd.dma[ep_id]);
+  _dcd.dma[ep_id].total_bytes = total_bytes;
+
+  prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes);
+
+	return true;
+}
+
+//--------------------------------------------------------------------+
+// IRQ
+//--------------------------------------------------------------------+
+static void bus_reset(void)
+{
+  tu_memclr(&_dcd, sizeof(dcd_data_t));
+
+  // disable all non-control endpoints on bus reset
+  for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
+  {
+    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+  }
+
+  _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
+
+  LPC_USB->EPINUSE      = 0;
+  LPC_USB->EPBUFCFG     = 0;
+  LPC_USB->EPSKIP       = 0xFFFFFFFF;
+
+  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
+  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
+  LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK | BIT_(0) | BIT_(1); // enable device status & control endpoints
+}
+
+static void process_xfer_isr(uint32_t int_status)
+{
+  for(uint8_t ep_id = 0; ep_id < EP_COUNT; ep_id++ )
+  {
+    if ( BIT_TEST_(int_status, ep_id) )
+    {
+      ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
+      xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
+
+      xfer_dma->xferred_bytes += xfer_dma->nbytes - ep_cs->nbytes;
+
+      if ( (ep_cs->nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
+      {
+        // There is more data to transfer
+        // buff_offset has been already increased by hw to correct value for next transfer
+        prepare_ep_xfer(ep_id, ep_cs->buffer_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
+      }
+      else
+      {
+        xfer_dma->total_bytes = xfer_dma->xferred_bytes;
+
+        uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
+
+        // TODO no way determine if the transfer is failed or not
+        dcd_event_xfer_complete(0, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
+      }
+    }
+  }
+}
+
+void USB_IRQHandler(void)
+{
+  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
+
+  uint32_t int_status = LPC_USB->INTSTAT & LPC_USB->INTEN;
+  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
+
+  if (int_status == 0) return;
+
+  //------------- Device Status -------------//
+  if ( int_status & INT_DEVICE_STATUS_MASK )
+  {
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    {
+      bus_reset();
+      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+    }
+
+    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    {
+      // device disconnect
+      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      {
+        // debouncing as this can be set when device is powering
+        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+      }
+    }
+
+    // TODO support suspend & resume
+    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    {
+      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
+      { // suspend signal, bus idle for more than 3ms
+        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+        {
+          dcd_event_bus_signal(0, DCD_EVENT_SUSPENDED, true);
+        }
+      }
+    }
+//        else
+//      { // resume signal
+//    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+//      }
+//    }
+  }
+
+  // Setup Receive
+  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  {
+    // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
+    _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
+    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
+
+    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+
+    dcd_event_setup_received(0, _dcd.setup_packet, true);
+
+    // keep waiting for next setup
+    _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
+
+    // clear bit0
+    int_status = BIT_CLR_(int_status, 0);
+  }
+
+  // Endpoint transfer complete interrupt
+  process_xfer_isr(int_status);
+}
+
+#endif
+
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
deleted file mode 100644
index 568bcc586..000000000
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc_11_13_15.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     dcd_lpc11_13_15.c
-    @author   hathach (tinyusb.org)
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2013, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
-
-#include "chip.h"
-#include "device/dcd.h"
-#include "dcd_lpc11_13_15.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-// Number of endpoints
-#define EP_COUNT 10
-
-// only SRAM1 & USB RAM can be used for transfer
-#define SRAM_REGION   0x20000000
-
-/* Although device controller are the same. DMA of
- * - LPC11u can only transfer up to nbytes = 64
- * - LPC13 can transfer nbytes = 1023 (maximum)
- * - LPC15 can ???
- */
-enum {
-  DMA_NBYTES_MAX = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
-};
-
-enum {
-  INT_SOF_MASK           = BIT_(30),
-  INT_DEVICE_STATUS_MASK = BIT_(31)
-};
-
-enum {
-  CMDSTAT_DEVICE_ADDR_MASK    = BIT_(7 )-1,
-  CMDSTAT_DEVICE_ENABLE_MASK  = BIT_(7 ),
-  CMDSTAT_SETUP_RECEIVED_MASK = BIT_(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = BIT_(16), ///< reflect the softconnect only, does not reflect the actual attached state
-  CMDSTAT_DEVICE_SUSPEND_MASK = BIT_(17),
-  CMDSTAT_CONNECT_CHANGE_MASK = BIT_(24),
-  CMDSTAT_SUSPEND_CHANGE_MASK = BIT_(25),
-  CMDSTAT_RESET_CHANGE_MASK   = BIT_(26),
-  CMDSTAT_VBUS_DEBOUNCED_MASK = BIT_(28),
-};
-
-typedef struct ATTR_PACKED
-{
-  // Bits 21:6 (aligned 64) used in conjunction with bit 31:22 of DATABUFSTART
-  volatile uint16_t buffer_offset;
-
-  volatile uint16_t nbytes : 10 ;
-  uint16_t is_iso          : 1  ;
-  uint16_t toggle_mode     : 1  ;
-  uint16_t toggle_reset    : 1  ;
-  uint16_t stall           : 1  ;
-  uint16_t disable         : 1  ;
-  volatile uint16_t active : 1  ;
-}ep_cmd_sts_t;
-
-TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
-
-typedef struct
-{
-  uint16_t total_bytes;
-  uint16_t xferred_bytes;
-
-  uint16_t nbytes;
-}xfer_dma_t;
-
-// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
-// current_td is used to keep track of number of remaining & xferred bytes of the current request.
-typedef struct
-{
-  // 256 byte aligned, 2 for double buffer (not used)
-  // Each cmd_sts can only transfer up to DMA_NBYTES_MAX bytes each
-  ep_cmd_sts_t ep[EP_COUNT][2];
-
-  xfer_dma_t dma[EP_COUNT];
-
-  ATTR_ALIGNED(64) uint8_t setup_packet[8];
-}dcd_data_t;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-
-// EP list must be 256-byte aligned
-CFG_TUSB_MEM_SECTION ATTR_ALIGNED(256) static dcd_data_t _dcd;
-
-static inline uint16_t get_buf_offset(void const * buffer)
-{
-  uint32_t addr = (uint32_t) buffer;
-  TU_ASSERT( (addr & 0x3f) == 0, 0 );
-  return ( (addr >> 6) & 0xFFFFUL ) ;
-}
-
-static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
-{
-  return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
-}
-
-//--------------------------------------------------------------------+
-// CONTROLLER API
-//--------------------------------------------------------------------+
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport; // discard compiler's warning
-  NVIC_EnableIRQ(USB0_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport; // discard compiler's warning
-  NVIC_DisableIRQ(USB0_IRQn);
-}
-
-bool tusb_hal_init(void)
-{
-  // TODO remove
-  return true;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
-}
-
-void dcd_set_config(uint8_t rhport, uint8_t config_num)
-{
-
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-
-  LPC_USB->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
-  LPC_USB->DEVCMDSTAT |= dev_addr;
-}
-
-bool dcd_init(uint8_t rhport)
-{
-  (void) rhport;
-
-  // Setup PLL clock, and power
-  Chip_USB_Init();
-
-  LPC_USB->EPLISTSTART  = (uint32_t) _dcd.ep;
-  LPC_USB->DATABUFSTART = SRAM_REGION;
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK;
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
-                          CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-
-  NVIC_EnableIRQ(USB0_IRQn);
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  if ( edpt_number(ep_addr) == 0 )
-  {
-    // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
-    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 1;
-  }
-  else
-  {
-    uint8_t const ep_id = ep_addr2id(ep_addr);
-    _dcd.ep[ep_id][0].stall = 1;
-  }
-}
-
-bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const ep_id = ep_addr2id(ep_addr);
-  return _dcd.ep[ep_id][0].stall;
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
-{
-  uint8_t const ep_id = ep_addr2id(edpt_addr);
-
-  _dcd.ep[ep_id][0].stall        = 0;
-  _dcd.ep[ep_id][0].toggle_reset = 1;
-  _dcd.ep[ep_id][0].toggle_mode  = 0;
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  (void) rhport;
-
-  // TODO not support ISO yet
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
-
-  //------------- Prepare Queue Head -------------//
-  uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
-
-  // Check if endpoint is available
-  TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
-
-  tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
-  _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
-
-  // Enable EP interrupt
-  LPC_USB->INTEN |= BIT_(ep_id);
-
-  return true;
-}
-
-bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const ep_id = ep_addr2id(ep_addr);
-  return _dcd.ep[ep_id][0].active;
-}
-
-static void prepare_ep_xfer(uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
-{
-  uint16_t const nbytes = tu_min16(total_bytes, DMA_NBYTES_MAX);
-
-  _dcd.dma[ep_id].nbytes = nbytes;
-
-  _dcd.ep[ep_id][0].buffer_offset = buf_offset;
-  _dcd.ep[ep_id][0].nbytes        = nbytes;
-  _dcd.ep[ep_id][0].active        = 1;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
-  uint8_t const ep_id = ep_addr2id(ep_addr);
-
-  tu_varclr(&_dcd.dma[ep_id]);
-  _dcd.dma[ep_id].total_bytes = total_bytes;
-
-  prepare_ep_xfer(ep_id, get_buf_offset(buffer), total_bytes);
-
-	return true;
-}
-
-//--------------------------------------------------------------------+
-// IRQ
-//--------------------------------------------------------------------+
-static void bus_reset(void)
-{
-  tu_memclr(&_dcd, sizeof(dcd_data_t));
-
-  // disable all non-control endpoints on bus reset
-  for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
-  {
-    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
-  }
-
-  _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
-
-  LPC_USB->EPINUSE      = 0;
-  LPC_USB->EPBUFCFG     = 0;
-  LPC_USB->EPSKIP       = 0xFFFFFFFF;
-
-  LPC_USB->INTSTAT      = LPC_USB->INTSTAT; // clear all pending interrupt
-  LPC_USB->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK; // clear setup received interrupt
-  LPC_USB->INTEN        = INT_DEVICE_STATUS_MASK | BIT_(0) | BIT_(1); // enable device status & control endpoints
-}
-
-static void process_xfer_isr(uint32_t int_status)
-{
-  for(uint8_t ep_id = 0; ep_id < EP_COUNT; ep_id++ )
-  {
-    if ( BIT_TEST_(int_status, ep_id) )
-    {
-      ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
-      xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
-
-      xfer_dma->xferred_bytes += xfer_dma->nbytes - ep_cs->nbytes;
-
-      if ( (ep_cs->nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
-      {
-        // There is more data to transfer
-        // buff_offset has been already increased by hw to correct value for next transfer
-        prepare_ep_xfer(ep_id, ep_cs->buffer_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
-      }
-      else
-      {
-        xfer_dma->total_bytes = xfer_dma->xferred_bytes;
-
-        uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
-
-        // TODO no way determine if the transfer is failed or not
-        dcd_event_xfer_complete(0, ep_addr, xfer_dma->xferred_bytes, XFER_RESULT_SUCCESS, true);
-      }
-    }
-  }
-}
-
-void USB_IRQHandler(void)
-{
-  uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
-
-  uint32_t int_status = LPC_USB->INTSTAT & LPC_USB->INTEN;
-  LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;
-
-  //------------- Device Status -------------//
-  if ( int_status & INT_DEVICE_STATUS_MASK )
-  {
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
-    if ( dev_cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
-    {
-      bus_reset();
-      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
-    }
-
-    if (dev_cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
-    {
-      // device disconnect
-      if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-      {
-        // debouncing as this can be set when device is powering
-        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
-      }
-    }
-
-    // TODO support suspend & resume
-    if (dev_cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
-    {
-      if (dev_cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
-      { // suspend signal, bus idle for more than 3ms
-        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-        if (dev_cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-        {
-          dcd_event_bus_signal(0, DCD_EVENT_SUSPENDED, true);
-        }
-      }
-    }
-//        else
-//      { // resume signal
-//    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
-//      }
-//    }
-  }
-
-  // Setup Receive
-  if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
-  {
-    // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
-    _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
-    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
-
-    LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
-
-    dcd_event_setup_received(0, _dcd.setup_packet, true);
-
-    // keep waiting for next setup
-    _dcd.ep[0][1].buffer_offset = get_buf_offset(_dcd.setup_packet);
-
-    // clear bit0
-    int_status = BIT_CLR_(int_status, 0);
-  }
-
-  // Endpoint transfer complete interrupt
-  process_xfer_isr(int_status);
-}
-
-#endif
-
-- 
cgit v1.3.1


From c1336dff03032288d48704b055b507e175df2ac6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Dec 2018 11:53:56 +0700
Subject: lpc move Chip_USB_Init() out of stack to bsp

---
 hw/bsp/ea4357/board_ea4357.c                   | 45 ++++++++++++++++++++
 hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c |  3 ++
 hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c   |  4 +-
 hw/bsp/mcb1800/board_mcb1800.c                 | 43 +++++++++++++++++++
 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c |  3 --
 src/portable/nxp/lpc18_43/hal_lpc18_43.c       | 59 --------------------------
 6 files changed, 93 insertions(+), 64 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/ea4357/board_ea4357.c b/hw/bsp/ea4357/board_ea4357.c
index d59e4cb3c..42b71e992 100644
--- a/hw/bsp/ea4357/board_ea4357.c
+++ b/hw/bsp/ea4357/board_ea4357.c
@@ -40,6 +40,7 @@
 
 #include "../board.h"
 #include "pca9532.h"
+#include "tusb.h"
 
 #define BOARD_UART_PORT           LPC_USART0
 #define BOARD_UART_PIN_PORT       0x0f
@@ -171,6 +172,50 @@ void board_init(void)
 #endif
 
   //------------- USB -------------//
+  enum {
+    USBMODE_DEVICE = 2,
+    USBMODE_HOST   = 3
+  };
+
+  enum {
+    USBMODE_VBUS_LOW  = 0,
+    USBMODE_VBUS_HIGH = 1
+  };
+
+  // USB0
+#if CFG_TUSB_RHPORT0_MODE
+  Chip_USB0_Init();
+
+  // Reset controller
+  LPC_USB0->USBCMD_D |= 0x02;
+
+  // Set mode
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+  #else // TODO OTG
+    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
+    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+  #endif
+#endif
+
+  // USB1
+#if CFG_TUSB_RHPORT1_MODE
+  Chip_USB1_Init();
+
+  // Reset controller
+  LPC_USB1->USBCMD_D |= 0x02;
+
+  // Set mode
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+  #else // TODO OTG
+    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
+  #endif
+
+  // USB1 as fullspeed
+  LPC_USB1->PORTSC1_D |= (1<<24);
+#endif
+
   // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
   Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
 
diff --git a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
index 4c8e0809c..b9ef30ab8 100644
--- a/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
+++ b/hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
@@ -95,6 +95,9 @@ void board_init(void)
 
   //------------- UART -------------//
   //UARTInit(CFG_UART_BAUDRATE);
+
+  // USB
+  Chip_USB_Init(); // Setup PLL clock, and power
 }
 
 /*------------------------------------------------------------------*/
diff --git a/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c b/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
index 1ae21efab..94ad34a6f 100644
--- a/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
+++ b/hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
@@ -72,8 +72,6 @@ static const PINMUX_GRP_T pinmuxing[] =
   {0,  1,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_1 used for CLKOUT */
   {0,  2,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)},	/* PIO0_2 used for SSEL */
   {0,  3,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_3 used for USB_VBUS */
-  {0,  4,  (IOCON_FUNC1 | IOCON_FASTI2C_EN)},							/* PIO0_4 used for SCL */
-  {0,  5,  (IOCON_FUNC1 | IOCON_FASTI2C_EN)},							/* PIO0_5 used for SDA */
   {0,  6,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_6 used for USB_CONNECT */
   {0,  8,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_8 used for MISO0 */
   {0,  9,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_9 used for MOSI0 */
@@ -111,6 +109,8 @@ void board_init(void)
   //------------- UART -------------//
   //UARTInit(CFG_UART_BAUDRATE);
 
+  // USB
+  Chip_USB_Init(); // Setup PLL clock, and power
 }
 
 /*------------------------------------------------------------------*/
diff --git a/hw/bsp/mcb1800/board_mcb1800.c b/hw/bsp/mcb1800/board_mcb1800.c
index 2aed87418..5b7a846ef 100644
--- a/hw/bsp/mcb1800/board_mcb1800.c
+++ b/hw/bsp/mcb1800/board_mcb1800.c
@@ -143,6 +143,49 @@ void board_init(void)
 #endif
 
   //------------- USB -------------//
+  enum {
+    USBMODE_DEVICE = 2,
+    USBMODE_HOST   = 3
+  };
+
+  enum {
+    USBMODE_VBUS_LOW  = 0,
+    USBMODE_VBUS_HIGH = 1
+  };
+
+  // USB0
+#if CFG_TUSB_RHPORT0_MODE
+  Chip_USB0_Init();
+
+  // Reset controller
+  LPC_USB0->USBCMD_D |= 0x02;
+
+  // Set mode
+  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+    LPC_USB0->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+  #else // TODO OTG
+    LPC_USB0->USBMODE_D = USBMODE_DEVICE;
+    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
+  #endif
+#endif
+
+  // USB1
+#if CFG_TUSB_RHPORT1_MODE
+  Chip_USB1_Init();
+
+  // Reset controller
+  LPC_USB1->USBCMD_D |= 0x02;
+
+  // Set mode
+  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
+    LPC_USB1->USBMODE_H = USBMODE_HOST | (USBMODE_VBUS_HIGH << 5);
+  #else // TODO OTG
+    LPC_USB1->USBMODE_D = USBMODE_DEVICE;
+  #endif
+
+  // USB1 as fullspeed
+  LPC_USB1->PORTSC1_D |= (1<<24);
+#endif
 }
 
 //------------- LED -------------//
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
index 1ae070a73..9c5991cef 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
@@ -180,9 +180,6 @@ bool dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
-  // Setup PLL clock, and power
-  Chip_USB_Init();
-
   LPC_USB->EPLISTSTART  = (uint32_t) _dcd.ep;
   LPC_USB->DATABUFSTART = SRAM_REGION;
 
diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
index f91cf1309..152072cab 100644
--- a/src/portable/nxp/lpc18_43/hal_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
@@ -42,16 +42,6 @@
 
 #include "chip.h"
 
-enum {
-  LPC43XX_USBMODE_DEVICE = 2,
-  LPC43XX_USBMODE_HOST   = 3
-};
-
-enum {
-  LPC43XX_USBMODE_VBUS_LOW  = 0,
-  LPC43XX_USBMODE_VBUS_HIGH = 1
-};
-
 void tusb_hal_int_enable(uint8_t rhport)
 {
   NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
@@ -62,57 +52,8 @@ void tusb_hal_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
 }
 
-
-static void hal_controller_reset(uint8_t rhport)
-{ // TODO timeout expired to prevent trap
-  volatile uint32_t * p_reg_usbcmd;
-
-  p_reg_usbcmd = (rhport ? &LPC_USB1->USBCMD_D : &LPC_USB0->USBCMD_D);
-// NXP chip powered with non-host mode --> sts bit is not correctly reflected
-  (*p_reg_usbcmd) |= BIT_(1);
-
-//  tu_timeout_t timeout;
-//  tu_timeout_set(&timeout, 2); // should not take longer the time to stop controller
-  while( ((*p_reg_usbcmd) & BIT_(1)) /*&& !tu_timeout_expired(&timeout)*/) {}
-//
-//  return tu_timeout_expired(&timeout) ? TUSB_ERROR_OSAL_TIMEOUT : TUSB_ERROR_NONE;
-}
-
 bool tusb_hal_init(void)
 {
-  // USB0
-#if CFG_TUSB_RHPORT0_MODE
-  Chip_USB0_Init();
-
-  // reset controller & set role
-  hal_controller_reset(0);
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    LPC_USB0->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB0->USBMODE_D = LPC43XX_USBMODE_DEVICE;
-    LPC_USB0->OTGSC = (1<<3) | (1<<0) /*| (1<<16)| (1<<24)| (1<<25)| (1<<26)| (1<<27)| (1<<28)| (1<<29)| (1<<30)*/;
-    #if CFG_TUD_FULLSPEED // TODO for easy testing
-      LPC_USB0->PORTSC1_D |= (1<<24); // force full speed
-    #endif
-  #endif
-#endif
-
-  // USB1
-#if CFG_TUSB_RHPORT1_MODE
-  Chip_USB1_Init();
-
-  hal_controller_reset(1);
-
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    LPC_USB1->USBMODE_H = LPC43XX_USBMODE_HOST | (LPC43XX_USBMODE_VBUS_HIGH << 5);
-  #else // TODO OTG
-    LPC_USB1->USBMODE_D = LPC43XX_USBMODE_DEVICE;
-  #endif
-
-  LPC_USB1->PORTSC1_D |= (1<<24); // TODO abstract, force rhport to fullspeed
-#endif
-
   return true;
 }
 
-- 
cgit v1.3.1


From 6048a3bff48dc588849f83f4088367d20b6bc651 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Dec 2018 12:22:33 +0700
Subject: remove dcd_connect/disconnect since there is no usage now

---
 doxygen/porting.md                             |  4 +++-
 src/device/dcd.h                               | 12 ++++++------
 src/portable/microchip/samd21/dcd_samd21.c     |  9 ---------
 src/portable/microchip/samd51/dcd_samd51.c     |  9 ---------
 src/portable/nordic/nrf5x/dcd_nrf5x.c          |  9 ---------
 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c |  6 ------
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c       |  6 ------
 src/portable/nxp/lpc18_43/dcd_lpc18_43.c       |  5 -----
 8 files changed, 9 insertions(+), 51 deletions(-)

(limited to 'src')

diff --git a/doxygen/porting.md b/doxygen/porting.md
index be917d6f7..00aad6a08 100644
--- a/doxygen/porting.md
+++ b/doxygen/porting.md
@@ -79,7 +79,6 @@ After the USB device is setup, the USB device code works by processing events on
 All of the code for the low-level device API is in `src/portable/<vendor>/<chip family>/dcd_<chip family>.c`.
 
 #### Device Setup
-`dcd_connect`, `dcd_disconnect` and `dcd_set_config` are not currently used and can be left empty.
 
 ##### dcd_init
 Initializes the USB peripheral for device mode and enables it.
@@ -89,6 +88,9 @@ Called when the device is given a new bus address.
 
 If your peripheral automatically changes address during enumeration (like the nrf52) you may leave this empty and also no queue an event for the corresponding SETUP packet.
 
+##### dcd_set_config
+Called when the device received SET_CONFIG request, you can leave this empty if your peripheral does not require any specific action.
+
 #### Special events
 You must let TinyUSB know when certain events occur so that it can continue its work. There are a few methods you can call to queue events for TinyUSB to process.
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index db84df839..6b1356cbf 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -90,14 +90,14 @@ typedef struct ATTR_ALIGNED(4)
 TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct");
 
 /*------------------------------------------------------------------*/
-/* Device API (Weak is optional)
+/* Device API
  *------------------------------------------------------------------*/
-bool dcd_init             (uint8_t rhport);
-void dcd_set_address      (uint8_t rhport, uint8_t dev_addr);
-void dcd_set_config       (uint8_t rhport, uint8_t config_num);
+bool dcd_init       (uint8_t rhport);
+void dcd_int_enable (uint8_t rhport);
+void dcd_int_disable(uint8_t rhport);
 
-void dcd_connect          (uint8_t rhport) ATTR_WEAK;
-void dcd_disconnect       (uint8_t rhport) ATTR_WEAK;
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr);
+void dcd_set_config (uint8_t rhport, uint8_t config_num);
 
 /*------------------------------------------------------------------*/
 /* Event Function
diff --git a/src/portable/microchip/samd21/dcd_samd21.c b/src/portable/microchip/samd21/dcd_samd21.c
index dda75cee8..5436259dd 100644
--- a/src/portable/microchip/samd21/dcd_samd21.c
+++ b/src/portable/microchip/samd21/dcd_samd21.c
@@ -82,15 +82,6 @@ bool dcd_init (uint8_t rhport)
   return true;
 }
 
-void dcd_connect (uint8_t rhport)
-{
-
-}
-void dcd_disconnect (uint8_t rhport)
-{
-
-}
-
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/microchip/samd51/dcd_samd51.c b/src/portable/microchip/samd51/dcd_samd51.c
index d0ad17f92..0e8b23d83 100644
--- a/src/portable/microchip/samd51/dcd_samd51.c
+++ b/src/portable/microchip/samd51/dcd_samd51.c
@@ -82,15 +82,6 @@ bool dcd_init (uint8_t rhport)
   return true;
 }
 
-void dcd_connect (uint8_t rhport)
-{
-  (void) rhport;
-}
-void dcd_disconnect (uint8_t rhport)
-{
-  (void) rhport;
-}
-
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index e1e53a83e..2118a4bdc 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -195,15 +195,6 @@ bool dcd_init (uint8_t rhport)
   return true;
 }
 
-void dcd_connect (uint8_t rhport)
-{
-  (void) rhport;
-}
-void dcd_disconnect (uint8_t rhport)
-{
-  (void) rhport;
-}
-
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
index 9c5991cef..26674d9e9 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
@@ -157,12 +157,6 @@ bool tusb_hal_init(void)
   return true;
 }
 
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  LPC_USB->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
-}
-
 void dcd_set_config(uint8_t rhport, uint8_t config_num)
 {
 
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 8504cbf51..8763d1e18 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -202,12 +202,6 @@ bool dcd_init(uint8_t rhport)
   return TUSB_ERROR_NONE;
 }
 
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 1);
-}
-
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
index 8f5e3b457..9423b64a9 100644
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
@@ -92,11 +92,6 @@ static dcd_data_t* const dcd_data_ptr[2] =
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
-void dcd_connect(uint8_t rhport)
-{
-  LPC_USB[rhport]->USBCMD_D |= BIT_(0);
-}
-
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
-- 
cgit v1.3.1


From a73017fdc23f7bedf38e754cba3a4ffbcf8d4c27 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Dec 2018 13:20:25 +0700
Subject: hal clean up

- replace tusb_hal_int_enable/disable to dcd_int_enable/disable,
hcd_int_enable/disable
- remove tusb_hal_init(), this will be part of dcd_init/hcd_init,
anything beyond dcd/hcd should be inited by bsp
---
 doxygen/porting.md                             | 17 ++---
 hw/bsp/ea4357/board_ea4357.c                   |  2 +
 hw/bsp/mcb1800/board_mcb1800.c                 |  2 +
 src/device/usbd.c                              | 21 ++++---
 src/portable/microchip/samd21/dcd_samd21.c     | 26 ++++++++
 src/portable/microchip/samd21/hal_samd21.c     | 81 ------------------------
 src/portable/microchip/samd51/dcd_samd51.c     | 31 ++++++++++
 src/portable/microchip/samd51/hal_samd51.c     | 86 --------------------------
 src/portable/nordic/nrf5x/dcd_nrf5x.c          | 12 ++++
 src/portable/nordic/nrf5x/hal_nrf5x.c          | 21 -------
 src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c | 14 ++---
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c       | 12 ++++
 src/portable/nxp/lpc17_40/hal_lpc17_40.c       | 20 ------
 src/portable/nxp/lpc18_43/dcd_lpc18_43.c       | 11 +++-
 src/portable/nxp/lpc18_43/hal_lpc18_43.c       | 15 -----
 src/tusb.c                                     |  3 -
 src/tusb_hal.h                                 | 37 +++--------
 17 files changed, 123 insertions(+), 288 deletions(-)
 delete mode 100644 src/portable/microchip/samd21/hal_samd21.c
 delete mode 100644 src/portable/microchip/samd51/hal_samd51.c

(limited to 'src')

diff --git a/doxygen/porting.md b/doxygen/porting.md
index 00aad6a08..5a464fa6b 100644
--- a/doxygen/porting.md
+++ b/doxygen/porting.md
@@ -59,19 +59,6 @@ The OPT_OS_NONE option is the only option which requires an MCU specific functio
 
 `tusb_hal_millis` is also provided in `hw/bsp/<board name>/board_<board name>.c` because it may vary with MCU use.
 
-### Hardware Abstraction Layer (HAL)
-The hardware abstraction layer is a minimal set of abstractions used in both Device and Host USB modes.
-
-The HAL implementations are located in `src/portable/<vendor>/<chip family>/hal_<chip family>.c`.
-
-#### tusb_hal_init
-
-The HAL init is responsible for configuring common settings of USB peripheral such as pad calibration.
-
-#### tusb_hal_int_enable / tusb_hal_int_disable
-
-Enables or disables the USB interrupt(s). May be used to prevent concurrency issues when mutating data structures shared between main code and the interrupt handler.
-
 ### Device API
 
 After the USB device is setup, the USB device code works by processing events on the main thread (by calling `tusb_task`). These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing.
@@ -83,6 +70,10 @@ All of the code for the low-level device API is in `src/portable/<vendor>/<chip
 ##### dcd_init
 Initializes the USB peripheral for device mode and enables it.
 
+#### dcd_int_enable / dcd_int_disable
+
+Enables or disables the USB device interrupt(s). May be used to prevent concurrency issues when mutating data structures shared between main code and the interrupt handler.
+
 ##### dcd_set_address
 Called when the device is given a new bus address.
 
diff --git a/hw/bsp/ea4357/board_ea4357.c b/hw/bsp/ea4357/board_ea4357.c
index 42b71e992..eb447518c 100644
--- a/hw/bsp/ea4357/board_ea4357.c
+++ b/hw/bsp/ea4357/board_ea4357.c
@@ -188,6 +188,7 @@ void board_init(void)
 
   // Reset controller
   LPC_USB0->USBCMD_D |= 0x02;
+  while( LPC_USB0->USBCMD_D & 0x02 ) {}
 
   // Set mode
   #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
@@ -204,6 +205,7 @@ void board_init(void)
 
   // Reset controller
   LPC_USB1->USBCMD_D |= 0x02;
+  while( LPC_USB1->USBCMD_D & 0x02 ) {}
 
   // Set mode
   #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
diff --git a/hw/bsp/mcb1800/board_mcb1800.c b/hw/bsp/mcb1800/board_mcb1800.c
index 5b7a846ef..8474fbff3 100644
--- a/hw/bsp/mcb1800/board_mcb1800.c
+++ b/hw/bsp/mcb1800/board_mcb1800.c
@@ -159,6 +159,7 @@ void board_init(void)
 
   // Reset controller
   LPC_USB0->USBCMD_D |= 0x02;
+  while( LPC_USB0->USBCMD_D & 0x02 ) {}
 
   // Set mode
   #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
@@ -175,6 +176,7 @@ void board_init(void)
 
   // Reset controller
   LPC_USB1->USBCMD_D |= 0x02;
+  while( LPC_USB1->USBCMD_D & 0x02 ) {}
 
   // Set mode
   #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 81fcfe959..ddb63cebb 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -190,23 +190,26 @@ bool tud_mounted(void)
 //--------------------------------------------------------------------+
 tusb_error_t usbd_init (void)
 {
+  // Init device queue & task
+  _usbd_q = osal_queue_create(&_usbd_qdef);
+  TU_VERIFY(_usbd_q, TUSB_ERROR_OSAL_QUEUE_FAILED);
+
+  osal_task_create(&_usbd_task_def);
+
+  // Init class drivers
+  for (uint8_t i = 0; i < USBD_CLASS_DRIVER_COUNT; i++) usbd_class_drivers[i].init();
+
+  // Init device controller driver
   #if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
   dcd_init(0);
+  dcd_int_enable(0);
   #endif
 
   #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   dcd_init(1);
+  dcd_int_enable(1);
   #endif
 
-  //------------- Task init -------------//
-  _usbd_q = osal_queue_create(&_usbd_qdef);
-  TU_VERIFY(_usbd_q, TUSB_ERROR_OSAL_QUEUE_FAILED);
-
-  osal_task_create(&_usbd_task_def);
-
-  //------------- class init -------------//
-  for (uint8_t i = 0; i < USBD_CLASS_DRIVER_COUNT; i++) usbd_class_drivers[i].init();
-
   return TUSB_ERROR_NONE;
 }
 
diff --git a/src/portable/microchip/samd21/dcd_samd21.c b/src/portable/microchip/samd21/dcd_samd21.c
index 5436259dd..57c4c4d9d 100644
--- a/src/portable/microchip/samd21/dcd_samd21.c
+++ b/src/portable/microchip/samd21/dcd_samd21.c
@@ -72,6 +72,20 @@ static void bus_reset(void) {
 bool dcd_init (uint8_t rhport)
 {
   (void) rhport;
+
+  // Reset to get in a clean state.
+  USB->DEVICE.CTRLA.bit.SWRST = true;
+  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) {}
+  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) {}
+
+  USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+  USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+  USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
+
+  USB->DEVICE.QOSCTRL.bit.CQOS = USB_QOSCTRL_CQOS_HIGH_Val;
+  USB->DEVICE.QOSCTRL.bit.DQOS = USB_QOSCTRL_DQOS_HIGH_Val;
+
+  // Configure registers
   USB->DEVICE.DESCADD.reg = (uint32_t) &sram_registers;
   USB->DEVICE.CTRLB.reg = USB_DEVICE_CTRLB_SPDCONF_FS;
   USB->DEVICE.CTRLA.reg = USB_CTRLA_MODE_DEVICE | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY;
@@ -82,6 +96,18 @@ bool dcd_init (uint8_t rhport)
   return true;
 }
 
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_IRQn);
+}
+
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/microchip/samd21/hal_samd21.c b/src/portable/microchip/samd21/hal_samd21.c
deleted file mode 100644
index 9f04630ea..000000000
--- a/src/portable/microchip/samd21/hal_samd21.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_nrf5x.c
-    @author   hathach
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2018, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMD21
-
-#include "sam.h"
-
-#include "tusb_hal.h"
-
-
-/*------------------------------------------------------------------*/
-/* TUSB HAL
- *------------------------------------------------------------------*/
-bool tusb_hal_init(void)
-{
-  // Reset to get in a clean state.
-  USB->DEVICE.CTRLA.bit.SWRST = true;
-  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) {}
-  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) {}
-
-  USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
-  USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
-  USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
-
-  USB->DEVICE.QOSCTRL.bit.CQOS = USB_QOSCTRL_CQOS_HIGH_Val;
-  USB->DEVICE.QOSCTRL.bit.DQOS = USB_QOSCTRL_DQOS_HIGH_Val;
-
-  tusb_hal_int_enable(0);
-  return true;
-}
-
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USB_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_IRQn);
-}
-
-#endif
diff --git a/src/portable/microchip/samd51/dcd_samd51.c b/src/portable/microchip/samd51/dcd_samd51.c
index 0e8b23d83..ba53d5598 100644
--- a/src/portable/microchip/samd51/dcd_samd51.c
+++ b/src/portable/microchip/samd51/dcd_samd51.c
@@ -73,6 +73,19 @@ bool dcd_init (uint8_t rhport)
 {
   (void) rhport;
 
+  // Reset to get in a clean state.
+  USB->DEVICE.CTRLA.bit.SWRST = true;
+  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) {}
+  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) {}
+
+  USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+  USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+  USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
+
+  USB->DEVICE.QOSCTRL.bit.CQOS = 3;
+  USB->DEVICE.QOSCTRL.bit.DQOS = 3;
+
+  // Configure registers
   USB->DEVICE.DESCADD.reg = (uint32_t) &sram_registers;
   USB->DEVICE.CTRLB.reg = USB_DEVICE_CTRLB_SPDCONF_FS;
   USB->DEVICE.CTRLA.reg = USB_CTRLA_MODE_DEVICE | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY;
@@ -82,6 +95,24 @@ bool dcd_init (uint8_t rhport)
   return true;
 }
 
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB_0_IRQn);
+  NVIC_EnableIRQ(USB_1_IRQn);
+  NVIC_EnableIRQ(USB_2_IRQn);
+  NVIC_EnableIRQ(USB_3_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_3_IRQn);
+  NVIC_DisableIRQ(USB_2_IRQn);
+  NVIC_DisableIRQ(USB_1_IRQn);
+  NVIC_DisableIRQ(USB_0_IRQn);
+}
+
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/microchip/samd51/hal_samd51.c b/src/portable/microchip/samd51/hal_samd51.c
deleted file mode 100644
index 49212b74c..000000000
--- a/src/portable/microchip/samd51/hal_samd51.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/**************************************************************************/
-/*!
-    @file     hal_nrf5x.c
-    @author   hathach
-
-    @section LICENSE
-
-    Software License Agreement (BSD License)
-
-    Copyright (c) 2018, hathach (tinyusb.org)
-    All rights reserved.
-
-    Redistribution and use in source and binary forms, with or without
-    modification, are permitted provided that the following conditions are met:
-    1. Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holders nor the
-    names of its contributors may be used to endorse or promote products
-    derived from this software without specific prior written permission.
-
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
-    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
-    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-    This file is part of the tinyusb stack.
-*/
-/**************************************************************************/
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMD51
-
-#include "sam.h"
-
-#include "tusb_hal.h"
-
-/*------------------------------------------------------------------*/
-/* TUSB HAL
- *------------------------------------------------------------------*/
-bool tusb_hal_init(void)
-{
-  // Reset to get in a clean state.
-  USB->DEVICE.CTRLA.bit.SWRST = true;
-  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) {}
-  while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) {}
-
-  USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
-  USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
-  USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos;
-
-  USB->DEVICE.QOSCTRL.bit.CQOS = 3;
-  USB->DEVICE.QOSCTRL.bit.DQOS = 3;
-
-  tusb_hal_int_enable(0);
-  return true;
-}
-
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USB_0_IRQn);
-  NVIC_EnableIRQ(USB_1_IRQn);
-  NVIC_EnableIRQ(USB_2_IRQn);
-  NVIC_EnableIRQ(USB_3_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_3_IRQn);
-  NVIC_DisableIRQ(USB_2_IRQn);
-  NVIC_DisableIRQ(USB_1_IRQn);
-  NVIC_DisableIRQ(USB_0_IRQn);
-}
-
-#endif
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 2118a4bdc..c7a4f413f 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -195,6 +195,18 @@ bool dcd_init (uint8_t rhport)
   return true;
 }
 
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USBD_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USBD_IRQn);
+}
+
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/nordic/nrf5x/hal_nrf5x.c b/src/portable/nordic/nrf5x/hal_nrf5x.c
index f40e904d7..4cbcd1788 100644
--- a/src/portable/nordic/nrf5x/hal_nrf5x.c
+++ b/src/portable/nordic/nrf5x/hal_nrf5x.c
@@ -128,27 +128,6 @@ static void hfclk_disable(void)
   nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
 }
 
-
-/*------------------------------------------------------------------*/
-/* TUSB HAL
- *------------------------------------------------------------------*/
-bool tusb_hal_init(void)
-{
-  return true;
-}
-
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USBD_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USBD_IRQn);
-}
-
 /*------------------------------------------------------------------*/
 /* Controller Start up Sequence (USBD 51.4 specs)
  *------------------------------------------------------------------*/
diff --git a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
index 26674d9e9..69c2759de 100644
--- a/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
+++ b/src/portable/nxp/lpc11_13_15/dcd_lpc11_13_15.c
@@ -139,24 +139,18 @@ static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
-void tusb_hal_int_enable(uint8_t rhport)
+void dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport; // discard compiler's warning
+  (void) rhport;
   NVIC_EnableIRQ(USB0_IRQn);
 }
 
-void tusb_hal_int_disable(uint8_t rhport)
+void dcd_int_disable(uint8_t rhport)
 {
-  (void) rhport; // discard compiler's warning
+  (void) rhport;
   NVIC_DisableIRQ(USB0_IRQn);
 }
 
-bool tusb_hal_init(void)
-{
-  // TODO remove
-  return true;
-}
-
 void dcd_set_config(uint8_t rhport, uint8_t config_num)
 {
 
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 8763d1e18..84eb0c121 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -202,6 +202,18 @@ bool dcd_init(uint8_t rhport)
   return TUSB_ERROR_NONE;
 }
 
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_IRQn);
+}
+
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
diff --git a/src/portable/nxp/lpc17_40/hal_lpc17_40.c b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
index 70df70510..7509dac58 100644
--- a/src/portable/nxp/lpc17_40/hal_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hal_lpc17_40.c
@@ -42,26 +42,6 @@
 
 #include "chip.h"
 
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USB_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_IRQn);
-}
-
-//--------------------------------------------------------------------+
-// IMPLEMENTATION
-//--------------------------------------------------------------------+
-bool tusb_hal_init(void)
-{
-  return true;
-}
-
 void USB_IRQHandler(void)
 {
   extern void hal_dcd_isr(uint8_t rhport);
diff --git a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
index 9423b64a9..7f6442f8c 100644
--- a/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/dcd_lpc18_43.c
@@ -158,10 +158,17 @@ bool dcd_init(uint8_t rhport)
   lpc_usb->USBCMD_D &= ~0x00FF0000; // Interrupt Threshold Interval = 0
   lpc_usb->USBCMD_D |= BIT_(0); // connect
 
-  // enable interrupt
+  return true;
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
   NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
+}
 
-  return true;
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/lpc18_43/hal_lpc18_43.c b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
index 152072cab..2978bebf6 100644
--- a/src/portable/nxp/lpc18_43/hal_lpc18_43.c
+++ b/src/portable/nxp/lpc18_43/hal_lpc18_43.c
@@ -42,21 +42,6 @@
 
 #include "chip.h"
 
-void tusb_hal_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-void tusb_hal_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
-}
-
-bool tusb_hal_init(void)
-{
-  return true;
-}
-
 void hal_dcd_isr(uint8_t rhport);
 
 #if CFG_TUSB_RHPORT0_MODE
diff --git a/src/tusb.c b/src/tusb.c
index e9db184f2..81c4907fb 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -47,14 +47,11 @@
 
 static bool _initialized = false;
 
-
 tusb_error_t tusb_init(void)
 {
   // skip if already initialized
   if (_initialized) return TUSB_ERROR_NONE;
 
-  TU_VERIFY( tusb_hal_init(), TUSB_ERROR_FAILED ) ; // hardware init
-
 #if MODE_HOST_SUPPORTED
   TU_ASSERT_ERR( usbh_init() ); // host stack init
 #endif
diff --git a/src/tusb_hal.h b/src/tusb_hal.h
index 85a2a8709..301e8c2f2 100644
--- a/src/tusb_hal.h
+++ b/src/tusb_hal.h
@@ -51,55 +51,37 @@ extern "C" {
 //--------------------------------------------------------------------+
 // HAL API
 //--------------------------------------------------------------------+
-/** \ingroup group_mcu
- * \defgroup group_hal Hardware Abtract Layer (HAL)
- * Hardware Abstraction Layer (HAL) is an abstraction layer, between the physical hardware and the tinyusb stack.
- * Its function is to hide differences in hardware from most of MCUs, so that most of the stack code does not need to be changed to
- * run on systems with a different MCU.
- * HAL are sets of routines that emulate some platform-specific details, giving programs direct access to the hardware resources.
- *  @{ */
-
-/** \brief    Initialize USB controller hardware
- * \returns   true if succeeded
- * \note      This function is invoked by \ref tusb_init as part of the initialization.
- */
-bool tusb_hal_init(void);
-
-/** \brief 			Enable USB Interrupt on a specific USB Controller
- * \param[in]		rhport	is a zero-based index to identify USB controller's ID
- */
-void tusb_hal_int_enable(uint8_t rhport);
-
-/** \brief 			Disable USB Interrupt on a specific USB Controller
- * \param[in]		rhport	is a zero-based index to identify USB controller's ID
- */
-void tusb_hal_int_disable(uint8_t rhport);
 
 // Only required to implement if using No RTOS (osal_none)
 uint32_t tusb_hal_millis(void);
 
+// TODO remove
+extern void dcd_int_enable (uint8_t rhport);
+extern void dcd_int_disable(uint8_t rhport);
 
 // Enable all ports' interrupt
+// TODO remove
 static inline void tusb_hal_int_enable_all(void)
 {
 #ifdef CFG_TUSB_RHPORT0_MODE
-  tusb_hal_int_enable(0);
+  dcd_int_enable(0);
 #endif
 
 #ifdef CFG_TUSB_RHPORT0_MODE
-  tusb_hal_int_enable(1);
+  dcd_int_enable(1);
 #endif
 }
 
 // Disable all ports' interrupt
+// TODO remove
 static inline void tusb_hal_int_disable_all(void)
 {
 #ifdef CFG_TUSB_RHPORT0_MODE
-  tusb_hal_int_disable(0);
+  dcd_int_disable(0);
 #endif
 
 #ifdef CFG_TUSB_RHPORT0_MODE
-  tusb_hal_int_disable(1);
+  dcd_int_disable(1);
 #endif
 }
 
@@ -111,4 +93,3 @@ static inline void tusb_hal_int_disable_all(void)
 
 #endif /* _TUSB_HAL_H_ */
 
-/** @} */
-- 
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